* [U-Boot] [PATCH v4 2/2] amcore: add support for amcore board
@ 2013-01-22 22:23 Angelo Dureghello
0 siblings, 0 replies; only message in thread
From: Angelo Dureghello @ 2013-01-22 22:23 UTC (permalink / raw)
To: u-boot
Signed-off-by: Angelo Dureghello <sysamfw@gmail.com>
Cc: Jason Jin <jason.jin@freescale.com>
---
Changes for v2:
- None
Changes for v3:
- Fix code format issues
Changes for v4:
- Added MAINTAINERS file entry
- Removed all unnecessary blank lines
- Added get_ram_size in sdram init
- Reused already existing sdram test routine
- Removed custom flash.c, used std mtd/CFI driver
---
MAINTAINERS | 4 +
board/sysam/amcore/Makefile | 43 ++++++
board/sysam/amcore/amcore.c | 160 +++++++++++++++++++++
board/sysam/amcore/config.mk | 23 +++
board/sysam/amcore/u-boot.lds | 101 ++++++++++++++
boards.cfg | 1 +
include/configs/amcore.h | 220 +++++++++++++++++++++++++++++
7 files changed, 552 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 28c052d..1d27cb7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1137,6 +1137,10 @@ Wolfgang Wegner <w.wegner@astro-kom.de>
astro_mcf5373l MCF5373L
+Angelo Dureghello <sysamfw@gmail.com>
+
+ amcore mcf5307
+
#########################################################################
# AVR32 Systems: #
# #
diff --git a/arch/m68k/cpu/mcf530x/Makefile b/arch/m68k/cpu/mcf530x/Makefile
new file mode 100644
index 0000000..3c5a1c2
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (c) 2011 Angelo Dureghello <sysamfw@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# CFLAGS += -DET_DEBUG
+
+LIB = $(obj)lib$(CPU).o
+
+START = start.o
+COBJS = interrupts.o cpu.o speed.o cpu_init.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/m68k/cpu/mcf530x/config.mk b/arch/m68k/cpu/mcf530x/config.mk
new file mode 100644
index 0000000..924cd7f
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5307:=$(shell grep CONFIG_M5307 $(TOPDIR)/include/$(cfg))
+
+ifneq (,$(findstring CONFIG_M5307,$(is5307)))
+PLATFORM_CPPFLAGS += -mcpu=5307
+endif
diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c
new file mode 100644
index 0000000..5aac085
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/cpu.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#include "cpu.h"
+
+#ifdef CONFIG_M5307
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ /* enable watchdog/reset, set timeout to 0 and wait */
+ out_8(&sim->sypcr, SYPCR_SWE | SYPCR_SWRI);
+
+ /* wait for watchdog reset */
+ for (;;)
+ ;
+
+ /* we don't return! */
+ return 0;
+}
+
+int checkcpu(void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n",
+ strmhz(buf, CONFIG_SYS_CPU_CLK));
+ return 0;
+}
+#endif
diff --git a/arch/m68k/cpu/mcf530x/cpu.h b/arch/m68k/cpu/mcf530x/cpu.h
new file mode 100644
index 0000000..fd47f9a
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/cpu.h
@@ -0,0 +1,33 @@
+/*
+ * cpu.h
+ *
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+/* Use this to create board specific reset functions */
+void board_reset(void) __attribute__((__weak__));
+
+#endif /* _CPU_H_ */
diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c
new file mode 100644
index 0000000..796685e
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/cpu_init.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_M5307)
+/*
+ * Simple mcf5307 chip select module init.
+ *
+ * Note: this chip has an issue reported in the device "errata":
+ * MCF5307ER Rev 4.2 reports @ section 35:
+ * Corrupted Return PC in Exception Stack Frame
+ * When processing an autovectored interrupt an error can occur that
+ * causes 0xFFFFFFFF to be written as the return PC value in the
+ * exception stack frame. The problem is caused by a conflict between
+ * an internal autovector access and a chip select mapped to the IACK
+ * address space (0xFFFFXXXX).
+ * Workaround:
+ * Set the C/I bit in the chip select mask register (CSMR) for the
+ * chip select that is mapped to 0xFFFFXXXX.
+ * This will prevent the chip select from asserting for IACK accesses.
+ */
+
+#define MCF5307_SP_ERR_FIX(cs_base, mask) \
+ do { \
+ if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \
+ 0xffff0000) \
+ setbits_be32(&mask, CSMR_CI); \
+ } while (0)
+
+void init_csm(void)
+{
+ csm_t *csm = (csm_t *) (MMAP_CSM);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
+ defined(CONFIG_SYS_CS0_CTRL))
+ out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
+ out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
+ defined(CONFIG_SYS_CS1_CTRL))
+ out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
+ defined(CONFIG_SYS_CS2_CTRL))
+ out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
+ defined(CONFIG_SYS_CS3_CTRL))
+ out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
+ defined(CONFIG_SYS_CS4_CTRL))
+ out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
+ out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
+ defined(CONFIG_SYS_CS5_CTRL))
+ out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
+ out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
+ defined(CONFIG_SYS_CS6_CTRL))
+ out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
+ out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
+ out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
+ defined(CONFIG_SYS_CS7_CTRL))
+ out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
+ out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
+ out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
+#endif
+}
+
+/*
+ * Set up the memory map and initialize registers
+ */
+void cpu_init_f(void)
+{
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ out_8(&sim->sypcr, 0x00);
+ out_8(&sim->swivr, 0x0f);
+ out_8(&sim->swsr, 0x00);
+ out_8(&sim->mpark, 0x00);
+
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ /* timer 2 not masked */
+ out_be32(&icr->imr, 0xfffffbff);
+
+ out_8(&icr->icr0, 0x00); /* sw watchdog */
+ out_8(&icr->icr1, 0x00); /* timer 1 */
+ out_8(&icr->icr2, 0x88); /* timer 2 */
+ out_8(&icr->icr3, 0x00); /* i2c */
+ out_8(&icr->icr4, 0x00); /* uart 0 */
+ out_8(&icr->icr5, 0x00); /* uart 1 */
+ out_8(&icr->icr6, 0x00); /* dma 0 */
+ out_8(&icr->icr7, 0x00); /* dma 1 */
+ out_8(&icr->icr8, 0x00); /* dma 2 */
+ out_8(&icr->icr9, 0x00); /* dma 3 */
+
+ /* Chipselect Init */
+ init_csm();
+
+ /* enable data/instruction cache now */
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return 0;
+}
+
+void uart_port_conf(void)
+{
+}
+
+void arch_preboot_os(void)
+{
+ /*
+ * OS can change interrupt offsets and are about to boot the OS so
+ * we need to make sure we disable all async interrupts.
+ */
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ out_8(&icr->icr1, 0x00); /* timer 1 */
+ out_8(&icr->icr2, 0x00); /* timer 2 */
+}
+#endif
diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c
new file mode 100644
index 0000000..e63552b
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/interrupts.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_M5307
+int interrupt_init(void)
+{
+ enable_interrupts();
+
+ return 0;
+}
+
+void dtimer_intr_setup(void)
+{
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ /* clearing TIMER2 mask, so enabling the related interrupt */
+ out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400);
+ /* set TIMER2 interrupt priority */
+ out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI);
+}
+#endif
diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c
new file mode 100644
index 0000000..94a8116
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/speed.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#if defined(CONFIG_M5307)
+ gd->bus_clk = CONFIG_SYS_CLK;
+ gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+#endif
+
+ return 0;
+}
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
new file mode 100644
index 0000000..2801e5f
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <timestamp.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#define _START _start
+#define _FAULT _fault
+
+#define SAVE_ALL \
+ move.w #0x2700,%sr; /* disable intrs */ \
+ subl #60,%sp; /* space for 15 regs */ \
+ moveml %d0-%d7/%a0-%a6,%sp@; \
+
+#define RESTORE_ALL \
+ moveml %sp@,%d0-%d7/%a0-%a6; \
+ addl #60,%sp; /* space for 15 regs */ \
+ rte
+
+/*
+ * If we come from a pre-loader we don't need an initial exception
+ * table.
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+
+.text
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
+#if defined(CONFIG_M5307) && \
+ (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+.long _start - CONFIG_SYS_TEXT_BASE
+#else
+.long _START
+#endif
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+#endif
+
+ .text
+ .globl _start
+_start:
+ nop
+ nop
+ move.w #0x2700,%sr
+
+ /* set MBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.c %d0, %MBAR
+
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.c %d0, %RAMBAR
+
+ /* DS 4.8.2 (Cache Organization) invalidate and disable cache */
+ move.l #CF_CACR_CINVA, %d0
+ movec %d0, %CACR
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
+ /*
+ * if we come from a pre-loader we have no exception table and
+ * therefore no VBR to set
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
+ movec %d0, %VBR
+#endif
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(ICACHE_STATUS), %a1 /* icache */
+ move.l #(DCACHE_STATUS), %a2 /* dcache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+
+ /*
+ * set stackpointer to internal sram end - 80
+ * (global data struct size + some bytes)
+ * get some stackspace for the first c-code,
+ */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ clr.l %sp at -
+
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
+
+ /* run low-level CPU init code (from flash) */
+ bsr cpu_init_f
+
+ /* run low-level board init code (from flash) */
+ bsr board_init_f
+
+ /* board_init_f() does not return */
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+ .globl relocate_code
+relocate_code:
+ link.w %a6,#0
+ move.l 8(%a6), %sp /* set new stack pointer */
+ move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
+ move.l 16(%a6), %a0 /* Save copy of Destination Address */
+
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
+ move.l #__init_end, %a2
+ move.l %a0, %a3
+
+ /* copy the code to RAM */
+1:
+ move.l (%a1)+, (%a3)+
+ cmp.l %a1,%a2
+ bgt.s 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+ move.l %a0, %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+ jmp (%a1)
+
+in_ram:
+
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ move.l %a0, %a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
+ move.l %a0, %d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+6:
+ clr.l (%a1)+
+ cmp.l %a1,%d1
+ bgt.s 6b
+
+ /*
+ * fix got table in RAM
+ */
+ move.l %a0, %a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
+ /* * fix got pointer register a5 */
+ move.l %a1,%a5
+
+ move.l %a0, %a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
+
+7:
+ move.l (%a1),%d1
+ sub.l #_start,%d1
+ add.l %a0,%d1
+ move.l %d1,(%a1)+
+ cmp.l %a2, %a1
+ bne 7b
+
+ /* calculate relative jump to board_init_r in ram */
+ move.l %a0, %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+ /* set parameters for board_init_r */
+ move.l %a0,-(%sp) /* dest_addr */
+ move.l %d0,-(%sp) /* gd */
+#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \
+ defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
+ halt
+#endif
+ jsr (%a1)
+
+/*--------------------------------------------------------------------------*/
+/* exception code */
+ .globl _fault
+_fault:
+ jmp _fault
+
+ .globl _exc_handler
+_exc_handler:
+ SAVE_ALL
+ movel %sp,%sp at -
+ bsr exc_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+ .globl _int_handler
+_int_handler:
+ SAVE_ALL
+ movel %sp,%sp at -
+ bsr int_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+/*--------------------------------------------------------------------------*/
+
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index f9e2d15..dd932c3 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -31,7 +31,8 @@
#define CONFIG_CF_V2
#endif
-#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
+#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
+ defined(CONFIG_MCF5301x)
#define CONFIG_CF_V3
#endif
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 2aab463..e9bd1e6 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -256,6 +256,29 @@
#endif
#endif /* CONFIG_M5282 */
+#ifdef CONFIG_M5307
+#include <asm/immap_5307.h>
+#include <asm/m5307.h>
+
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
+ (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG (in_be32(MMAP_INTC))
+#define CONFIG_SYS_TMRINTR_NO (31)
+#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
+ MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5307 */
+
#if defined(CONFIG_MCF5301x)
#include <asm/immap_5301x.h>
#include <asm/m5301x.h>
diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h
new file mode 100644
index 0000000..e9aef5e
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5307.h
@@ -0,0 +1,134 @@
+/*
+ * MCF5307 Internal Memory Map
+ *
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5307__
+#define __IMMAP_5307__
+
+#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244)
+
+typedef struct sim {
+ u8 rsr;
+ u8 sypcr;
+ u8 swivr;
+ u8 swsr;
+ u16 par;
+ u8 irqpar;
+ u8 res1;
+ u8 pllcr;
+ u8 res2;
+ u16 res3;
+ u8 mpark;
+ u8 res4;
+ u16 res5;
+ u32 res6;
+} sim_t;
+
+typedef struct intctrl {
+ u32 ipr;
+ u32 imr;
+ u16 res7;
+ u8 res8;
+ u8 avr;
+ u8 icr0;
+ u8 icr1;
+ u8 icr2;
+ u8 icr3;
+ u8 icr4;
+ u8 icr5;
+ u8 icr6;
+ u8 icr7;
+ u8 icr8;
+ u8 icr9;
+ u16 res9;
+} intctrl_t;
+
+typedef struct csm {
+ u16 csar0; /* Chip-select Address */
+ u16 res1;
+ u32 csmr0; /* Chip-select Mask */
+ u16 res2;
+ u16 cscr0; /* Chip-select Control */
+ u16 csar1;
+ u16 res3;
+ u32 csmr1;
+ u16 res4;
+ u16 cscr1;
+ u16 csar2;
+ u16 res5;
+ u32 csmr2;
+ u16 res6;
+ u16 cscr2;
+ u16 csar3;
+ u16 res7;
+ u32 csmr3;
+ u16 res8;
+ u16 cscr3;
+ u16 csar4;
+ u16 res9;
+ u32 csmr4;
+ u16 res10;
+ u16 cscr4;
+ u16 csar5;
+ u16 res11;
+ u32 csmr5;
+ u16 res12;
+ u16 cscr5;
+ u16 csar6;
+ u16 res13;
+ u32 csmr6;
+ u16 res14;
+ u16 cscr6;
+ u16 csar7;
+ u16 res15;
+ u32 csmr7;
+ u16 res16;
+ u16 cscr7;
+} csm_t;
+
+typedef struct dramctrl {
+ u16 dcr;
+ u16 res1;
+ u32 res2;
+ u32 dacr0;
+ u32 dmr0;
+ u32 dacr1;
+ u32 dmr1;
+} dramctrl_t;
+
+typedef struct gpio {
+ u16 paddr;
+ u16 res1;
+ u16 padat;
+ u16 res2;
+} gpio_t;
+
+#endif /* __IMMAP_5307__ */
diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h
new file mode 100644
index 0000000..d91835b
--- /dev/null
+++ b/arch/m68k/include/asm/m5307.h
@@ -0,0 +1,86 @@
+/*
+ * mcf5307.h -- Definitions for Freescale Coldfire 5307
+ *
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef mcf5307_h
+#define mcf5307_h
+
+/*
+ * Size of internal RAM (RAMBAR)
+ */
+#define INT_RAM_SIZE 4096
+
+/* Bit definitions and macros for SYPCR */
+#define SYPCR_SWTAVAL 0x02
+#define SYPCR_SWTA 0x04
+#define SYPCR_SWT(x) ((x&0x3)<<3)
+#define SYPCR_SWP 0x20
+#define SYPCR_SWRI 0x40
+#define SYPCR_SWE 0x80
+
+/* Bit definitions and macros for CSMR */
+#define CSMR_V 0x01
+#define CSMR_UD 0x02
+#define CSMR_UC 0x04
+#define CSMR_SD 0x08
+#define CSMR_SC 0x10
+#define CSMR_CI 0x20
+#define CSMR_AM 0x40
+#define CSMR_WP 0x100
+
+/* Bit definitions and macros for DACR (SDRAM) */
+#define DACR_PM_CONTINUOUS 0x04
+#define DACR_IP_PRECHG_ALL 0x08
+#define DACR_PORT_SZ_32 0
+#define DACR_PORT_SZ_8 (1<<4)
+#define DACR_PORT_SZ_16 (2<<4)
+#define DACR_IMRS_INIT_CMD (1<<6)
+#define DACR_CMD_PIN(x) ((x&7)<<8)
+#define DACR_CASL(x) ((x&3)<<12)
+#define DACR_RE (1<<15)
+
+/* Bit definitions and macros for CSCR */
+#define CSCR_BSTW 0x08
+#define CSCR_BSTR 0x10
+#define CSCR_BEM 0x20
+#define CSCR_PS(x) ((x&0x3)<<6)
+#define CSCR_AA 0x100
+#define CSCR_WS ((x&0xf)<<10)
+
+/* Bit definitions for the ICR family of registers */
+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
+
+#endif /* mcf5307_h */
diff --git a/arch/m68k/include/asm/timer.h b/arch/m68k/include/asm/timer.h
index 1a5de05..528bce3 100644
--- a/arch/m68k/include/asm/timer.h
+++ b/arch/m68k/include/asm/timer.h
@@ -33,7 +33,8 @@
/****************************************************************************/
/* DMA Timer module registers */
typedef struct dtimer_ctrl {
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+ defined(CONFIG_M5272) || defined(CONFIG_M5307)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */
diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index a0e2441..7476970 100644
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -27,6 +27,7 @@
#include <asm/timer.h>
#include <asm/immap.h>
+#include <asm/io.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/sysam/amcore/Makefile b/board/sysam/amcore/Makefile
new file mode 100644
index 0000000..1fd25a8
--- /dev/null
+++ b/board/sysam/amcore/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (c) 2011 Angelo Dureghello <sysamfw@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
new file mode 100644
index 0000000..d40297e
--- /dev/null
+++ b/board/sysam/amcore/amcore.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Copy memory testdram() from sandburst/common/sb_common.c
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+void init_lcd(void)
+{
+ /*
+ * board can have a K0108 lcd connected on the parallel port,
+ * wired as below:
+ *
+ * fc cpu P0 P1 P2 P3 P4 P5 P6 P7 P10 P11 P12 P13 P14
+ * lcd D0 D1 D2 D3 D4 D5 D6 D7 CS1 CS2 RW DI E
+ *
+ * Starting up setting lines in high impedance
+ */
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ out_be16(&sim->par, 0x300);
+
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+
+ out_be16(&gpio->paddr, 0xfcff);
+ out_be16(&gpio->padat, 0x0c00);
+}
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("AMCORE v.001(alpha)\n");
+
+ init_lcd();
+
+ return 0;
+}
+
+/*
+ * in initdram we are here executing from flash
+ * case 1:
+ * is with no ACR/flash cache enabled
+ * nop = 40ns (scope measured)
+ */
+void fudelay(int usec)
+{
+ while (usec--)
+ asm volatile ("nop");
+}
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize, RC;
+
+ dramctrl_t *dc = (dramctrl_t *)(MMAP_DRAMC);
+
+ /*
+ * SDRAM MT48LC4M32B2 details
+ * Memory block 0: 16 MB of SDRAM at address $00000000
+ * Port size: 32-bit port
+ *
+ * Memory block 0 wired as follows:
+ * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
+ * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
+ *
+ * Ensure that there is a delay of at least 100 microseconds from
+ * processor reset to the following code so that the SDRAM is ready
+ * for commands.
+ */
+ fudelay(100);
+
+ /*
+ * DCR
+ * set proper RC as per specification
+ */
+ RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
+ RC = (RC * 15) >> 4;
+
+ /* 0x8000 is the faster option */
+ out_be16(&dc->dcr, 0x8200 | RC);
+
+ /*
+ * DACR0, page mode continuous, CMD on A20 0x0300
+ */
+ out_be32(&dc->dacr0, 0x00003304);
+
+ dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20)-1) & 0xfffc0000;
+ out_be32(&dc->dmr0, dramsize|1);
+
+ /* issue a PRECHARGE ALL */
+ out_be32(&dc->dacr0, 0x0000330c);
+ out_be32(0x00000004, 0xbeaddeed);
+ /* issue AUTOREFRESH */
+ out_be32(&dc->dacr0, 0x0000b304);
+ /* let refresh occour */
+ fudelay(1);
+
+ out_be32(&dc->dacr0, 0x0000b344);
+ out_be32(0x00000c00, 0xbeaddeed);
+
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE,
+ (CONFIG_SYS_SDRAM_SIZE<<20));
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+/* memory test */
+int testdram(void)
+{
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+ uint *p;
+
+ printf("Testing SDRAM: ");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("OK\n");
+
+ return 0;
+}
+#endif
diff --git a/board/sysam/amcore/config.mk b/board/sysam/amcore/config.mk
new file mode 100644
index 0000000..cb45c2c
--- /dev/null
+++ b/board/sysam/amcore/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright (c) 2011 Angelo Dureghello <sysamfw@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffc00000
diff --git a/board/sysam/amcore/u-boot.lds b/board/sysam/amcore/u-boot.lds
new file mode 100644
index 0000000..ccb770d
--- /dev/null
+++ b/board/sysam/amcore/u-boot.lds
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2011 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf530x/start.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.sdata)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end__ = . ;
+ PROVIDE (end = .);
+}
diff --git a/boards.cfg b/boards.cfg
index e4b0d44..6e9b952 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -388,6 +388,7 @@ M5271EVB m68k mcf52x2 m5271evb freesca
M5272C3 m68k mcf52x2 m5272c3 freescale
M5275EVB m68k mcf52x2 m5275evb freescale
M5282EVB m68k mcf52x2 m5282evb freescale
+amcore m68k mcf530x amcore sysam
astro_mcf5373l m68k mcf532x mcf5373l astro
M53017EVB m68k mcf532x m53017evb freescale
M5329AFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=0
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
new file mode 100644
index 0000000..c8545f8
--- /dev/null
+++ b/include/configs/amcore.h
@@ -0,0 +1,220 @@
+/*
+ * Configuation settings for the Sysam AMCORE board.
+ *
+ * Copyright (c) 2012 Angelo Dureghello <sysamfw@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _AMCORE_H
+#define _AMCORE_H
+
+/*
+ * AMCORE flash memory map
+ *
+ * As per CONFIG_SYS_SST_SECTSZ, amcore SST39VF3201B flash
+ * is organized into 1024 x 4K small secotrs (total 4MB).
+ *
+ * 0xffc00000 flash start
+ * 0xffc00000 u-boot code (128-4kB)
+ * 0xffc1f000 u-boot env (4kB)
+ * -----------------------------------------
+ * 0xffc20000 to
+ * 0xffffffff reserved for os usage
+ */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF530x /* define processor family */
+#define CONFIG_M5307 /* define processor type */
+
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , \
+ 57600, 115200 }
+
+/* autoboot delay in seconds */
+#define CONFIG_BOOTDELAY 1
+/* autoboot command */
+#define CONFIG_BOOTCOMMAND "bootm ffc20000"
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_TIMER
+#define CONFIG_CMD_DIAG
+
+#define CONFIG_SYS_PROMPT "amcore$ "
+#undef CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+/* Console I/O buff. size */
+#define CONFIG_SYS_CBSIZE 1024
+#else
+#define CONFIG_SYS_CBSIZE 256
+#endif
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+
+#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
+
+#undef CONFIG_SYS_DRAM_TEST /* default undef */
+#define CONFIG_SYS_MEMTEST_START 0x0
+#define CONFIG_SYS_MEMTEST_END 0x1000000
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+/* bypass PLL for test purpose */
+#undef CONFIG_SYS_PLL_BYPASS
+/* MCF5307 cpu run at 90MHz, set as bus clock x 2 */
+#define CONFIG_SYS_CLK 45000000
+#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size of used SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE 16 /* in MB */
+#define CONFIG_SYS_FLASH_BASE 0xffc00000
+#define CONFIG_SYS_TEXT_BASE 0xffc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+/* amcore design has flash data bytes wired swapped */
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+/* reserve 128-4KB */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN ((128-4)*1024)
+#define CONFIG_SYS_MALLOC_LEN (1*1024*1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x1000 /* Size of env. data */
+#define CONFIG_ENV_SECT_SIZE 0x1000 /* see README */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*
+ * Cache Configuration
+ *
+ * Special 8K version 3 core cache.
+ * This is a single unified instruction/data cache.
+ * sdram - single region - no masks
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+ CF_ACR_EN)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
+ CF_CACR_EC)
+
+/*
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
+/* 4MB, AA=0,V=1 C/I BIT for errata */
+#define CONFIG_SYS_CS0_MASK 0x003f0001
+/* WS=10, AA=1, PS=16bit (10) */
+#define CONFIG_SYS_CS0_CTRL 0x1980
+
+
+/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
+#define CONFIG_SYS_CS1_BASE 0x3000
+#define CONFIG_SYS_CS1_MASK 0x00070001
+#define CONFIG_SYS_CS1_CTRL 0x0100
+
+#endif /*_AMCORE_H*/
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2013-01-22 22:23 [U-Boot] [PATCH v4 2/2] amcore: add support for amcore board Angelo Dureghello
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