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From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: "André Hentschel" <nerv@dawncrow.de>
Cc: linux-arch@vger.kernel.org, will.deacon@arm.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Greg KH <gregkh@linuxfoundation.org>
Subject: Re: [PATCH] arm: Preserve TPIDRURW on context switch
Date: Wed, 6 Feb 2013 22:51:50 +0000	[thread overview]
Message-ID: <20130206225150.GL17833@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <5112DC7E.4020108@dawncrow.de>

On Wed, Feb 06, 2013 at 11:43:10PM +0100, André Hentschel wrote:
> There are more and more applications coming to WinRT, Wine could support them,
> but mostly they expect to have the thread environment block (TEB) in TPIDRURW.
> This register must be preserved per thread instead of being cleared.

I'd prefer this was done a little more sensitively to those CPUs where
loads/stores are expensive, namely:

> +
> +	@ preserve TPIDRURW register state
> +	get_tls2	r3, r4, r5
> +	str	r3, [r1, #TI_TP2_VALUE]
> +	ldr	r3, [r2, #TI_TP2_VALUE]
> +	set_tls2	r3, r4, r5

those two loads/stores get omitted from the thread switching if the CPU
doesn't support it.  Do you think that's something you could do?

WARNING: multiple messages have this Message-ID (diff)
From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm: Preserve TPIDRURW on context switch
Date: Wed, 6 Feb 2013 22:51:50 +0000	[thread overview]
Message-ID: <20130206225150.GL17833@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <5112DC7E.4020108@dawncrow.de>

On Wed, Feb 06, 2013 at 11:43:10PM +0100, Andr? Hentschel wrote:
> There are more and more applications coming to WinRT, Wine could support them,
> but mostly they expect to have the thread environment block (TEB) in TPIDRURW.
> This register must be preserved per thread instead of being cleared.

I'd prefer this was done a little more sensitively to those CPUs where
loads/stores are expensive, namely:

> +
> +	@ preserve TPIDRURW register state
> +	get_tls2	r3, r4, r5
> +	str	r3, [r1, #TI_TP2_VALUE]
> +	ldr	r3, [r2, #TI_TP2_VALUE]
> +	set_tls2	r3, r4, r5

those two loads/stores get omitted from the thread switching if the CPU
doesn't support it.  Do you think that's something you could do?

  reply	other threads:[~2013-02-06 22:55 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-02-06 22:43 [PATCH] arm: Preserve TPIDRURW on context switch André Hentschel
2013-02-06 22:43 ` André Hentschel
2013-02-06 22:51 ` Russell King - ARM Linux [this message]
2013-02-06 22:51   ` Russell King - ARM Linux
2013-02-06 23:01   ` André Hentschel
2013-02-06 23:01     ` André Hentschel
2013-02-08 15:48     ` Will Deacon
2013-02-08 15:48       ` Will Deacon
2013-02-08 15:48       ` Will Deacon
2013-02-09 16:44       ` André Hentschel
2013-02-09 16:44         ` André Hentschel
2013-02-09 16:44         ` André Hentschel
2013-02-12 14:02       ` André Hentschel
2013-02-12 14:02         ` André Hentschel
2013-02-12 14:02         ` André Hentschel
2013-02-12 14:09         ` Will Deacon
2013-02-12 14:09           ` Will Deacon
2013-02-12 14:09           ` Will Deacon
2013-02-12 14:14           ` André Hentschel
2013-02-12 14:14             ` André Hentschel
2013-02-12 14:14             ` André Hentschel
2013-02-12 15:02           ` Matthieu CASTET
2013-02-12 15:02             ` Matthieu CASTET
2013-02-20 19:34             ` André Hentschel
2013-02-20 19:34               ` André Hentschel
2013-02-20 19:34               ` André Hentschel
2013-02-21 10:33               ` Will Deacon
2013-02-21 10:33                 ` Will Deacon
2013-02-21 10:33                 ` Will Deacon

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