[PATCH] clk: tegra: Implement locking for super clock

[PATCH] clk: tegra: Implement locking for super clock

[Peter De Schrijver]

Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-super.c |   18 +++++++++++++++---
 1 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 7ad48a8..2fd924d 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
 {
 	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
 	u32 val, state;
+	int err = 0;
 	u8 parent_index, shift;
+	unsigned long flags = 0;
+
+	if (mux->lock)
+		spin_lock_irqsave(mux->lock, flags);
 
 	val = readl_relaxed(mux->reg);
 	state = val & SUPER_STATE_MASK;
@@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
 					       (index == mux->pllx_index))) {
 		parent_index = clk_super_get_parent(hw);
 		if ((parent_index == mux->div2_index) ||
-		    (parent_index == mux->pllx_index))
-			return -EINVAL;
+		    (parent_index == mux->pllx_index)) {
+			err = -EINVAL;
+			goto out;
+		}
 
 		val ^= SUPER_LP_DIV2_BYPASS;
 		writel_relaxed(val, mux->reg);
@@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
 
 	writel_relaxed(val, mux->reg);
 	udelay(2);
-	return 0;
+
+out:
+	if (mux->lock)
+		spin_unlock_irqrestore(mux->lock, flags);
+
+	return err;
 }
 
 const struct clk_ops tegra_clk_super_ops = {
-- 
1.7.7.rc0.72.g4b5ea.dirty

Re: [PATCH] clk: tegra: Implement locking for super clock

[Mike Turquette]

Quoting Peter De Schrijver (2013-02-07 08:24:14)
> Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
> actually used by the code. Fixed with this patch.
> 
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/clk-super.c |   18 +++++++++++++++---
>  1 files changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
> index 7ad48a8..2fd924d 100644
> --- a/drivers/clk/tegra/clk-super.c
> +++ b/drivers/clk/tegra/clk-super.c
> @@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
>  {
>         struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
>         u32 val, state;
> +       int err = 0;
>         u8 parent_index, shift;
> +       unsigned long flags = 0;

I don't think initializing flags to zero is necessary but it is not a
big deal.  Is gcc throwing a warning?  Otherwise:

Acked-by: Mike Turquette <mturquette@linaro.org>

Regards,
Mike

Re: [PATCH] clk: tegra: Implement locking for super clock

[Stephen Warren]

On 02/07/2013 11:57 AM, Mike Turquette wrote:
> Quoting Peter De Schrijver (2013-02-07 08:24:14)
>> Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
>> actually used by the code. Fixed with this patch.
>>
>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>> ---
>>  drivers/clk/tegra/clk-super.c |   18 +++++++++++++++---
>>  1 files changed, 15 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
>> index 7ad48a8..2fd924d 100644
>> --- a/drivers/clk/tegra/clk-super.c
>> +++ b/drivers/clk/tegra/clk-super.c
>> @@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
>>  {
>>         struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
>>         u32 val, state;
>> +       int err = 0;
>>         u8 parent_index, shift;
>> +       unsigned long flags = 0;
> 
> I don't think initializing flags to zero is necessary but it is not a
> big deal.  Is gcc throwing a warning?  Otherwise:
> 
> Acked-by: Mike Turquette <mturquette@linaro.org>

I've applied this to Tegra's for-3.9/soc-ccf-fixes branch. If you want
to repost given Mike's comments, I can take an updated version.

Re: [PATCH] clk: tegra: Implement locking for super clock

[Peter De Schrijver]

On Thu, Feb 07, 2013 at 07:57:42PM +0100, Mike Turquette wrote:
> Quoting Peter De Schrijver (2013-02-07 08:24:14)
> > Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
> > actually used by the code. Fixed with this patch.
> > 
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > ---
> >  drivers/clk/tegra/clk-super.c |   18 +++++++++++++++---
> >  1 files changed, 15 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
> > index 7ad48a8..2fd924d 100644
> > --- a/drivers/clk/tegra/clk-super.c
> > +++ b/drivers/clk/tegra/clk-super.c
> > @@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
> >  {
> >         struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
> >         u32 val, state;
> > +       int err = 0;
> >         u8 parent_index, shift;
> > +       unsigned long flags = 0;
> 
> I don't think initializing flags to zero is necessary but it is not a
> big deal.  Is gcc throwing a warning?  Otherwise:
> 

Yes. gcc throws a warning if it's not initialized.

Cheers,

Peter.

Re: [PATCH] clk: tegra: Implement locking for super clock

[Prashant Gaikwad]

On Thursday 07 February 2013 09:54 PM, Peter De Schrijver wrote:
> Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
> actually used by the code. Fixed with this patch.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>

Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>

> ---
>   drivers/clk/tegra/clk-super.c |   18 +++++++++++++++---
>   1 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
> index 7ad48a8..2fd924d 100644
> --- a/drivers/clk/tegra/clk-super.c
> +++ b/drivers/clk/tegra/clk-super.c
> @@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
>   {
>   	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
>   	u32 val, state;
> +	int err = 0;
>   	u8 parent_index, shift;
> +	unsigned long flags = 0;
> +
> +	if (mux->lock)
> +		spin_lock_irqsave(mux->lock, flags);
>   
>   	val = readl_relaxed(mux->reg);
>   	state = val & SUPER_STATE_MASK;
> @@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
>   					       (index == mux->pllx_index))) {
>   		parent_index = clk_super_get_parent(hw);
>   		if ((parent_index == mux->div2_index) ||
> -		    (parent_index == mux->pllx_index))
> -			return -EINVAL;
> +		    (parent_index == mux->pllx_index)) {
> +			err = -EINVAL;
> +			goto out;
> +		}
>   
>   		val ^= SUPER_LP_DIV2_BYPASS;
>   		writel_relaxed(val, mux->reg);
> @@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
>   
>   	writel_relaxed(val, mux->reg);
>   	udelay(2);
> -	return 0;
> +
> +out:
> +	if (mux->lock)
> +		spin_unlock_irqrestore(mux->lock, flags);
> +
> +	return err;
>   }
>   
>   const struct clk_ops tegra_clk_super_ops = {