[RFC v3] Better BE support for ARM

[RFC v3] Better BE support for ARM

[Ben Dooks]

This is a smaller version of the previous series that adds some fixes
for ARM big endian (BE8) mode on some of the latest ARMv7 systems as
well as fix a few issues that where found whilst doing this.

The new series should be less intrusive, as we alter less and use an
assembly macro to remove anything we do not need if we are not in BE8
mode. If it was not for secondary CPU initialisations and resume paths
we could do this with a pre-boot shim for loading from LE boot loaders.x

Since the issue of the ATAGS endian-ness is still in discussion, this
has been removed from the series. If the system was booted from an LE
enviromnent which uses FDT, then this patch set should work. The ATAGS
code will be posted as a separate series.

The fixes for ASID allocation when big endian has already been sent to
the patch system.

[PATCH 1/9] ARM: fix ARCH_IXP4xx usage of ARCH_SUPPORTS_BIG_ENDIAN

[Ben Dooks]

The Kconfig for arch/arm/mach-ixp4xx has a local definition
of ARCH_SUPPORTS_BIG_ENDIAN which could be used elsewhere.
This means that if IXP4xx is selected and this symbol is
selected eleswhere then an warning is produced.

Clean the following error up by making the symbol be
selected by the main ARCH_IXP4XX definition and have a
common definition in arch/arm/mm/Kconfig

warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX)
warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX)
---
 arch/arm/Kconfig             |    1 +
 arch/arm/mach-ixp4xx/Kconfig |    4 ----
 arch/arm/mm/Kconfig          |    6 ++++++
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 67874b8..d3f6c4f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -517,6 +517,7 @@ config ARCH_IXP4XX
 	bool "IXP4xx-based"
 	depends on MMU
 	select ARCH_HAS_DMA_SET_COHERENT_MASK
+	select ARCH_SUPPORTS_BIG_ENDIAN
 	select ARCH_REQUIRE_GPIOLIB
 	select CLKSRC_MMIO
 	select CPU_XSCALE
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 73a2d90..72de05f 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -1,9 +1,5 @@
 if ARCH_IXP4XX
 
-config ARCH_SUPPORTS_BIG_ENDIAN
-	bool
-	default y
-
 menu "Intel IXP4xx Implementation Options"
 
 comment "IXP4xx Platforms"
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 3fd629d..85cefb5 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -895,3 +895,9 @@ config ARCH_HAS_BARRIERS
 	help
 	  This option allows the use of custom mandatory barriers
 	  included via the mach/barriers.h file.
+
+config ARCH_SUPPORTS_BIG_ENDIAN
+	bool
+	help
+	  This option specifies the architecture can support big endian
+	  operation.
-- 
1.7.10.4

[PATCH 2/9] ARM: fixup_pv_table bug when CPU_ENDIAN_BE8

[Ben Dooks]

The fixup_pv_table assumes that the instructions are in the same
endian configuration as the data, but when the CPU is running in
BE8 the instructions stay in little-endian format.

Make sure if CONFIG_CPU_ENDIAN_BE8 is set that we do all the
alterations to the instructions taking in to account the LDR/STR
will be swapping the data endian-ness.

Since the code is only modifying a byte, we avoid dual-swapping
the data, and just change the bits we clear and ORR in.

Note, not tested against an actual bug, it looked wrong.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/kernel/head.S |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 486a15a..cc15384 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -576,8 +576,14 @@ __fixup_a_pv_table:
 #else
 	b	2f
 1:	ldr	ip, [r7, r3]
+#ifdef CONFIG_CPU_ENDIAN_BE8
+	@ in BE8, we load data in BE, but instructions still in LE
+	bic	ip, ip, #0xff000000
+	orr	ip, ip, r6, lsl#24
+#else
 	bic	ip, ip, #0x000000ff
 	orr	ip, ip, r6	@ mask in offset bits 31-24
+#endif
 	str	ip, [r7, r3]
 2:	cmp	r4, r5
 	ldrcc	r7, [r4], #4	@ use branch for delay slot
-- 
1.7.10.4

[PATCH 3/9] ARM: asm: Add ARM_BE8() assembly helper

[Ben Dooks]

Add ARM_BE8() helper to wrap any code conditional on being
compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert
existing places where this is to use it.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

Conflicts:
	arch/arm/include/asm/assembler.h
---
 arch/arm/boot/compressed/head.S  |    8 ++------
 arch/arm/include/asm/assembler.h |    7 +++++++
 arch/arm/kernel/entry-armv.S     |    5 ++---
 arch/arm/kernel/entry-common.S   |    4 +---
 arch/arm/mm/abort-ev6.S          |    5 ++---
 arch/arm/mm/proc-v6.S            |    4 +---
 arch/arm/mm/proc-v7.S            |    4 +---
 7 files changed, 16 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fe4d9c3..15ebdd6 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -678,9 +678,7 @@ __armv4_mmu_cache_on:
 		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
 		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
 		orr	r0, r0, #0x0030
-#ifdef CONFIG_CPU_ENDIAN_BE8
-		orr	r0, r0, #1 << 25	@ big-endian page tables
-#endif
+ ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
 		bl	__common_mmu_cache_on
 		mov	r0, #0
 		mcr	p15, 0, r0, c8, c7, 0	@ flush I,D TLBs
@@ -707,9 +705,7 @@ __armv7_mmu_cache_on:
 		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)
 						@ (needed for ARM1176)
 #ifdef CONFIG_MMU
-#ifdef CONFIG_CPU_ENDIAN_BE8
-		orr	r0, r0, #1 << 25	@ big-endian page tables
-#endif
+ ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
 		mrcne   p15, 0, r6, c2, c0, 2   @ read ttb control reg
 		orrne	r0, r0, #1		@ MMU enabled
 		movne	r1, #0xfffffffd		@ domain 0 = client
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index eb87200..dbcbd08 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -53,6 +53,13 @@
 #define put_byte_3      lsl #0
 #endif
 
+/* Select code for any configuration running in BE8 mode */
+#ifdef CONFIG_ARM_CPU_ENDIAN_BE8
+#define ARM_BE8(code...) code
+#else
+#define ARM_BE8(code...)
+#endif
+
 /*
  * Data preload for architectures that support it
  */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..291d295 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -457,9 +457,8 @@ __und_usr:
 	bne	__und_usr_thumb
 	sub	r4, r2, #4			@ ARM instr@LR - 4
 1:	ldrt	r0, [r4]
-#ifdef CONFIG_CPU_ENDIAN_BE8
-	rev	r0, r0				@ little endian instruction
-#endif
+ ARM_BE8(rev	r0, r0)				@ little endian instruction
+
 	@ r0 = 32-bit ARM instruction which caused the exception
 	@ r2 = PC value for the following instruction (:= regs->ARM_pc)
 	@ r4 = PC value for the faulting instruction
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index a6c301e..d5988afc 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -368,9 +368,7 @@ ENTRY(vector_swi)
 #else
 	ldr	r10, [lr, #-4]			@ get SWI instruction
 #endif
-#ifdef CONFIG_CPU_ENDIAN_BE8
-	rev	r10, r10			@ little endian instruction
-#endif
+ ARM_BE8(rev	r10, r10)			@ little endian instruction
 
 #elif defined(CONFIG_AEABI)
 
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 8074199..3815a82 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -38,9 +38,8 @@ ENTRY(v6_early_abort)
 	bne	do_DataAbort
 	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR
 	ldr	r3, [r4]			@ read aborted ARM instruction
-#ifdef CONFIG_CPU_ENDIAN_BE8
-	rev	r3, r3
-#endif
+ ARM_BE8(rev	r3, r3)
+
 	do_ldrd_abort tmp=ip, insn=r3
 	tst	r3, #1 << 20			@ L = 0 -> write
 	orreq	r1, r1, #1 << 11		@ yes.
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index bcaaa8d..2f060fa 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -220,9 +220,7 @@ __v6_setup:
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
 	ldmia	r5, {r5, r6}
-#ifdef CONFIG_CPU_ENDIAN_BE8
-	orr	r6, r6, #1 << 25		@ big-endian page tables
-#endif
+ ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
 	mrc	p15, 0, r0, c1, c0, 0		@ read control register
 	bic	r0, r0, r5			@ clear bits them
 	orr	r0, r0, r6			@ set them
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a3c015..d17996b 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -328,9 +328,7 @@ __v7_setup:
 #endif
 	adr	r5, v7_crval
 	ldmia	r5, {r5, r6}
-#ifdef CONFIG_CPU_ENDIAN_BE8
-	orr	r6, r6, #1 << 25		@ big-endian page tables
-#endif
+ ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
 #ifdef CONFIG_SWP_EMULATE
 	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
 	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
-- 
1.7.10.4

[PATCH 4/9] ARM: set BE8 if LE in head code

[Ben Dooks]

If we are booting in LE and compiled for BE8, then add code to
set the state to bE8. Since the instruction stream is always LE,
we do not need to do anything special to the instruction.

Also ensure that the secondary processors are started in the same mode.

Note, we do add about 20 bytes to the kernel image, but it seems easier
to do this than adding another configuration to change.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/compressed/head.S |    1 +
 arch/arm/kernel/head.S          |    4 ++++
 arch/arm/mm/proc-v7.S           |    1 +
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 15ebdd6..06b0f15 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -134,6 +134,7 @@ start:
 		.word	_edata			@ zImage end address
  THUMB(		.thumb			)
 1:
+ ARM_BE8(	setend	be )			@ go BE8 if LE, no-op if BE8
 		mrs	r9, cpsr
 #ifdef CONFIG_ARM_VIRT_EXT
 		bl	__hyp_stub_install	@ get into SVC mode, reversibly
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index cc15384..a112994 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -77,6 +77,7 @@
 
 	__HEAD
 ENTRY(stext)
+ ARM_BE8(setend	be )			@ ensure we are in BE8 mode
 
  THUMB(	adr	r9, BSYM(1f)	)	@ Kernel is always entered in ARM.
  THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel,
@@ -333,6 +334,9 @@ ENTRY(secondary_startup)
 	 * the processor type - there is no need to check the machine type
 	 * as it has already been validated by the primary processor.
 	 */
+
+ ARM_BE8(setend	be)				@ if system starts LE, go BE8
+
 #ifdef CONFIG_ARM_VIRT_EXT
 	bl	__hyp_stub_install_secondary
 #endif
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index d17996b..28bb018 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -109,6 +109,7 @@ ENTRY(cpu_v7_do_suspend)
 ENDPROC(cpu_v7_do_suspend)
 
 ENTRY(cpu_v7_do_resume)
+ ARM_BE8(setend	be )			@ ensure we are BE8
 	mov	ip, #0
 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
-- 
1.7.10.4

[PATCH 5/9] ARM: pl01x debug code endian fix

[Ben Dooks]

The PL01X debug code needs to take into account which endian mode the
processor is running in. If it is big-endian, ensure the data is swapped
appropriately.

Note, we could do this slightly more efficiently if we have an macro to
do the necessary swap for the bits used by test.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/include/asm/hardware/debug-pl01x.S |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/hardware/debug-pl01x.S b/arch/arm/include/asm/hardware/debug-pl01x.S
index f9fd083..6489d1f 100644
--- a/arch/arm/include/asm/hardware/debug-pl01x.S
+++ b/arch/arm/include/asm/hardware/debug-pl01x.S
@@ -18,12 +18,14 @@
 
 		.macro	waituart,rd,rx
 1001:		ldr	\rd, [\rx, #UART01x_FR]
+ ARM_BE8(	rev	\rd, \rd )
 		tst	\rd, #UART01x_FR_TXFF
 		bne	1001b
 		.endm
 
 		.macro	busyuart,rd,rx
 1001:		ldr	\rd, [\rx, #UART01x_FR]
+ ARM_BE8(	rev	\rd, \rd )
 		tst	\rd, #UART01x_FR_BUSY
 		bne	1001b
 		.endm
-- 
1.7.10.4

[PATCH 6/9] ARM: twd: data endian fix

[Ben Dooks]

Ensure the twd driver uses the correct calls to access the hardware
to ensure that we do not end up with data in the wrong endian format.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/kernel/smp_twd.c |   24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 49f335d..3756f42 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -46,7 +46,7 @@ static void twd_set_mode(enum clock_event_mode mode,
 	case CLOCK_EVT_MODE_PERIODIC:
 		ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
 			| TWD_TIMER_CONTROL_PERIODIC;
-		__raw_writel(DIV_ROUND_CLOSEST(twd_timer_rate, HZ),
+		writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ),
 			twd_base + TWD_TIMER_LOAD);
 		break;
 	case CLOCK_EVT_MODE_ONESHOT:
@@ -59,18 +59,18 @@ static void twd_set_mode(enum clock_event_mode mode,
 		ctrl = 0;
 	}
 
-	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
+	writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
 }
 
 static int twd_set_next_event(unsigned long evt,
 			struct clock_event_device *unused)
 {
-	unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
+	unsigned long ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
 
 	ctrl |= TWD_TIMER_CONTROL_ENABLE;
 
-	__raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
-	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
+	writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER);
+	writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
 
 	return 0;
 }
@@ -83,8 +83,8 @@ static int twd_set_next_event(unsigned long evt,
  */
 static int twd_timer_ack(void)
 {
-	if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
-		__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
+	if (readl_relaxed(twd_base + TWD_TIMER_INTSTAT)) {
+		writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
 		return 1;
 	}
 
@@ -210,15 +210,15 @@ static void __cpuinit twd_calibrate_rate(void)
 		waitjiffies += 5;
 
 				 /* enable, no interrupt or reload */
-		__raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
+		writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL);
 
 				 /* maximum value */
-		__raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
+		writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
 
 		while (get_jiffies_64() < waitjiffies)
 			udelay(10);
 
-		count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
+		count = readl_relaxed(twd_base + TWD_TIMER_COUNTER);
 
 		twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
 
@@ -273,7 +273,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
 	 * bother with the below.
 	 */
 	if (per_cpu(percpu_setup_called, cpu)) {
-		__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
+		writel_relaxed(0, twd_base + TWD_TIMER_CONTROL);
 		clockevents_register_device(*__this_cpu_ptr(twd_evt));
 		enable_percpu_irq(clk->irq, 0);
 		return 0;
@@ -305,7 +305,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
 	 * The following is done once per CPU the first time .setup() is
 	 * called.
 	 */
-	__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
+	writel_relaxed(0, twd_base + TWD_TIMER_CONTROL);
 
 	clk->name = "local_timer";
 	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
-- 
1.7.10.4

[PATCH 7/9] ARM: smp_scu: data endian fixes

[Ben Dooks]

The smp_scu driver needs to use the relaxed readl/write accessors
to avoid any issues with the endian mode the processor core is in.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/kernel/smp_scu.c |   14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 45eac87..0fcd0ce 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -28,7 +28,7 @@
  */
 unsigned int __init scu_get_core_count(void __iomem *scu_base)
 {
-	unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG);
+	unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG);
 	return (ncores & 0x03) + 1;
 }
 
@@ -42,19 +42,19 @@ void scu_enable(void __iomem *scu_base)
 #ifdef CONFIG_ARM_ERRATA_764369
 	/* Cortex-A9 only */
 	if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
-		scu_ctrl = __raw_readl(scu_base + 0x30);
+		scu_ctrl = readl_relaxed(scu_base + 0x30);
 		if (!(scu_ctrl & 1))
-			__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
+			writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
 	}
 #endif
 
-	scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
+	scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
 	/* already enabled? */
 	if (scu_ctrl & 1)
 		return;
 
 	scu_ctrl |= 1;
-	__raw_writel(scu_ctrl, scu_base + SCU_CTRL);
+	writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
 
 	/*
 	 * Ensure that the data accessed by CPU0 before the SCU was
@@ -80,9 +80,9 @@ int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 	if (mode > 3 || mode == 1 || cpu > 3)
 		return -EINVAL;
 
-	val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
+	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
 	val |= mode;
-	__raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
+	writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
 
 	return 0;
 }
-- 
1.7.10.4

[PATCH 8/9] highbank: enable big-endian

[Ben Dooks]

Apart from a xgmac driver issue, the highbank seems to work correctly in
big-endian mode. Allow the selection of big-endian in the system.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/mach-highbank/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 551c97e..9373571 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -13,3 +13,4 @@ config ARCH_HIGHBANK
 	select HAVE_SMP
 	select SPARSE_IRQ
 	select USE_OF
+	select ARCH_SUPPORTS_BIG_ENDIAN
-- 
1.7.10.4

[PATCH 9/9] mvebu: support running big-endian

[Ben Dooks]

Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/mach-mvebu/Kconfig        |    1 +
 arch/arm/mach-mvebu/coherency_ll.S |    3 +++
 arch/arm/mach-mvebu/headsmp.S      |    2 ++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 440b13e..2afa026 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,5 +1,6 @@
 config ARCH_MVEBU
 	bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+	select ARCH_SUPPORTS_BIG_ENDIAN
 	select CLKSRC_MMIO
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 53e8391..bc2d70d 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -20,6 +20,8 @@
 #define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
 #define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
 
+#include <asm/assembler.h>
+
 	.text
 /*
  * r0: Coherency fabric base register address
@@ -29,6 +31,7 @@ ENTRY(ll_set_cpu_coherent)
 	/* Create bit by cpu index */
 	mov	r3, #(1 << 24)
 	lsl	r1, r3, r1
+ARM_BE8(rev	r1, r1)
 
 	/* Add CPU to SMP group - Atomic */
 	add	r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ed..3b77eac 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -36,6 +36,8 @@
  */
 ENTRY(armada_xp_secondary_startup)
 
+ ARM_BE8(setend	be )			@ go BE8 if booted LE
+
 	/* Read CPU id */
 	mrc     p15, 0, r1, c0, c0, 5
 	and     r1, r1, #0xF
-- 
1.7.10.4

[PATCH 3/9] ARM: asm: Add ARM_BE8() assembly helper

[Nicolas Pitre]

On Wed, 13 Feb 2013, Ben Dooks wrote:

> Add ARM_BE8() helper to wrap any code conditional on being
> compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert
> existing places where this is to use it.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

Acked-by: Nicolas Pitre <nico@linaro.org>

> 
> Conflicts:
> 	arch/arm/include/asm/assembler.h

Don't forget to get rid of the above in your commit message.

> ---
>  arch/arm/boot/compressed/head.S  |    8 ++------
>  arch/arm/include/asm/assembler.h |    7 +++++++
>  arch/arm/kernel/entry-armv.S     |    5 ++---
>  arch/arm/kernel/entry-common.S   |    4 +---
>  arch/arm/mm/abort-ev6.S          |    5 ++---
>  arch/arm/mm/proc-v6.S            |    4 +---
>  arch/arm/mm/proc-v7.S            |    4 +---
>  7 files changed, 16 insertions(+), 21 deletions(-)
> 
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index fe4d9c3..15ebdd6 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -678,9 +678,7 @@ __armv4_mmu_cache_on:
>  		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
>  		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
>  		orr	r0, r0, #0x0030
> -#ifdef CONFIG_CPU_ENDIAN_BE8
> -		orr	r0, r0, #1 << 25	@ big-endian page tables
> -#endif
> + ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
>  		bl	__common_mmu_cache_on
>  		mov	r0, #0
>  		mcr	p15, 0, r0, c8, c7, 0	@ flush I,D TLBs
> @@ -707,9 +705,7 @@ __armv7_mmu_cache_on:
>  		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)
>  						@ (needed for ARM1176)
>  #ifdef CONFIG_MMU
> -#ifdef CONFIG_CPU_ENDIAN_BE8
> -		orr	r0, r0, #1 << 25	@ big-endian page tables
> -#endif
> + ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
>  		mrcne   p15, 0, r6, c2, c0, 2   @ read ttb control reg
>  		orrne	r0, r0, #1		@ MMU enabled
>  		movne	r1, #0xfffffffd		@ domain 0 = client
> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> index eb87200..dbcbd08 100644
> --- a/arch/arm/include/asm/assembler.h
> +++ b/arch/arm/include/asm/assembler.h
> @@ -53,6 +53,13 @@
>  #define put_byte_3      lsl #0
>  #endif
>  
> +/* Select code for any configuration running in BE8 mode */
> +#ifdef CONFIG_ARM_CPU_ENDIAN_BE8
> +#define ARM_BE8(code...) code
> +#else
> +#define ARM_BE8(code...)
> +#endif
> +
>  /*
>   * Data preload for architectures that support it
>   */
> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index 0f82098..291d295 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -457,9 +457,8 @@ __und_usr:
>  	bne	__und_usr_thumb
>  	sub	r4, r2, #4			@ ARM instr at LR - 4
>  1:	ldrt	r0, [r4]
> -#ifdef CONFIG_CPU_ENDIAN_BE8
> -	rev	r0, r0				@ little endian instruction
> -#endif
> + ARM_BE8(rev	r0, r0)				@ little endian instruction
> +
>  	@ r0 = 32-bit ARM instruction which caused the exception
>  	@ r2 = PC value for the following instruction (:= regs->ARM_pc)
>  	@ r4 = PC value for the faulting instruction
> diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
> index a6c301e..d5988afc 100644
> --- a/arch/arm/kernel/entry-common.S
> +++ b/arch/arm/kernel/entry-common.S
> @@ -368,9 +368,7 @@ ENTRY(vector_swi)
>  #else
>  	ldr	r10, [lr, #-4]			@ get SWI instruction
>  #endif
> -#ifdef CONFIG_CPU_ENDIAN_BE8
> -	rev	r10, r10			@ little endian instruction
> -#endif
> + ARM_BE8(rev	r10, r10)			@ little endian instruction
>  
>  #elif defined(CONFIG_AEABI)
>  
> diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
> index 8074199..3815a82 100644
> --- a/arch/arm/mm/abort-ev6.S
> +++ b/arch/arm/mm/abort-ev6.S
> @@ -38,9 +38,8 @@ ENTRY(v6_early_abort)
>  	bne	do_DataAbort
>  	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR
>  	ldr	r3, [r4]			@ read aborted ARM instruction
> -#ifdef CONFIG_CPU_ENDIAN_BE8
> -	rev	r3, r3
> -#endif
> + ARM_BE8(rev	r3, r3)
> +
>  	do_ldrd_abort tmp=ip, insn=r3
>  	tst	r3, #1 << 20			@ L = 0 -> write
>  	orreq	r1, r1, #1 << 11		@ yes.
> diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
> index bcaaa8d..2f060fa 100644
> --- a/arch/arm/mm/proc-v6.S
> +++ b/arch/arm/mm/proc-v6.S
> @@ -220,9 +220,7 @@ __v6_setup:
>  #endif /* CONFIG_MMU */
>  	adr	r5, v6_crval
>  	ldmia	r5, {r5, r6}
> -#ifdef CONFIG_CPU_ENDIAN_BE8
> -	orr	r6, r6, #1 << 25		@ big-endian page tables
> -#endif
> + ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
>  	mrc	p15, 0, r0, c1, c0, 0		@ read control register
>  	bic	r0, r0, r5			@ clear bits them
>  	orr	r0, r0, r6			@ set them
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 3a3c015..d17996b 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -328,9 +328,7 @@ __v7_setup:
>  #endif
>  	adr	r5, v7_crval
>  	ldmia	r5, {r5, r6}
> -#ifdef CONFIG_CPU_ENDIAN_BE8
> -	orr	r6, r6, #1 << 25		@ big-endian page tables
> -#endif
> + ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
>  #ifdef CONFIG_SWP_EMULATE
>  	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
>  	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
> -- 
> 1.7.10.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

[PATCH 4/9] ARM: set BE8 if LE in head code

[Nicolas Pitre]

On Wed, 13 Feb 2013, Ben Dooks wrote:

> If we are booting in LE and compiled for BE8, then add code to
> set the state to bE8. Since the instruction stream is always LE,
> we do not need to do anything special to the instruction.
> 
> Also ensure that the secondary processors are started in the same mode.
> 
> Note, we do add about 20 bytes to the kernel image, but it seems easier
> to do this than adding another configuration to change.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

Comment below.

> ---
>  arch/arm/boot/compressed/head.S |    1 +
>  arch/arm/kernel/head.S          |    4 ++++
>  arch/arm/mm/proc-v7.S           |    1 +
>  3 files changed, 6 insertions(+)
> 
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 15ebdd6..06b0f15 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -134,6 +134,7 @@ start:
>  		.word	_edata			@ zImage end address
>   THUMB(		.thumb			)
>  1:
> + ARM_BE8(	setend	be )			@ go BE8 if LE, no-op if BE8
>  		mrs	r9, cpsr
>  #ifdef CONFIG_ARM_VIRT_EXT
>  		bl	__hyp_stub_install	@ get into SVC mode, reversibly
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index cc15384..a112994 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -77,6 +77,7 @@
>  
>  	__HEAD
>  ENTRY(stext)
> + ARM_BE8(setend	be )			@ ensure we are in BE8 mode
>  
>   THUMB(	adr	r9, BSYM(1f)	)	@ Kernel is always entered in ARM.
>   THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel,
> @@ -333,6 +334,9 @@ ENTRY(secondary_startup)
>  	 * the processor type - there is no need to check the machine type
>  	 * as it has already been validated by the primary processor.
>  	 */
> +
> + ARM_BE8(setend	be)				@ if system starts LE, go BE8
> +
>  #ifdef CONFIG_ARM_VIRT_EXT
>  	bl	__hyp_stub_install_secondary
>  #endif
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index d17996b..28bb018 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -109,6 +109,7 @@ ENTRY(cpu_v7_do_suspend)
>  ENDPROC(cpu_v7_do_suspend)
>  
>  ENTRY(cpu_v7_do_resume)
> + ARM_BE8(setend	be )			@ ensure we are BE8

This is wrong.  You want to insert this in 
arch/arm/kernel/sleep.S:cpu_resume which is the main entry point for 
resuming.


Nicolas

[RFC v3] Better BE support for ARM

[Ben Dooks]

On 13/02/13 10:55, Ben Dooks wrote:
> This is a smaller version of the previous series that adds some fixes
> for ARM big endian (BE8) mode on some of the latest ARMv7 systems as
> well as fix a few issues that where found whilst doing this.
>
> The new series should be less intrusive, as we alter less and use an
> assembly macro to remove anything we do not need if we are not in BE8
> mode. If it was not for secondary CPU initialisations and resume paths
> we could do this with a pre-boot shim for loading from LE boot loaders.x
>
> Since the issue of the ATAGS endian-ness is still in discussion, this
> has been removed from the series. If the system was booted from an LE
> enviromnent which uses FDT, then this patch set should work. The ATAGS
> code will be posted as a separate series.
>
> The fixes for ASID allocation when big endian has already been sent to
> the patch system.

Russell, any objections to get this pulled for 3.9-rc series?

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

[PATCH 1/9] ARM: fix ARCH_IXP4xx usage of ARCH_SUPPORTS_BIG_ENDIAN

[Krzysztof Halasa]

Ben Dooks <ben.dooks@codethink.co.uk> writes:

> The Kconfig for arch/arm/mach-ixp4xx has a local definition
> of ARCH_SUPPORTS_BIG_ENDIAN which could be used elsewhere.
> This means that if IXP4xx is selected and this symbol is
> selected eleswhere then an warning is produced.
>
> Clean the following error up by making the symbol be
> selected by the main ARCH_IXP4XX definition and have a
> common definition in arch/arm/mm/Kconfig
>
> warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX)
> warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX)

I don't know if the above would happen but as I think this isn't
IXP4xx-specific it should be defined by IXP4xx. At least ARM,
if not a "global" (we have other big endian ports).

The patch looks good enough to me.

>  arch/arm/Kconfig             |    1 +
>  arch/arm/mach-ixp4xx/Kconfig |    4 ----
>  arch/arm/mm/Kconfig          |    6 ++++++
>  3 files changed, 7 insertions(+), 4 deletions(-)
-- 
Krzysztof Halasa

[RFC v3] Better BE support for ARM

[Dave Martin]

On Wed, Feb 13, 2013 at 10:55:18AM +0000, Ben Dooks wrote:
> This is a smaller version of the previous series that adds some fixes
> for ARM big endian (BE8) mode on some of the latest ARMv7 systems as
> well as fix a few issues that where found whilst doing this.
> 
> The new series should be less intrusive, as we alter less and use an
> assembly macro to remove anything we do not need if we are not in BE8
> mode. If it was not for secondary CPU initialisations and resume paths
> we could do this with a pre-boot shim for loading from LE boot loaders.x
> 
> Since the issue of the ATAGS endian-ness is still in discussion, this
> has been removed from the series. If the system was booted from an LE
> enviromnent which uses FDT, then this patch set should work. The ATAGS
> code will be posted as a separate series.
> 
> The fixes for ASID allocation when big endian has already been sent to
> the patch system.

You may also want to take a look at the following series -- I don't remember
how mature this stuff was, but it doesn't look like it every got merged.
It could make sense to combine some parts of it with your series, unless
the author wants to pick it up again.

http://lists.infradead.org/pipermail/linux-arm-kernel/2011-December/075728.html

This contains draft fixes for some things we don't yet have, like non-broken
module loading.

Cheers
---Dave

[PATCH 2/9] ARM: fixup_pv_table bug when CPU_ENDIAN_BE8

[Dave Martin]

On Wed, Feb 13, 2013 at 10:55:20AM +0000, Ben Dooks wrote:
> The fixup_pv_table assumes that the instructions are in the same
> endian configuration as the data, but when the CPU is running in
> BE8 the instructions stay in little-endian format.
> 
> Make sure if CONFIG_CPU_ENDIAN_BE8 is set that we do all the
> alterations to the instructions taking in to account the LDR/STR
> will be swapping the data endian-ness.
> 
> Since the code is only modifying a byte, we avoid dual-swapping
> the data, and just change the bits we clear and ORR in.
> 
> Note, not tested against an actual bug, it looked wrong.

This looks reasonable, but the Thumb case code would need a similar fix.

Should we have LE()/BE8() macros etc. in assembler.h, similar to
ARM()/THUMB()?  This would help save on #ifdefs.

Cheers
---Dave

> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>  arch/arm/kernel/head.S |    6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 486a15a..cc15384 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -576,8 +576,14 @@ __fixup_a_pv_table:
>  #else
>  	b	2f
>  1:	ldr	ip, [r7, r3]
> +#ifdef CONFIG_CPU_ENDIAN_BE8
> +	@ in BE8, we load data in BE, but instructions still in LE
> +	bic	ip, ip, #0xff000000
> +	orr	ip, ip, r6, lsl#24
> +#else
>  	bic	ip, ip, #0x000000ff
>  	orr	ip, ip, r6	@ mask in offset bits 31-24
> +#endif
>  	str	ip, [r7, r3]
>  2:	cmp	r4, r5
>  	ldrcc	r7, [r4], #4	@ use branch for delay slot
> -- 
> 1.7.10.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/9] ARM: asm: Add ARM_BE8() assembly helper

[Dave Martin]

On Wed, Feb 13, 2013 at 11:27:38PM -0500, Nicolas Pitre wrote:
> On Wed, 13 Feb 2013, Ben Dooks wrote:
> 
> > Add ARM_BE8() helper to wrap any code conditional on being
> > compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert
> > existing places where this is to use it.
> > 
> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> Acked-by: Nicolas Pitre <nico@linaro.org>

Ditto comments on the previous patch.  You could also add LE().
Is the ARM_ prefix really necessary for ARM-specific assembler
macros?

If the macro name is 5 characters or fewer, then

	<space> macro( <tab> 

fits nicely in the first tab column, helping to keep the assembler
tidy, as per the ARM() and THUMB() macros.

Cheers
---Dave

> 
> > 
> > Conflicts:
> > 	arch/arm/include/asm/assembler.h
> 
> Don't forget to get rid of the above in your commit message.
> 
> > ---
> >  arch/arm/boot/compressed/head.S  |    8 ++------
> >  arch/arm/include/asm/assembler.h |    7 +++++++
> >  arch/arm/kernel/entry-armv.S     |    5 ++---
> >  arch/arm/kernel/entry-common.S   |    4 +---
> >  arch/arm/mm/abort-ev6.S          |    5 ++---
> >  arch/arm/mm/proc-v6.S            |    4 +---
> >  arch/arm/mm/proc-v7.S            |    4 +---
> >  7 files changed, 16 insertions(+), 21 deletions(-)
> > 
> > diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> > index fe4d9c3..15ebdd6 100644
> > --- a/arch/arm/boot/compressed/head.S
> > +++ b/arch/arm/boot/compressed/head.S
> > @@ -678,9 +678,7 @@ __armv4_mmu_cache_on:
> >  		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
> >  		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
> >  		orr	r0, r0, #0x0030
> > -#ifdef CONFIG_CPU_ENDIAN_BE8
> > -		orr	r0, r0, #1 << 25	@ big-endian page tables
> > -#endif
> > + ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
> >  		bl	__common_mmu_cache_on
> >  		mov	r0, #0
> >  		mcr	p15, 0, r0, c8, c7, 0	@ flush I,D TLBs
> > @@ -707,9 +705,7 @@ __armv7_mmu_cache_on:
> >  		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)
> >  						@ (needed for ARM1176)
> >  #ifdef CONFIG_MMU
> > -#ifdef CONFIG_CPU_ENDIAN_BE8
> > -		orr	r0, r0, #1 << 25	@ big-endian page tables
> > -#endif
> > + ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
> >  		mrcne   p15, 0, r6, c2, c0, 2   @ read ttb control reg
> >  		orrne	r0, r0, #1		@ MMU enabled
> >  		movne	r1, #0xfffffffd		@ domain 0 = client
> > diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> > index eb87200..dbcbd08 100644
> > --- a/arch/arm/include/asm/assembler.h
> > +++ b/arch/arm/include/asm/assembler.h
> > @@ -53,6 +53,13 @@
> >  #define put_byte_3      lsl #0
> >  #endif
> >  
> > +/* Select code for any configuration running in BE8 mode */
> > +#ifdef CONFIG_ARM_CPU_ENDIAN_BE8
> > +#define ARM_BE8(code...) code
> > +#else
> > +#define ARM_BE8(code...)
> > +#endif
> > +
> >  /*
> >   * Data preload for architectures that support it
> >   */
> > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> > index 0f82098..291d295 100644
> > --- a/arch/arm/kernel/entry-armv.S
> > +++ b/arch/arm/kernel/entry-armv.S
> > @@ -457,9 +457,8 @@ __und_usr:
> >  	bne	__und_usr_thumb
> >  	sub	r4, r2, #4			@ ARM instr at LR - 4
> >  1:	ldrt	r0, [r4]
> > -#ifdef CONFIG_CPU_ENDIAN_BE8
> > -	rev	r0, r0				@ little endian instruction
> > -#endif
> > + ARM_BE8(rev	r0, r0)				@ little endian instruction
> > +
> >  	@ r0 = 32-bit ARM instruction which caused the exception
> >  	@ r2 = PC value for the following instruction (:= regs->ARM_pc)
> >  	@ r4 = PC value for the faulting instruction
> > diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
> > index a6c301e..d5988afc 100644
> > --- a/arch/arm/kernel/entry-common.S
> > +++ b/arch/arm/kernel/entry-common.S
> > @@ -368,9 +368,7 @@ ENTRY(vector_swi)
> >  #else
> >  	ldr	r10, [lr, #-4]			@ get SWI instruction
> >  #endif
> > -#ifdef CONFIG_CPU_ENDIAN_BE8
> > -	rev	r10, r10			@ little endian instruction
> > -#endif
> > + ARM_BE8(rev	r10, r10)			@ little endian instruction
> >  
> >  #elif defined(CONFIG_AEABI)
> >  
> > diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
> > index 8074199..3815a82 100644
> > --- a/arch/arm/mm/abort-ev6.S
> > +++ b/arch/arm/mm/abort-ev6.S
> > @@ -38,9 +38,8 @@ ENTRY(v6_early_abort)
> >  	bne	do_DataAbort
> >  	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR
> >  	ldr	r3, [r4]			@ read aborted ARM instruction
> > -#ifdef CONFIG_CPU_ENDIAN_BE8
> > -	rev	r3, r3
> > -#endif
> > + ARM_BE8(rev	r3, r3)
> > +
> >  	do_ldrd_abort tmp=ip, insn=r3
> >  	tst	r3, #1 << 20			@ L = 0 -> write
> >  	orreq	r1, r1, #1 << 11		@ yes.
> > diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
> > index bcaaa8d..2f060fa 100644
> > --- a/arch/arm/mm/proc-v6.S
> > +++ b/arch/arm/mm/proc-v6.S
> > @@ -220,9 +220,7 @@ __v6_setup:
> >  #endif /* CONFIG_MMU */
> >  	adr	r5, v6_crval
> >  	ldmia	r5, {r5, r6}
> > -#ifdef CONFIG_CPU_ENDIAN_BE8
> > -	orr	r6, r6, #1 << 25		@ big-endian page tables
> > -#endif
> > + ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
> >  	mrc	p15, 0, r0, c1, c0, 0		@ read control register
> >  	bic	r0, r0, r5			@ clear bits them
> >  	orr	r0, r0, r6			@ set them
> > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > index 3a3c015..d17996b 100644
> > --- a/arch/arm/mm/proc-v7.S
> > +++ b/arch/arm/mm/proc-v7.S
> > @@ -328,9 +328,7 @@ __v7_setup:
> >  #endif
> >  	adr	r5, v7_crval
> >  	ldmia	r5, {r5, r6}
> > -#ifdef CONFIG_CPU_ENDIAN_BE8
> > -	orr	r6, r6, #1 << 25		@ big-endian page tables
> > -#endif
> > + ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
> >  #ifdef CONFIG_SWP_EMULATE
> >  	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
> >  	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
> > -- 
> > 1.7.10.4
> > 
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 
> 
> _______________________________________________
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> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 5/9] ARM: pl01x debug code endian fix

[Dave Martin]

On Wed, Feb 13, 2013 at 10:55:23AM +0000, Ben Dooks wrote:
> The PL01X debug code needs to take into account which endian mode the
> processor is running in. If it is big-endian, ensure the data is swapped
> appropriately.

Looks reasonable ... has you been able to test this?
 
> Note, we could do this slightly more efficiently if we have an macro to
> do the necessary swap for the bits used by test.

arch/arm/include/asm/opcodes.h has some swabbing macros which work in
assembler.  Would those help?  I'm wondering whether those ought to move
somewhere else, with cpu_to_mem style wrappers.  Currently, the only
wrappers there are tailored for handling opcodes, but the principle is
the same.

Cheers
---Dave

> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>  arch/arm/include/asm/hardware/debug-pl01x.S |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/include/asm/hardware/debug-pl01x.S b/arch/arm/include/asm/hardware/debug-pl01x.S
> index f9fd083..6489d1f 100644
> --- a/arch/arm/include/asm/hardware/debug-pl01x.S
> +++ b/arch/arm/include/asm/hardware/debug-pl01x.S
> @@ -18,12 +18,14 @@
>  
>  		.macro	waituart,rd,rx
>  1001:		ldr	\rd, [\rx, #UART01x_FR]
> + ARM_BE8(	rev	\rd, \rd )
>  		tst	\rd, #UART01x_FR_TXFF
>  		bne	1001b
>  		.endm
>  
>  		.macro	busyuart,rd,rx
>  1001:		ldr	\rd, [\rx, #UART01x_FR]
> + ARM_BE8(	rev	\rd, \rd )
>  		tst	\rd, #UART01x_FR_BUSY
>  		bne	1001b
>  		.endm
> -- 
> 1.7.10.4
> 
> 
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> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel