[PATCH 0/8] SIRF multiplatform support

[PATCH 0/8] SIRF multiplatform support

[Arnd Bergmann]

Here goes another one. Since the SIRF platforms are relatively new and
clean, they are easy to convert to multiplatform, so I did that and
fixed up a few other things in the process as well.

Barry, could you test these and report back if everything still works
for you?

Thomas, John, Linus: Are you ok with the irqchip/clocksource/pinctrl
changes?

Arnd Bergmann (8):
  pinctrl: sirf: convert to linear irq domain
  ARM: sirf: fix prima2 interrupt lookup
  ARM: sirf: move irq driver to drivers/irqchip
  ARM: sirf: enable sparse IRQ
  ARM: sirf: move debug-macro.S to include/debug/sirf.S
  ARM: sirf: use clocksource_of infrastructure
  ARM: sirf: enable multiplatform support
  ARM: sirf: enable support in multi_v7_defconfig

 arch/arm/Kconfig                                   |  16 ---
 arch/arm/Kconfig.debug                             |   1 +
 arch/arm/configs/multi_v7_defconfig                |   6 +
 .../include/mach/uart.h => include/debug/sirf.S}   |  29 +++--
 arch/arm/mach-prima2/Kconfig                       |  12 ++
 arch/arm/mach-prima2/Makefile                      |   4 +-
 arch/arm/mach-prima2/common.c                      |  24 ++--
 arch/arm/mach-prima2/common.h                      |   4 +-
 arch/arm/mach-prima2/include/mach/clkdev.h         |  15 ---
 arch/arm/mach-prima2/include/mach/debug-macro.S    |  29 -----
 arch/arm/mach-prima2/include/mach/entry-macro.S    |  22 ----
 arch/arm/mach-prima2/include/mach/hardware.h       |  15 ---
 arch/arm/mach-prima2/include/mach/irqs.h           |  17 ---
 arch/arm/mach-prima2/include/mach/map.h            |  18 ---
 arch/arm/mach-prima2/include/mach/timex.h          |  14 ---
 arch/arm/mach-prima2/include/mach/uncompress.h     |  41 -------
 arch/arm/mach-prima2/irq.c                         | 129 ---------------------
 arch/arm/mach-prima2/lluart.c                      |  14 ++-
 arch/arm/mach-prima2/platsmp.c                     |   1 -
 drivers/clocksource/Makefile                       |   2 +
 .../clocksource}/timer-marco.c                     |  25 +---
 .../clocksource}/timer-prima2.c                    |  42 ++-----
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-sirfsoc.c                      | 123 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-sirf.c                     |  10 +-
 25 files changed, 210 insertions(+), 404 deletions(-)
 rename arch/arm/{mach-prima2/include/mach/uart.h => include/debug/sirf.S} (55%)
 delete mode 100644 arch/arm/mach-prima2/include/mach/clkdev.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-prima2/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-prima2/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/map.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/timex.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-prima2/irq.c
 rename {arch/arm/mach-prima2 => drivers/clocksource}/timer-marco.c (94%)
 rename {arch/arm/mach-prima2 => drivers/clocksource}/timer-prima2.c (90%)
 create mode 100644 drivers/irqchip/irq-sirfsoc.c

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>


-- 
1.8.1.2

[PATCH 1/8] pinctrl: sirf: convert to linear irq domain

[Arnd Bergmann]

The sirf platforms use no hardcoded IRQ numbers, so there is no reason to
use the legacy domain, and by converting to the linear domain, we get
a more efficient representation of sparse IRQs and remove the dependency
on the mach/irqs.h header file.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/pinctrl/pinctrl-sirf.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index d02498b..a0bc78b 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -1485,7 +1485,6 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
 	struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
 	u32 status, ctrl;
 	int idx = 0;
-	unsigned int first_irq;
 	struct irq_chip *chip = irq_get_chip(irq);
 
 	chained_irq_enter(chip, desc);
@@ -1499,8 +1498,6 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
 		return;
 	}
 
-	first_irq = bank->domain->revmap_data.legacy.first_irq;
-
 	while (status) {
 		ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
 
@@ -1511,7 +1508,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
 		if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
 			pr_debug("%s: gpio id %d idx %d happens\n",
 				__func__, bank->id, idx);
-			generic_handle_irq(first_irq + idx);
+			generic_handle_irq(irq_find_mapping(bank->domain, idx));
 		}
 
 		idx++;
@@ -1770,9 +1767,8 @@ static int sirfsoc_gpio_probe(struct device_node *np)
 			goto out;
 		}
 
-		bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
-			SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
-			&sirfsoc_gpio_irq_simple_ops, bank);
+		bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
+						&sirfsoc_gpio_irq_simple_ops, bank);
 
 		if (!bank->domain) {
 			pr_err("%s: Failed to create irqdomain\n", np->full_name);
-- 
1.8.1.2

[PATCH 2/8] ARM: sirf: fix prima2 interrupt lookup

[Arnd Bergmann]

We must not read the interrupts property manually but instead
use irq_of_parse_and_map() to guarantee that we get the correct
interrupt number once we stop using the legacy IRQ domain.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/mach-prima2/timer-prima2.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-prima2/timer-prima2.c b/arch/arm/mach-prima2/timer-prima2.c
index 6da584f..9829083 100644
--- a/arch/arm/mach-prima2/timer-prima2.c
+++ b/arch/arm/mach-prima2/timer-prima2.c
@@ -16,6 +16,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <mach/map.h>
 #include <asm/sched_clock.h>
@@ -223,7 +224,6 @@ static struct of_device_id timer_ids[] = {
 static void __init sirfsoc_of_timer_map(void)
 {
 	struct device_node *np;
-	const unsigned int *intspec;
 
 	np = of_find_matching_node(NULL, timer_ids);
 	if (!np)
@@ -233,9 +233,7 @@ static void __init sirfsoc_of_timer_map(void)
 		panic("unable to map timer cpu registers\n");
 
 	/* Get the interrupts property */
-	intspec = of_get_property(np, "interrupts", NULL);
-	BUG_ON(!intspec);
-	sirfsoc_timer_irq.irq = be32_to_cpup(intspec);
+	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
 
 	of_node_put(np);
 }
-- 
1.8.1.2

[PATCH 3/8] ARM: sirf: move irq driver to drivers/irqchip

[Arnd Bergmann]

This updates the irqchip drier for prima2 to the current practices by
moving it into drivers/irqchip and integrating it into the irqchip_init
infrastructure. We also now use a linear irq domain as a preparation
for sparse IRQ suport.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
---
 arch/arm/mach-prima2/common.c |  10 +---
 arch/arm/mach-prima2/irq.c    | 129 ------------------------------------------
 drivers/irqchip/Makefile      |   1 +
 drivers/irqchip/irq-sirfsoc.c | 123 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 126 insertions(+), 137 deletions(-)
 delete mode 100644 arch/arm/mach-prima2/irq.c
 create mode 100644 drivers/irqchip/irq-sirfsoc.c

diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 72efb4f..15c14df 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -46,11 +46,8 @@ static const char *atlas6_dt_match[] __initdata = {
 DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song@csr.com> */
 	.map_io         = sirfsoc_map_io,
-	.init_irq	= sirfsoc_of_irq_init,
+	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_prima2_timer_init,
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-	.handle_irq     = sirfsoc_handle_irq,
-#endif
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = atlas6_dt_match,
@@ -67,11 +64,8 @@ static const char *prima2_dt_match[] __initdata = {
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song@csr.com> */
 	.map_io         = sirfsoc_map_io,
-	.init_irq	= sirfsoc_of_irq_init,
+	.init_irq	= irqchip_init,
 	.init_time	= sirfsoc_prima2_timer_init,
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-	.handle_irq     = sirfsoc_handle_irq,
-#endif
 	.dma_zone_size	= SZ_256M,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
deleted file mode 100644
index 6c0f3e9..0000000
--- a/arch/arm/mach-prima2/irq.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * interrupt controller support for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/irqdomain.h>
-#include <linux/syscore_ops.h>
-#include <asm/mach/irq.h>
-#include <asm/exception.h>
-#include <mach/hardware.h>
-
-#define SIRFSOC_INT_RISC_MASK0          0x0018
-#define SIRFSOC_INT_RISC_MASK1          0x001C
-#define SIRFSOC_INT_RISC_LEVEL0         0x0020
-#define SIRFSOC_INT_RISC_LEVEL1         0x0024
-#define SIRFSOC_INIT_IRQ_ID		0x0038
-
-void __iomem *sirfsoc_intc_base;
-
-static __init void
-sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
-{
-	struct irq_chip_generic *gc;
-	struct irq_chip_type *ct;
-
-	gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
-	ct = gc->chip_types;
-
-	ct->chip.irq_mask = irq_gc_mask_clr_bit;
-	ct->chip.irq_unmask = irq_gc_mask_set_bit;
-	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
-
-	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
-}
-
-static __init void sirfsoc_irq_init(void)
-{
-	sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
-	sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
-			SIRFSOC_INTENAL_IRQ_END + 1 - 32);
-
-	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
-	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
-
-	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
-	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
-}
-
-asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
-{
-	u32 irqstat, irqnr;
-
-	irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
-	irqnr = irqstat & 0xff;
-
-	handle_IRQ(irqnr, regs);
-}
-
-static struct of_device_id intc_ids[]  = {
-	{ .compatible = "sirf,prima2-intc" },
-	{},
-};
-
-void __init sirfsoc_of_irq_init(void)
-{
-	struct device_node *np;
-
-	np = of_find_matching_node(NULL, intc_ids);
-	if (!np)
-		return;
-
-	sirfsoc_intc_base = of_iomap(np, 0);
-	if (!sirfsoc_intc_base)
-		panic("unable to map intc cpu registers\n");
-
-	irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
-		&irq_domain_simple_ops, NULL);
-
-	of_node_put(np);
-
-	sirfsoc_irq_init();
-}
-
-struct sirfsoc_irq_status {
-	u32 mask0;
-	u32 mask1;
-	u32 level0;
-	u32 level1;
-};
-
-static struct sirfsoc_irq_status sirfsoc_irq_st;
-
-static int sirfsoc_irq_suspend(void)
-{
-	sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
-	sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
-	sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
-	sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
-
-	return 0;
-}
-
-static void sirfsoc_irq_resume(void)
-{
-	writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
-	writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
-	writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
-	writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
-}
-
-static struct syscore_ops sirfsoc_irq_syscore_ops = {
-	.suspend	= sirfsoc_irq_suspend,
-	.resume		= sirfsoc_irq_resume,
-};
-
-static int __init sirfsoc_irq_pm_init(void)
-{
-	register_syscore_ops(&sirfsoc_irq_syscore_ops);
-	return 0;
-}
-device_initcall(sirfsoc_irq_pm_init);
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 98e3b87..5cb6bd2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi.o
 obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
 obj-$(CONFIG_ARM_GIC)			+= irq-gic.o
 obj-$(CONFIG_ARM_VIC)			+= irq-vic.o
+obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c
new file mode 100644
index 0000000..9a6a925
--- /dev/null
+++ b/drivers/irqchip/irq-sirfsoc.c
@@ -0,0 +1,123 @@
+/*
+ * interrupt controller support for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/irqdomain.h>
+#include <linux/syscore_ops.h>
+#include <asm/mach/irq.h>
+#include <asm/exception.h>
+#include "irqchip.h"
+
+#define SIRFSOC_INT_RISC_MASK0          0x0018
+#define SIRFSOC_INT_RISC_MASK1          0x001C
+#define SIRFSOC_INT_RISC_LEVEL0         0x0020
+#define SIRFSOC_INT_RISC_LEVEL1         0x0024
+#define SIRFSOC_INIT_IRQ_ID		0x0038
+
+#define SIRFSOC_NUM_IRQS		128
+
+static struct irq_domain *sirfsoc_irqdomain;
+
+static __init void
+sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
+{
+	struct irq_chip_generic *gc;
+	struct irq_chip_type *ct;
+
+	gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
+	ct = gc->chip_types;
+
+	ct->chip.irq_mask = irq_gc_mask_clr_bit;
+	ct->chip.irq_unmask = irq_gc_mask_set_bit;
+	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
+
+	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
+}
+
+static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
+{
+	void __iomem *base = sirfsoc_irqdomain->host_data;
+	u32 irqstat, irqnr;
+
+	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
+	irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff);
+
+	handle_IRQ(irqnr, regs);
+}
+
+static void __init sirfsoc_irq_init(struct device_node *np, struct device_node *parent)
+{
+	void __iomem *base = of_iomap(np, 0);
+	if (!base)
+		panic("unable to map intc cpu registers\n");
+
+	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
+				 &irq_domain_simple_ops, base);
+
+	sirfsoc_alloc_gc(base, 0, 32);
+	sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);
+
+	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
+	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
+
+	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
+	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
+
+	set_handle_irq(sirfsoc_handle_irq);
+}
+IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
+
+struct sirfsoc_irq_status {
+	u32 mask0;
+	u32 mask1;
+	u32 level0;
+	u32 level1;
+};
+
+static struct sirfsoc_irq_status sirfsoc_irq_st;
+
+static int sirfsoc_irq_suspend(void)
+{
+	void __iomem *base = sirfsoc_irqdomain->host_data;
+
+	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
+	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
+	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
+	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
+
+	return 0;
+}
+
+static void sirfsoc_irq_resume(void)
+{
+	void __iomem *base = sirfsoc_irqdomain->host_data;
+
+	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
+	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
+	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
+	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
+}
+
+static struct syscore_ops sirfsoc_irq_syscore_ops = {
+	.suspend	= sirfsoc_irq_suspend,
+	.resume		= sirfsoc_irq_resume,
+};
+
+static int __init sirfsoc_irq_pm_init(void)
+{
+	if (!sirfsoc_irqdomain)
+		return 0;
+
+	register_syscore_ops(&sirfsoc_irq_syscore_ops);
+	return 0;
+}
+device_initcall(sirfsoc_irq_pm_init);
-- 
1.8.1.2

[PATCH 4/8] ARM: sirf: enable sparse IRQ

[Arnd Bergmann]

Now that both irqchips for sirf are converted to not rely on
legacy domains, let's move all of the platform over to sparse
IRQ.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/Kconfig                         |  1 +
 arch/arm/mach-prima2/include/mach/irqs.h | 17 -----------------
 2 files changed, 1 insertion(+), 17 deletions(-)
 delete mode 100644 arch/arm/mach-prima2/include/mach/irqs.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5bfd584..c674b32 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -427,6 +427,7 @@ config ARCH_SIRF
 	select PINCTRL
 	select PINCTRL_SIRF
 	select USE_OF
+	select SPARSE_IRQ
 	help
 	  Support for CSR SiRFprimaII/Marco/Polo platforms
 
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
deleted file mode 100644
index b778a0f..0000000
--- a/arch/arm/mach-prima2/include/mach/irqs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/irqs.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#define SIRFSOC_INTENAL_IRQ_START  0
-#define SIRFSOC_INTENAL_IRQ_END    127
-#define SIRFSOC_GPIO_IRQ_START     (SIRFSOC_INTENAL_IRQ_END + 1)
-#define NR_IRQS	288
-
-#endif
-- 
1.8.1.2

[PATCH 5/8] ARM: sirf: move debug-macro.S to include/debug/sirf.S

[Arnd Bergmann]

The new style ll_debug implementation for multiplatform requires the
platform glue to be in include/debug, so let's move it there to
separate the debugging logic from the platform code.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/Kconfig.debug                                  |  1 +
 .../include/mach/debug-macro.S => include/debug/sirf.S} | 17 +++++++++++++++--
 arch/arm/mach-prima2/lluart.c                           | 12 +++++++++++-
 3 files changed, 27 insertions(+), 3 deletions(-)
 rename arch/arm/{mach-prima2/include/mach/debug-macro.S => include/debug/sirf.S} (53%)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index acdddda..a69334d 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -592,6 +592,7 @@ config DEBUG_LL_INCLUDE
 	default "debug/mvebu.S" if DEBUG_MVEBU_UART
 	default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
 	default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
+	default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
 	default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
 	default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
 	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/include/debug/sirf.S
similarity index 53%
rename from arch/arm/mach-prima2/include/mach/debug-macro.S
rename to arch/arm/include/debug/sirf.S
index cd97492..dbf250c 100644
--- a/arch/arm/mach-prima2/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/sirf.S
@@ -6,8 +6,21 @@
  * Licensed under GPLv2 or later.
  */
 
-#include <mach/hardware.h>
-#include <mach/uart.h>
+#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xb0060000
+#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xcc060000
+#else
+#define SIRFSOC_UART1_PA_BASE          0
+#endif
+
+#define SIRFSOC_UART1_VA_BASE		0xFEC60000
+
+#define SIRFSOC_UART_TXFIFO_STATUS	0x0114
+#define SIRFSOC_UART_TXFIFO_DATA	0x0118
+
+#define SIRFSOC_UART1_TXFIFO_FULL                       (1 << 5)
+#define SIRFSOC_UART1_TXFIFO_EMPTY			(1 << 6)
 
 	.macro	addruart, rp, rv, tmp
 	ldr	\rp, =SIRFSOC_UART1_PA_BASE		@ physical
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c
index a89f9b3..7222481 100644
--- a/arch/arm/mach-prima2/lluart.c
+++ b/arch/arm/mach-prima2/lluart.c
@@ -10,7 +10,17 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <mach/map.h>
-#include <mach/uart.h>
+
+#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xb0060000
+#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xcc060000
+#else
+#define SIRFSOC_UART1_PA_BASE          0
+#endif
+
+#define SIRFSOC_UART1_VA_BASE          SIRFSOC_VA(0x060000)
+#define SIRFSOC_UART1_SIZE		SZ_4K
 
 void __init sirfsoc_map_lluart(void)
 {
-- 
1.8.1.2

[PATCH 6/8] ARM: sirf: use clocksource_of infrastructure

[Arnd Bergmann]

This moves the two sirf clocksource drivers to drivers/clocksource
and integrates them into the framework for locating the clock sources
automatically.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
---
 arch/arm/mach-prima2/Makefile                      |  2 --
 arch/arm/mach-prima2/common.c                      | 14 ++++++--
 arch/arm/mach-prima2/common.h                      |  3 --
 drivers/clocksource/Makefile                       |  2 ++
 .../clocksource}/timer-marco.c                     | 25 +++-----------
 .../clocksource}/timer-prima2.c                    | 38 ++++------------------
 6 files changed, 24 insertions(+), 60 deletions(-)
 rename {arch/arm/mach-prima2 => drivers/clocksource}/timer-marco.c (94%)
 rename {arch/arm/mach-prima2 => drivers/clocksource}/timer-prima2.c (92%)

diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index bfe360c..4e1d3d2 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -7,5 +7,3 @@ obj-$(CONFIG_SUSPEND) += pm.o sleep.o
 obj-$(CONFIG_SIRF_IRQ) += irq.o
 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
-obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
-obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 15c14df..944d8ca 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -6,6 +6,7 @@
  * Licensed under GPLv2 or later.
  */
 
+#include <linux/clocksource.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/irqchip.h>
@@ -31,6 +32,13 @@ void __init sirfsoc_init_late(void)
 	sirfsoc_pm_init();
 }
 
+static __init void sirfsoc_init_time(void)
+{
+	/* initialize clocking early, we want to set the OS timer */
+	sirfsoc_of_clk_init();
+	clocksource_of_init();
+}
+
 static __init void sirfsoc_map_io(void)
 {
 	sirfsoc_map_lluart();
@@ -47,7 +55,7 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song@csr.com> */
 	.map_io         = sirfsoc_map_io,
 	.init_irq	= irqchip_init,
-	.init_time	= sirfsoc_prima2_timer_init,
+	.init_time	= sirfsoc_init_time,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = atlas6_dt_match,
@@ -65,7 +73,7 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song@csr.com> */
 	.map_io         = sirfsoc_map_io,
 	.init_irq	= irqchip_init,
-	.init_time	= sirfsoc_prima2_timer_init,
+	.init_time	= sirfsoc_init_time,
 	.dma_zone_size	= SZ_256M,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
@@ -85,7 +93,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
 	.smp            = smp_ops(sirfsoc_smp_ops),
 	.map_io         = sirfsoc_map_io,
 	.init_irq	= irqchip_init,
-	.init_time	= sirfsoc_marco_timer_init,
+	.init_time	= sirfsoc_init_time,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = marco_dt_match,
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index b7c26b6..54262cf 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -13,9 +13,6 @@
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
-extern void sirfsoc_prima2_timer_init(void);
-extern void sirfsoc_marco_timer_init(void);
-
 extern struct smp_operations   sirfsoc_smp_ops;
 extern void sirfsoc_secondary_startup(void);
 extern void sirfsoc_cpu_die(unsigned int cpu);
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 4d8283a..5e2176f 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU)	+= nomadik-mtu.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)	+= clksrc-dbx500-prcmu.o
 obj-$(CONFIG_ARMADA_370_XP_TIMER)	+= time-armada-370-xp.o
 obj-$(CONFIG_ARCH_BCM2835)	+= bcm2835_timer.o
+obj-$(CONFIG_ARCH_MARCO)	+= timer-marco.o
+obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o
 obj-$(CONFIG_SUNXI_TIMER)	+= sunxi_timer.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)	+= vt8500_timer.o
diff --git a/arch/arm/mach-prima2/timer-marco.c b/drivers/clocksource/timer-marco.c
similarity index 94%
rename from arch/arm/mach-prima2/timer-marco.c
rename to drivers/clocksource/timer-marco.c
index f4eea2e..97738db 100644
--- a/arch/arm/mach-prima2/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -21,8 +21,6 @@
 #include <asm/localtimer.h>
 #include <asm/mach/time.h>
 
-#include "common.h"
-
 #define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
 #define SIRFSOC_TIMER_32COUNTER_1_CTRL			0x0004
 #define SIRFSOC_TIMER_MATCH_0				0x0018
@@ -53,7 +51,6 @@ static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
 
 static void __iomem *sirfsoc_timer_base;
-static void __init sirfsoc_of_timer_map(void);
 
 /* disable count and interrupt */
 static inline void sirfsoc_timer_count_disable(int idx)
@@ -242,15 +239,12 @@ static void __init sirfsoc_clockevent_init(void)
 }
 
 /* initialize the kernel jiffy timer source */
-void __init sirfsoc_marco_timer_init(void)
+static void __init sirfsoc_marco_timer_init(void)
 {
 	unsigned long rate;
 	u32 timer_div;
 	struct clk *clk;
 
-	/* initialize clocking early, we want to set the OS timer */
-	sirfsoc_of_clk_init();
-
 	/* timer's input clock is io clock */
 	clk = clk_get_sys("io", NULL);
 
@@ -260,8 +254,6 @@ void __init sirfsoc_marco_timer_init(void)
 	BUG_ON(rate < CLOCK_TICK_RATE);
 	BUG_ON(rate % CLOCK_TICK_RATE);
 
-	sirfsoc_of_timer_map();
-
 	/* Initialize the timer dividers */
 	timer_div = rate / CLOCK_TICK_RATE - 1;
 	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
@@ -286,18 +278,8 @@ void __init sirfsoc_marco_timer_init(void)
 	sirfsoc_clockevent_init();
 }
 
-static struct of_device_id timer_ids[] = {
-	{ .compatible = "sirf,marco-tick" },
-	{},
-};
-
-static void __init sirfsoc_of_timer_map(void)
+static void __init sirfsoc_of_timer_init(struct device_node *np)
 {
-	struct device_node *np;
-
-	np = of_find_matching_node(NULL, timer_ids);
-	if (!np)
-		return;
 	sirfsoc_timer_base = of_iomap(np, 0);
 	if (!sirfsoc_timer_base)
 		panic("unable to map timer cpu registers\n");
@@ -312,5 +294,6 @@ static void __init sirfsoc_of_timer_map(void)
 		panic("No irq passed for timer1 via DT\n");
 #endif
 
-	of_node_put(np);
+	sirfsoc_marco_timer_init();
 }
+CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );
diff --git a/arch/arm/mach-prima2/timer-prima2.c b/drivers/clocksource/timer-prima2.c
similarity index 92%
rename from arch/arm/mach-prima2/timer-prima2.c
rename to drivers/clocksource/timer-prima2.c
index 9829083..7608826 100644
--- a/arch/arm/mach-prima2/timer-prima2.c
+++ b/drivers/clocksource/timer-prima2.c
@@ -18,12 +18,9 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
-#include <mach/map.h>
 #include <asm/sched_clock.h>
 #include <asm/mach/time.h>
 
-#include "common.h"
-
 #define SIRFSOC_TIMER_COUNTER_LO	0x0000
 #define SIRFSOC_TIMER_COUNTER_HI	0x0004
 #define SIRFSOC_TIMER_MATCH_0		0x0008
@@ -56,7 +53,6 @@ static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
 
 static void __iomem *sirfsoc_timer_base;
-static void __init sirfsoc_of_timer_map(void);
 
 /* timer0 interrupt handler */
 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
@@ -182,14 +178,11 @@ static void __init sirfsoc_clockevent_init(void)
 }
 
 /* initialize the kernel jiffy timer source */
-void __init sirfsoc_prima2_timer_init(void)
+static void __init sirfsoc_prima2_timer_init(struct device_node *np)
 {
 	unsigned long rate;
 	struct clk *clk;
 
-	/* initialize clocking early, we want to set the OS timer */
-	sirfsoc_of_clk_init();
-
 	/* timer's input clock is io clock */
 	clk = clk_get_sys("io", NULL);
 
@@ -200,7 +193,11 @@ void __init sirfsoc_prima2_timer_init(void)
 	BUG_ON(rate < CLOCK_TICK_RATE);
 	BUG_ON(rate % CLOCK_TICK_RATE);
 
-	sirfsoc_of_timer_map();
+	sirfsoc_timer_base = of_iomap(np, 0);
+	if (!sirfsoc_timer_base)
+		panic("unable to map timer cpu registers\n");
+
+	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
 
 	writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
@@ -215,25 +212,4 @@ void __init sirfsoc_prima2_timer_init(void)
 
 	sirfsoc_clockevent_init();
 }
-
-static struct of_device_id timer_ids[] = {
-	{ .compatible = "sirf,prima2-tick" },
-	{},
-};
-
-static void __init sirfsoc_of_timer_map(void)
-{
-	struct device_node *np;
-
-	np = of_find_matching_node(NULL, timer_ids);
-	if (!np)
-		return;
-	sirfsoc_timer_base = of_iomap(np, 0);
-	if (!sirfsoc_timer_base)
-		panic("unable to map timer cpu registers\n");
-
-	/* Get the interrupts property */
-	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
-
-	of_node_put(np);
-}
+CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick", sirfsoc_prima2_timer_init);
-- 
1.8.1.2

[PATCH 7/8] ARM: sirf: enable multiplatform support

[Arnd Bergmann]

All the prerequisites are there now, so we can move sirf into multiplatform.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/Kconfig                                | 17 ----------
 arch/arm/mach-prima2/Kconfig                    | 12 ++++++++
 arch/arm/mach-prima2/Makefile                   |  2 ++
 arch/arm/mach-prima2/common.h                   |  3 ++
 arch/arm/mach-prima2/include/mach/clkdev.h      | 15 ---------
 arch/arm/mach-prima2/include/mach/entry-macro.S | 22 -------------
 arch/arm/mach-prima2/include/mach/hardware.h    | 15 ---------
 arch/arm/mach-prima2/include/mach/map.h         | 18 -----------
 arch/arm/mach-prima2/include/mach/timex.h       | 14 ---------
 arch/arm/mach-prima2/include/mach/uart.h        | 29 -----------------
 arch/arm/mach-prima2/include/mach/uncompress.h  | 41 -------------------------
 arch/arm/mach-prima2/lluart.c                   |  2 +-
 arch/arm/mach-prima2/platsmp.c                  |  1 -
 13 files changed, 18 insertions(+), 173 deletions(-)
 delete mode 100644 arch/arm/mach-prima2/include/mach/clkdev.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-prima2/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/map.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/timex.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/uart.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/uncompress.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c674b32..1bcec63 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -49,7 +49,6 @@ config ARM
 	select HAVE_REGS_AND_STACK_ACCESS_API
 	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_UID16
-	select HAVE_VIRT_TO_BUS
 	select KTIME_SCALAR
 	select PERF_USE_VMALLOC
 	select RTC_LIB
@@ -415,22 +414,6 @@ config ARCH_GEMINI
 	help
 	  Support for the Cortina Systems Gemini family SoCs
 
-config ARCH_SIRF
-	bool "CSR SiRF"
-	select ARCH_REQUIRE_GPIOLIB
-	select AUTO_ZRELADDR
-	select COMMON_CLK
-	select GENERIC_CLOCKEVENTS
-	select GENERIC_IRQ_CHIP
-	select MIGHT_HAVE_CACHE_L2X0
-	select NO_IOPORT
-	select PINCTRL
-	select PINCTRL_SIRF
-	select USE_OF
-	select SPARSE_IRQ
-	help
-	  Support for CSR SiRFprimaII/Marco/Polo platforms
-
 config ARCH_EBSA110
 	bool "EBSA-110"
 	select ARCH_USES_GETTIMEOFFSET
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index b3be799..587c0bd 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -1,3 +1,15 @@
+config ARCH_SIRF
+	bool "CSR SiRF" if ARCH_MULTI_V7
+	select ARCH_REQUIRE_GPIOLIB
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_IRQ_CHIP
+	select MIGHT_HAVE_CACHE_L2X0
+	select NO_IOPORT
+	select PINCTRL
+	select PINCTRL_SIRF
+	help
+	  Support for CSR SiRFprimaII/Marco/Polo platforms
+
 if ARCH_SIRF
 
 menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 4e1d3d2..f9ee89b 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -7,3 +7,5 @@ obj-$(CONFIG_SUSPEND) += pm.o sleep.o
 obj-$(CONFIG_SIRF_IRQ) += irq.o
 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
+
+CFLAGS_hotplug.o += -march=armv7-a
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 54262cf..81135cd 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -13,6 +13,9 @@
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
+#define SIRFSOC_VA_BASE		_AC(0xFEC00000, UL)
+#define SIRFSOC_VA(x)		(SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
+
 extern struct smp_operations   sirfsoc_smp_ops;
 extern void sirfsoc_secondary_startup(void);
 extern void sirfsoc_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h
deleted file mode 100644
index 6693251..0000000
--- a/arch/arm/mach-prima2/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/clkdev.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S
deleted file mode 100644
index 86434e7..0000000
--- a/arch/arm/mach-prima2/include/mach/entry-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/entry-macro.S
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <mach/hardware.h>
-
-#define SIRFSOC_INT_ID 0x38
-
-	.macro  get_irqnr_preamble, base, tmp
-	ldr     \base, =sirfsoc_intc_base
-	ldr     \base, [\base]
-	.endm
-
-	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-	ldr \irqnr, [\base, #SIRFSOC_INT_ID]	@ Get the highest priority irq
-	cmp \irqnr, #0x40			@ the irq num can't be larger than 0x3f
-	movges \irqnr, #0
-	.endm
diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h
deleted file mode 100644
index 105b969..0000000
--- a/arch/arm/mach-prima2/include/mach/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/hardware.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_HARDWARE_H__
-#define __MACH_HARDWARE_H__
-
-#include <asm/sizes.h>
-#include <mach/map.h>
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
deleted file mode 100644
index 6f24353..0000000
--- a/arch/arm/mach-prima2/include/mach/map.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * memory & I/O static mapping definitions for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_PRIMA2_MAP_H__
-#define __MACH_PRIMA2_MAP_H__
-
-#include <linux/const.h>
-
-#define SIRFSOC_VA_BASE		_AC(0xFEC00000, UL)
-
-#define SIRFSOC_VA(x)		(SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h
deleted file mode 100644
index d6f98a7..0000000
--- a/arch/arm/mach-prima2/include/mach/timex.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/timex.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_TIMEX_H__
-#define __MACH_TIMEX_H__
-
-#define CLOCK_TICK_RATE  1000000
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h
deleted file mode 100644
index c10510d..0000000
--- a/arch/arm/mach-prima2/include/mach/uart.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/uart.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_PRIMA2_SIRFSOC_UART_H
-#define __MACH_PRIMA2_SIRFSOC_UART_H
-
-/* UART-1: used as serial debug port */
-#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
-#define SIRFSOC_UART1_PA_BASE          0xb0060000
-#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
-#define SIRFSOC_UART1_PA_BASE          0xcc060000
-#else
-#define SIRFSOC_UART1_PA_BASE          0
-#endif
-#define SIRFSOC_UART1_VA_BASE          SIRFSOC_VA(0x060000)
-#define SIRFSOC_UART1_SIZE		SZ_4K
-
-#define SIRFSOC_UART_TXFIFO_STATUS	0x0114
-#define SIRFSOC_UART_TXFIFO_DATA	0x0118
-
-#define SIRFSOC_UART1_TXFIFO_FULL                       (1 << 5)
-#define SIRFSOC_UART1_TXFIFO_EMPTY			(1 << 6)
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
deleted file mode 100644
index d1513a3..0000000
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/uncompress.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/uart.h>
-
-void arch_decomp_setup(void)
-{
-}
-
-static __inline__ void putc(char c)
-{
-	/*
-	 * during kernel decompression, all mappings are flat:
-	 *  virt_addr == phys_addr
-	 */
-	if (!SIRFSOC_UART1_PA_BASE)
-		return;
-
-	while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
-		& SIRFSOC_UART1_TXFIFO_FULL)
-		barrier();
-
-	__raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
-}
-
-static inline void flush(void)
-{
-}
-
-#endif
-
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c
index 7222481..99c0c92 100644
--- a/arch/arm/mach-prima2/lluart.c
+++ b/arch/arm/mach-prima2/lluart.c
@@ -9,7 +9,7 @@
 #include <linux/kernel.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
-#include <mach/map.h>
+#include "common.h"
 
 #if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
 #define SIRFSOC_UART1_PA_BASE          0xb0060000
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 4b78831..d52e322 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -18,7 +18,6 @@
 #include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
-#include <mach/map.h>
 
 #include "common.h"
 
-- 
1.8.1.2

[PATCH 8/8] ARM: sirf: enable support in multi_v7_defconfig

[Arnd Bergmann]

This enables all sirf specific drivers in the defconfig.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/configs/multi_v7_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e31d442..44ec305 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -3,6 +3,7 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
+CONFIG_ARCH_SIRF=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_SOCFPGA=y
@@ -34,12 +35,16 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SIRFSOC=y
+CONFIG_SERIAL_SIRFSOC_CONSOLE=y
 CONFIG_IPMI_HANDLER=y
 CONFIG_IPMI_SI=y
 CONFIG_I2C=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_SIRF=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
+CONFIG_SPI_SIRF=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -58,3 +63,4 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
 CONFIG_PL330_DMA=y
+CONFIG_SIRF_DMA=y
-- 
1.8.1.2

[PATCH 0/8] SIRF multiplatform support

[Arnd Bergmann]

On Wednesday 20 March 2013, Arnd Bergmann wrote:
> 
> Here goes another one. Since the SIRF platforms are relatively new and
> clean, they are easy to convert to multiplatform, so I did that and
> fixed up a few other things in the process as well.
> 
> Barry, could you test these and report back if everything still works
> for you?
> 
> Thomas, John, Linus: Are you ok with the irqchip/clocksource/pinctrl
> changes?
> 

I should have mentioned that my patches also depend on the clocksource
changes from Rob Herring. Barry, when you test this, you can get the
branch from the "sirf/multiplatform" branch of the arm-soc tree.

	Arnd

[PATCH 1/8] pinctrl: sirf: convert to linear irq domain

[Barry Song]

Hi Arnd,

2013/3/20 Arnd Bergmann <arnd@arndb.de>:
> The sirf platforms use no hardcoded IRQ numbers, so there is no reason to
> use the legacy domain, and by converting to the linear domain, we get
> a more efficient representation of sparse IRQs and remove the dependency
> on the mach/irqs.h header file.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Cc: Linus Walleij <linus.walleij@linaro.org>

a dependency issue is recently i sent a patch for re-arch sirf
pinctrl, pull the soc-specific pin/group/functionality layout out of
the drivers/pinctrl/pinctrl-sirf.c, and created new seperate
soc-layout files for prima2 and atlas6 in drivers/pinctrl/sirf.
Barry Song:
[PATCH]pinctrl:sirf:re-arch and add support for new SiRFatlas6 SoC
http://www.spinics.net/lists/arm-kernel/msg230700.html
i will merge yours with that.

Hi Linus,
would you give some comments about that sirf re-arch patch, i hope all
of them could be in 3.10.

> ---
>  drivers/pinctrl/pinctrl-sirf.c | 10 +++-------
>  1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
> index d02498b..a0bc78b 100644
> --- a/drivers/pinctrl/pinctrl-sirf.c
> +++ b/drivers/pinctrl/pinctrl-sirf.c
> @@ -1485,7 +1485,6 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)

-barry

[PATCH 2/8] ARM: sirf: fix prima2 interrupt lookup

[Barry Song]

2013/3/20 Arnd Bergmann <arnd@arndb.de>:
> We must not read the interrupts property manually but instead
> use irq_of_parse_and_map() to guarantee that we get the correct
> interrupt number once we stop using the legacy IRQ domain.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Tested-by: Barry Song <Baohua.Song@csr.com>

> ---
>  arch/arm/mach-prima2/timer-prima2.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-prima2/timer-prima2.c b/arch/arm/mach-prima2/timer-prima2.c
> index 6da584f..9829083 100644
> --- a/arch/arm/mach-prima2/timer-prima2.c
> +++ b/arch/arm/mach-prima2/timer-prima2.c
> @@ -16,6 +16,7 @@
>  #include <linux/err.h>
>  #include <linux/slab.h>
>  #include <linux/of.h>
> +#include <linux/of_irq.h>
>  #include <linux/of_address.h>
>  #include <mach/map.h>
>  #include <asm/sched_clock.h>
> @@ -223,7 +224,6 @@ static struct of_device_id timer_ids[] = {
>  static void __init sirfsoc_of_timer_map(void)
>  {
>         struct device_node *np;
> -       const unsigned int *intspec;
>
>         np = of_find_matching_node(NULL, timer_ids);
>         if (!np)
> @@ -233,9 +233,7 @@ static void __init sirfsoc_of_timer_map(void)
>                 panic("unable to map timer cpu registers\n");
>
>         /* Get the interrupts property */
> -       intspec = of_get_property(np, "interrupts", NULL);
> -       BUG_ON(!intspec);
> -       sirfsoc_timer_irq.irq = be32_to_cpup(intspec);
> +       sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
>
>         of_node_put(np);
>  }
> --
> 1.8.1.2

[PATCH 1/8] pinctrl: sirf: convert to linear irq domain

[Barry Song]

Hi Arnd,

2013/3/20 Arnd Bergmann <arnd@arndb.de>:
> The sirf platforms use no hardcoded IRQ numbers, so there is no reason to
> use the legacy domain, and by converting to the linear domain, we get
> a more efficient representation of sparse IRQs and remove the dependency
> on the mach/irqs.h header file.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
>  drivers/pinctrl/pinctrl-sirf.c | 10 +++-------
>  1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
> index d02498b..a0bc78b 100644
> --- a/drivers/pinctrl/pinctrl-sirf.c
> +++ b/drivers/pinctrl/pinctrl-sirf.c
> @@ -1485,7 +1485,6 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
>         struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
>         u32 status, ctrl;
>         int idx = 0;
> -       unsigned int first_irq;
>         struct irq_chip *chip = irq_get_chip(irq);
>
>         chained_irq_enter(chip, desc);
> @@ -1499,8 +1498,6 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
>                 return;
>         }
>
> -       first_irq = bank->domain->revmap_data.legacy.first_irq;
> -
>         while (status) {
>                 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
>
> @@ -1511,7 +1508,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
>                 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
>                         pr_debug("%s: gpio id %d idx %d happens\n",
>                                 __func__, bank->id, idx);
> -                       generic_handle_irq(first_irq + idx);
> +                       generic_handle_irq(irq_find_mapping(bank->domain, idx));

drop first_irq and replace first_irq + idx by
irq_find_mapping(bank->domain, idx) is fine.

>                 }
>
>                 idx++;
> @@ -1770,9 +1767,8 @@ static int sirfsoc_gpio_probe(struct device_node *np)
>                         goto out;
>                 }
>
> -               bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
> -                       SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
> -                       &sirfsoc_gpio_irq_simple_ops, bank);
> +               bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
> +                                               &sirfsoc_gpio_irq_simple_ops, bank);

this line breaks the gpio/irq mapping and gpio irq_domain:

       printk("%s gpio_to_irq: %d %d %d\n", __func__,
               gpio_to_irq(0), gpio_to_irq(32), gpio_to_irq(65));

result:
sdhci_sirf_probe gpio_to_irq: 0 0 0

for the old codes, it works:
sdhci_sirf_probe gpio_to_irq: 128 160 193

>
>                 if (!bank->domain) {
>                         pr_err("%s: Failed to create irqdomain\n", np->full_name);
> --
> 1.8.1.2

-barry

[PATCH 3/8] ARM: sirf: move irq driver to drivers/irqchip

[Barry Song]

2013/3/20, Arnd Bergmann <arnd@arndb.de>:
> This updates the irqchip drier for prima2 to the current practices by
> moving it into drivers/irqchip and integrating it into the irqchip_init
> infrastructure. We also now use a linear irq domain as a preparation
> for sparse IRQ suport.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> ---
>  arch/arm/mach-prima2/common.c |  10 +---
>  arch/arm/mach-prima2/irq.c    | 129
> ------------------------------------------
>  drivers/irqchip/Makefile      |   1 +
>  drivers/irqchip/irq-sirfsoc.c | 123
> ++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 126 insertions(+), 137 deletions(-)
>  delete mode 100644 arch/arm/mach-prima2/irq.c
>  create mode 100644 drivers/irqchip/irq-sirfsoc.c
>
> diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
> index 72efb4f..15c14df 100644
> --- a/arch/arm/mach-prima2/common.c
> +++ b/arch/arm/mach-prima2/common.c
> @@ -46,11 +46,8 @@ static const char *atlas6_dt_match[] __initdata = {
>  DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
>  	/* Maintainer: Barry Song <baohua.song@csr.com> */
>  	.map_io         = sirfsoc_map_io,
> -	.init_irq	= sirfsoc_of_irq_init,
> +	.init_irq	= irqchip_init,
>  	.init_time	= sirfsoc_prima2_timer_init,
> -#ifdef CONFIG_MULTI_IRQ_HANDLER
> -	.handle_irq     = sirfsoc_handle_irq,
> -#endif
>  	.init_machine	= sirfsoc_mach_init,
>  	.init_late	= sirfsoc_init_late,
>  	.dt_compat      = atlas6_dt_match,
> @@ -67,11 +64,8 @@ static const char *prima2_dt_match[] __initdata = {
>  DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
>  	/* Maintainer: Barry Song <baohua.song@csr.com> */
>  	.map_io         = sirfsoc_map_io,
> -	.init_irq	= sirfsoc_of_irq_init,
> +	.init_irq	= irqchip_init,
>  	.init_time	= sirfsoc_prima2_timer_init,
> -#ifdef CONFIG_MULTI_IRQ_HANDLER
> -	.handle_irq     = sirfsoc_handle_irq,
> -#endif
>  	.dma_zone_size	= SZ_256M,
>  	.init_machine	= sirfsoc_mach_init,
>  	.init_late	= sirfsoc_init_late,
> diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
> deleted file mode 100644
> index 6c0f3e9..0000000
> --- a/arch/arm/mach-prima2/irq.c
> +++ /dev/null
> @@ -1,129 +0,0 @@
> -/*
> - * interrupt controller support for CSR SiRFprimaII
> - *
> - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group
> company.
> - *
> - * Licensed under GPLv2 or later.
> - */
> -
> -#include <linux/init.h>
> -#include <linux/io.h>
> -#include <linux/irq.h>
> -#include <linux/of.h>
> -#include <linux/of_address.h>
> -#include <linux/irqdomain.h>
> -#include <linux/syscore_ops.h>
> -#include <asm/mach/irq.h>
> -#include <asm/exception.h>
> -#include <mach/hardware.h>
> -
> -#define SIRFSOC_INT_RISC_MASK0          0x0018
> -#define SIRFSOC_INT_RISC_MASK1          0x001C
> -#define SIRFSOC_INT_RISC_LEVEL0         0x0020
> -#define SIRFSOC_INT_RISC_LEVEL1         0x0024
> -#define SIRFSOC_INIT_IRQ_ID		0x0038
> -
> -void __iomem *sirfsoc_intc_base;
> -
> -static __init void
> -sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int
> num)
> -{
> -	struct irq_chip_generic *gc;
> -	struct irq_chip_type *ct;
> -
> -	gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base,
> handle_level_irq);
> -	ct = gc->chip_types;
> -
> -	ct->chip.irq_mask = irq_gc_mask_clr_bit;
> -	ct->chip.irq_unmask = irq_gc_mask_set_bit;
> -	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
> -
> -	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
> IRQ_NOREQUEST, 0);
> -}
> -
> -static __init void sirfsoc_irq_init(void)
> -{
> -	sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
> -	sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
> -			SIRFSOC_INTENAL_IRQ_END + 1 - 32);
> -
> -	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
> -	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
> -
> -	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
> -	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
> -}
> -
> -asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs
> *regs)
> -{
> -	u32 irqstat, irqnr;
> -
> -	irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
> -	irqnr = irqstat & 0xff;
> -
> -	handle_IRQ(irqnr, regs);
> -}
> -
> -static struct of_device_id intc_ids[]  = {
> -	{ .compatible = "sirf,prima2-intc" },
> -	{},
> -};
> -
> -void __init sirfsoc_of_irq_init(void)
> -{
> -	struct device_node *np;
> -
> -	np = of_find_matching_node(NULL, intc_ids);
> -	if (!np)
> -		return;
> -
> -	sirfsoc_intc_base = of_iomap(np, 0);
> -	if (!sirfsoc_intc_base)
> -		panic("unable to map intc cpu registers\n");
> -
> -	irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
> -		&irq_domain_simple_ops, NULL);
> -
> -	of_node_put(np);
> -
> -	sirfsoc_irq_init();
> -}
> -
> -struct sirfsoc_irq_status {
> -	u32 mask0;
> -	u32 mask1;
> -	u32 level0;
> -	u32 level1;
> -};
> -
> -static struct sirfsoc_irq_status sirfsoc_irq_st;
> -
> -static int sirfsoc_irq_suspend(void)
> -{
> -	sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base +
> SIRFSOC_INT_RISC_MASK0);
> -	sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base +
> SIRFSOC_INT_RISC_MASK1);
> -	sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base +
> SIRFSOC_INT_RISC_LEVEL0);
> -	sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base +
> SIRFSOC_INT_RISC_LEVEL1);
> -
> -	return 0;
> -}
> -
> -static void sirfsoc_irq_resume(void)
> -{
> -	writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base +
> SIRFSOC_INT_RISC_MASK0);
> -	writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base +
> SIRFSOC_INT_RISC_MASK1);
> -	writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base +
> SIRFSOC_INT_RISC_LEVEL0);
> -	writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base +
> SIRFSOC_INT_RISC_LEVEL1);
> -}
> -
> -static struct syscore_ops sirfsoc_irq_syscore_ops = {
> -	.suspend	= sirfsoc_irq_suspend,
> -	.resume		= sirfsoc_irq_resume,
> -};
> -
> -static int __init sirfsoc_irq_pm_init(void)
> -{
> -	register_syscore_ops(&sirfsoc_irq_syscore_ops);
> -	return 0;
> -}
> -device_initcall(sirfsoc_irq_pm_init);
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 98e3b87..5cb6bd2 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi.o
>  obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
>  obj-$(CONFIG_ARM_GIC)			+= irq-gic.o
>  obj-$(CONFIG_ARM_VIC)			+= irq-vic.o
> +obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
>  obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
> diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c
> new file mode 100644
> index 0000000..9a6a925
> --- /dev/null
> +++ b/drivers/irqchip/irq-sirfsoc.c
> @@ -0,0 +1,123 @@
> +/*
> + * interrupt controller support for CSR SiRFprimaII
> + *
> + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group
> company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/irqdomain.h>
> +#include <linux/syscore_ops.h>
> +#include <asm/mach/irq.h>
> +#include <asm/exception.h>
> +#include "irqchip.h"
> +
> +#define SIRFSOC_INT_RISC_MASK0          0x0018
> +#define SIRFSOC_INT_RISC_MASK1          0x001C
> +#define SIRFSOC_INT_RISC_LEVEL0         0x0020
> +#define SIRFSOC_INT_RISC_LEVEL1         0x0024
> +#define SIRFSOC_INIT_IRQ_ID		0x0038
> +
> +#define SIRFSOC_NUM_IRQS		128
> +
> +static struct irq_domain *sirfsoc_irqdomain;
> +
> +static __init void
> +sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int
> num)
> +{
> +	struct irq_chip_generic *gc;
> +	struct irq_chip_type *ct;
> +
> +	gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base,
> handle_level_irq);
> +	ct = gc->chip_types;
> +
> +	ct->chip.irq_mask = irq_gc_mask_clr_bit;
> +	ct->chip.irq_unmask = irq_gc_mask_set_bit;
> +	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
> +
> +	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
> IRQ_NOREQUEST, 0);
> +}
> +
> +static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct
> pt_regs *regs)
> +{
> +	void __iomem *base = sirfsoc_irqdomain->host_data;
> +	u32 irqstat, irqnr;
> +
> +	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
> +	irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff);
> +
> +	handle_IRQ(irqnr, regs);
> +}
> +
> +static void __init sirfsoc_irq_init(struct device_node *np, struct
> device_node *parent)

this function should be changed from void to int.

> +{
> +	void __iomem *base = of_iomap(np, 0);
> +	if (!base)
> +		panic("unable to map intc cpu registers\n");
> +
> +	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
> +				 &irq_domain_simple_ops, base);

this breaks the hwirq and irq mapping. the hwirq 0 is mapped to
no_irqs, then setup_irq will fail in
drivers/clocksource/timer-prima2.c.

-barry

[PATCH 6/8] ARM: sirf: use clocksource_of infrastructure

[Barry Song]

2013/3/20, Arnd Bergmann <arnd@arndb.de>:
> This moves the two sirf clocksource drivers to drivers/clocksource
> and integrates them into the framework for locating the clock sources
> automatically.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Cc: John Stultz <john.stultz@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>

Tested-by: Barry Song <Baohua.Song@csr.com>

-barry

[PATCH 1/8] pinctrl: sirf: convert to linear irq domain

[Arnd Bergmann]

On Monday 25 March 2013, Barry Song wrote:
> > @@ -1770,9 +1767,8 @@ static int sirfsoc_gpio_probe(struct device_node *np)
> >                         goto out;
> >                 }
> >
> > -               bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
> > -                       SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
> > -                       &sirfsoc_gpio_irq_simple_ops, bank);
> > +               bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
> > +                                               &sirfsoc_gpio_irq_simple_ops, bank);
> 
> this line breaks the gpio/irq mapping and gpio irq_domain:
> 
>        printk("%s gpio_to_irq: %d %d %d\n", __func__,
>                gpio_to_irq(0), gpio_to_irq(32), gpio_to_irq(65));
> 
> result:
> sdhci_sirf_probe gpio_to_irq: 0 0 0
> 
> for the old codes, it works:
> sdhci_sirf_probe gpio_to_irq: 128 160 193

Does it work if you add the hunk below?

I think the problem is that with irq_domain_add_linear, we don't create
a mapping for all the interrupts right away.

	Arnd

diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index d02498b..5f031ca 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -1347,7 +1347,7 @@ static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 	struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
 		struct sirfsoc_gpio_bank, chip);
 
-	return irq_find_mapping(bank->domain, offset);
+	return irq_create_mapping(bank->domain, offset);
 }
 
 static inline int sirfsoc_gpio_to_offset(unsigned int gpio)

[PATCH 3/8] ARM: sirf: move irq driver to drivers/irqchip

[Arnd Bergmann]

On Monday 25 March 2013, Barry Song wrote:
> 2013/3/20, Arnd Bergmann <arnd@arndb.de>:

> > +static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct
> > pt_regs *regs)
> > +{
> > +	void __iomem *base = sirfsoc_irqdomain->host_data;
> > +	u32 irqstat, irqnr;
> > +
> > +	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
> > +	irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff);
> > +
> > +	handle_IRQ(irqnr, regs);
> > +}
> > +
> > +static void __init sirfsoc_irq_init(struct device_node *np, struct
> > device_node *parent)
> 
> this function should be changed from void to int.

Right.

> > +{
> > +	void __iomem *base = of_iomap(np, 0);
> > +	if (!base)
> > +		panic("unable to map intc cpu registers\n");
> > +
> > +	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
> > +				 &irq_domain_simple_ops, base);
> 
> this breaks the hwirq and irq mapping. the hwirq 0 is mapped to
> no_irqs, then setup_irq will fail in
> drivers/clocksource/timer-prima2.c.

Hmm, I don't understand yet what is going on there. This should create
a domain with all dynamically allocated interrupt descriptors,
and the hwirq number is just local to the controller then.

Without patch 2 of the series, this would fail, because that interrupt
is not mapped, but as far as I can tell, we correctly instantiate
the domain here, so the irq_of_parse_and_map() in sirfsoc_of_timer_map
should return a valid interrupt number. Can you check what it returns
instead? Does it work if you revert to a legacy domain here?

	Arnd

[PATCH 5/8] ARM: sirf: move debug-macro.S to include/debug/sirf.S

[Barry Song]

2013/3/20, Arnd Bergmann <arnd@arndb.de>:
> The new style ll_debug implementation for multiplatform requires the
> platform glue to be in include/debug, so let's move it there to
> separate the debugging logic from the platform code.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Tested-by: Barry Song <Baohua.Song@csr.com>

[PATCH 3/8] ARM: sirf: move irq driver to drivers/irqchip

[Barry Song]

2013/3/25, Arnd Bergmann <arnd@arndb.de>:
> On Monday 25 March 2013, Barry Song wrote:
>> 2013/3/20, Arnd Bergmann <arnd@arndb.de>:
>
>> > +static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct
>> > pt_regs *regs)
>> > +{
>> > +	void __iomem *base = sirfsoc_irqdomain->host_data;
>> > +	u32 irqstat, irqnr;
>> > +
>> > +	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
>> > +	irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff);
>> > +
>> > +	handle_IRQ(irqnr, regs);
>> > +}
>> > +
>> > +static void __init sirfsoc_irq_init(struct device_node *np, struct
>> > device_node *parent)
>>
>> this function should be changed from void to int.
>
> Right.
>
>> > +{
>> > +	void __iomem *base = of_iomap(np, 0);
>> > +	if (!base)
>> > +		panic("unable to map intc cpu registers\n");
>> > +
>> > +	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
>> > +				 &irq_domain_simple_ops, base);
>>
>> this breaks the hwirq and irq mapping. the hwirq 0 is mapped to
>> no_irqs, then setup_irq will fail in
>> drivers/clocksource/timer-prima2.c.
>
> Hmm, I don't understand yet what is going on there. This should create
> a domain with all dynamically allocated interrupt descriptors,
> and the hwirq number is just local to the controller then.

suppose we think the hardware register flag bit of timer-prima2 is 0,
irq_of_parse_and_map() will return 16 in patch2 for the timer-prima2
which uses the 1st hardware IRQ in the system.

if add nr_irqs=288 in ATLAS6 machine, irq_of_parse_and_map() will
return 288 in patch2. it looks like the first hw irq will always be
mapped to nr_irqs.

>
> Without patch 2 of the series, this would fail, because that interrupt
> is not mapped, but as far as I can tell, we correctly instantiate
> the domain here, so the irq_of_parse_and_map() in sirfsoc_of_timer_map
> should return a valid interrupt number. Can you check what it returns
> instead? Does it work if you revert to a legacy domain here?

actually patch2 can work without patch3 by irq_domain_add legacy. as
you can see, my old timer-marco.c uses irq_of_parse_and_map() instead
of reading interrupts manually.

the irq mapping works with the following changes:
-------------------------------------------------------------------------
-------------------------------------------------------------------------
arch/arm/mach-prima2/common.c:

 DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
        .map_io         = sirfsoc_map_io,
+       .nr_irqs        = 288,
        .init_irq       = irqchip_init,
        .init_time      = sirfsoc_init_time,
        .init_machine   = sirfsoc_mach_init,

-------------------------------------------------------------------------
-------------------------------------------------------------------------
drivers/irqchip/irq-sirfsoc.c:
index 9a6a925..271f905 100644
--- a/drivers/irqchip/irq-sirfsoc.c
+++ b/drivers/irqchip/irq-sirfsoc.c
@@ -54,13 +54,13 @@ static asmlinkage void __exception_irq_entry
sirfsoc_handle_irq(struct pt_regs *
        handle_IRQ(irqnr, regs);
 }

-static void __init sirfsoc_irq_init(struct device_node *np, struct
device_node *parent)
+static int __init sirfsoc_irq_init(struct device_node *np, struct
device_node *parent)
 {
        void __iomem *base = of_iomap(np, 0);
        if (!base)
                panic("unable to map intc cpu registers\n");

-       sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
+       sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0,
                                 &irq_domain_simple_ops, base);

        sirfsoc_alloc_gc(base, 0, 32);
@@ -73,6 +73,8 @@ static void __init sirfsoc_irq_init(struct
device_node *np, struct device_node *
        writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);

        set_handle_irq(sirfsoc_handle_irq);
+
+       return 0;
 }
 IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);

-------------------------------------------------------------------------
-------------------------------------------------------------------------
drivers/pinctrl/pinctrl-sirf.c:
-                bank->domain = irq_domain_add_linear(np,
SIRFSOC_GPIO_BANK_SIZE,
+                bank->domain = irq_domain_add_legacy(np,
SIRFSOC_GPIO_BANK_SIZE,
+                        128 + i * SIRFSOC_GPIO_BANK_SIZE, 0,
                        &sirfsoc_gpio_irq_simple_ops, bank);

@@ -65,13 +74,14 @@ MACHINE_END

-barry

[PATCH 1/8] pinctrl: sirf: convert to linear irq domain

[Barry Song]

2013/3/25, Arnd Bergmann <arnd@arndb.de>:
> On Monday 25 March 2013, Barry Song wrote:
>> > @@ -1770,9 +1767,8 @@ static int sirfsoc_gpio_probe(struct device_node
>> > *np)
>> >                         goto out;
>> >                 }
>> >
>> > -               bank->domain = irq_domain_add_legacy(np,
>> > SIRFSOC_GPIO_BANK_SIZE,
>> > -                       SIRFSOC_GPIO_IRQ_START + i *
>> > SIRFSOC_GPIO_BANK_SIZE, 0,
>> > -                       &sirfsoc_gpio_irq_simple_ops, bank);
>> > +               bank->domain = irq_domain_add_linear(np,
>> > SIRFSOC_GPIO_BANK_SIZE,
>> > +
>> > &sirfsoc_gpio_irq_simple_ops, bank);
>>
>> this line breaks the gpio/irq mapping and gpio irq_domain:
>>
>>        printk("%s gpio_to_irq: %d %d %d\n", __func__,
>>                gpio_to_irq(0), gpio_to_irq(32), gpio_to_irq(65));
>>
>> result:
>> sdhci_sirf_probe gpio_to_irq: 0 0 0
>>
>> for the old codes, it works:
>> sdhci_sirf_probe gpio_to_irq: 128 160 193
>
> Does it work if you add the hunk below?
>
> I think the problem is that with irq_domain_add_linear, we don't create
> a mapping for all the interrupts right away.
>
> 	Arnd
>
> diff --git a/drivers/pinctrl/pinctrl-sirf.c
> b/drivers/pinctrl/pinctrl-sirf.c
> index d02498b..5f031ca 100644
> --- a/drivers/pinctrl/pinctrl-sirf.c
> +++ b/drivers/pinctrl/pinctrl-sirf.c
> @@ -1347,7 +1347,7 @@ static inline int sirfsoc_gpio_to_irq(struct gpio_chip
> *chip, unsigned offset)
>  	struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
>  		struct sirfsoc_gpio_bank, chip);
>
> -	return irq_find_mapping(bank->domain, offset);
> +	return irq_create_mapping(bank->domain, offset);

yes. this one works now. the only problem is
drivers/irqchip/irq-sirfsoc.c  still fails by irq_domain_add_linear().
the old irq_domain_add_legacy() works for
drivers/irqchip/irq-sirfsoc.c.

-barry

[PATCH 7/8] ARM: sirf: enable multiplatform support

[Barry Song]

> diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h
> b/arch/arm/mach-prima2/include/mach/uncompress.h
> deleted file mode 100644
> index d1513a3..0000000
> --- a/arch/arm/mach-prima2/include/mach/uncompress.h
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -/*
> - * arch/arm/mach-prima2/include/mach/uncompress.h
> - *
> - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group
> company.
> - *
> - * Licensed under GPLv2 or later.
> - */
> -
> -#ifndef __ASM_ARCH_UNCOMPRESS_H
> -#define __ASM_ARCH_UNCOMPRESS_H
> -
> -#include <linux/io.h>
> -#include <mach/hardware.h>
> -#include <mach/uart.h>
> -
> -void arch_decomp_setup(void)
> -{
> -}
> -
> -static __inline__ void putc(char c)
> -{
> -	/*
> -	 * during kernel decompression, all mappings are flat:
> -	 *  virt_addr == phys_addr
> -	 */
> -	if (!SIRFSOC_UART1_PA_BASE)
> -		return;
> -
> -	while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE +
> SIRFSOC_UART_TXFIFO_STATUS)
> -		& SIRFSOC_UART1_TXFIFO_FULL)
> -		barrier();
> -
> -	__raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE +
> SIRFSOC_UART_TXFIFO_DATA);
> -}
> -
> -static inline void flush(void)
> -{
> -}
> -
> -#endif

will this mean we will don't support "uncompress ..." printed in the
early uncompress stage before lluart work?

-barry

[PATCH 8/8] ARM: sirf: enable support in multi_v7_defconfig

[Barry Song]

2013/3/20, Arnd Bergmann <arnd@arndb.de>:
> This enables all sirf specific drivers in the defconfig.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Reviewed-by: Barry Song <Baohua.Song@csr.com>

[PATCH 4/8] ARM: sirf: enable sparse IRQ

[Barry Song]

2013/3/20, Arnd Bergmann <arnd@arndb.de>:
> Now that both irqchips for sirf are converted to not rely on
> legacy domains, let's move all of the platform over to sparse
> IRQ.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
>  arch/arm/Kconfig                         |  1 +
>  arch/arm/mach-prima2/include/mach/irqs.h | 17 -----------------
>  2 files changed, 1 insertion(+), 17 deletions(-)
>  delete mode 100644 arch/arm/mach-prima2/include/mach/irqs.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5bfd584..c674b32 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -427,6 +427,7 @@ config ARCH_SIRF
>  	select PINCTRL
>  	select PINCTRL_SIRF
>  	select USE_OF
> +	select SPARSE_IRQ
>  	help
>  	  Support for CSR SiRFprimaII/Marco/Polo platforms
>
> diff --git a/arch/arm/mach-prima2/include/mach/irqs.h
> b/arch/arm/mach-prima2/include/mach/irqs.h
> deleted file mode 100644
> index b778a0f..0000000
> --- a/arch/arm/mach-prima2/include/mach/irqs.h
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -/*
> - * arch/arm/mach-prima2/include/mach/irqs.h
> - *
> - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group
> company.
> - *
> - * Licensed under GPLv2 or later.
> - */
> -
> -#ifndef __ASM_ARCH_IRQS_H
> -#define __ASM_ARCH_IRQS_H
> -
> -#define SIRFSOC_INTENAL_IRQ_START  0
> -#define SIRFSOC_INTENAL_IRQ_END    127
> -#define SIRFSOC_GPIO_IRQ_START     (SIRFSOC_INTENAL_IRQ_END + 1)
> -#define NR_IRQS	288

after dropping NR_IRQS and enabling SPARSE_IRQ, should we add .nr_irqs
= 288 to MACHINE_START(ATLAS6/PRIMA2/MARCO_DT...)?

-barry

[PATCH 4/8] ARM: sirf: enable sparse IRQ

[Arnd Bergmann]

On Monday 25 March 2013, Barry Song wrote:
> > -#define SIRFSOC_INTENAL_IRQ_START  0
> > -#define SIRFSOC_INTENAL_IRQ_END    127
> > -#define SIRFSOC_GPIO_IRQ_START     (SIRFSOC_INTENAL_IRQ_END + 1)
> > -#define NR_IRQS      288
> 
> after dropping NR_IRQS and enabling SPARSE_IRQ, should we add .nr_irqs
> = 288 to MACHINE_START(ATLAS6/PRIMA2/MARCO_DT...)?
> 

No, that's only necessary as long as we need legacy irq domains. If we
can figure out how to get the irqchip driver to use the linear domain,
it is not needed any more. If we move only the pinctrl domain to
linear but leave the main irqchip as legacy, we should set .nr_irqs=128.

	Arnd

[PATCH 7/8] ARM: sirf: enable multiplatform support

[Arnd Bergmann]

On Monday 25 March 2013, Barry Song wrote:
> will this mean we will don't support "uncompress ..." printed in the
> early uncompress stage before lluart work?

No, with the work that Shawn Guo did, the uncompress code will fall back
to an implementation based on the debug_ll code now, so you still get
the early output.

	Arnd

[PATCH 3/8] ARM: sirf: move irq driver to drivers/irqchip

[Arnd Bergmann]

On Monday 25 March 2013, Barry Song wrote:
> 2013/3/25, Arnd Bergmann <arnd@arndb.de>:
> > On Monday 25 March 2013, Barry Song wrote:
> >> 2013/3/20, Arnd Bergmann <arnd@arndb.de>:
> >> this breaks the hwirq and irq mapping. the hwirq 0 is mapped to
> >> no_irqs, then setup_irq will fail in
> >> drivers/clocksource/timer-prima2.c.
> >
> > Hmm, I don't understand yet what is going on there. This should create
> > a domain with all dynamically allocated interrupt descriptors,
> > and the hwirq number is just local to the controller then.
> 
> suppose we think the hardware register flag bit of timer-prima2 is 0,
> irq_of_parse_and_map() will return 16 in patch2 for the timer-prima2
> which uses the 1st hardware IRQ in the system.
> 
> if add nr_irqs=288 in ATLAS6 machine, irq_of_parse_and_map() will
> return 288 in patch2. it looks like the first hw irq will always be
> mapped to nr_irqs.

right.

> > Without patch 2 of the series, this would fail, because that interrupt
> > is not mapped, but as far as I can tell, we correctly instantiate
> > the domain here, so the irq_of_parse_and_map() in sirfsoc_of_timer_map
> > should return a valid interrupt number. Can you check what it returns
> > instead? Does it work if you revert to a legacy domain here?
> 
> actually patch2 can work without patch3 by irq_domain_add legacy. as
> you can see, my old timer-marco.c uses irq_of_parse_and_map() instead
> of reading interrupts manually.

Yes, irq_of_parse_and_map() should always work.

>         void __iomem *base = of_iomap(np, 0);
>         if (!base)
>                 panic("unable to map intc cpu registers\n");
> 
> -       sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
> +       sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0,
>                                  &irq_domain_simple_ops, base);
> 
>         sirfsoc_alloc_gc(base, 0, 32);
> ...
> drivers/pinctrl/pinctrl-sirf.c:
> -                bank->domain = irq_domain_add_linear(np,
> SIRFSOC_GPIO_BANK_SIZE,
> +                bank->domain = irq_domain_add_legacy(np,
> SIRFSOC_GPIO_BANK_SIZE,
> +                        128 + i * SIRFSOC_GPIO_BANK_SIZE, 0,
>                         &sirfsoc_gpio_irq_simple_ops, bank);

Right, but if we do this, we encode static IRQ numbers into the
irqchip drivers, which should not be necessary if all interrupts
can be mapped dynamically.

This means that the interrupt numbers that Linux reports in
/proc/interrupts will all change, but I don't see anything that
still depends on those, unless you have additional out of tree
patches that rely on hardcoded numbers.

Digging a bit deeper, I found that the generic irqchip implemmentation
does not deal with linear irq domains yet. There was a patch[1] least
year from Rob Herring, but it never got merged. I guess we can move
back to using the legacy domain for drivers/irqchip/irq-sirfsoc.c for
now and hardwire the assumption that its interrupts start at number 0.

	Arnd

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/082455.html

[PATCH 0/8] SIRF multiplatform support

[Arnd Bergmann]

On Wednesday 20 March 2013, Arnd Bergmann wrote:
> Here goes another one. Since the SIRF platforms are relatively new and
> clean, they are easy to convert to multiplatform, so I did that and
> fixed up a few other things in the process as well.
> 
> Barry, could you test these and report back if everything still works
> for you?

Hi Barry,

I've updated the branch at 

git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git prima2/multiplatform

now to fix the problems you pointed out. Can you check if it all works now?

	Arnd

[PATCH 0/8] SIRF multiplatform support

[Barry Song]

2013/3/25, Arnd Bergmann <arnd@arndb.de>:
> On Wednesday 20 March 2013, Arnd Bergmann wrote:
>> Here goes another one. Since the SIRF platforms are relatively new and
>> clean, they are easy to convert to multiplatform, so I did that and
>> fixed up a few other things in the process as well.
>>
>> Barry, could you test these and report back if everything still works
>> for you?
>
> Hi Barry,
>
> I've updated the branch at
>
> git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> prima2/multiplatform
>
> now to fix the problems you pointed out. Can you check if it all works now?
>
> 	Arnd
Hi Arnd,
everything is fine except that:
1. Shawn Guo's uncompress debug patch is not in the tree, so the
uncompress debug is break. but that is not an issue

2. i want to change:
#define SIRFSOC_NUM_IRQS                128
to:
#define SIRFSOC_NUM_IRQS                64
the old 128 is suitable for marco, in fact prima2/atlas6 is 64. in
order that all SoCs can use the same irqs.h headfile, i pick the
biggest value. since now we have moved to linear irq, i want to fix it
back.

then nr_irqs in DT_MACHINE_START(ATLAS6_DT/PRIMA2_DT should also take 64.

3. will we have similar codes between prima2 and marco for initilizing
timer tick?
CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick",
sirfsoc_of_timer_init );
CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick",
sirfsoc_prima2_timer_init);

will we change "CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer,
"sirf,marco-tick", sirfsoc_of_timer_init )" to things like
"CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick",
sirfsoc_marco_timer_init )" as prima2 does and drop

anyway, this is a trivial issue.

-barry

[PATCH 0/8] SIRF multiplatform support

[Arnd Bergmann]

On Tuesday 26 March 2013, Barry Song wrote:
> everything is fine except that:
> 1. Shawn Guo's uncompress debug patch is not in the tree, so the
> uncompress debug is break. but that is not an issue

Right.

> 2. i want to change:
> #define SIRFSOC_NUM_IRQS                128
> to:
> #define SIRFSOC_NUM_IRQS                64
> the old 128 is suitable for marco, in fact prima2/atlas6 is 64. in
> order that all SoCs can use the same irqs.h headfile, i pick the
> biggest value. since now we have moved to linear irq, i want to fix it
> back.
>
> then nr_irqs in DT_MACHINE_START(ATLAS6_DT/PRIMA2_DT should also take 64.

Yes, sounds good.
 
> 3. will we have similar codes between prima2 and marco for initilizing
> timer tick?
> CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick",
> sirfsoc_of_timer_init );
> CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick",
> sirfsoc_prima2_timer_init);
> 
> will we change "CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer,
> "sirf,marco-tick", sirfsoc_of_timer_init )" to things like
> "CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick",
> sirfsoc_marco_timer_init )" as prima2 does and drop
> 
> anyway, this is a trivial issue.

Yes, it seemed less invasive to do it without that change for marco.

Since these changes are now just cosmetic, how about I pull the branch
I have into the arm-soc tree and you do any further changes you'd like
on top?

It may also be a good point in time now to rename the directory to
mach-sirf or mach-sirfsoc now as you suggested for an earlier release,
since we have moved a lot of code out of it now. Any patches against
the drivers that are getting moved will have to change anyway.

	Arnd

[PATCH 0/8] SIRF multiplatform support

[Barry Song]

2013/3/26 Arnd Bergmann <arnd@arndb.de>:
> On Tuesday 26 March 2013, Barry Song wrote:
>> everything is fine except that:
>> 1. Shawn Guo's uncompress debug patch is not in the tree, so the
>> uncompress debug is break. but that is not an issue
>
> Right.
>
>> 2. i want to change:
>> #define SIRFSOC_NUM_IRQS                128
>> to:
>> #define SIRFSOC_NUM_IRQS                64
>> the old 128 is suitable for marco, in fact prima2/atlas6 is 64. in
>> order that all SoCs can use the same irqs.h headfile, i pick the
>> biggest value. since now we have moved to linear irq, i want to fix it
>> back.
>>
>> then nr_irqs in DT_MACHINE_START(ATLAS6_DT/PRIMA2_DT should also take 64.
>
> Yes, sounds good.
>
>> 3. will we have similar codes between prima2 and marco for initilizing
>> timer tick?
>> CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick",
>> sirfsoc_of_timer_init );
>> CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick",
>> sirfsoc_prima2_timer_init);
>>
>> will we change "CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer,
>> "sirf,marco-tick", sirfsoc_of_timer_init )" to things like
>> "CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick",
>> sirfsoc_marco_timer_init )" as prima2 does and drop
>>
>> anyway, this is a trivial issue.
>
> Yes, it seemed less invasive to do it without that change for marco.
>
> Since these changes are now just cosmetic, how about I pull the branch
> I have into the arm-soc tree and you do any further changes you'd like
> on top?

agree.

>
> It may also be a good point in time now to rename the directory to
> mach-sirf or mach-sirfsoc now as you suggested for an earlier release,
> since we have moved a lot of code out of it now. Any patches against
> the drivers that are getting moved will have to change anyway.

yes. i do like we rename mach-prima2 to mach-sirf. as prima2, atlas6,
marco are all CSR SiRF family SoCs.

>
>         Arnd

-barry