* [PATCH 01/11] drm/i915: sprite support for ValleyView v3
@ 2013-03-28 16:55 Jesse Barnes
2013-03-28 16:55 ` [PATCH 02/11] drm/i915: add sprite assertion function for VLV Jesse Barnes
` (11 more replies)
0 siblings, 12 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
No constant alpha yet though, that needs a new ioctl and/or property to
get/set.
v2: use drm_plane_format_cpp (Ville)
fix up vlv_disable_plane, remove IVB bits (Ville)
remove error path rework (Ville)
fix component order confusion (Ville)
clean up platform init (Ville)
use compute_offset_xtiled (Ville)
v3: fix up more format confusion (Ville)
update to new page offset function (Ville)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_dma.c | 4 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 57 +++++++++
drivers/gpu/drm/i915/intel_display.c | 13 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_sprite.c | 213 ++++++++++++++++++++++++++++++++--
6 files changed, 277 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ebcfe2e..4be58e3 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
mutex_init(&dev_priv->rps.hw_lock);
mutex_init(&dev_priv->modeset_restore_lock);
+ dev_priv->num_plane = 1;
+ if (IS_VALLEYVIEW(dev))
+ dev_priv->num_plane = 2;
+
ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
if (ret)
goto out_gem_unload;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1657d873..2832cdb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -914,6 +914,7 @@ typedef struct drm_i915_private {
bool enable_hotplug_processing;
int num_pch_pll;
+ int num_plane;
unsigned long cfb_size;
unsigned int cfb_fb;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bceca11..d0f7cb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3261,6 +3261,63 @@
#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
+#define _SPACNTR 0x72180
+#define SP_ENABLE (1<<31)
+#define SP_GEAMMA_ENABLE (1<<30)
+#define SP_PIXFORMAT_MASK (0xf<<26)
+#define SP_FORMAT_YUV422 (0<<26)
+#define SP_FORMAT_BGR565 (5<<26)
+#define SP_FORMAT_BGRX8888 (6<<26)
+#define SP_FORMAT_BGRA8888 (7<<26)
+#define SP_FORMAT_RGBX1010102 (8<<26)
+#define SP_FORMAT_RGBA1010102 (9<<26)
+#define SP_FORMAT_RGBX8888 (0xe<<26)
+#define SP_FORMAT_RGBA8888 (0xf<<26)
+#define SP_SOURCE_KEY (1<<22)
+#define SP_YUV_BYTE_ORDER_MASK (3<<16)
+#define SP_YUV_ORDER_YUYV (0<<16)
+#define SP_YUV_ORDER_UYVY (1<<16)
+#define SP_YUV_ORDER_YVYU (2<<16)
+#define SP_YUV_ORDER_VYUY (3<<16)
+#define SP_TILED (1<<10)
+#define _SPALINOFF 0x72184
+#define _SPASTRIDE 0x72188
+#define _SPAPOS 0x7218c
+#define _SPASIZE 0x72190
+#define _SPAKEYMINVAL 0x72194
+#define _SPAKEYMSK 0x72198
+#define _SPASURF 0x7219c
+#define _SPAKEYMAXVAL 0x721a0
+#define _SPATILEOFF 0x721a4
+#define _SPACONSTALPHA 0x721a8
+#define _SPAGAMC 0x721f4
+
+#define _SPBCNTR 0x72280
+#define _SPBLINOFF 0x72284
+#define _SPBSTRIDE 0x72288
+#define _SPBPOS 0x7228c
+#define _SPBSIZE 0x72290
+#define _SPBKEYMINVAL 0x72294
+#define _SPBKEYMSK 0x72298
+#define _SPBSURF 0x7229c
+#define _SPBKEYMAXVAL 0x722a0
+#define _SPBTILEOFF 0x722a4
+#define _SPBCONSTALPHA 0x722a8
+#define _SPBGAMC 0x722f4
+
+#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
+
/* VBIOS regs */
#define VGACNTRL 0x71400
# define VGA_DISP_DISABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7307974..537cd0f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8525,6 +8525,8 @@ int intel_framebuffer_init(struct drm_device *dev,
case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_BGRX8888:
case DRM_FORMAT_ARGB8888:
break;
case DRM_FORMAT_XRGB1555:
@@ -8855,7 +8857,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- int i, ret;
+ int i, j, ret;
drm_mode_config_init(dev);
@@ -8891,9 +8893,12 @@ void intel_modeset_init(struct drm_device *dev)
for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
intel_crtc_init(dev, i);
- ret = intel_plane_init(dev, i);
- if (ret)
- DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
+ for (j = 0; j < dev_priv->num_plane; j++) {
+ ret = intel_plane_init(dev, i, j);
+ if (ret)
+ DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
+ i, j, ret);
+ }
}
intel_cpu_pll_init(dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 599e978..8940741 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -242,6 +242,7 @@ struct intel_crtc {
struct intel_plane {
struct drm_plane base;
+ int plane;
enum pipe pipe;
struct drm_i915_gem_object *obj;
bool can_scale;
@@ -488,7 +489,7 @@ extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern int intel_edp_target_clock(struct intel_encoder *,
struct drm_display_mode *mode);
extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
-extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
+extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
enum plane plane);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 1b6eb76..2699026 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -37,6 +37,174 @@
#include "i915_drv.h"
static void
+vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
+ struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
+ unsigned int crtc_w, unsigned int crtc_h,
+ uint32_t x, uint32_t y,
+ uint32_t src_w, uint32_t src_h)
+{
+ struct drm_device *dev = dplane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(dplane);
+ int pipe = intel_plane->pipe;
+ int plane = intel_plane->plane;
+ u32 sprctl;
+ unsigned long sprsurf_offset, linear_offset;
+ int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+
+ sprctl = I915_READ(SPCNTR(pipe, plane));
+
+ /* Mask out pixel format bits in case we change it */
+ sprctl &= ~SP_PIXFORMAT_MASK;
+ sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
+ sprctl &= ~SP_TILED;
+
+ switch (fb->pixel_format) {
+ case DRM_FORMAT_YUYV:
+ sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
+ break;
+ case DRM_FORMAT_YVYU:
+ sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
+ break;
+ case DRM_FORMAT_UYVY:
+ sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
+ break;
+ case DRM_FORMAT_VYUY:
+ sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
+ break;
+ case DRM_FORMAT_RGB565:
+ sprctl |= SP_FORMAT_BGR565;
+ break;
+ case DRM_FORMAT_XRGB8888:
+ sprctl |= SP_FORMAT_BGRX8888;
+ break;
+ case DRM_FORMAT_ARGB8888:
+ sprctl |= SP_FORMAT_BGRA8888;
+ break;
+ case DRM_FORMAT_XBGR2101010:
+ sprctl |= SP_FORMAT_RGBX1010102;
+ break;
+ case DRM_FORMAT_ABGR2101010:
+ sprctl |= SP_FORMAT_RGBA1010102;
+ break;
+ case DRM_FORMAT_XBGR8888:
+ sprctl |= SP_FORMAT_RGBX8888;
+ break;
+ case DRM_FORMAT_ABGR8888:
+ sprctl |= SP_FORMAT_RGBA8888;
+ break;
+ default:
+ /*
+ * If we get here one of the upper layers failed to filter
+ * out the unsupported plane formats
+ */
+ BUG();
+ break;
+ }
+
+ if (obj->tiling_mode != I915_TILING_NONE)
+ sprctl |= SP_TILED;
+
+ sprctl |= SP_ENABLE;
+
+ /* Sizes are 0 based */
+ src_w--;
+ src_h--;
+ crtc_w--;
+ crtc_h--;
+
+ intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
+
+ I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
+ I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
+
+ linear_offset = y * fb->pitches[0] + x * pixel_size;
+ sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
+ obj->tiling_mode,
+ pixel_size,
+ fb->pitches[0]);
+ linear_offset -= sprsurf_offset;
+
+ if (obj->tiling_mode != I915_TILING_NONE)
+ I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
+ else
+ I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
+
+ I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
+ I915_WRITE(SPCNTR(pipe, plane), sprctl);
+ I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset +
+ sprsurf_offset);
+ POSTING_READ(SPSURF(pipe, plane));
+}
+
+static void
+vlv_disable_plane(struct drm_plane *dplane)
+{
+ struct drm_device *dev = dplane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(dplane);
+ int pipe = intel_plane->pipe;
+ int plane = intel_plane->plane;
+
+ I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
+ ~SP_ENABLE);
+ /* Activate double buffered register update */
+ I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
+ POSTING_READ(SPSURF(pipe, plane));
+}
+
+static int
+vlv_update_colorkey(struct drm_plane *dplane,
+ struct drm_intel_sprite_colorkey *key)
+{
+ struct drm_device *dev = dplane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(dplane);
+ int pipe = intel_plane->pipe;
+ int plane = intel_plane->plane;
+ u32 sprctl;
+
+ if (key->flags & I915_SET_COLORKEY_DESTINATION)
+ return -EINVAL;
+
+ I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
+ I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
+ I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
+
+ sprctl = I915_READ(SPCNTR(pipe, plane));
+ sprctl &= ~SP_SOURCE_KEY;
+ if (key->flags & I915_SET_COLORKEY_SOURCE)
+ sprctl |= SP_SOURCE_KEY;
+ I915_WRITE(SPCNTR(pipe, plane), sprctl);
+
+ POSTING_READ(SPKEYMSK(pipe, plane));
+
+ return 0;
+}
+
+static void
+vlv_get_colorkey(struct drm_plane *dplane,
+ struct drm_intel_sprite_colorkey *key)
+{
+ struct drm_device *dev = dplane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(dplane);
+ int pipe = intel_plane->pipe;
+ int plane = intel_plane->plane;
+ u32 sprctl;
+
+ key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
+ key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
+ key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
+
+ sprctl = I915_READ(SPCNTR(pipe, plane));
+ if (sprctl & SP_SOURCE_KEY)
+ key->flags = I915_SET_COLORKEY_SOURCE;
+ else
+ key->flags = I915_SET_COLORKEY_NONE;
+}
+
+static void
ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
@@ -670,8 +838,22 @@ static uint32_t snb_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static uint32_t vlv_plane_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+};
+
int
-intel_plane_init(struct drm_device *dev, enum pipe pipe)
+intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
struct intel_plane *intel_plane;
unsigned long possible_crtcs;
@@ -710,14 +892,26 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
intel_plane->can_scale = false;
else
intel_plane->can_scale = true;
- intel_plane->max_downscale = 2;
- intel_plane->update_plane = ivb_update_plane;
- intel_plane->disable_plane = ivb_disable_plane;
- intel_plane->update_colorkey = ivb_update_colorkey;
- intel_plane->get_colorkey = ivb_get_colorkey;
-
- plane_formats = snb_plane_formats;
- num_plane_formats = ARRAY_SIZE(snb_plane_formats);
+
+ if (IS_VALLEYVIEW(dev)) {
+ intel_plane->max_downscale = 1;
+ intel_plane->update_plane = vlv_update_plane;
+ intel_plane->disable_plane = vlv_disable_plane;
+ intel_plane->update_colorkey = vlv_update_colorkey;
+ intel_plane->get_colorkey = vlv_get_colorkey;
+
+ plane_formats = vlv_plane_formats;
+ num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
+ } else {
+ intel_plane->max_downscale = 2;
+ intel_plane->update_plane = ivb_update_plane;
+ intel_plane->disable_plane = ivb_disable_plane;
+ intel_plane->update_colorkey = ivb_update_colorkey;
+ intel_plane->get_colorkey = ivb_get_colorkey;
+
+ plane_formats = snb_plane_formats;
+ num_plane_formats = ARRAY_SIZE(snb_plane_formats);
+ }
break;
default:
@@ -726,6 +920,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
}
intel_plane->pipe = pipe;
+ intel_plane->plane = plane;
possible_crtcs = (1 << pipe);
ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
&intel_plane_funcs,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 02/11] drm/i915: add sprite assertion function for VLV
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-03-28 16:55 ` [PATCH 03/11] drm/i915: update VLV PLL and DPIO code v8 Jesse Barnes
` (10 subsequent siblings)
11 siblings, 0 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
Need to make sure sprites are disabled before shutting off a pipe.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 537cd0f..58e3a7c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1288,6 +1288,25 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
}
}
+static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ int reg, i;
+ u32 val;
+
+ if (!IS_VALLEYVIEW(dev_priv->dev))
+ return;
+
+ /* Need to check both planes against the pipe */
+ for (i = 0; i < dev_priv->num_plane; i++) {
+ reg = SPCNTR(pipe, i);
+ val = I915_READ(reg);
+ WARN((val & SP_ENABLE),
+ "sprite %d assertion failure, should be off on pipe %c but is still active\n",
+ pipe * 2 + i, pipe_name(pipe));
+ }
+}
+
static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
{
u32 val;
@@ -1872,6 +1891,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
* or we might hang the display.
*/
assert_planes_disabled(dev_priv, pipe);
+ assert_sprites_disabled(dev_priv, pipe);
/* Don't disable pipe A or pipe A PLLs if needed */
if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 03/11] drm/i915: update VLV PLL and DPIO code v8
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
2013-03-28 16:55 ` [PATCH 02/11] drm/i915: add sprite assertion function for VLV Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-04-02 18:47 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 04/11] drm/i915/dp: fix up VLV DP handling v2 Jesse Barnes
` (9 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Update
vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
appropriate programming.
We need to make sure that the tx lane reset occurs in both the full mode
set and DPMS paths, so factor things out to allow that.
v2: use different DPIO_DIVISOR values for VGA and DisplayPort
v3: Fix update pll logic to use same DPIO_DIVISOR & DPIO_REFSFR values
for all display interfaces
v4: collapse with various updates
v5: squash with crtc enable/pll enable bits
v6: split out DP code (jbarnes)
put phyready check under IS_VALLEYVIEW (jbarnes)
remove unneeded check in 9xx pll div update (Jani)
wrap VLV pll update call in IS_VALLEYVIEW (Jani)
move port enable back to end of crtc enable (jbarnes)
put phyready check under IS_VALLEYVIEW (jbarnes)
v7: fix up conflicts against latest drm-intel-next-queued
v8: use DPIO reg names, fix pipes (Jani)
from mPhy_registers_VLV2_ww20p5 doc
Signed-off-by: Pallavi G <pallavi.g@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 107 ++++++++++++-
drivers/gpu/drm/i915/intel_display.c | 274 ++++++++++++++++++++++++++--------
2 files changed, 320 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d0f7cb9..858a712 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -362,6 +362,11 @@
#define DPIO_SFR_BYPASS (1<<1)
#define DPIO_RESET (1<<0)
+#define _DPIO_TX3_SWING_CTL4_A 0x690
+#define _DPIO_TX3_SWING_CTL4_B 0x2a90
+#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \
+ _DPIO_TX3_SWING_CTL4_B)
+
#define _DPIO_DIV_A 0x800c
#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
#define DPIO_K_SHIFT (24) /* 4 bits */
@@ -389,14 +394,109 @@
#define _DPIO_CORE_CLK_B 0x803c
#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
+#define _DPIO_IREF_CTL_A 0x8040
+#define _DPIO_IREF_CTL_B 0x8060
+#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
+
+#define DPIO_IREF_BCAST 0xc044
+#define _DPIO_IREF_A 0x8044
+#define _DPIO_IREF_B 0x8064
+#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)
+
+#define _DPIO_PLL_CML_A 0x804c
+#define _DPIO_PLL_CML_B 0x806c
+#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)
+
#define _DPIO_LFP_COEFF_A 0x8048
#define _DPIO_LFP_COEFF_B 0x8068
#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
+#define DPIO_CALIBRATION 0x80ac
+
#define DPIO_FASTCLK_DISABLE 0x8100
-#define DPIO_DATA_CHANNEL1 0x8220
-#define DPIO_DATA_CHANNEL2 0x8420
+#define _DPIO_PCS_TX_0 0x8200
+#define _DPIO_PCS_TX_1 0x8400
+#define DPIO_PCS_TX_LANE2_RESET (1<<16)
+#define DPIO_PCS_TX_LANE1_RESET (1<<7)
+#define DPIO_PCS_TX(pipe) _PIPE(pipe, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)
+
+#define _DPIO_PCS_CLK_0 0x8204
+#define _DPIO_PCS_CLK_1 0x8404
+#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
+#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
+#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
+#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
+#define DPIO_PCS_CLK(pipe) _PIPE(pipe, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)
+
+#define _DPIO_PCS_CTL_OVR1_A 0x8224
+#define _DPIO_PCS_CTL_OVR1_B 0x8424
+#define DPIO_PCS_CTL_OVER1(pipe) _PIPE(pipe, _DPIO_PCS_CTL_OVR1_A, \
+ _DPIO_PCS_CTL_OVR1_B)
+
+#define _DPIO_PCS_STAGGER0_A 0x822c
+#define _DPIO_PCS_STAGGER0_B 0x842c
+#define DPIO_PCS_STAGGER0(pipe) _PIPE(pipe, _DPIO_PCS_STAGGER0_A, \
+ _DPIO_PCS_STAGGER0_B)
+
+#define _DPIO_PCS_STAGGER1_A 0x8230
+#define _DPIO_PCS_STAGGER1_B 0x8430
+#define DPIO_PCS_STAGGER1(pipe) _PIPE(pipe, _DPIO_PCS_STAGGER1_A, \
+ _DPIO_PCS_STAGGER1_B)
+
+#define _DPIO_PCS_CLOCKBUF0_A 0x8238
+#define _DPIO_PCS_CLOCKBUF0_B 0x8438
+#define DPIO_PCS_CLOCKBUF0(pipe) _PIPE(pipe, _DPIO_PCS_CLOCKBUF0_A, \
+ _DPIO_PCS_CLOCKBUF0_B)
+
+#define _DPIO_PCS_CLOCKBUF8_A 0x825c
+#define _DPIO_PCS_CLOCKBUF8_B 0x845c
+#define DPIO_PCS_CLOCKBUF8(pipe) _PIPE(pipe, _DPIO_PCS_CLOCKBUF8_A, \
+ _DPIO_PCS_CLOCKBUF8_B)
+
+#define _DPIO_TX_SWING_CTL2_A 0x8288
+#define _DPIO_TX_SWING_CTL2_B 0x8488
+#define DPIO_TX_SWING_CTL2(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL2_A, \
+ _DPIO_TX_SWING_CTL2_B)
+
+#define _DPIO_TX_SWING_CTL3_A 0x828c
+#define _DPIO_TX_SWING_CTL3_B 0x848c
+#define DPIO_TX_SWING_CTL3(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL3_A, \
+ _DPIO_TX_SWING_CTL3_B)
+
+#define _DPIO_TX_SWING_CTL4_A 0x8290
+#define _DPIO_TX_SWING_CTL4_B 0x8490
+#define DPIO_TX_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \
+ _DPIO_TX_SWING_CTL4_B)
+
+#define _DPIO_TX_OCALINIT_0 0x8294
+#define _DPIO_TX_OCALINIT_1 0x8494
+#define DPIO_TX_OCALINIT_EN (1<<31)
+#define DPIO_TX_OCALINIT(pipe) _PIPE(pipe, _DPIO_TX_OCALINIT_0, \
+ _DPIO_TX_OCALINIT_1)
+
+#define _DPIO_TX_CTL_0 0x82ac
+#define _DPIO_TX_CTL_1 0x84ac
+#define DPIO_TX_CTL(pipe) _PIPE(pipe, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)
+
+#define _DPIO_TX_LANE_0 0x82b8
+#define _DPIO_TX_LANE_1 0x84b8
+#define DPIO_TX_LANE(pipe) _PIPE(pipe, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
+
+#define _DPIO_DATA_CHANNEL1 0x8220
+#define _DPIO_DATA_CHANNEL2 0x8420
+#define DPIO_DATA_CHANNEL(pipe) _PIPE(pipe, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
+
+#define _DPIO_DATA_LANE0 0x0220
+#define _DPIO_DATA_LANE1 0x0420
+#define _DPIO_DATA_LANE2 0x2620
+#define _DPIO_DATA_LANE3 0x2820
+#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
+#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1 0x8220
+#define DPIO_DATA_CHANNEL2 0x8420
+
+#define DPIO_TX_BROADCAST 0xc044
/*
* Fence registers
@@ -957,7 +1057,10 @@
#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
#define DPLL_LOCK_VLV (1<<15)
+#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
+#define DPLL_PORTC_READY_MASK (0xf << 4)
+#define DPLL_PORTB_READY_MASK (0xf)
#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
/*
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 58e3a7c..9cb0b53 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3696,6 +3696,72 @@ g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
}
}
+static void vlv_pll_enable_reset(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
+ u32 val;
+ val = intel_dpio_read(dev_priv, _DPIO_DATA_LANE0);
+ if (pipe)
+ val |= (1<<21);
+ val |= (1<<20);
+ intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, val);
+
+ intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(pipe),
+ 0x00760018);
+ intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(pipe),
+ 0x00400888);
+
+ intel_dpio_write(dev_priv, DPIO_PCS_TX(pipe),
+ DPIO_PCS_TX_LANE2_RESET |
+ DPIO_PCS_TX_LANE1_RESET);
+ intel_dpio_write(dev_priv, DPIO_PCS_CLK(pipe),
+ DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
+ DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
+ (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
+ DPIO_PCS_CLK_SOFT_RESET);
+
+ intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(pipe), 0);
+ intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(pipe),
+ 0x2b245f5f);
+ intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(pipe),
+ 0x5578b83a);
+ intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(pipe),
+ 0x0c782040);
+ intel_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(pipe),
+ 0x2b247878);
+ intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(pipe), 0x00030000);
+ intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(pipe),
+ 0x00002000);
+ intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(pipe),
+ DPIO_TX_OCALINIT_EN);
+
+ }
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+ u32 val;
+ val = intel_dpio_read(dev_priv, _DPIO_DATA_LANE2);
+ if (pipe)
+ val |= (1<<21);
+ val |= (1<<20);
+ intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, val);
+
+ intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(pipe),
+ 0x00760018);
+ intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(pipe),
+ 0x00400888);
+
+ intel_dpio_write(dev_priv, DPIO_PCS_TX(pipe), 0x10080);
+ intel_dpio_write(dev_priv, DPIO_PCS_CLK(pipe), 0x00600060);
+ }
+}
+
static void i9xx_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -3704,6 +3770,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
+ u32 port_mask;
WARN_ON(!crtc->enabled);
@@ -3715,10 +3782,27 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
intel_enable_pll(dev_priv, pipe);
+ if (IS_VALLEYVIEW(dev)) {
+ mutex_lock(&dev_priv->dpio_lock);
+ vlv_pll_enable_reset(crtc);
+ mutex_unlock(&dev_priv->dpio_lock);
+ }
+
for_each_encoder_on_crtc(dev, crtc, encoder)
if (encoder->pre_enable)
encoder->pre_enable(encoder);
+ if (IS_VALLEYVIEW(dev)) {
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ port_mask = DPLL_PORTB_READY_MASK;
+ else
+ port_mask = DPLL_PORTC_READY_MASK; /* eDP on port C */
+
+ if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 100))
+ DRM_ERROR("timed out waiting for port ready\n");
+ }
+
intel_enable_pipe(dev_priv, pipe, false);
intel_enable_plane(dev_priv, plane, pipe);
if (IS_G4X(dev))
@@ -3770,6 +3854,21 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
I915_WRITE(PFIT_CONTROL, 0);
+ for_each_encoder_on_crtc(dev, crtc, encoder)
+ if (encoder->post_disable)
+ encoder->post_disable(encoder);
+
+ /* Reset lane for VLV platform*/
+ if (IS_VALLEYVIEW(dev)) {
+ mutex_lock(&dev_priv->dpio_lock);
+ intel_dpio_write(dev_priv, DPIO_PCS_TX(pipe), 0x00000000);
+ intel_dpio_write(dev_priv, DPIO_PCS_CLK(pipe), 0x00e00060);
+
+ if (pipe)
+ vlv_init_dpio(dev);
+ mutex_unlock(&dev_priv->dpio_lock);
+ }
+
intel_disable_pll(dev_priv, pipe);
intel_crtc->active = false;
@@ -4338,6 +4437,31 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
}
}
+static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
+{
+ u32 reg_val;
+
+ /*
+ * PLLB opamp always calibrates to max value of 0x3f, force enable it
+ * and set it to a reasonable value instead.
+ */
+ reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
+ reg_val &= 0xffffff30;
+ intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+
+ reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
+ reg_val &= 0x8cffffff;
+ intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
+
+ reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
+ reg_val &= 0xffffff00;
+ intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+
+ reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
+ reg_val &= 0xb0ffffff;
+ intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
+}
+
static void vlv_update_pll(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
@@ -4348,23 +4472,14 @@ static void vlv_update_pll(struct drm_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
- u32 dpll, mdiv, pdiv;
+ u32 dpll, mdiv;
u32 bestn, bestm1, bestm2, bestp1, bestp2;
- bool is_sdvo;
- u32 temp;
+ bool is_hdmi;
+ u32 coreclk, reg_val;
mutex_lock(&dev_priv->dpio_lock);
- is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
- intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
-
- dpll = DPLL_VGA_MODE_DIS;
- dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
- dpll |= DPLL_REFA_CLK_ENABLE_VLV;
- dpll |= DPLL_INTEGRATED_CLOCK_VLV;
-
- I915_WRITE(DPLL(pipe), dpll);
- POSTING_READ(DPLL(pipe));
+ is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
bestn = clock->n;
bestm1 = clock->m1;
@@ -4372,71 +4487,99 @@ static void vlv_update_pll(struct drm_crtc *crtc,
bestp1 = clock->p1;
bestp2 = clock->p2;
- /*
- * In Valleyview PLL and program lane counter registers are exposed
- * through DPIO interface
- */
+ /* See eDP HDMI DPIO driver vbios notes doc */
+
+ /* PLL B needs special handling */
+ if (pipe)
+ vlv_pllb_recal_opamp(dev_priv);
+
+ /* Set up Tx target for periodic Rcomp update */
+ intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
+
+ /* Disable target IRef on PLL */
+ reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
+ reg_val &= 0x00ffffff;
+ intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
+
+ intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+ if (adjusted_mode->clock == 162000)
+ intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
+ 0x009f0003);
+ else
+ intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
+ 0x00d0000f);
+
+ } else
+ intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
+ 0x009f0003);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+ if (!pipe)
+ intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+ 0x0df40000);
+ else
+ intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+ 0x0df70000);
+ } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
+ if (!pipe)
+ intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+ 0x0df70000);
+ else
+ intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+ 0x0df40000);
+ }
+
mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
mdiv |= ((bestn << DPIO_N_SHIFT));
mdiv |= (1 << DPIO_POST_DIV_SHIFT);
mdiv |= (1 << DPIO_K_SHIFT);
+ intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+
mdiv |= DPIO_ENABLE_CALIBRATION;
intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
- intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
+ coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
+ coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
+ intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
- pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
- (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
- (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
- (5 << DPIO_CLK_BIAS_CTL_SHIFT);
- intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
+ intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
- intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
+ /* Enable DPIO clock input */
+ dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
+ DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
+ if (pipe)
+ dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
POSTING_READ(DPLL(pipe));
+ udelay(150);
+
if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
DRM_ERROR("DPLL %d failed to lock\n", pipe);
- intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
-
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
- intel_dp_set_m_n(crtc, mode, adjusted_mode);
-
- I915_WRITE(DPLL(pipe), dpll);
-
- /* Wait for the clocks to stabilize. */
- POSTING_READ(DPLL(pipe));
- udelay(150);
+ if (is_hdmi) {
+ u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
- temp = 0;
- if (is_sdvo) {
- temp = intel_mode_get_pixel_multiplier(adjusted_mode);
if (temp > 1)
temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
else
temp = 0;
- }
- I915_WRITE(DPLL_MD(pipe), temp);
- POSTING_READ(DPLL_MD(pipe));
- /* Now program lane control registers */
- if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
- || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
- {
- temp = 0x1000C4;
- if(pipe == 1)
- temp |= (1 << 21);
- intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
+ I915_WRITE(DPLL_MD(pipe), temp);
+ POSTING_READ(DPLL_MD(pipe));
}
- if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
- {
- temp = 0x1000C4;
- if(pipe == 1)
- temp |= (1 << 21);
- intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
+
+ vlv_pll_enable_reset(crtc);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+ intel_dp_set_m_n(crtc, mode, adjusted_mode);
}
mutex_unlock(&dev_priv->dpio_lock);
@@ -4748,11 +4891,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
i8xx_update_pll(crtc, adjusted_mode, &clock,
has_reduced_clock ? &reduced_clock : NULL,
num_connectors);
- else if (IS_VALLEYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev)) {
+ refclk = i9xx_get_refclk(crtc, num_connectors);
vlv_update_pll(crtc, mode, adjusted_mode, &clock,
has_reduced_clock ? &reduced_clock : NULL,
num_connectors);
- else
+ } else
i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
has_reduced_clock ? &reduced_clock : NULL,
num_connectors);
@@ -4845,6 +4989,21 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
intel_update_watermarks(dev);
+ if (IS_VALLEYVIEW(dev)) {
+ u32 port_mask;
+
+ /* Wait for Phy status bits to go low */
+ for_each_encoder_on_crtc(dev, crtc, encoder) {
+ if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
+ encoder->type == INTEL_OUTPUT_HDMI)
+ port_mask = DPLL_PORTB_READY_MASK;
+ else
+ port_mask = DPLL_PORTC_READY_MASK; /* eDP */
+ if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 100))
+ DRM_ERROR("timed out waiting for port ready\n");
+ }
+ }
+
return ret;
}
@@ -9284,9 +9443,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
ironlake_teardown_rc6(dev);
- if (IS_VALLEYVIEW(dev))
- vlv_init_dpio(dev);
-
mutex_unlock(&dev->struct_mutex);
/* Disable the irq before mode object teardown, for the irq might
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 04/11] drm/i915/dp: fix up VLV DP handling v2
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
2013-03-28 16:55 ` [PATCH 02/11] drm/i915: add sprite assertion function for VLV Jesse Barnes
2013-03-28 16:55 ` [PATCH 03/11] drm/i915: update VLV PLL and DPIO code v8 Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-04-02 18:49 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 05/11] drm/i915: panel power sequencing for VLV eDP v2 Jesse Barnes
` (8 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
Needed to handle pre/post enable/disable paths on VLV and avoid a few
fields that are marked reserved on VLV.
v2: don't set color range or DP PLL fields (Jani)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_dp.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2f2ec42..7fb9213 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -941,7 +941,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
else
intel_dp->DP |= DP_PLL_FREQ_270MHZ;
} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
- if (!HAS_PCH_SPLIT(dev))
+ if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
intel_dp->DP |= intel_dp->color_range;
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -956,7 +956,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
if (intel_crtc->pipe == 1)
intel_dp->DP |= DP_PIPEB_SELECT;
- if (is_cpu_edp(intel_dp)) {
+ if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
/* don't miss out required setting for eDP */
if (adjusted_mode->clock < 200000)
intel_dp->DP |= DP_PLL_FREQ_160MHZ;
@@ -1388,10 +1388,12 @@ static void intel_disable_dp(struct intel_encoder *encoder)
static void intel_post_disable_dp(struct intel_encoder *encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct drm_device *dev = encoder->base.dev;
if (is_cpu_edp(intel_dp)) {
intel_dp_link_down(intel_dp);
- ironlake_edp_pll_off(intel_dp);
+ if (!IS_VALLEYVIEW(dev))
+ ironlake_edp_pll_off(intel_dp);
}
}
@@ -1417,8 +1419,9 @@ static void intel_enable_dp(struct intel_encoder *encoder)
static void intel_pre_enable_dp(struct intel_encoder *encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct drm_device *dev = encoder->base.dev;
- if (is_cpu_edp(intel_dp))
+ if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ironlake_edp_pll_on(intel_dp);
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 05/11] drm/i915: panel power sequencing for VLV eDP v2
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
` (2 preceding siblings ...)
2013-03-28 16:55 ` [PATCH 04/11] drm/i915/dp: fix up VLV DP handling v2 Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-04-02 18:57 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 06/11] drm/i915: add power context allocation and setup on VLV v4 Jesse Barnes
` (7 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
PPS register offsets have changed in Valleyview.
v2: don't clobber port select bits on VLV when fixing up PPS timings
don't bother with G4x PPS regs (Jani)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 ++
drivers/gpu/drm/i915/intel_dp.c | 173 +++++++++++++++++++++++++++------------
2 files changed, 131 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 858a712..834e79f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4182,6 +4182,15 @@
#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
+#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
+#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
+#define VLV_PIPE_PP_ON_DELAYS(pipe) \
+ _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
+#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
+ _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
+#define VLV_PIPE_PP_DIVISOR(pipe) \
+ _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
+
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
#define PANEL_UNLOCK_REGS (0xabcd << 16)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7fb9213..dd9efe8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -294,16 +294,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_stat_reg;
- return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ return (I915_READ(pp_stat_reg) & PP_ON) != 0;
}
static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_ctrl_reg;
- return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
}
static void
@@ -311,14 +315,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_stat_reg, pp_ctrl_reg;
if (!is_edp(intel_dp))
return;
+
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
WARN(1, "eDP powered off while attempting aux channel communication.\n");
DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
- I915_READ(PCH_PP_STATUS),
- I915_READ(PCH_PP_CONTROL));
+ I915_READ(pp_stat_reg),
+ I915_READ(pp_ctrl_reg));
}
}
@@ -986,16 +995,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 pp_stat_reg, pp_ctrl_reg;
+
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
- mask, value,
- I915_READ(PCH_PP_STATUS),
- I915_READ(PCH_PP_CONTROL));
+ mask, value,
+ I915_READ(pp_stat_reg),
+ I915_READ(pp_ctrl_reg));
- if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
+ if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
DRM_ERROR("Panel status timeout: status %08x control %08x\n",
- I915_READ(PCH_PP_STATUS),
- I915_READ(PCH_PP_CONTROL));
+ I915_READ(pp_stat_reg),
+ I915_READ(pp_ctrl_reg));
}
}
@@ -1022,9 +1035,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
* is locked
*/
-static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
{
- u32 control = I915_READ(PCH_PP_CONTROL);
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 control;
+ u32 pp_ctrl_reg;
+
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ control = I915_READ(pp_ctrl_reg);
control &= ~PANEL_UNLOCK_MASK;
control |= PANEL_UNLOCK_REGS;
@@ -1036,6 +1055,7 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
u32 pp;
+ u32 pp_stat_reg, pp_ctrl_reg;
if (!is_edp(intel_dp))
return;
@@ -1054,13 +1074,16 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
if (!ironlake_edp_have_panel_power(intel_dp))
ironlake_wait_panel_power_cycle(intel_dp);
- pp = ironlake_get_pp_control(dev_priv);
+ pp = ironlake_get_pp_control(intel_dp);
pp |= EDP_FORCE_VDD;
- I915_WRITE(PCH_PP_CONTROL, pp);
- POSTING_READ(PCH_PP_CONTROL);
- DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
- I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+ I915_WRITE(pp_ctrl_reg, pp);
+ POSTING_READ(pp_ctrl_reg);
+ DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+ I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
/*
* If the panel wasn't on, delay before accessing aux channel
*/
@@ -1075,19 +1098,23 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
u32 pp;
+ u32 pp_stat_reg, pp_ctrl_reg;
WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
- pp = ironlake_get_pp_control(dev_priv);
+ pp = ironlake_get_pp_control(intel_dp);
pp &= ~EDP_FORCE_VDD;
- I915_WRITE(PCH_PP_CONTROL, pp);
- POSTING_READ(PCH_PP_CONTROL);
- /* Make sure sequencer is idle before allowing subsequent activity */
- DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
- I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
+ pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+ I915_WRITE(pp_ctrl_reg, pp);
+ POSTING_READ(pp_ctrl_reg);
+ /* Make sure sequencer is idle before allowing subsequent activity */
+ DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+ I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
msleep(intel_dp->panel_power_down_delay);
}
}
@@ -1131,6 +1158,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
u32 pp;
+ u32 pp_ctrl_reg;
if (!is_edp(intel_dp))
return;
@@ -1144,7 +1172,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
ironlake_wait_panel_power_cycle(intel_dp);
- pp = ironlake_get_pp_control(dev_priv);
+ pp = ironlake_get_pp_control(intel_dp);
if (IS_GEN5(dev)) {
/* ILK workaround: disable reset around power sequence */
pp &= ~PANEL_POWER_RESET;
@@ -1156,8 +1184,10 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
if (!IS_GEN5(dev))
pp |= PANEL_POWER_RESET;
- I915_WRITE(PCH_PP_CONTROL, pp);
- POSTING_READ(PCH_PP_CONTROL);
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+ I915_WRITE(pp_ctrl_reg, pp);
+ POSTING_READ(pp_ctrl_reg);
ironlake_wait_panel_on(intel_dp);
@@ -1173,6 +1203,7 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
u32 pp;
+ u32 pp_ctrl_reg;
if (!is_edp(intel_dp))
return;
@@ -1181,12 +1212,15 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
- pp = ironlake_get_pp_control(dev_priv);
+ pp = ironlake_get_pp_control(intel_dp);
/* We need to switch off panel power _and_ force vdd, for otherwise some
* panels get very unhappy and cease to work. */
pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
- I915_WRITE(PCH_PP_CONTROL, pp);
- POSTING_READ(PCH_PP_CONTROL);
+
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+ I915_WRITE(pp_ctrl_reg, pp);
+ POSTING_READ(pp_ctrl_reg);
intel_dp->want_panel_vdd = false;
@@ -1200,6 +1234,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
u32 pp;
+ u32 pp_ctrl_reg;
if (!is_edp(intel_dp))
return;
@@ -1212,10 +1247,13 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
* allowing it to appear.
*/
msleep(intel_dp->backlight_on_delay);
- pp = ironlake_get_pp_control(dev_priv);
+ pp = ironlake_get_pp_control(intel_dp);
pp |= EDP_BLC_ENABLE;
- I915_WRITE(PCH_PP_CONTROL, pp);
- POSTING_READ(PCH_PP_CONTROL);
+
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+ I915_WRITE(pp_ctrl_reg, pp);
+ POSTING_READ(pp_ctrl_reg);
intel_panel_enable_backlight(dev, pipe);
}
@@ -1225,6 +1263,7 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
u32 pp;
+ u32 pp_ctrl_reg;
if (!is_edp(intel_dp))
return;
@@ -1232,10 +1271,13 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
intel_panel_disable_backlight(dev);
DRM_DEBUG_KMS("\n");
- pp = ironlake_get_pp_control(dev_priv);
+ pp = ironlake_get_pp_control(intel_dp);
pp &= ~EDP_BLC_ENABLE;
- I915_WRITE(PCH_PP_CONTROL, pp);
- POSTING_READ(PCH_PP_CONTROL);
+
+ pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+ I915_WRITE(pp_ctrl_reg, pp);
+ POSTING_READ(pp_ctrl_reg);
msleep(intel_dp->backlight_off_delay);
}
@@ -2626,15 +2668,28 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
struct drm_i915_private *dev_priv = dev->dev_private;
struct edp_power_seq cur, vbt, spec, final;
u32 pp_on, pp_off, pp_div, pp;
+ int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
+
+ if (HAS_PCH_SPLIT(dev)) {
+ pp_control_reg = PCH_PP_CONTROL;
+ pp_on_reg = PCH_PP_ON_DELAYS;
+ pp_off_reg = PCH_PP_OFF_DELAYS;
+ pp_div_reg = PCH_PP_DIVISOR;
+ } else {
+ pp_control_reg = PIPEA_PP_CONTROL;
+ pp_on_reg = PIPEA_PP_ON_DELAYS;
+ pp_off_reg = PIPEA_PP_OFF_DELAYS;
+ pp_div_reg = PIPEA_PP_DIVISOR;
+ }
/* Workaround: Need to write PP_CONTROL with the unlock key as
* the very first thing. */
- pp = ironlake_get_pp_control(dev_priv);
- I915_WRITE(PCH_PP_CONTROL, pp);
+ pp = ironlake_get_pp_control(intel_dp);
+ I915_WRITE(pp_control_reg, pp);
- pp_on = I915_READ(PCH_PP_ON_DELAYS);
- pp_off = I915_READ(PCH_PP_OFF_DELAYS);
- pp_div = I915_READ(PCH_PP_DIVISOR);
+ pp_on = I915_READ(pp_on_reg);
+ pp_off = I915_READ(pp_off_reg);
+ pp_div = I915_READ(pp_div_reg);
/* Pull timing values out of registers */
cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
@@ -2709,7 +2764,22 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
struct edp_power_seq *seq)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 pp_on, pp_off, pp_div;
+ u32 pp_on, pp_off, pp_div, port_sel = 0;
+ int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
+ int pp_on_reg, pp_off_reg, pp_div_reg;
+
+ if (HAS_PCH_SPLIT(dev)) {
+ pp_on_reg = PCH_PP_ON_DELAYS;
+ pp_off_reg = PCH_PP_OFF_DELAYS;
+ pp_div_reg = PCH_PP_DIVISOR;
+ } else {
+ pp_on_reg = PIPEA_PP_ON_DELAYS;
+ pp_off_reg = PIPEA_PP_OFF_DELAYS;
+ pp_div_reg = PIPEA_PP_DIVISOR;
+ }
+
+ if (IS_VALLEYVIEW(dev))
+ port_sel = I915_READ(pp_on_reg) & 0xc0000000;
/* And finally store the new values in the power sequencer. */
pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
@@ -2718,8 +2788,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
- pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
- << PP_REFERENCE_DIVIDER_SHIFT;
+ pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
<< PANEL_POWER_CYCLE_DELAY_SHIFT);
@@ -2727,19 +2796,21 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
* power sequencer any more. */
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
if (is_cpu_edp(intel_dp))
- pp_on |= PANEL_POWER_PORT_DP_A;
+ port_sel = PANEL_POWER_PORT_DP_A;
else
- pp_on |= PANEL_POWER_PORT_DP_D;
+ port_sel = PANEL_POWER_PORT_DP_D;
}
- I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
- I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
- I915_WRITE(PCH_PP_DIVISOR, pp_div);
+ pp_on |= port_sel;
+
+ I915_WRITE(pp_on_reg, pp_on);
+ I915_WRITE(pp_off_reg, pp_off);
+ I915_WRITE(pp_div_reg, pp_div);
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
- I915_READ(PCH_PP_ON_DELAYS),
- I915_READ(PCH_PP_OFF_DELAYS),
- I915_READ(PCH_PP_DIVISOR));
+ I915_READ(pp_on_reg),
+ I915_READ(pp_off_reg),
+ I915_READ(pp_div_reg));
}
void
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 06/11] drm/i915: add power context allocation and setup on VLV v4
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
` (3 preceding siblings ...)
2013-03-28 16:55 ` [PATCH 05/11] drm/i915: panel power sequencing for VLV eDP v2 Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-03-28 16:55 ` [PATCH 07/11] drm/i915: fix VLV limits and m/n/p calculations v2 Jesse Barnes
` (6 subsequent siblings)
11 siblings, 0 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
The Gunit has a separate reg for this, so allocate some stolen space for
the power context and initialize the reg.
v2: check for allocation before freeing at cleanup (Jani)
v3: add comment about stolen allocation (Chris)
check for lock bit before init (jbarnes)
v4: check for allocation before init (jbarnes)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_stolen.c | 55 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2832cdb..182c494 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1023,6 +1023,8 @@ typedef struct drm_i915_private {
struct i915_gpu_error gpu_error;
+ struct drm_mm_node *vlv_pctx;
+
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index efaaba5..36c9af4 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -171,11 +171,63 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev)
dev_priv->cfb_size = 0;
}
+static void i915_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_mm_node *pctx;
+ unsigned long pctx_paddr;
+ int pctx_size = 24*1024;
+
+ if (I915_READ(VLV_PCBR)) /* BIOS set it up already */
+ return;
+
+ /*
+ * From the Gunit register HAS:
+ * The Gfx driver is expected to program this register and ensure
+ * proper allocation within Gfx stolen memory. For example, this
+ * register should be programmed such than the PCBR range does not
+ * overlap with other ranges, such as the frame buffer, protected
+ * memory, or any other relevant ranges.
+ */
+ pctx = drm_mm_search_free(&dev_priv->mm.stolen, pctx_size, 4096, 0);
+ if (pctx)
+ pctx = drm_mm_get_block(pctx, pctx_size, 4096);
+ if (!pctx)
+ goto err;
+
+ pctx_paddr = dev_priv->mm.stolen_base + pctx->start;
+ if (!pctx_paddr)
+ goto err_free_pctx;
+
+ dev_priv->vlv_pctx = pctx;
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+
+ return;
+
+err_free_pctx:
+ drm_mm_put_block(pctx);
+err:
+ DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
+}
+
+static void i915_cleanup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (!dev_priv->vlv_pctx)
+ return;
+
+ I915_WRITE(VLV_PCBR, 0);
+ drm_mm_put_block(dev_priv->vlv_pctx);
+}
+
void i915_gem_cleanup_stolen(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
i915_gem_stolen_cleanup_compression(dev);
+ if (IS_VALLEYVIEW(dev) && i915_powersave)
+ i915_cleanup_pctx(dev);
drm_mm_takedown(&dev_priv->mm.stolen);
}
@@ -193,6 +245,9 @@ int i915_gem_init_stolen(struct drm_device *dev)
/* Basic memrange allocator for stolen space */
drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->gtt.stolen_size);
+ if (IS_VALLEYVIEW(dev) && i915_powersave)
+ i915_setup_pctx(dev);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 834e79f..68051d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -677,6 +677,7 @@
#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 07/11] drm/i915: fix VLV limits and m/n/p calculations v2
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
` (4 preceding siblings ...)
2013-03-28 16:55 ` [PATCH 06/11] drm/i915: add power context allocation and setup on VLV v4 Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-04-02 18:59 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 08/11] drm/i915: add Punit read/write routines for VLV Jesse Barnes
` (5 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
From: Pallavi G <pallavi.g@intel.com>
For high res modes m n p calculation is fixed for VLV platform.
v2: use 64 bit types and math (Ville)
Signed-off-by: Pallavi G <pallavi.g@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9cb0b53..5cc12dc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -31,6 +31,7 @@
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/vgaarb.h>
+#include <linux/math64.h>
#include <drm/drm_edid.h>
#include <drm/drmP.h>
#include "intel_drv.h"
@@ -396,21 +397,21 @@ static const intel_limit_t intel_limits_vlv_dac = {
.m1 = { .min = 2, .max = 3 },
.m2 = { .min = 11, .max = 156 },
.p = { .min = 10, .max = 30 },
- .p1 = { .min = 2, .max = 3 },
+ .p1 = { .min = 1, .max = 3 },
.p2 = { .dot_limit = 270000,
.p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
};
static const intel_limit_t intel_limits_vlv_hdmi = {
- .dot = { .min = 20000, .max = 165000 },
- .vco = { .min = 4000000, .max = 5994000},
- .n = { .min = 1, .max = 7 },
+ .dot = { .min = 25000, .max = 180000 },
+ .vco = { .min = 4040000, .max = 5960000 },
+ .n = { .min = 1, .max = 5 },
.m = { .min = 60, .max = 300 }, /* guess */
.m1 = { .min = 2, .max = 3 },
- .m2 = { .min = 11, .max = 156 },
+ .m2 = { .min = 15, .max = 149 },
.p = { .min = 10, .max = 30 },
- .p1 = { .min = 2, .max = 3 },
+ .p1 = { .min = 1, .max = 3 },
.p2 = { .dot_limit = 270000,
.p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
@@ -424,7 +425,7 @@ static const intel_limit_t intel_limits_vlv_dp = {
.m1 = { .min = 2, .max = 3 },
.m2 = { .min = 11, .max = 156 },
.p = { .min = 10, .max = 30 },
- .p1 = { .min = 2, .max = 3 },
+ .p1 = { .min = 1, .max = 3 },
.p2 = { .dot_limit = 270000,
.p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
@@ -822,10 +823,13 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
int target, int refclk, intel_clock_t *match_clock,
intel_clock_t *best_clock)
{
+#define LONG_OVERFLOW 0x7FFFFFFF
+#define DIFF_OVERFLOW (LONG_OVERFLOW/10000)
+
u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
u32 m, n, fastclk;
u32 updrate, minupdate, fracbits, p;
- unsigned long bestppm, ppm, absppm;
+ s64 bestppm, ppm, absppm, ppmdiff;
int dotclk, flag;
flag = 0;
@@ -854,8 +858,9 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
m = m1 * m2;
vco = updrate * m;
if (vco >= limit->vco.min && vco < limit->vco.max) {
- ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
- absppm = (ppm > 0) ? ppm : (-ppm);
+ ppmdiff = div_s64((100*vco), p) - (100*fastclk);
+ absppm = div_s64((abs64(ppmdiff)*10000), fastclk);
+
if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
bestppm = 0;
flag = 1;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 08/11] drm/i915: add Punit read/write routines for VLV
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
` (5 preceding siblings ...)
2013-03-28 16:55 ` [PATCH 07/11] drm/i915: fix VLV limits and m/n/p calculations v2 Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-04-02 11:37 ` Ville Syrjälä
2013-04-02 18:23 ` [PATCH] drm/i915: add Punit read/write routines for VLV v2 Jesse Barnes
2013-03-28 16:55 ` [PATCH 09/11] drm/i915: turbo & RC6 support for VLV v3 Jesse Barnes
` (4 subsequent siblings)
11 siblings, 2 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
Slightly different than other platforms.
v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 53 +++++++++++++++++++++++++++++++++++++++
3 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 182c494..642cb1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1845,6 +1845,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68051d6..87a59eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4451,6 +4451,28 @@
#define GEN6_PCODE_DATA 0x138128
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
+#define VLV_IOSF_DOORBELL_REQ 0x182100
+#define IOSF_DEVFN_SHIFT 24
+#define IOSF_OPCODE_SHIFT 16
+#define IOSF_PORT_SHIFT 8
+#define IOSF_BYTE_ENABLES_SHIFT 4
+#define IOSF_BAR_SHIFT 1
+#define IOSF_SB_BUSY (1<<0)
+#define IOSF_PORT_PUNIT 0x4
+#define VLV_IOSF_DATA 0x182104
+#define VLV_IOSF_ADDR 0x182108
+
+#define PUNIT_REG_GPU_LFM 0xd3
+#define PUNIT_REG_GPU_FREQ_REQ 0xd4
+#define PUNIT_REG_GPU_FREQ_STS 0xd8
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
+
+#define PUNIT_OPCODE_REG_READ 6
+#define PUNIT_OPCODE_REG_WRITE 7
+
+#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+
#define GEN6_GT_CORE_STATUS 0x138060
#define GEN6_CORE_CPD_STATE_MASK (7<<4)
#define GEN6_RCn_MASK 7
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6fa9b79..8256d0d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4525,3 +4525,56 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
return 0;
}
+
+static int vlv_punit_rw(struct drm_i915_private *dev_priv, u8 opcode,
+ u8 addr, u32 *val)
+{
+ u32 cmd, devfn, port, be, bar;
+
+ bar = 0;
+ be = 0xf;
+ port = IOSF_PORT_PUNIT;
+ devfn = 16;
+
+ cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
+ (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
+ (bar << IOSF_BAR_SHIFT);
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+ DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
+ opcode == PUNIT_OPCODE_REG_READ ?
+ "read" : "write");
+ return -EAGAIN;
+ }
+
+ I915_WRITE(VLV_IOSF_ADDR, addr);
+ if (opcode == PUNIT_OPCODE_REG_WRITE)
+ I915_WRITE(VLV_IOSF_DATA, *val);
+ I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
+
+ if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
+ 500)) {
+ DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
+ opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
+ addr);
+ return -ETIMEDOUT;
+ }
+
+ if (opcode == PUNIT_OPCODE_REG_READ)
+ *val = I915_READ(VLV_IOSF_DATA);
+ I915_WRITE(VLV_IOSF_DATA, 0);
+
+ return 0;
+}
+
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+{
+ return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_READ, addr, val);
+}
+
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+{
+ return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_WRITE, addr, &val);
+}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 09/11] drm/i915: turbo & RC6 support for VLV v3
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
` (6 preceding siblings ...)
2013-03-28 16:55 ` [PATCH 08/11] drm/i915: add Punit read/write routines for VLV Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-04-02 18:23 ` [PATCH] drm/i915: turbo & RC6 support for VLV v4 Jesse Barnes
2013-03-28 16:55 ` [PATCH 10/11] drm/i915/dp: program VSwing and Preemphasis control settings on VLV Jesse Barnes
` (3 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
From: Ben Widawsky <ben@bwidawsk.net>
Uses slightly different interfaces than other platforms.
v2: track actual set freq, not requested (Rohit)
fix debug prints in init code (Jesse)
v3: don't write sleep reg (Jesse)
re-add RC6 wake limit write (Ben)
fixup thresholds to match other platforms (Ben)
clean up mem freq calculation (Ben)
clean up debug prints (Ben)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 145 +++++++++++++++++++++++++++++++++++++--
4 files changed, 147 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 642cb1f..68f1256 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1816,6 +1816,7 @@ extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void intel_init_pch_refclk(struct drm_device *dev);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
+extern void valleyview_set_rps(struct drm_device *dev, u8 val);
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
extern int intel_enable_rc6(const struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3c2b05c..46f6f1a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -394,7 +394,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
*/
if (!(new_delay > dev_priv->rps.max_delay ||
new_delay < dev_priv->rps.min_delay)) {
- gen6_set_rps(dev_priv->dev, new_delay);
+ if (IS_VALLEYVIEW(dev_priv->dev))
+ valleyview_set_rps(dev_priv->dev, new_delay);
+ else
+ gen6_set_rps(dev_priv->dev, new_delay);
}
mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87a59eb..ea7d16d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4369,6 +4369,7 @@
#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
+#define GEN7_RC_CTL_TO_MODE (1<<28)
#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
#define GEN6_RC_CTL_HW_ENABLE (1<<31)
#define GEN6_RP_DOWN_TIMEOUT 0xA010
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8256d0d..2b02702 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2477,6 +2477,47 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(val * 50);
}
+void valleyview_set_rps(struct drm_device *dev, u8 val)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long timeout = jiffies + msecs_to_jiffies(100);
+ u32 limits = gen6_rps_limits(dev_priv, &val);
+ u32 pval;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+ WARN_ON(val > dev_priv->rps.max_delay);
+ WARN_ON(val < dev_priv->rps.min_delay);
+
+ if (val == dev_priv->rps.cur_delay)
+ return;
+
+ valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+
+ do {
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ if (time_after(jiffies, timeout)) {
+ DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
+ break;
+ }
+ udelay(10);
+ } while (pval & 1);
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ if ((pval >> 8) != val)
+ DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
+ val, pval >> 8);
+
+ /* Make sure we continue to get interrupts
+ * until we hit the minimum or maximum frequencies.
+ */
+ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
+
+ dev_priv->rps.cur_delay = pval >> 8;
+
+ trace_intel_gpu_freq_change(val);
+}
+
+
static void gen6_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2716,6 +2757,97 @@ static void gen6_update_ring_freq(struct drm_device *dev)
}
}
+static void valleyview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, val;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ if ((gtfifodbg = I915_READ(GTFIFODBG))) {
+ DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ gen6_gt_force_wake_get(dev_priv);
+
+ I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+ I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
+ I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
+ I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
+ I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000);
+
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+ I915_WRITE(GEN6_RP_UP_EI, 66000);
+ I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+ I915_WRITE(GEN6_RP_CONTROL,
+ GEN6_RP_MEDIA_TURBO |
+ GEN6_RP_MEDIA_HW_NORMAL_MODE |
+ GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE |
+ GEN6_RP_UP_BUSY_AVG |
+ GEN6_RP_DOWN_IDLE_CONT);
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
+ I915_WRITE(GEN6_RC_CONTROL,
+ GEN6_RC_CTL_RC6pp_ENABLE |
+ GEN6_RC_CTL_RC6p_ENABLE |
+ GEN6_RC_CTL_RC6_ENABLE |
+ GEN7_RC_CTL_TO_MODE |
+ GEN6_RC_CTL_HW_ENABLE);
+
+ valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
+ DRM_DEBUG_DRIVER("max GPU freq: %d\n", (val >> 16) & 0xff);
+ dev_priv->rps.max_delay = (val >> 16) & 0xff;
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+ DRM_DEBUG_DRIVER("min GPU freq: %d\n", val & 0xff);
+ dev_priv->rps.min_delay = val & 0xff;
+
+ valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS2, &val);
+ DRM_DEBUG_DRIVER("max GPLL freq: %d\n", val);
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
+ dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3);
+ DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
+
+ DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 8 ? "yes" : "no");
+ DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+ DRM_DEBUG_DRIVER("current GPU freq: %x\n", (val >> 8) & 0xff);
+ dev_priv->rps.cur_delay = (val >> 8) & 0xff;
+
+ val = 0xd500;
+ DRM_DEBUG_DRIVER("setting GPU freq to %d\n", (val >> 8) & 0xff);
+
+ valleyview_set_rps(dev_priv->dev, (val >> 8) & 0xff);
+
+ /* requires MSI enabled */
+ I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+ spin_lock_irq(&dev_priv->rps.lock);
+ WARN_ON(dev_priv->rps.pm_iir != 0);
+ I915_WRITE(GEN6_PMIMR, 0);
+ spin_unlock_irq(&dev_priv->rps.lock);
+ /* enable all PM interrupts */
+ I915_WRITE(GEN6_PMINTRMSK, 0);
+
+ gen6_gt_force_wake_put(dev_priv);
+}
+
void ironlake_teardown_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3442,7 +3574,7 @@ void intel_disable_gt_powersave(struct drm_device *dev)
if (IS_IRONLAKE_M(dev)) {
ironlake_disable_drps(dev);
ironlake_disable_rc6(dev);
- } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
+ } else if (INTEL_INFO(dev)->gen >= 6) {
cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
mutex_lock(&dev_priv->rps.hw_lock);
gen6_disable_rps(dev);
@@ -3458,8 +3590,13 @@ static void intel_gen6_powersave_work(struct work_struct *work)
struct drm_device *dev = dev_priv->dev;
mutex_lock(&dev_priv->rps.hw_lock);
- gen6_enable_rps(dev);
- gen6_update_ring_freq(dev);
+
+ if (IS_VALLEYVIEW(dev)) {
+ valleyview_enable_rps(dev);
+ } else {
+ gen6_enable_rps(dev);
+ gen6_update_ring_freq(dev);
+ }
mutex_unlock(&dev_priv->rps.hw_lock);
}
@@ -3471,7 +3608,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
ironlake_enable_drps(dev);
ironlake_enable_rc6(dev);
intel_init_emon(dev);
- } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
+ } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
/*
* PCU communication is slow and this doesn't need to be
* done at any specific time, so do this out of our fast path
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 10/11] drm/i915/dp: program VSwing and Preemphasis control settings on VLV
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
` (7 preceding siblings ...)
2013-03-28 16:55 ` [PATCH 09/11] drm/i915: turbo & RC6 support for VLV v3 Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-04-02 19:04 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use " Jesse Barnes
` (2 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
From: Pallavi G <pallavi.g@intel.com>
Program few Tx buffer Swing control settings through DPIO.
Signed-off-by: Pallavi G <pallavi.g@intel.com>
Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 114 +++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 115 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5cc12dc..4364829 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -451,8 +451,7 @@ u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
return I915_READ(DPIO_DATA);
}
-static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
- u32 val)
+void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
{
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dd9efe8..557a33b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1527,7 +1527,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
+ if (IS_VALLEYVIEW(dev))
+ return DP_TRAIN_VOLTAGE_SWING_1200;
+ else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
return DP_TRAIN_VOLTAGE_SWING_800;
else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
return DP_TRAIN_VOLTAGE_SWING_1200;
@@ -1552,7 +1554,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
default:
return DP_TRAIN_PRE_EMPHASIS_0;
}
- } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev)) {
+ switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ return DP_TRAIN_PRE_EMPHASIS_9_5;
+ case DP_TRAIN_VOLTAGE_SWING_600:
+ return DP_TRAIN_PRE_EMPHASIS_6;
+ case DP_TRAIN_VOLTAGE_SWING_800:
+ return DP_TRAIN_PRE_EMPHASIS_3_5;
+ case DP_TRAIN_VOLTAGE_SWING_1200:
+ default:
+ return DP_TRAIN_PRE_EMPHASIS_0;
+ }
+ } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_400:
return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1577,15 +1591,111 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
}
}
+static void vlv_set_vswing_pre_emphasis(struct intel_dp *intel_dp, uint8_t v,
+ uint8_t p)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long Demph_reg_value, Preemph_reg_value,
+ Uniqtranscale_reg_value;
+ switch (p) {
+ case DP_TRAIN_PRE_EMPHASIS_0:
+ Preemph_reg_value = 0x0004000;
+ switch (v) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ Demph_reg_value = 0x2B405555;
+ Uniqtranscale_reg_value = 0x552AB83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_600:
+ Demph_reg_value = 0x2B404040;
+ Uniqtranscale_reg_value = 0x5548B83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_800:
+ Demph_reg_value = 0x2B245555;
+ Uniqtranscale_reg_value = 0x5560B83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_1200:
+ Demph_reg_value = 0x2B405555;
+ Uniqtranscale_reg_value = 0x5598DA3A;
+ break;
+ default:
+ return;
+ }
+ break;
+ case DP_TRAIN_PRE_EMPHASIS_3_5:
+ Preemph_reg_value = 0x0002000;
+ switch (v) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ Demph_reg_value = 0x2B404040;
+ Uniqtranscale_reg_value = 0x5552B83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_600:
+ Demph_reg_value = 0x2B404848;
+ Uniqtranscale_reg_value = 0x5580B83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_800:
+ Demph_reg_value = 0x2B404040;
+ Uniqtranscale_reg_value = 0x55ADDA3A;
+ break;
+ default:
+ return;
+ }
+ break;
+ case DP_TRAIN_PRE_EMPHASIS_6:
+ Preemph_reg_value = 0x0000000;
+ switch (v) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ Demph_reg_value = 0x2B305555;
+ Uniqtranscale_reg_value = 0x5570B83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_600:
+ Demph_reg_value = 0x2B2B4040;
+ Uniqtranscale_reg_value = 0x55ADDA3A;
+ break;
+ default:
+ return;
+ }
+ break;
+ case DP_TRAIN_PRE_EMPHASIS_9_5:
+ Preemph_reg_value = 0x0006000;
+ switch (v) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ Demph_reg_value = 0x1B405555;
+ Uniqtranscale_reg_value = 0x55ADDA3A;
+ break;
+ default:
+ return;
+ }
+ break;
+ default:
+ return;
+ }
+
+ /* eDP is only on port C */
+ mutex_lock(&dev_priv->dpio_lock);
+ intel_dpio_write(dev_priv, 0x8494, 0x00000000);
+ intel_dpio_write(dev_priv, 0x8490, Demph_reg_value);
+ intel_dpio_write(dev_priv, 0x8488, Uniqtranscale_reg_value);
+ intel_dpio_write(dev_priv, 0x848c, 0x0C782040);
+ intel_dpio_write(dev_priv, 0x842c, 0x00030000);
+ intel_dpio_write(dev_priv, 0x8424, Preemph_reg_value);
+ intel_dpio_write(dev_priv, 0x8494, 0x80000000);
+ mutex_unlock(&dev_priv->dpio_lock);
+}
+
static void
intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
uint8_t v = 0;
uint8_t p = 0;
int lane;
uint8_t voltage_max;
uint8_t preemph_max;
+ if (IS_VALLEYVIEW(dev))
+ vlv_set_vswing_pre_emphasis(intel_dp, v, p);
+
for (lane = 0; lane < intel_dp->lane_count; lane++) {
uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8940741..5bee2ea 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -661,6 +661,8 @@ extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
+extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
+ u32 val);
/* Power-related functions, located in intel_pm.c */
extern void intel_init_pm(struct drm_device *dev);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
` (8 preceding siblings ...)
2013-03-28 16:55 ` [PATCH 10/11] drm/i915/dp: program VSwing and Preemphasis control settings on VLV Jesse Barnes
@ 2013-03-28 16:55 ` Jesse Barnes
2013-04-02 10:37 ` Ville Syrjälä
2013-04-02 18:25 ` [PATCH] drm/i915: drop DPFLIPSTAT enables on VLV v3 Jesse Barnes
2013-04-02 10:26 ` [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Ville Syrjälä
2013-04-02 18:22 ` [PATCH] drm/i915: sprite support for ValleyView v4 Jesse Barnes
11 siblings, 2 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-03-28 16:55 UTC (permalink / raw)
To: intel-gfx
Thus preventing the display from keeping the GT awake with unnecessary
signals.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2b02702..de9f898 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
* when flip and other events complete. So enable
* all the GUnit->GT interrupts here
*/
- I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
- PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
+ I915_WRITE(VLV_DPFLIPSTAT,
SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
- PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
- PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
+ PLANEB_FLIPDONE_INT_EN |
SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
PLANEA_FLIPDONE_INT_EN);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH 01/11] drm/i915: sprite support for ValleyView v3
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
` (9 preceding siblings ...)
2013-03-28 16:55 ` [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use " Jesse Barnes
@ 2013-04-02 10:26 ` Ville Syrjälä
2013-04-02 18:12 ` Jesse Barnes
2013-04-02 18:22 ` [PATCH] drm/i915: sprite support for ValleyView v4 Jesse Barnes
11 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2013-04-02 10:26 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Mar 28, 2013 at 09:55:37AM -0700, Jesse Barnes wrote:
> No constant alpha yet though, that needs a new ioctl and/or property to
> get/set.
>
> v2: use drm_plane_format_cpp (Ville)
> fix up vlv_disable_plane, remove IVB bits (Ville)
> remove error path rework (Ville)
> fix component order confusion (Ville)
> clean up platform init (Ville)
> use compute_offset_xtiled (Ville)
> v3: fix up more format confusion (Ville)
> update to new page offset function (Ville)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 4 +
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 57 +++++++++
> drivers/gpu/drm/i915/intel_display.c | 13 ++-
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_sprite.c | 213 ++++++++++++++++++++++++++++++++--
> 6 files changed, 277 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index ebcfe2e..4be58e3 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
> mutex_init(&dev_priv->rps.hw_lock);
> mutex_init(&dev_priv->modeset_restore_lock);
>
> + dev_priv->num_plane = 1;
> + if (IS_VALLEYVIEW(dev))
> + dev_priv->num_plane = 2;
> +
> ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
> if (ret)
> goto out_gem_unload;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1657d873..2832cdb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -914,6 +914,7 @@ typedef struct drm_i915_private {
> bool enable_hotplug_processing;
>
> int num_pch_pll;
> + int num_plane;
>
> unsigned long cfb_size;
> unsigned int cfb_fb;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bceca11..d0f7cb9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3261,6 +3261,63 @@
> #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
> #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>
> +#define _SPACNTR 0x72180
> +#define SP_ENABLE (1<<31)
> +#define SP_GEAMMA_ENABLE (1<<30)
> +#define SP_PIXFORMAT_MASK (0xf<<26)
> +#define SP_FORMAT_YUV422 (0<<26)
> +#define SP_FORMAT_BGR565 (5<<26)
> +#define SP_FORMAT_BGRX8888 (6<<26)
> +#define SP_FORMAT_BGRA8888 (7<<26)
> +#define SP_FORMAT_RGBX1010102 (8<<26)
> +#define SP_FORMAT_RGBA1010102 (9<<26)
> +#define SP_FORMAT_RGBX8888 (0xe<<26)
> +#define SP_FORMAT_RGBA8888 (0xf<<26)
> +#define SP_SOURCE_KEY (1<<22)
> +#define SP_YUV_BYTE_ORDER_MASK (3<<16)
> +#define SP_YUV_ORDER_YUYV (0<<16)
> +#define SP_YUV_ORDER_UYVY (1<<16)
> +#define SP_YUV_ORDER_YVYU (2<<16)
> +#define SP_YUV_ORDER_VYUY (3<<16)
> +#define SP_TILED (1<<10)
> +#define _SPALINOFF 0x72184
> +#define _SPASTRIDE 0x72188
> +#define _SPAPOS 0x7218c
> +#define _SPASIZE 0x72190
> +#define _SPAKEYMINVAL 0x72194
> +#define _SPAKEYMSK 0x72198
> +#define _SPASURF 0x7219c
> +#define _SPAKEYMAXVAL 0x721a0
> +#define _SPATILEOFF 0x721a4
> +#define _SPACONSTALPHA 0x721a8
> +#define _SPAGAMC 0x721f4
> +
> +#define _SPBCNTR 0x72280
> +#define _SPBLINOFF 0x72284
> +#define _SPBSTRIDE 0x72288
> +#define _SPBPOS 0x7228c
> +#define _SPBSIZE 0x72290
> +#define _SPBKEYMINVAL 0x72294
> +#define _SPBKEYMSK 0x72298
> +#define _SPBSURF 0x7229c
> +#define _SPBKEYMAXVAL 0x722a0
> +#define _SPBTILEOFF 0x722a4
> +#define _SPBCONSTALPHA 0x722a8
> +#define _SPBGAMC 0x722f4
> +
> +#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
> +#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
> +#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
> +#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> +#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
> +#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
> +
> /* VBIOS regs */
> #define VGACNTRL 0x71400
> # define VGA_DISP_DISABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7307974..537cd0f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8525,6 +8525,8 @@ int intel_framebuffer_init(struct drm_device *dev,
> case DRM_FORMAT_C8:
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_BGRX8888:
These guys shouldn't be here.
Drop this hunk, and then you get:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> case DRM_FORMAT_ARGB8888:
> break;
> case DRM_FORMAT_XRGB1555:
> @@ -8855,7 +8857,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
> void intel_modeset_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int i, ret;
> + int i, j, ret;
>
> drm_mode_config_init(dev);
>
> @@ -8891,9 +8893,12 @@ void intel_modeset_init(struct drm_device *dev)
>
> for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
> intel_crtc_init(dev, i);
> - ret = intel_plane_init(dev, i);
> - if (ret)
> - DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
> + for (j = 0; j < dev_priv->num_plane; j++) {
> + ret = intel_plane_init(dev, i, j);
> + if (ret)
> + DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
> + i, j, ret);
> + }
> }
>
> intel_cpu_pll_init(dev);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 599e978..8940741 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -242,6 +242,7 @@ struct intel_crtc {
>
> struct intel_plane {
> struct drm_plane base;
> + int plane;
> enum pipe pipe;
> struct drm_i915_gem_object *obj;
> bool can_scale;
> @@ -488,7 +489,7 @@ extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
> extern int intel_edp_target_clock(struct intel_encoder *,
> struct drm_display_mode *mode);
> extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
> -extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
> +extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
> extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
> enum plane plane);
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 1b6eb76..2699026 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -37,6 +37,174 @@
> #include "i915_drv.h"
>
> static void
> +vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
> + struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
> + unsigned int crtc_w, unsigned int crtc_h,
> + uint32_t x, uint32_t y,
> + uint32_t src_w, uint32_t src_h)
> +{
> + struct drm_device *dev = dplane->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_plane *intel_plane = to_intel_plane(dplane);
> + int pipe = intel_plane->pipe;
> + int plane = intel_plane->plane;
> + u32 sprctl;
> + unsigned long sprsurf_offset, linear_offset;
> + int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> +
> + sprctl = I915_READ(SPCNTR(pipe, plane));
> +
> + /* Mask out pixel format bits in case we change it */
> + sprctl &= ~SP_PIXFORMAT_MASK;
> + sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
> + sprctl &= ~SP_TILED;
> +
> + switch (fb->pixel_format) {
> + case DRM_FORMAT_YUYV:
> + sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
> + break;
> + case DRM_FORMAT_YVYU:
> + sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
> + break;
> + case DRM_FORMAT_UYVY:
> + sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
> + break;
> + case DRM_FORMAT_VYUY:
> + sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
> + break;
> + case DRM_FORMAT_RGB565:
> + sprctl |= SP_FORMAT_BGR565;
> + break;
> + case DRM_FORMAT_XRGB8888:
> + sprctl |= SP_FORMAT_BGRX8888;
> + break;
> + case DRM_FORMAT_ARGB8888:
> + sprctl |= SP_FORMAT_BGRA8888;
> + break;
> + case DRM_FORMAT_XBGR2101010:
> + sprctl |= SP_FORMAT_RGBX1010102;
> + break;
> + case DRM_FORMAT_ABGR2101010:
> + sprctl |= SP_FORMAT_RGBA1010102;
> + break;
> + case DRM_FORMAT_XBGR8888:
> + sprctl |= SP_FORMAT_RGBX8888;
> + break;
> + case DRM_FORMAT_ABGR8888:
> + sprctl |= SP_FORMAT_RGBA8888;
> + break;
> + default:
> + /*
> + * If we get here one of the upper layers failed to filter
> + * out the unsupported plane formats
> + */
> + BUG();
> + break;
> + }
> +
> + if (obj->tiling_mode != I915_TILING_NONE)
> + sprctl |= SP_TILED;
> +
> + sprctl |= SP_ENABLE;
> +
> + /* Sizes are 0 based */
> + src_w--;
> + src_h--;
> + crtc_w--;
> + crtc_h--;
> +
> + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
> +
> + I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
> + I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
> +
> + linear_offset = y * fb->pitches[0] + x * pixel_size;
> + sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
> + obj->tiling_mode,
> + pixel_size,
> + fb->pitches[0]);
> + linear_offset -= sprsurf_offset;
> +
> + if (obj->tiling_mode != I915_TILING_NONE)
> + I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
> + else
> + I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
> +
> + I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
> + I915_WRITE(SPCNTR(pipe, plane), sprctl);
> + I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset +
> + sprsurf_offset);
> + POSTING_READ(SPSURF(pipe, plane));
> +}
> +
> +static void
> +vlv_disable_plane(struct drm_plane *dplane)
> +{
> + struct drm_device *dev = dplane->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_plane *intel_plane = to_intel_plane(dplane);
> + int pipe = intel_plane->pipe;
> + int plane = intel_plane->plane;
> +
> + I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
> + ~SP_ENABLE);
> + /* Activate double buffered register update */
> + I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
> + POSTING_READ(SPSURF(pipe, plane));
> +}
> +
> +static int
> +vlv_update_colorkey(struct drm_plane *dplane,
> + struct drm_intel_sprite_colorkey *key)
> +{
> + struct drm_device *dev = dplane->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_plane *intel_plane = to_intel_plane(dplane);
> + int pipe = intel_plane->pipe;
> + int plane = intel_plane->plane;
> + u32 sprctl;
> +
> + if (key->flags & I915_SET_COLORKEY_DESTINATION)
> + return -EINVAL;
> +
> + I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
> + I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
> + I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
> +
> + sprctl = I915_READ(SPCNTR(pipe, plane));
> + sprctl &= ~SP_SOURCE_KEY;
> + if (key->flags & I915_SET_COLORKEY_SOURCE)
> + sprctl |= SP_SOURCE_KEY;
> + I915_WRITE(SPCNTR(pipe, plane), sprctl);
> +
> + POSTING_READ(SPKEYMSK(pipe, plane));
> +
> + return 0;
> +}
> +
> +static void
> +vlv_get_colorkey(struct drm_plane *dplane,
> + struct drm_intel_sprite_colorkey *key)
> +{
> + struct drm_device *dev = dplane->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_plane *intel_plane = to_intel_plane(dplane);
> + int pipe = intel_plane->pipe;
> + int plane = intel_plane->plane;
> + u32 sprctl;
> +
> + key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
> + key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
> + key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
> +
> + sprctl = I915_READ(SPCNTR(pipe, plane));
> + if (sprctl & SP_SOURCE_KEY)
> + key->flags = I915_SET_COLORKEY_SOURCE;
> + else
> + key->flags = I915_SET_COLORKEY_NONE;
> +}
> +
> +static void
> ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
> struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
> unsigned int crtc_w, unsigned int crtc_h,
> @@ -670,8 +838,22 @@ static uint32_t snb_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
> +static uint32_t vlv_plane_formats[] = {
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ABGR2101010,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> +};
> +
> int
> -intel_plane_init(struct drm_device *dev, enum pipe pipe)
> +intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
> {
> struct intel_plane *intel_plane;
> unsigned long possible_crtcs;
> @@ -710,14 +892,26 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
> intel_plane->can_scale = false;
> else
> intel_plane->can_scale = true;
> - intel_plane->max_downscale = 2;
> - intel_plane->update_plane = ivb_update_plane;
> - intel_plane->disable_plane = ivb_disable_plane;
> - intel_plane->update_colorkey = ivb_update_colorkey;
> - intel_plane->get_colorkey = ivb_get_colorkey;
> -
> - plane_formats = snb_plane_formats;
> - num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> +
> + if (IS_VALLEYVIEW(dev)) {
> + intel_plane->max_downscale = 1;
> + intel_plane->update_plane = vlv_update_plane;
> + intel_plane->disable_plane = vlv_disable_plane;
> + intel_plane->update_colorkey = vlv_update_colorkey;
> + intel_plane->get_colorkey = vlv_get_colorkey;
> +
> + plane_formats = vlv_plane_formats;
> + num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> + } else {
> + intel_plane->max_downscale = 2;
> + intel_plane->update_plane = ivb_update_plane;
> + intel_plane->disable_plane = ivb_disable_plane;
> + intel_plane->update_colorkey = ivb_update_colorkey;
> + intel_plane->get_colorkey = ivb_get_colorkey;
> +
> + plane_formats = snb_plane_formats;
> + num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> + }
> break;
>
> default:
> @@ -726,6 +920,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
> }
>
> intel_plane->pipe = pipe;
> + intel_plane->plane = plane;
> possible_crtcs = (1 << pipe);
> ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
> &intel_plane_funcs,
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV
2013-03-28 16:55 ` [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use " Jesse Barnes
@ 2013-04-02 10:37 ` Ville Syrjälä
2013-04-02 18:09 ` Jesse Barnes
2013-04-02 18:25 ` [PATCH] drm/i915: drop DPFLIPSTAT enables on VLV v3 Jesse Barnes
1 sibling, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2013-04-02 10:37 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Mar 28, 2013 at 09:55:47AM -0700, Jesse Barnes wrote:
> Thus preventing the display from keeping the GT awake with unnecessary
> signals.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2b02702..de9f898 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> * when flip and other events complete. So enable
> * all the GUnit->GT interrupts here
> */
> - I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
> - PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
> + I915_WRITE(VLV_DPFLIPSTAT,
> SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
> - PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
> - PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
> + PLANEB_FLIPDONE_INT_EN |
> SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
> PLANEA_FLIPDONE_INT_EN);
We're not doing CS page flips w/ sprites currently, so I think you
could drop the sprite bits too.
Actually, now that I think about it, do we need any bits enabled here?
i915_gem_execbuffer_wait_for_flips() is gone, so AFAICS GT no longer
needs to know when page flips complete.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 08/11] drm/i915: add Punit read/write routines for VLV
2013-03-28 16:55 ` [PATCH 08/11] drm/i915: add Punit read/write routines for VLV Jesse Barnes
@ 2013-04-02 11:37 ` Ville Syrjälä
2013-04-02 18:19 ` Jesse Barnes
2013-04-02 18:23 ` [PATCH] drm/i915: add Punit read/write routines for VLV v2 Jesse Barnes
1 sibling, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2013-04-02 11:37 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Mar 28, 2013 at 09:55:44AM -0700, Jesse Barnes wrote:
> Slightly different than other platforms.
>
> v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 53 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 77 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 182c494..642cb1f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1845,6 +1845,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
>
> int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
> int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
> +int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
>
> #define __i915_read(x, y) \
> u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 68051d6..87a59eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4451,6 +4451,28 @@
> #define GEN6_PCODE_DATA 0x138128
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
>
> +#define VLV_IOSF_DOORBELL_REQ 0x182100
> +#define IOSF_DEVFN_SHIFT 24
> +#define IOSF_OPCODE_SHIFT 16
> +#define IOSF_PORT_SHIFT 8
> +#define IOSF_BYTE_ENABLES_SHIFT 4
> +#define IOSF_BAR_SHIFT 1
> +#define IOSF_SB_BUSY (1<<0)
> +#define IOSF_PORT_PUNIT 0x4
> +#define VLV_IOSF_DATA 0x182104
> +#define VLV_IOSF_ADDR 0x182108
> +
> +#define PUNIT_REG_GPU_LFM 0xd3
> +#define PUNIT_REG_GPU_FREQ_REQ 0xd4
> +#define PUNIT_REG_GPU_FREQ_STS 0xd8
> +#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
These should be part of the turbo patch.
> +
> +#define PUNIT_OPCODE_REG_READ 6
> +#define PUNIT_OPCODE_REG_WRITE 7
> +
> +#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> +#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
Ditto.
> +
> #define GEN6_GT_CORE_STATUS 0x138060
> #define GEN6_CORE_CPD_STATE_MASK (7<<4)
> #define GEN6_RCn_MASK 7
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6fa9b79..8256d0d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4525,3 +4525,56 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>
> return 0;
> }
> +
> +static int vlv_punit_rw(struct drm_i915_private *dev_priv, u8 opcode,
> + u8 addr, u32 *val)
> +{
> + u32 cmd, devfn, port, be, bar;
> +
> + bar = 0;
> + be = 0xf;
> + port = IOSF_PORT_PUNIT;
> + devfn = 16;
PCI_DEVFN(2,0) maybe? I think I'm missing some doc that tells
me what kind of magic devfn and bar should contain.
Apart from those small nits:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> + cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> + (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
> + (bar << IOSF_BAR_SHIFT);
> +
> + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> + if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
> + DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
> + opcode == PUNIT_OPCODE_REG_READ ?
> + "read" : "write");
> + return -EAGAIN;
> + }
> +
> + I915_WRITE(VLV_IOSF_ADDR, addr);
> + if (opcode == PUNIT_OPCODE_REG_WRITE)
> + I915_WRITE(VLV_IOSF_DATA, *val);
> + I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
> +
> + if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
> + 500)) {
> + DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
> + opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
> + addr);
> + return -ETIMEDOUT;
> + }
> +
> + if (opcode == PUNIT_OPCODE_REG_READ)
> + *val = I915_READ(VLV_IOSF_DATA);
> + I915_WRITE(VLV_IOSF_DATA, 0);
> +
> + return 0;
> +}
> +
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
> +{
> + return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_READ, addr, val);
> +}
> +
> +int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
> +{
> + return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_WRITE, addr, &val);
> +}
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV
2013-04-02 10:37 ` Ville Syrjälä
@ 2013-04-02 18:09 ` Jesse Barnes
2013-04-02 18:14 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-04-02 18:09 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, 2 Apr 2013 13:37:50 +0300
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Mar 28, 2013 at 09:55:47AM -0700, Jesse Barnes wrote:
> > Thus preventing the display from keeping the GT awake with unnecessary
> > signals.
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 6 ++----
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 2b02702..de9f898 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> > * when flip and other events complete. So enable
> > * all the GUnit->GT interrupts here
> > */
> > - I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
> > - PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
> > + I915_WRITE(VLV_DPFLIPSTAT,
> > SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
> > - PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
> > - PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
> > + PLANEB_FLIPDONE_INT_EN |
> > SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
> > PLANEA_FLIPDONE_INT_EN);
>
> We're not doing CS page flips w/ sprites currently, so I think you
> could drop the sprite bits too.
Ok thanks, will drop.
>
> Actually, now that I think about it, do we need any bits enabled here?
> i915_gem_execbuffer_wait_for_flips() is gone, so AFAICS GT no longer
> needs to know when page flips complete.
We still use the flipdone interrupt for tracking fb state though, for
unpinning the buffer.
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 01/11] drm/i915: sprite support for ValleyView v3
2013-04-02 10:26 ` [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Ville Syrjälä
@ 2013-04-02 18:12 ` Jesse Barnes
0 siblings, 0 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-04-02 18:12 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, 2 Apr 2013 13:26:47 +0300
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Mar 28, 2013 at 09:55:37AM -0700, Jesse Barnes wrote:
> > No constant alpha yet though, that needs a new ioctl and/or property to
> > get/set.
> >
> > v2: use drm_plane_format_cpp (Ville)
> > fix up vlv_disable_plane, remove IVB bits (Ville)
> > remove error path rework (Ville)
> > fix component order confusion (Ville)
> > clean up platform init (Ville)
> > use compute_offset_xtiled (Ville)
> > v3: fix up more format confusion (Ville)
> > update to new page offset function (Ville)
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 4 +
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 57 +++++++++
> > drivers/gpu/drm/i915/intel_display.c | 13 ++-
> > drivers/gpu/drm/i915/intel_drv.h | 3 +-
> > drivers/gpu/drm/i915/intel_sprite.c | 213 ++++++++++++++++++++++++++++++++--
> > 6 files changed, 277 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index ebcfe2e..4be58e3 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
> > mutex_init(&dev_priv->rps.hw_lock);
> > mutex_init(&dev_priv->modeset_restore_lock);
> >
> > + dev_priv->num_plane = 1;
> > + if (IS_VALLEYVIEW(dev))
> > + dev_priv->num_plane = 2;
> > +
> > ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
> > if (ret)
> > goto out_gem_unload;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 1657d873..2832cdb 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -914,6 +914,7 @@ typedef struct drm_i915_private {
> > bool enable_hotplug_processing;
> >
> > int num_pch_pll;
> > + int num_plane;
> >
> > unsigned long cfb_size;
> > unsigned int cfb_fb;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index bceca11..d0f7cb9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3261,6 +3261,63 @@
> > #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
> > #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
> >
> > +#define _SPACNTR 0x72180
> > +#define SP_ENABLE (1<<31)
> > +#define SP_GEAMMA_ENABLE (1<<30)
> > +#define SP_PIXFORMAT_MASK (0xf<<26)
> > +#define SP_FORMAT_YUV422 (0<<26)
> > +#define SP_FORMAT_BGR565 (5<<26)
> > +#define SP_FORMAT_BGRX8888 (6<<26)
> > +#define SP_FORMAT_BGRA8888 (7<<26)
> > +#define SP_FORMAT_RGBX1010102 (8<<26)
> > +#define SP_FORMAT_RGBA1010102 (9<<26)
> > +#define SP_FORMAT_RGBX8888 (0xe<<26)
> > +#define SP_FORMAT_RGBA8888 (0xf<<26)
> > +#define SP_SOURCE_KEY (1<<22)
> > +#define SP_YUV_BYTE_ORDER_MASK (3<<16)
> > +#define SP_YUV_ORDER_YUYV (0<<16)
> > +#define SP_YUV_ORDER_UYVY (1<<16)
> > +#define SP_YUV_ORDER_YVYU (2<<16)
> > +#define SP_YUV_ORDER_VYUY (3<<16)
> > +#define SP_TILED (1<<10)
> > +#define _SPALINOFF 0x72184
> > +#define _SPASTRIDE 0x72188
> > +#define _SPAPOS 0x7218c
> > +#define _SPASIZE 0x72190
> > +#define _SPAKEYMINVAL 0x72194
> > +#define _SPAKEYMSK 0x72198
> > +#define _SPASURF 0x7219c
> > +#define _SPAKEYMAXVAL 0x721a0
> > +#define _SPATILEOFF 0x721a4
> > +#define _SPACONSTALPHA 0x721a8
> > +#define _SPAGAMC 0x721f4
> > +
> > +#define _SPBCNTR 0x72280
> > +#define _SPBLINOFF 0x72284
> > +#define _SPBSTRIDE 0x72288
> > +#define _SPBPOS 0x7228c
> > +#define _SPBSIZE 0x72290
> > +#define _SPBKEYMINVAL 0x72294
> > +#define _SPBKEYMSK 0x72298
> > +#define _SPBSURF 0x7229c
> > +#define _SPBKEYMAXVAL 0x722a0
> > +#define _SPBTILEOFF 0x722a4
> > +#define _SPBCONSTALPHA 0x722a8
> > +#define _SPBGAMC 0x722f4
> > +
> > +#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
> > +#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
> > +#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
> > +#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
> > +#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
> > +#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
> > +#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
> > +#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
> > +#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> > +#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
> > +#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
> > +#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
> > +
> > /* VBIOS regs */
> > #define VGACNTRL 0x71400
> > # define VGA_DISP_DISABLE (1 << 31)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 7307974..537cd0f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8525,6 +8525,8 @@ int intel_framebuffer_init(struct drm_device *dev,
> > case DRM_FORMAT_C8:
> > case DRM_FORMAT_RGB565:
> > case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_BGRX8888:
>
> These guys shouldn't be here.
>
> Drop this hunk, and then you get:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
Fixed, thanks.
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV
2013-04-02 18:09 ` Jesse Barnes
@ 2013-04-02 18:14 ` Ville Syrjälä
2013-04-02 18:20 ` Jesse Barnes
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2013-04-02 18:14 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Tue, Apr 02, 2013 at 11:09:30AM -0700, Jesse Barnes wrote:
> On Tue, 2 Apr 2013 13:37:50 +0300
> Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>
> > On Thu, Mar 28, 2013 at 09:55:47AM -0700, Jesse Barnes wrote:
> > > Thus preventing the display from keeping the GT awake with unnecessary
> > > signals.
> > >
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 6 ++----
> > > 1 file changed, 2 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 2b02702..de9f898 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> > > * when flip and other events complete. So enable
> > > * all the GUnit->GT interrupts here
> > > */
> > > - I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
> > > - PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
> > > + I915_WRITE(VLV_DPFLIPSTAT,
> > > SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
> > > - PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
> > > - PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
> > > + PLANEB_FLIPDONE_INT_EN |
> > > SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
> > > PLANEA_FLIPDONE_INT_EN);
> >
> > We're not doing CS page flips w/ sprites currently, so I think you
> > could drop the sprite bits too.
>
> Ok thanks, will drop.
>
> >
> > Actually, now that I think about it, do we need any bits enabled here?
> > i915_gem_execbuffer_wait_for_flips() is gone, so AFAICS GT no longer
> > needs to know when page flips complete.
>
> We still use the flipdone interrupt for tracking fb state though, for
> unpinning the buffer.
AFAIK this register only controls the display->GT signals, but
shouldn't affect the CPU display interrupts.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 08/11] drm/i915: add Punit read/write routines for VLV
2013-04-02 11:37 ` Ville Syrjälä
@ 2013-04-02 18:19 ` Jesse Barnes
0 siblings, 0 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-04-02 18:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, 2 Apr 2013 14:37:42 +0300
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Mar 28, 2013 at 09:55:44AM -0700, Jesse Barnes wrote:
> > Slightly different than other platforms.
> >
> > v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine.
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Fixed these up, thanks.
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV
2013-04-02 18:14 ` Ville Syrjälä
@ 2013-04-02 18:20 ` Jesse Barnes
0 siblings, 0 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-04-02 18:20 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, 2 Apr 2013 21:14:30 +0300
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Apr 02, 2013 at 11:09:30AM -0700, Jesse Barnes wrote:
> > On Tue, 2 Apr 2013 13:37:50 +0300
> > Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >
> > > On Thu, Mar 28, 2013 at 09:55:47AM -0700, Jesse Barnes wrote:
> > > > Thus preventing the display from keeping the GT awake with unnecessary
> > > > signals.
> > > >
> > > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_pm.c | 6 ++----
> > > > 1 file changed, 2 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 2b02702..de9f898 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> > > > * when flip and other events complete. So enable
> > > > * all the GUnit->GT interrupts here
> > > > */
> > > > - I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
> > > > - PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
> > > > + I915_WRITE(VLV_DPFLIPSTAT,
> > > > SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
> > > > - PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
> > > > - PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
> > > > + PLANEB_FLIPDONE_INT_EN |
> > > > SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
> > > > PLANEA_FLIPDONE_INT_EN);
> > >
> > > We're not doing CS page flips w/ sprites currently, so I think you
> > > could drop the sprite bits too.
> >
> > Ok thanks, will drop.
> >
> > >
> > > Actually, now that I think about it, do we need any bits enabled here?
> > > i915_gem_execbuffer_wait_for_flips() is gone, so AFAICS GT no longer
> > > needs to know when page flips complete.
> >
> > We still use the flipdone interrupt for tracking fb state though, for
> > unpinning the buffer.
>
> AFAIK this register only controls the display->GT signals, but
> shouldn't affect the CPU display interrupts.
Oh right, it should just enable the wait events... so yeah we can drop
it if/until we start using vblank waits again.
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH] drm/i915: sprite support for ValleyView v4
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
` (10 preceding siblings ...)
2013-04-02 10:26 ` [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Ville Syrjälä
@ 2013-04-02 18:22 ` Jesse Barnes
2013-04-02 19:08 ` Daniel Vetter
11 siblings, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-04-02 18:22 UTC (permalink / raw)
To: intel-gfx
No constant alpha yet though, that needs a new ioctl and/or property to
get/set.
v2: use drm_plane_format_cpp (Ville)
fix up vlv_disable_plane, remove IVB bits (Ville)
remove error path rework (Ville)
fix component order confusion (Ville)
clean up platform init (Ville)
use compute_offset_xtiled (Ville)
v3: fix up more format confusion (Ville)
update to new page offset function (Ville)
v4: remove incorrect formats from framebuffer_init (Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_dma.c | 4 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 57 +++++++++
drivers/gpu/drm/i915/intel_display.c | 11 +-
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_sprite.c | 213 ++++++++++++++++++++++++++++++++--
6 files changed, 275 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ebcfe2e..4be58e3 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
mutex_init(&dev_priv->rps.hw_lock);
mutex_init(&dev_priv->modeset_restore_lock);
+ dev_priv->num_plane = 1;
+ if (IS_VALLEYVIEW(dev))
+ dev_priv->num_plane = 2;
+
ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
if (ret)
goto out_gem_unload;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1657d873..2832cdb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -914,6 +914,7 @@ typedef struct drm_i915_private {
bool enable_hotplug_processing;
int num_pch_pll;
+ int num_plane;
unsigned long cfb_size;
unsigned int cfb_fb;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bceca11..d0f7cb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3261,6 +3261,63 @@
#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
+#define _SPACNTR 0x72180
+#define SP_ENABLE (1<<31)
+#define SP_GEAMMA_ENABLE (1<<30)
+#define SP_PIXFORMAT_MASK (0xf<<26)
+#define SP_FORMAT_YUV422 (0<<26)
+#define SP_FORMAT_BGR565 (5<<26)
+#define SP_FORMAT_BGRX8888 (6<<26)
+#define SP_FORMAT_BGRA8888 (7<<26)
+#define SP_FORMAT_RGBX1010102 (8<<26)
+#define SP_FORMAT_RGBA1010102 (9<<26)
+#define SP_FORMAT_RGBX8888 (0xe<<26)
+#define SP_FORMAT_RGBA8888 (0xf<<26)
+#define SP_SOURCE_KEY (1<<22)
+#define SP_YUV_BYTE_ORDER_MASK (3<<16)
+#define SP_YUV_ORDER_YUYV (0<<16)
+#define SP_YUV_ORDER_UYVY (1<<16)
+#define SP_YUV_ORDER_YVYU (2<<16)
+#define SP_YUV_ORDER_VYUY (3<<16)
+#define SP_TILED (1<<10)
+#define _SPALINOFF 0x72184
+#define _SPASTRIDE 0x72188
+#define _SPAPOS 0x7218c
+#define _SPASIZE 0x72190
+#define _SPAKEYMINVAL 0x72194
+#define _SPAKEYMSK 0x72198
+#define _SPASURF 0x7219c
+#define _SPAKEYMAXVAL 0x721a0
+#define _SPATILEOFF 0x721a4
+#define _SPACONSTALPHA 0x721a8
+#define _SPAGAMC 0x721f4
+
+#define _SPBCNTR 0x72280
+#define _SPBLINOFF 0x72284
+#define _SPBSTRIDE 0x72288
+#define _SPBPOS 0x7228c
+#define _SPBSIZE 0x72290
+#define _SPBKEYMINVAL 0x72294
+#define _SPBKEYMSK 0x72298
+#define _SPBSURF 0x7229c
+#define _SPBKEYMAXVAL 0x722a0
+#define _SPBTILEOFF 0x722a4
+#define _SPBCONSTALPHA 0x722a8
+#define _SPBGAMC 0x722f4
+
+#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
+
/* VBIOS regs */
#define VGACNTRL 0x71400
# define VGA_DISP_DISABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7307974..afea89d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8855,7 +8855,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- int i, ret;
+ int i, j, ret;
drm_mode_config_init(dev);
@@ -8891,9 +8891,12 @@ void intel_modeset_init(struct drm_device *dev)
for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
intel_crtc_init(dev, i);
- ret = intel_plane_init(dev, i);
- if (ret)
- DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
+ for (j = 0; j < dev_priv->num_plane; j++) {
+ ret = intel_plane_init(dev, i, j);
+ if (ret)
+ DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
+ i, j, ret);
+ }
}
intel_cpu_pll_init(dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 599e978..8940741 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -242,6 +242,7 @@ struct intel_crtc {
struct intel_plane {
struct drm_plane base;
+ int plane;
enum pipe pipe;
struct drm_i915_gem_object *obj;
bool can_scale;
@@ -488,7 +489,7 @@ extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern int intel_edp_target_clock(struct intel_encoder *,
struct drm_display_mode *mode);
extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
-extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
+extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
enum plane plane);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 1b6eb76..2699026 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -37,6 +37,174 @@
#include "i915_drv.h"
static void
+vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
+ struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
+ unsigned int crtc_w, unsigned int crtc_h,
+ uint32_t x, uint32_t y,
+ uint32_t src_w, uint32_t src_h)
+{
+ struct drm_device *dev = dplane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(dplane);
+ int pipe = intel_plane->pipe;
+ int plane = intel_plane->plane;
+ u32 sprctl;
+ unsigned long sprsurf_offset, linear_offset;
+ int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+
+ sprctl = I915_READ(SPCNTR(pipe, plane));
+
+ /* Mask out pixel format bits in case we change it */
+ sprctl &= ~SP_PIXFORMAT_MASK;
+ sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
+ sprctl &= ~SP_TILED;
+
+ switch (fb->pixel_format) {
+ case DRM_FORMAT_YUYV:
+ sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
+ break;
+ case DRM_FORMAT_YVYU:
+ sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
+ break;
+ case DRM_FORMAT_UYVY:
+ sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
+ break;
+ case DRM_FORMAT_VYUY:
+ sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
+ break;
+ case DRM_FORMAT_RGB565:
+ sprctl |= SP_FORMAT_BGR565;
+ break;
+ case DRM_FORMAT_XRGB8888:
+ sprctl |= SP_FORMAT_BGRX8888;
+ break;
+ case DRM_FORMAT_ARGB8888:
+ sprctl |= SP_FORMAT_BGRA8888;
+ break;
+ case DRM_FORMAT_XBGR2101010:
+ sprctl |= SP_FORMAT_RGBX1010102;
+ break;
+ case DRM_FORMAT_ABGR2101010:
+ sprctl |= SP_FORMAT_RGBA1010102;
+ break;
+ case DRM_FORMAT_XBGR8888:
+ sprctl |= SP_FORMAT_RGBX8888;
+ break;
+ case DRM_FORMAT_ABGR8888:
+ sprctl |= SP_FORMAT_RGBA8888;
+ break;
+ default:
+ /*
+ * If we get here one of the upper layers failed to filter
+ * out the unsupported plane formats
+ */
+ BUG();
+ break;
+ }
+
+ if (obj->tiling_mode != I915_TILING_NONE)
+ sprctl |= SP_TILED;
+
+ sprctl |= SP_ENABLE;
+
+ /* Sizes are 0 based */
+ src_w--;
+ src_h--;
+ crtc_w--;
+ crtc_h--;
+
+ intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
+
+ I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
+ I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
+
+ linear_offset = y * fb->pitches[0] + x * pixel_size;
+ sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
+ obj->tiling_mode,
+ pixel_size,
+ fb->pitches[0]);
+ linear_offset -= sprsurf_offset;
+
+ if (obj->tiling_mode != I915_TILING_NONE)
+ I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
+ else
+ I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
+
+ I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
+ I915_WRITE(SPCNTR(pipe, plane), sprctl);
+ I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset +
+ sprsurf_offset);
+ POSTING_READ(SPSURF(pipe, plane));
+}
+
+static void
+vlv_disable_plane(struct drm_plane *dplane)
+{
+ struct drm_device *dev = dplane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(dplane);
+ int pipe = intel_plane->pipe;
+ int plane = intel_plane->plane;
+
+ I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
+ ~SP_ENABLE);
+ /* Activate double buffered register update */
+ I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
+ POSTING_READ(SPSURF(pipe, plane));
+}
+
+static int
+vlv_update_colorkey(struct drm_plane *dplane,
+ struct drm_intel_sprite_colorkey *key)
+{
+ struct drm_device *dev = dplane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(dplane);
+ int pipe = intel_plane->pipe;
+ int plane = intel_plane->plane;
+ u32 sprctl;
+
+ if (key->flags & I915_SET_COLORKEY_DESTINATION)
+ return -EINVAL;
+
+ I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
+ I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
+ I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
+
+ sprctl = I915_READ(SPCNTR(pipe, plane));
+ sprctl &= ~SP_SOURCE_KEY;
+ if (key->flags & I915_SET_COLORKEY_SOURCE)
+ sprctl |= SP_SOURCE_KEY;
+ I915_WRITE(SPCNTR(pipe, plane), sprctl);
+
+ POSTING_READ(SPKEYMSK(pipe, plane));
+
+ return 0;
+}
+
+static void
+vlv_get_colorkey(struct drm_plane *dplane,
+ struct drm_intel_sprite_colorkey *key)
+{
+ struct drm_device *dev = dplane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(dplane);
+ int pipe = intel_plane->pipe;
+ int plane = intel_plane->plane;
+ u32 sprctl;
+
+ key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
+ key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
+ key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
+
+ sprctl = I915_READ(SPCNTR(pipe, plane));
+ if (sprctl & SP_SOURCE_KEY)
+ key->flags = I915_SET_COLORKEY_SOURCE;
+ else
+ key->flags = I915_SET_COLORKEY_NONE;
+}
+
+static void
ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
@@ -670,8 +838,22 @@ static uint32_t snb_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static uint32_t vlv_plane_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+};
+
int
-intel_plane_init(struct drm_device *dev, enum pipe pipe)
+intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
struct intel_plane *intel_plane;
unsigned long possible_crtcs;
@@ -710,14 +892,26 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
intel_plane->can_scale = false;
else
intel_plane->can_scale = true;
- intel_plane->max_downscale = 2;
- intel_plane->update_plane = ivb_update_plane;
- intel_plane->disable_plane = ivb_disable_plane;
- intel_plane->update_colorkey = ivb_update_colorkey;
- intel_plane->get_colorkey = ivb_get_colorkey;
-
- plane_formats = snb_plane_formats;
- num_plane_formats = ARRAY_SIZE(snb_plane_formats);
+
+ if (IS_VALLEYVIEW(dev)) {
+ intel_plane->max_downscale = 1;
+ intel_plane->update_plane = vlv_update_plane;
+ intel_plane->disable_plane = vlv_disable_plane;
+ intel_plane->update_colorkey = vlv_update_colorkey;
+ intel_plane->get_colorkey = vlv_get_colorkey;
+
+ plane_formats = vlv_plane_formats;
+ num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
+ } else {
+ intel_plane->max_downscale = 2;
+ intel_plane->update_plane = ivb_update_plane;
+ intel_plane->disable_plane = ivb_disable_plane;
+ intel_plane->update_colorkey = ivb_update_colorkey;
+ intel_plane->get_colorkey = ivb_get_colorkey;
+
+ plane_formats = snb_plane_formats;
+ num_plane_formats = ARRAY_SIZE(snb_plane_formats);
+ }
break;
default:
@@ -726,6 +920,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
}
intel_plane->pipe = pipe;
+ intel_plane->plane = plane;
possible_crtcs = (1 << pipe);
ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
&intel_plane_funcs,
--
1.7.10.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH] drm/i915: add Punit read/write routines for VLV v2
2013-03-28 16:55 ` [PATCH 08/11] drm/i915: add Punit read/write routines for VLV Jesse Barnes
2013-04-02 11:37 ` Ville Syrjälä
@ 2013-04-02 18:23 ` Jesse Barnes
2013-04-02 19:00 ` Daniel Vetter
1 sibling, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-04-02 18:23 UTC (permalink / raw)
To: intel-gfx
Slightly different than other platforms.
v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine.
v3: drop turbo defines from this patch (Ville)
use PCI_DEVFN(2,0) instead of open coding (Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 14 +++++++++++
drivers/gpu/drm/i915/intel_pm.c | 53 +++++++++++++++++++++++++++++++++++++++
3 files changed, 69 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 182c494..642cb1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1845,6 +1845,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68051d6..85f8b0b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4451,6 +4451,20 @@
#define GEN6_PCODE_DATA 0x138128
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
+#define VLV_IOSF_DOORBELL_REQ 0x182100
+#define IOSF_DEVFN_SHIFT 24
+#define IOSF_OPCODE_SHIFT 16
+#define IOSF_PORT_SHIFT 8
+#define IOSF_BYTE_ENABLES_SHIFT 4
+#define IOSF_BAR_SHIFT 1
+#define IOSF_SB_BUSY (1<<0)
+#define IOSF_PORT_PUNIT 0x4
+#define VLV_IOSF_DATA 0x182104
+#define VLV_IOSF_ADDR 0x182108
+
+#define PUNIT_OPCODE_REG_READ 6
+#define PUNIT_OPCODE_REG_WRITE 7
+
#define GEN6_GT_CORE_STATUS 0x138060
#define GEN6_CORE_CPD_STATE_MASK (7<<4)
#define GEN6_RCn_MASK 7
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6fa9b79..9776281 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4525,3 +4525,56 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
return 0;
}
+
+static int vlv_punit_rw(struct drm_i915_private *dev_priv, u8 opcode,
+ u8 addr, u32 *val)
+{
+ u32 cmd, devfn, port, be, bar;
+
+ bar = 0;
+ be = 0xf;
+ port = IOSF_PORT_PUNIT;
+ devfn = PCI_DEVFN(2,0);
+
+ cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
+ (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
+ (bar << IOSF_BAR_SHIFT);
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+ DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
+ opcode == PUNIT_OPCODE_REG_READ ?
+ "read" : "write");
+ return -EAGAIN;
+ }
+
+ I915_WRITE(VLV_IOSF_ADDR, addr);
+ if (opcode == PUNIT_OPCODE_REG_WRITE)
+ I915_WRITE(VLV_IOSF_DATA, *val);
+ I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
+
+ if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
+ 500)) {
+ DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
+ opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
+ addr);
+ return -ETIMEDOUT;
+ }
+
+ if (opcode == PUNIT_OPCODE_REG_READ)
+ *val = I915_READ(VLV_IOSF_DATA);
+ I915_WRITE(VLV_IOSF_DATA, 0);
+
+ return 0;
+}
+
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+{
+ return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_READ, addr, val);
+}
+
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+{
+ return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_WRITE, addr, &val);
+}
--
1.7.10.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH] drm/i915: turbo & RC6 support for VLV v4
2013-03-28 16:55 ` [PATCH 09/11] drm/i915: turbo & RC6 support for VLV v3 Jesse Barnes
@ 2013-04-02 18:23 ` Jesse Barnes
2013-04-05 20:09 ` [PATCH] drm/i915: turbo & RC6 support for VLV v5 Jesse Barnes
0 siblings, 1 reply; 32+ messages in thread
From: Jesse Barnes @ 2013-04-02 18:23 UTC (permalink / raw)
To: intel-gfx
From: Ben Widawsky <ben@bwidawsk.net>
Uses slightly different interfaces than other platforms.
v2: track actual set freq, not requested (Rohit)
fix debug prints in init code (Jesse)
v3: don't write sleep reg (Jesse)
re-add RC6 wake limit write (Ben)
fixup thresholds to match other platforms (Ben)
clean up mem freq calculation (Ben)
clean up debug prints (Ben)
v4: move defines from punit patch (Ville)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 9 +++
drivers/gpu/drm/i915/intel_pm.c | 145 +++++++++++++++++++++++++++++++++++++--
4 files changed, 155 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 642cb1f..68f1256 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1816,6 +1816,7 @@ extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void intel_init_pch_refclk(struct drm_device *dev);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
+extern void valleyview_set_rps(struct drm_device *dev, u8 val);
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
extern int intel_enable_rc6(const struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3c2b05c..46f6f1a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -394,7 +394,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
*/
if (!(new_delay > dev_priv->rps.max_delay ||
new_delay < dev_priv->rps.min_delay)) {
- gen6_set_rps(dev_priv->dev, new_delay);
+ if (IS_VALLEYVIEW(dev_priv->dev))
+ valleyview_set_rps(dev_priv->dev, new_delay);
+ else
+ gen6_set_rps(dev_priv->dev, new_delay);
}
mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 85f8b0b..e3fcc32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4369,6 +4369,7 @@
#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
+#define GEN7_RC_CTL_TO_MODE (1<<28)
#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
#define GEN6_RC_CTL_HW_ENABLE (1<<31)
#define GEN6_RP_DOWN_TIMEOUT 0xA010
@@ -4465,6 +4466,14 @@
#define PUNIT_OPCODE_REG_READ 6
#define PUNIT_OPCODE_REG_WRITE 7
+#define PUNIT_REG_GPU_LFM 0xd3
+#define PUNIT_REG_GPU_FREQ_REQ 0xd4
+#define PUNIT_REG_GPU_FREQ_STS 0xd8
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
+
+#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+
#define GEN6_GT_CORE_STATUS 0x138060
#define GEN6_CORE_CPD_STATE_MASK (7<<4)
#define GEN6_RCn_MASK 7
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9776281..fabe013 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2477,6 +2477,47 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(val * 50);
}
+void valleyview_set_rps(struct drm_device *dev, u8 val)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long timeout = jiffies + msecs_to_jiffies(100);
+ u32 limits = gen6_rps_limits(dev_priv, &val);
+ u32 pval;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+ WARN_ON(val > dev_priv->rps.max_delay);
+ WARN_ON(val < dev_priv->rps.min_delay);
+
+ if (val == dev_priv->rps.cur_delay)
+ return;
+
+ valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+
+ do {
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ if (time_after(jiffies, timeout)) {
+ DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
+ break;
+ }
+ udelay(10);
+ } while (pval & 1);
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ if ((pval >> 8) != val)
+ DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
+ val, pval >> 8);
+
+ /* Make sure we continue to get interrupts
+ * until we hit the minimum or maximum frequencies.
+ */
+ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
+
+ dev_priv->rps.cur_delay = pval >> 8;
+
+ trace_intel_gpu_freq_change(val);
+}
+
+
static void gen6_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2716,6 +2757,97 @@ static void gen6_update_ring_freq(struct drm_device *dev)
}
}
+static void valleyview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, val;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ if ((gtfifodbg = I915_READ(GTFIFODBG))) {
+ DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ gen6_gt_force_wake_get(dev_priv);
+
+ I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+ I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
+ I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
+ I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
+ I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000);
+
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+ I915_WRITE(GEN6_RP_UP_EI, 66000);
+ I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+ I915_WRITE(GEN6_RP_CONTROL,
+ GEN6_RP_MEDIA_TURBO |
+ GEN6_RP_MEDIA_HW_NORMAL_MODE |
+ GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE |
+ GEN6_RP_UP_BUSY_AVG |
+ GEN6_RP_DOWN_IDLE_CONT);
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
+ I915_WRITE(GEN6_RC_CONTROL,
+ GEN6_RC_CTL_RC6pp_ENABLE |
+ GEN6_RC_CTL_RC6p_ENABLE |
+ GEN6_RC_CTL_RC6_ENABLE |
+ GEN7_RC_CTL_TO_MODE |
+ GEN6_RC_CTL_HW_ENABLE);
+
+ valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
+ DRM_DEBUG_DRIVER("max GPU freq: %d\n", (val >> 16) & 0xff);
+ dev_priv->rps.max_delay = (val >> 16) & 0xff;
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+ DRM_DEBUG_DRIVER("min GPU freq: %d\n", val & 0xff);
+ dev_priv->rps.min_delay = val & 0xff;
+
+ valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS2, &val);
+ DRM_DEBUG_DRIVER("max GPLL freq: %d\n", val);
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
+ dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3);
+ DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
+
+ DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 8 ? "yes" : "no");
+ DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+ DRM_DEBUG_DRIVER("current GPU freq: %x\n", (val >> 8) & 0xff);
+ dev_priv->rps.cur_delay = (val >> 8) & 0xff;
+
+ val = 0xd500;
+ DRM_DEBUG_DRIVER("setting GPU freq to %d\n", (val >> 8) & 0xff);
+
+ valleyview_set_rps(dev_priv->dev, (val >> 8) & 0xff);
+
+ /* requires MSI enabled */
+ I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+ spin_lock_irq(&dev_priv->rps.lock);
+ WARN_ON(dev_priv->rps.pm_iir != 0);
+ I915_WRITE(GEN6_PMIMR, 0);
+ spin_unlock_irq(&dev_priv->rps.lock);
+ /* enable all PM interrupts */
+ I915_WRITE(GEN6_PMINTRMSK, 0);
+
+ gen6_gt_force_wake_put(dev_priv);
+}
+
void ironlake_teardown_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3442,7 +3574,7 @@ void intel_disable_gt_powersave(struct drm_device *dev)
if (IS_IRONLAKE_M(dev)) {
ironlake_disable_drps(dev);
ironlake_disable_rc6(dev);
- } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
+ } else if (INTEL_INFO(dev)->gen >= 6) {
cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
mutex_lock(&dev_priv->rps.hw_lock);
gen6_disable_rps(dev);
@@ -3458,8 +3590,13 @@ static void intel_gen6_powersave_work(struct work_struct *work)
struct drm_device *dev = dev_priv->dev;
mutex_lock(&dev_priv->rps.hw_lock);
- gen6_enable_rps(dev);
- gen6_update_ring_freq(dev);
+
+ if (IS_VALLEYVIEW(dev)) {
+ valleyview_enable_rps(dev);
+ } else {
+ gen6_enable_rps(dev);
+ gen6_update_ring_freq(dev);
+ }
mutex_unlock(&dev_priv->rps.hw_lock);
}
@@ -3471,7 +3608,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
ironlake_enable_drps(dev);
ironlake_enable_rc6(dev);
intel_init_emon(dev);
- } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
+ } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
/*
* PCU communication is slow and this doesn't need to be
* done at any specific time, so do this out of our fast path
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH] drm/i915: drop DPFLIPSTAT enables on VLV v3
2013-03-28 16:55 ` [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use " Jesse Barnes
2013-04-02 10:37 ` Ville Syrjälä
@ 2013-04-02 18:25 ` Jesse Barnes
1 sibling, 0 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-04-02 18:25 UTC (permalink / raw)
To: intel-gfx
We don't need this until we start using the wait event commands.
v2: move to i915_irq.c (Jesse)
drop unneeded sprite flip done enables (Ville)
v3: drop the DPFLIPSTAT enables altogether (Ville)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_pm.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fabe013..556e861 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4112,19 +4112,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
/*
- * On ValleyView, the GUnit needs to signal the GT
- * when flip and other events complete. So enable
- * all the GUnit->GT interrupts here
- */
- I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
- PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
- SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
- PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
- PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
- SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
- PLANEA_FLIPDONE_INT_EN);
-
- /*
* WaDisableVLVClockGating_VBIIssue
* Disable clock gating on th GCFG unit to prevent a delay
* in the reporting of vblank events.
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH 03/11] drm/i915: update VLV PLL and DPIO code v8
2013-03-28 16:55 ` [PATCH 03/11] drm/i915: update VLV PLL and DPIO code v8 Jesse Barnes
@ 2013-04-02 18:47 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-04-02 18:47 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Mar 28, 2013 at 09:55:39AM -0700, Jesse Barnes wrote:
> In Valleyview voltage swing, pre-emphasis and lane control registers can
> be programmed only through the h/w side band fabric. Update
> vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
> appropriate programming.
>
> We need to make sure that the tx lane reset occurs in both the full mode
> set and DPMS paths, so factor things out to allow that.
>
> v2: use different DPIO_DIVISOR values for VGA and DisplayPort
> v3: Fix update pll logic to use same DPIO_DIVISOR & DPIO_REFSFR values
> for all display interfaces
> v4: collapse with various updates
> v5: squash with crtc enable/pll enable bits
> v6: split out DP code (jbarnes)
> put phyready check under IS_VALLEYVIEW (jbarnes)
> remove unneeded check in 9xx pll div update (Jani)
> wrap VLV pll update call in IS_VALLEYVIEW (Jani)
> move port enable back to end of crtc enable (jbarnes)
> put phyready check under IS_VALLEYVIEW (jbarnes)
> v7: fix up conflicts against latest drm-intel-next-queued
> v8: use DPIO reg names, fix pipes (Jani)
> from mPhy_registers_VLV2_ww20p5 doc
>
> Signed-off-by: Pallavi G <pallavi.g@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Imo this is still a bit too horrible to live. Iirc I've had a massive
bikeshed review, but then noticed that I don't understand at all what this
code does and so dropped it. A few random things I've remembered:
- There's lots of magic pipe checks, imo if (pipe == PIPE_B) reads better
than if (pipe). Especially since we also have now platforms with more
than just 2 pipes. Also s/1/PIPE_B/ at some places.
- This patch does too much, e.g. vlv_init_dpio seems to now be used as a
generic reset function in crtc_disable, but is still called _init. Also
looks like an orthogonal patch to me.
- Some of the #defines are seriously misguided as to whether they're
dealing with a pipe or a port. Last time I've check some #defines
weren't used, but I didn't bother this time around with checking them
all again.
- Some of the intel_has_type checks look fishy and would look better when
replaced with a port enum or something like that. Others look like they
hardcode pll selections in strange ways (I have no clue with all that
magic).
- intel_mode_get_pixel_multiplier is gone, so this doesn't apply on latest
dinq.
- Some function extraction looks easily doable, e.g. extracting the "port
ready" wait in mode_set and crtc_enable
- I still suspect that some of these checks/hacks predate the modeset
rework since stuff is seemingly duplicated at a bunch of places ...
I think some gentle patch splitting, slight refactoring and liberal
sprinklig of FIXME comments should get this one here into shape.
Especially if we know that a given piece of code here is just pre-silicon
hacks or hard-wired to the sdv board layout.
Cheers, Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 107 ++++++++++++-
> drivers/gpu/drm/i915/intel_display.c | 274 ++++++++++++++++++++++++++--------
> 2 files changed, 320 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d0f7cb9..858a712 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -362,6 +362,11 @@
> #define DPIO_SFR_BYPASS (1<<1)
> #define DPIO_RESET (1<<0)
>
> +#define _DPIO_TX3_SWING_CTL4_A 0x690
> +#define _DPIO_TX3_SWING_CTL4_B 0x2a90
> +#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \
> + _DPIO_TX3_SWING_CTL4_B)
> +
> #define _DPIO_DIV_A 0x800c
> #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
> #define DPIO_K_SHIFT (24) /* 4 bits */
> @@ -389,14 +394,109 @@
> #define _DPIO_CORE_CLK_B 0x803c
> #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
>
> +#define _DPIO_IREF_CTL_A 0x8040
> +#define _DPIO_IREF_CTL_B 0x8060
> +#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
> +
> +#define DPIO_IREF_BCAST 0xc044
> +#define _DPIO_IREF_A 0x8044
> +#define _DPIO_IREF_B 0x8064
> +#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)
> +
> +#define _DPIO_PLL_CML_A 0x804c
> +#define _DPIO_PLL_CML_B 0x806c
> +#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)
> +
> #define _DPIO_LFP_COEFF_A 0x8048
> #define _DPIO_LFP_COEFF_B 0x8068
> #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
>
> +#define DPIO_CALIBRATION 0x80ac
> +
> #define DPIO_FASTCLK_DISABLE 0x8100
>
> -#define DPIO_DATA_CHANNEL1 0x8220
> -#define DPIO_DATA_CHANNEL2 0x8420
> +#define _DPIO_PCS_TX_0 0x8200
> +#define _DPIO_PCS_TX_1 0x8400
> +#define DPIO_PCS_TX_LANE2_RESET (1<<16)
> +#define DPIO_PCS_TX_LANE1_RESET (1<<7)
> +#define DPIO_PCS_TX(pipe) _PIPE(pipe, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)
> +
> +#define _DPIO_PCS_CLK_0 0x8204
> +#define _DPIO_PCS_CLK_1 0x8404
> +#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
> +#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
> +#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
> +#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
> +#define DPIO_PCS_CLK(pipe) _PIPE(pipe, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)
> +
> +#define _DPIO_PCS_CTL_OVR1_A 0x8224
> +#define _DPIO_PCS_CTL_OVR1_B 0x8424
> +#define DPIO_PCS_CTL_OVER1(pipe) _PIPE(pipe, _DPIO_PCS_CTL_OVR1_A, \
> + _DPIO_PCS_CTL_OVR1_B)
> +
> +#define _DPIO_PCS_STAGGER0_A 0x822c
> +#define _DPIO_PCS_STAGGER0_B 0x842c
> +#define DPIO_PCS_STAGGER0(pipe) _PIPE(pipe, _DPIO_PCS_STAGGER0_A, \
> + _DPIO_PCS_STAGGER0_B)
> +
> +#define _DPIO_PCS_STAGGER1_A 0x8230
> +#define _DPIO_PCS_STAGGER1_B 0x8430
> +#define DPIO_PCS_STAGGER1(pipe) _PIPE(pipe, _DPIO_PCS_STAGGER1_A, \
> + _DPIO_PCS_STAGGER1_B)
> +
> +#define _DPIO_PCS_CLOCKBUF0_A 0x8238
> +#define _DPIO_PCS_CLOCKBUF0_B 0x8438
> +#define DPIO_PCS_CLOCKBUF0(pipe) _PIPE(pipe, _DPIO_PCS_CLOCKBUF0_A, \
> + _DPIO_PCS_CLOCKBUF0_B)
> +
> +#define _DPIO_PCS_CLOCKBUF8_A 0x825c
> +#define _DPIO_PCS_CLOCKBUF8_B 0x845c
> +#define DPIO_PCS_CLOCKBUF8(pipe) _PIPE(pipe, _DPIO_PCS_CLOCKBUF8_A, \
> + _DPIO_PCS_CLOCKBUF8_B)
> +
> +#define _DPIO_TX_SWING_CTL2_A 0x8288
> +#define _DPIO_TX_SWING_CTL2_B 0x8488
> +#define DPIO_TX_SWING_CTL2(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL2_A, \
> + _DPIO_TX_SWING_CTL2_B)
> +
> +#define _DPIO_TX_SWING_CTL3_A 0x828c
> +#define _DPIO_TX_SWING_CTL3_B 0x848c
> +#define DPIO_TX_SWING_CTL3(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL3_A, \
> + _DPIO_TX_SWING_CTL3_B)
> +
> +#define _DPIO_TX_SWING_CTL4_A 0x8290
> +#define _DPIO_TX_SWING_CTL4_B 0x8490
> +#define DPIO_TX_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \
> + _DPIO_TX_SWING_CTL4_B)
> +
> +#define _DPIO_TX_OCALINIT_0 0x8294
> +#define _DPIO_TX_OCALINIT_1 0x8494
> +#define DPIO_TX_OCALINIT_EN (1<<31)
> +#define DPIO_TX_OCALINIT(pipe) _PIPE(pipe, _DPIO_TX_OCALINIT_0, \
> + _DPIO_TX_OCALINIT_1)
> +
> +#define _DPIO_TX_CTL_0 0x82ac
> +#define _DPIO_TX_CTL_1 0x84ac
> +#define DPIO_TX_CTL(pipe) _PIPE(pipe, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)
> +
> +#define _DPIO_TX_LANE_0 0x82b8
> +#define _DPIO_TX_LANE_1 0x84b8
> +#define DPIO_TX_LANE(pipe) _PIPE(pipe, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
> +
> +#define _DPIO_DATA_CHANNEL1 0x8220
> +#define _DPIO_DATA_CHANNEL2 0x8420
> +#define DPIO_DATA_CHANNEL(pipe) _PIPE(pipe, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
> +
> +#define _DPIO_DATA_LANE0 0x0220
> +#define _DPIO_DATA_LANE1 0x0420
> +#define _DPIO_DATA_LANE2 0x2620
> +#define _DPIO_DATA_LANE3 0x2820
> +#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
> +#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
> +#define DPIO_DATA_CHANNEL1 0x8220
> +#define DPIO_DATA_CHANNEL2 0x8420
> +
> +#define DPIO_TX_BROADCAST 0xc044
>
> /*
> * Fence registers
> @@ -957,7 +1057,10 @@
> #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
> #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
> #define DPLL_LOCK_VLV (1<<15)
> +#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
> #define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
> +#define DPLL_PORTC_READY_MASK (0xf << 4)
> +#define DPLL_PORTB_READY_MASK (0xf)
>
> #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
> /*
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 58e3a7c..9cb0b53 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3696,6 +3696,72 @@ g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
> }
> }
>
> +static void vlv_pll_enable_reset(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + int pipe = intel_crtc->pipe;
> +
> + WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
> +
> + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
> + u32 val;
> + val = intel_dpio_read(dev_priv, _DPIO_DATA_LANE0);
> + if (pipe)
> + val |= (1<<21);
> + val |= (1<<20);
> + intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, val);
> +
> + intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(pipe),
> + 0x00760018);
> + intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(pipe),
> + 0x00400888);
> +
> + intel_dpio_write(dev_priv, DPIO_PCS_TX(pipe),
> + DPIO_PCS_TX_LANE2_RESET |
> + DPIO_PCS_TX_LANE1_RESET);
> + intel_dpio_write(dev_priv, DPIO_PCS_CLK(pipe),
> + DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> + DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> + (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> + DPIO_PCS_CLK_SOFT_RESET);
> +
> + intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(pipe), 0);
> + intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(pipe),
> + 0x2b245f5f);
> + intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(pipe),
> + 0x5578b83a);
> + intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(pipe),
> + 0x0c782040);
> + intel_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(pipe),
> + 0x2b247878);
> + intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(pipe), 0x00030000);
> + intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(pipe),
> + 0x00002000);
> + intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(pipe),
> + DPIO_TX_OCALINIT_EN);
> +
> + }
> + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
> + intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> + u32 val;
> + val = intel_dpio_read(dev_priv, _DPIO_DATA_LANE2);
> + if (pipe)
> + val |= (1<<21);
> + val |= (1<<20);
> + intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, val);
> +
> + intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(pipe),
> + 0x00760018);
> + intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(pipe),
> + 0x00400888);
> +
> + intel_dpio_write(dev_priv, DPIO_PCS_TX(pipe), 0x10080);
> + intel_dpio_write(dev_priv, DPIO_PCS_CLK(pipe), 0x00600060);
> + }
> +}
> +
> static void i9xx_crtc_enable(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> @@ -3704,6 +3770,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> struct intel_encoder *encoder;
> int pipe = intel_crtc->pipe;
> int plane = intel_crtc->plane;
> + u32 port_mask;
>
> WARN_ON(!crtc->enabled);
>
> @@ -3715,10 +3782,27 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>
> intel_enable_pll(dev_priv, pipe);
>
> + if (IS_VALLEYVIEW(dev)) {
> + mutex_lock(&dev_priv->dpio_lock);
> + vlv_pll_enable_reset(crtc);
> + mutex_unlock(&dev_priv->dpio_lock);
> + }
> +
> for_each_encoder_on_crtc(dev, crtc, encoder)
> if (encoder->pre_enable)
> encoder->pre_enable(encoder);
>
> + if (IS_VALLEYVIEW(dev)) {
> + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
> + intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> + port_mask = DPLL_PORTB_READY_MASK;
> + else
> + port_mask = DPLL_PORTC_READY_MASK; /* eDP on port C */
> +
> + if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 100))
> + DRM_ERROR("timed out waiting for port ready\n");
> + }
> +
> intel_enable_pipe(dev_priv, pipe, false);
> intel_enable_plane(dev_priv, plane, pipe);
> if (IS_G4X(dev))
> @@ -3770,6 +3854,21 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
> ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
> I915_WRITE(PFIT_CONTROL, 0);
>
> + for_each_encoder_on_crtc(dev, crtc, encoder)
> + if (encoder->post_disable)
> + encoder->post_disable(encoder);
> +
> + /* Reset lane for VLV platform*/
> + if (IS_VALLEYVIEW(dev)) {
> + mutex_lock(&dev_priv->dpio_lock);
> + intel_dpio_write(dev_priv, DPIO_PCS_TX(pipe), 0x00000000);
> + intel_dpio_write(dev_priv, DPIO_PCS_CLK(pipe), 0x00e00060);
> +
> + if (pipe)
> + vlv_init_dpio(dev);
> + mutex_unlock(&dev_priv->dpio_lock);
> + }
> +
> intel_disable_pll(dev_priv, pipe);
>
> intel_crtc->active = false;
> @@ -4338,6 +4437,31 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
> }
> }
>
> +static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
> +{
> + u32 reg_val;
> +
> + /*
> + * PLLB opamp always calibrates to max value of 0x3f, force enable it
> + * and set it to a reasonable value instead.
> + */
> + reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
> + reg_val &= 0xffffff30;
> + intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
> +
> + reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
> + reg_val &= 0x8cffffff;
> + intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
> +
> + reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
> + reg_val &= 0xffffff00;
> + intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
> +
> + reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
> + reg_val &= 0xb0ffffff;
> + intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
> +}
> +
> static void vlv_update_pll(struct drm_crtc *crtc,
> struct drm_display_mode *mode,
> struct drm_display_mode *adjusted_mode,
> @@ -4348,23 +4472,14 @@ static void vlv_update_pll(struct drm_crtc *crtc,
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_crtc->pipe;
> - u32 dpll, mdiv, pdiv;
> + u32 dpll, mdiv;
> u32 bestn, bestm1, bestm2, bestp1, bestp2;
> - bool is_sdvo;
> - u32 temp;
> + bool is_hdmi;
> + u32 coreclk, reg_val;
>
> mutex_lock(&dev_priv->dpio_lock);
>
> - is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
> - intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> -
> - dpll = DPLL_VGA_MODE_DIS;
> - dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
> - dpll |= DPLL_REFA_CLK_ENABLE_VLV;
> - dpll |= DPLL_INTEGRATED_CLOCK_VLV;
> -
> - I915_WRITE(DPLL(pipe), dpll);
> - POSTING_READ(DPLL(pipe));
> + is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
>
> bestn = clock->n;
> bestm1 = clock->m1;
> @@ -4372,71 +4487,99 @@ static void vlv_update_pll(struct drm_crtc *crtc,
> bestp1 = clock->p1;
> bestp2 = clock->p2;
>
> - /*
> - * In Valleyview PLL and program lane counter registers are exposed
> - * through DPIO interface
> - */
> + /* See eDP HDMI DPIO driver vbios notes doc */
> +
> + /* PLL B needs special handling */
> + if (pipe)
> + vlv_pllb_recal_opamp(dev_priv);
> +
> + /* Set up Tx target for periodic Rcomp update */
> + intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
> +
> + /* Disable target IRef on PLL */
> + reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
> + reg_val &= 0x00ffffff;
> + intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
> +
> + intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
> +
> + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
> + intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> + if (adjusted_mode->clock == 162000)
> + intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
> + 0x009f0003);
> + else
> + intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
> + 0x00d0000f);
> +
> + } else
> + intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
> + 0x009f0003);
> +
> + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
> + intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> + if (!pipe)
> + intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
> + 0x0df40000);
> + else
> + intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
> + 0x0df70000);
> + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
> + if (!pipe)
> + intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
> + 0x0df70000);
> + else
> + intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
> + 0x0df40000);
> + }
> +
> mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
> mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
> mdiv |= ((bestn << DPIO_N_SHIFT));
> mdiv |= (1 << DPIO_POST_DIV_SHIFT);
> mdiv |= (1 << DPIO_K_SHIFT);
> + intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
> +
> mdiv |= DPIO_ENABLE_CALIBRATION;
> intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
>
> - intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
> + coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
> + coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
> + intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
>
> - pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
> - (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
> - (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
> - (5 << DPIO_CLK_BIAS_CTL_SHIFT);
> - intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
> + intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
>
> - intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
> + /* Enable DPIO clock input */
> + dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
> + DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
> + if (pipe)
> + dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
>
> dpll |= DPLL_VCO_ENABLE;
> I915_WRITE(DPLL(pipe), dpll);
> POSTING_READ(DPLL(pipe));
> + udelay(150);
> +
> if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> DRM_ERROR("DPLL %d failed to lock\n", pipe);
>
> - intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
> -
> - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> - intel_dp_set_m_n(crtc, mode, adjusted_mode);
> -
> - I915_WRITE(DPLL(pipe), dpll);
> -
> - /* Wait for the clocks to stabilize. */
> - POSTING_READ(DPLL(pipe));
> - udelay(150);
> + if (is_hdmi) {
> + u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
>
> - temp = 0;
> - if (is_sdvo) {
> - temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> if (temp > 1)
> temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> else
> temp = 0;
> - }
> - I915_WRITE(DPLL_MD(pipe), temp);
> - POSTING_READ(DPLL_MD(pipe));
>
> - /* Now program lane control registers */
> - if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
> - || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
> - {
> - temp = 0x1000C4;
> - if(pipe == 1)
> - temp |= (1 << 21);
> - intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
> + I915_WRITE(DPLL_MD(pipe), temp);
> + POSTING_READ(DPLL_MD(pipe));
> }
> - if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
> - {
> - temp = 0x1000C4;
> - if(pipe == 1)
> - temp |= (1 << 21);
> - intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
> +
> + vlv_pll_enable_reset(crtc);
> +
> + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
> + intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> + intel_dp_set_m_n(crtc, mode, adjusted_mode);
> }
>
> mutex_unlock(&dev_priv->dpio_lock);
> @@ -4748,11 +4891,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> i8xx_update_pll(crtc, adjusted_mode, &clock,
> has_reduced_clock ? &reduced_clock : NULL,
> num_connectors);
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev)) {
> + refclk = i9xx_get_refclk(crtc, num_connectors);
> vlv_update_pll(crtc, mode, adjusted_mode, &clock,
> has_reduced_clock ? &reduced_clock : NULL,
> num_connectors);
> - else
> + } else
> i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
> has_reduced_clock ? &reduced_clock : NULL,
> num_connectors);
> @@ -4845,6 +4989,21 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>
> intel_update_watermarks(dev);
>
> + if (IS_VALLEYVIEW(dev)) {
> + u32 port_mask;
> +
> + /* Wait for Phy status bits to go low */
> + for_each_encoder_on_crtc(dev, crtc, encoder) {
> + if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> + encoder->type == INTEL_OUTPUT_HDMI)
> + port_mask = DPLL_PORTB_READY_MASK;
> + else
> + port_mask = DPLL_PORTC_READY_MASK; /* eDP */
> + if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 100))
> + DRM_ERROR("timed out waiting for port ready\n");
> + }
> + }
> +
> return ret;
> }
>
> @@ -9284,9 +9443,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
>
> ironlake_teardown_rc6(dev);
>
> - if (IS_VALLEYVIEW(dev))
> - vlv_init_dpio(dev);
> -
> mutex_unlock(&dev->struct_mutex);
>
> /* Disable the irq before mode object teardown, for the irq might
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 04/11] drm/i915/dp: fix up VLV DP handling v2
2013-03-28 16:55 ` [PATCH 04/11] drm/i915/dp: fix up VLV DP handling v2 Jesse Barnes
@ 2013-04-02 18:49 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-04-02 18:49 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Mar 28, 2013 at 09:55:40AM -0700, Jesse Barnes wrote:
> Needed to handle pre/post enable/disable paths on VLV and avoid a few
> fields that are marked reserved on VLV.
>
> v2: don't set color range or DP PLL fields (Jani)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This maze of platform checks in our DP code is getting messy. Still,
queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_dp.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2f2ec42..7fb9213 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -941,7 +941,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> else
> intel_dp->DP |= DP_PLL_FREQ_270MHZ;
> } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
> - if (!HAS_PCH_SPLIT(dev))
> + if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
> intel_dp->DP |= intel_dp->color_range;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> @@ -956,7 +956,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> if (intel_crtc->pipe == 1)
> intel_dp->DP |= DP_PIPEB_SELECT;
>
> - if (is_cpu_edp(intel_dp)) {
> + if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> /* don't miss out required setting for eDP */
> if (adjusted_mode->clock < 200000)
> intel_dp->DP |= DP_PLL_FREQ_160MHZ;
> @@ -1388,10 +1388,12 @@ static void intel_disable_dp(struct intel_encoder *encoder)
> static void intel_post_disable_dp(struct intel_encoder *encoder)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> + struct drm_device *dev = encoder->base.dev;
>
> if (is_cpu_edp(intel_dp)) {
> intel_dp_link_down(intel_dp);
> - ironlake_edp_pll_off(intel_dp);
> + if (!IS_VALLEYVIEW(dev))
> + ironlake_edp_pll_off(intel_dp);
> }
> }
>
> @@ -1417,8 +1419,9 @@ static void intel_enable_dp(struct intel_encoder *encoder)
> static void intel_pre_enable_dp(struct intel_encoder *encoder)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> + struct drm_device *dev = encoder->base.dev;
>
> - if (is_cpu_edp(intel_dp))
> + if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
> ironlake_edp_pll_on(intel_dp);
> }
>
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 05/11] drm/i915: panel power sequencing for VLV eDP v2
2013-03-28 16:55 ` [PATCH 05/11] drm/i915: panel power sequencing for VLV eDP v2 Jesse Barnes
@ 2013-04-02 18:57 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-04-02 18:57 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Mar 28, 2013 at 09:55:41AM -0700, Jesse Barnes wrote:
> PPS register offsets have changed in Valleyview.
>
> v2: don't clobber port select bits on VLV when fixing up PPS timings
> don't bother with G4x PPS regs (Jani)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Someone should have seriously considered putting a pp_mmio_base somewhere
and switching this mess over to relative offsets, abolishing all the
VLV_PIPE_FOO and PIPE._BAR madness. Whoever is volunteered to enable the
pipe B pp stuff on vlv, please adjust your expectations ;-) Maybe even
consider shoveling everything into an intel_pp struct (including the
vbt/fixup code).
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 ++
> drivers/gpu/drm/i915/intel_dp.c | 173 +++++++++++++++++++++++++++------------
> 2 files changed, 131 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 858a712..834e79f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4182,6 +4182,15 @@
> #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
> #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
>
> +#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
> +#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
> +#define VLV_PIPE_PP_ON_DELAYS(pipe) \
> + _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
> +#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
> + _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
> +#define VLV_PIPE_PP_DIVISOR(pipe) \
> + _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
> +
> #define PCH_PP_STATUS 0xc7200
> #define PCH_PP_CONTROL 0xc7204
> #define PANEL_UNLOCK_REGS (0xabcd << 16)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7fb9213..dd9efe8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -294,16 +294,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 pp_stat_reg;
>
> - return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
> + pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> + return (I915_READ(pp_stat_reg) & PP_ON) != 0;
> }
>
> static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 pp_ctrl_reg;
>
> - return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> + return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
> }
>
> static void
> @@ -311,14 +315,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 pp_stat_reg, pp_ctrl_reg;
>
> if (!is_edp(intel_dp))
> return;
> +
> + pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
> WARN(1, "eDP powered off while attempting aux channel communication.\n");
> DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
> - I915_READ(PCH_PP_STATUS),
> - I915_READ(PCH_PP_CONTROL));
> + I915_READ(pp_stat_reg),
> + I915_READ(pp_ctrl_reg));
> }
> }
>
> @@ -986,16 +995,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 pp_stat_reg, pp_ctrl_reg;
> +
> + pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
>
> DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
> - mask, value,
> - I915_READ(PCH_PP_STATUS),
> - I915_READ(PCH_PP_CONTROL));
> + mask, value,
> + I915_READ(pp_stat_reg),
> + I915_READ(pp_ctrl_reg));
>
> - if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
> + if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
> DRM_ERROR("Panel status timeout: status %08x control %08x\n",
> - I915_READ(PCH_PP_STATUS),
> - I915_READ(PCH_PP_CONTROL));
> + I915_READ(pp_stat_reg),
> + I915_READ(pp_ctrl_reg));
> }
> }
>
> @@ -1022,9 +1035,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
> * is locked
> */
>
> -static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
> +static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
> {
> - u32 control = I915_READ(PCH_PP_CONTROL);
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 control;
> + u32 pp_ctrl_reg;
> +
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> + control = I915_READ(pp_ctrl_reg);
>
> control &= ~PANEL_UNLOCK_MASK;
> control |= PANEL_UNLOCK_REGS;
> @@ -1036,6 +1055,7 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 pp;
> + u32 pp_stat_reg, pp_ctrl_reg;
>
> if (!is_edp(intel_dp))
> return;
> @@ -1054,13 +1074,16 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
> if (!ironlake_edp_have_panel_power(intel_dp))
> ironlake_wait_panel_power_cycle(intel_dp);
>
> - pp = ironlake_get_pp_control(dev_priv);
> + pp = ironlake_get_pp_control(intel_dp);
> pp |= EDP_FORCE_VDD;
> - I915_WRITE(PCH_PP_CONTROL, pp);
> - POSTING_READ(PCH_PP_CONTROL);
> - DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
> - I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
>
> + pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> + I915_WRITE(pp_ctrl_reg, pp);
> + POSTING_READ(pp_ctrl_reg);
> + DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
> + I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
> /*
> * If the panel wasn't on, delay before accessing aux channel
> */
> @@ -1075,19 +1098,23 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 pp;
> + u32 pp_stat_reg, pp_ctrl_reg;
>
> WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
>
> if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
> - pp = ironlake_get_pp_control(dev_priv);
> + pp = ironlake_get_pp_control(intel_dp);
> pp &= ~EDP_FORCE_VDD;
> - I915_WRITE(PCH_PP_CONTROL, pp);
> - POSTING_READ(PCH_PP_CONTROL);
>
> - /* Make sure sequencer is idle before allowing subsequent activity */
> - DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
> - I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
> + pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> + I915_WRITE(pp_ctrl_reg, pp);
> + POSTING_READ(pp_ctrl_reg);
>
> + /* Make sure sequencer is idle before allowing subsequent activity */
> + DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
> + I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
> msleep(intel_dp->panel_power_down_delay);
> }
> }
> @@ -1131,6 +1158,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 pp;
> + u32 pp_ctrl_reg;
>
> if (!is_edp(intel_dp))
> return;
> @@ -1144,7 +1172,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
>
> ironlake_wait_panel_power_cycle(intel_dp);
>
> - pp = ironlake_get_pp_control(dev_priv);
> + pp = ironlake_get_pp_control(intel_dp);
> if (IS_GEN5(dev)) {
> /* ILK workaround: disable reset around power sequence */
> pp &= ~PANEL_POWER_RESET;
> @@ -1156,8 +1184,10 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
> if (!IS_GEN5(dev))
> pp |= PANEL_POWER_RESET;
>
> - I915_WRITE(PCH_PP_CONTROL, pp);
> - POSTING_READ(PCH_PP_CONTROL);
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> + I915_WRITE(pp_ctrl_reg, pp);
> + POSTING_READ(pp_ctrl_reg);
>
> ironlake_wait_panel_on(intel_dp);
>
> @@ -1173,6 +1203,7 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 pp;
> + u32 pp_ctrl_reg;
>
> if (!is_edp(intel_dp))
> return;
> @@ -1181,12 +1212,15 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
>
> WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
>
> - pp = ironlake_get_pp_control(dev_priv);
> + pp = ironlake_get_pp_control(intel_dp);
> /* We need to switch off panel power _and_ force vdd, for otherwise some
> * panels get very unhappy and cease to work. */
> pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
> - I915_WRITE(PCH_PP_CONTROL, pp);
> - POSTING_READ(PCH_PP_CONTROL);
> +
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> + I915_WRITE(pp_ctrl_reg, pp);
> + POSTING_READ(pp_ctrl_reg);
>
> intel_dp->want_panel_vdd = false;
>
> @@ -1200,6 +1234,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
> u32 pp;
> + u32 pp_ctrl_reg;
>
> if (!is_edp(intel_dp))
> return;
> @@ -1212,10 +1247,13 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
> * allowing it to appear.
> */
> msleep(intel_dp->backlight_on_delay);
> - pp = ironlake_get_pp_control(dev_priv);
> + pp = ironlake_get_pp_control(intel_dp);
> pp |= EDP_BLC_ENABLE;
> - I915_WRITE(PCH_PP_CONTROL, pp);
> - POSTING_READ(PCH_PP_CONTROL);
> +
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> + I915_WRITE(pp_ctrl_reg, pp);
> + POSTING_READ(pp_ctrl_reg);
>
> intel_panel_enable_backlight(dev, pipe);
> }
> @@ -1225,6 +1263,7 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 pp;
> + u32 pp_ctrl_reg;
>
> if (!is_edp(intel_dp))
> return;
> @@ -1232,10 +1271,13 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
> intel_panel_disable_backlight(dev);
>
> DRM_DEBUG_KMS("\n");
> - pp = ironlake_get_pp_control(dev_priv);
> + pp = ironlake_get_pp_control(intel_dp);
> pp &= ~EDP_BLC_ENABLE;
> - I915_WRITE(PCH_PP_CONTROL, pp);
> - POSTING_READ(PCH_PP_CONTROL);
> +
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> + I915_WRITE(pp_ctrl_reg, pp);
> + POSTING_READ(pp_ctrl_reg);
> msleep(intel_dp->backlight_off_delay);
> }
>
> @@ -2626,15 +2668,28 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct edp_power_seq cur, vbt, spec, final;
> u32 pp_on, pp_off, pp_div, pp;
> + int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
> +
> + if (HAS_PCH_SPLIT(dev)) {
> + pp_control_reg = PCH_PP_CONTROL;
> + pp_on_reg = PCH_PP_ON_DELAYS;
> + pp_off_reg = PCH_PP_OFF_DELAYS;
> + pp_div_reg = PCH_PP_DIVISOR;
> + } else {
> + pp_control_reg = PIPEA_PP_CONTROL;
> + pp_on_reg = PIPEA_PP_ON_DELAYS;
> + pp_off_reg = PIPEA_PP_OFF_DELAYS;
> + pp_div_reg = PIPEA_PP_DIVISOR;
> + }
>
> /* Workaround: Need to write PP_CONTROL with the unlock key as
> * the very first thing. */
> - pp = ironlake_get_pp_control(dev_priv);
> - I915_WRITE(PCH_PP_CONTROL, pp);
> + pp = ironlake_get_pp_control(intel_dp);
> + I915_WRITE(pp_control_reg, pp);
>
> - pp_on = I915_READ(PCH_PP_ON_DELAYS);
> - pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> - pp_div = I915_READ(PCH_PP_DIVISOR);
> + pp_on = I915_READ(pp_on_reg);
> + pp_off = I915_READ(pp_off_reg);
> + pp_div = I915_READ(pp_div_reg);
>
> /* Pull timing values out of registers */
> cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
> @@ -2709,7 +2764,22 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> struct edp_power_seq *seq)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - u32 pp_on, pp_off, pp_div;
> + u32 pp_on, pp_off, pp_div, port_sel = 0;
> + int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
> + int pp_on_reg, pp_off_reg, pp_div_reg;
> +
> + if (HAS_PCH_SPLIT(dev)) {
> + pp_on_reg = PCH_PP_ON_DELAYS;
> + pp_off_reg = PCH_PP_OFF_DELAYS;
> + pp_div_reg = PCH_PP_DIVISOR;
> + } else {
> + pp_on_reg = PIPEA_PP_ON_DELAYS;
> + pp_off_reg = PIPEA_PP_OFF_DELAYS;
> + pp_div_reg = PIPEA_PP_DIVISOR;
> + }
> +
> + if (IS_VALLEYVIEW(dev))
> + port_sel = I915_READ(pp_on_reg) & 0xc0000000;
>
> /* And finally store the new values in the power sequencer. */
> pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
> @@ -2718,8 +2788,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> /* Compute the divisor for the pp clock, simply match the Bspec
> * formula. */
> - pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
> - << PP_REFERENCE_DIVIDER_SHIFT;
> + pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
> pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
> << PANEL_POWER_CYCLE_DELAY_SHIFT);
>
> @@ -2727,19 +2796,21 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> * power sequencer any more. */
> if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> if (is_cpu_edp(intel_dp))
> - pp_on |= PANEL_POWER_PORT_DP_A;
> + port_sel = PANEL_POWER_PORT_DP_A;
> else
> - pp_on |= PANEL_POWER_PORT_DP_D;
> + port_sel = PANEL_POWER_PORT_DP_D;
> }
>
> - I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
> - I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
> - I915_WRITE(PCH_PP_DIVISOR, pp_div);
> + pp_on |= port_sel;
> +
> + I915_WRITE(pp_on_reg, pp_on);
> + I915_WRITE(pp_off_reg, pp_off);
> + I915_WRITE(pp_div_reg, pp_div);
>
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> - I915_READ(PCH_PP_ON_DELAYS),
> - I915_READ(PCH_PP_OFF_DELAYS),
> - I915_READ(PCH_PP_DIVISOR));
> + I915_READ(pp_on_reg),
> + I915_READ(pp_off_reg),
> + I915_READ(pp_div_reg));
> }
>
> void
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 07/11] drm/i915: fix VLV limits and m/n/p calculations v2
2013-03-28 16:55 ` [PATCH 07/11] drm/i915: fix VLV limits and m/n/p calculations v2 Jesse Barnes
@ 2013-04-02 18:59 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-04-02 18:59 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Mar 28, 2013 at 09:55:43AM -0700, Jesse Barnes wrote:
> From: Pallavi G <pallavi.g@intel.com>
>
> For high res modes m n p calculation is fixed for VLV platform.
>
> v2: use 64 bit types and math (Ville)
>
> Signed-off-by: Pallavi G <pallavi.g@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
I'd love to have a fixed dp pll values look-up table like we have for
other platforms, so that we use _exactly_ what the hw guys recommend.
Also: Did I mention that I've failed to count the indent level of the vlv
pll computation function? And iirc that's been promised to eventually get
fixed ...
I'll random-punt on this one here for now.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] drm/i915: add Punit read/write routines for VLV v2
2013-04-02 18:23 ` [PATCH] drm/i915: add Punit read/write routines for VLV v2 Jesse Barnes
@ 2013-04-02 19:00 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-04-02 19:00 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Tue, Apr 02, 2013 at 11:23:05AM -0700, Jesse Barnes wrote:
> Slightly different than other platforms.
>
> v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine.
> v3: drop turbo defines from this patch (Ville)
> use PCI_DEVFN(2,0) instead of open coding (Ville)
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 10/11] drm/i915/dp: program VSwing and Preemphasis control settings on VLV
2013-03-28 16:55 ` [PATCH 10/11] drm/i915/dp: program VSwing and Preemphasis control settings on VLV Jesse Barnes
@ 2013-04-02 19:04 ` Daniel Vetter
2013-04-02 19:13 ` Jesse Barnes
0 siblings, 1 reply; 32+ messages in thread
From: Daniel Vetter @ 2013-04-02 19:04 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Mar 28, 2013 at 09:55:46AM -0700, Jesse Barnes wrote:
> From: Pallavi G <pallavi.g@intel.com>
>
> Program few Tx buffer Swing control settings through DPIO.
>
> Signed-off-by: Pallavi G <pallavi.g@intel.com>
> Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Grumpy maintainer is more grumpy:
http://lists.freedesktop.org/archives/intel-gfx/2013-March/025831.html
Cheers, Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 +-
> drivers/gpu/drm/i915/intel_dp.c | 114 +++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 115 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5cc12dc..4364829 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -451,8 +451,7 @@ u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
> return I915_READ(DPIO_DATA);
> }
>
> -static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> - u32 val)
> +void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
> {
> WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dd9efe8..557a33b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1527,7 +1527,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
>
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
> + if (IS_VALLEYVIEW(dev))
> + return DP_TRAIN_VOLTAGE_SWING_1200;
> + else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
> return DP_TRAIN_VOLTAGE_SWING_800;
> else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
> return DP_TRAIN_VOLTAGE_SWING_1200;
> @@ -1552,7 +1554,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPHASIS_0;
> }
> - } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev)) {
> + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + return DP_TRAIN_PRE_EMPHASIS_9_5;
> + case DP_TRAIN_VOLTAGE_SWING_600:
> + return DP_TRAIN_PRE_EMPHASIS_6;
> + case DP_TRAIN_VOLTAGE_SWING_800:
> + return DP_TRAIN_PRE_EMPHASIS_3_5;
> + case DP_TRAIN_VOLTAGE_SWING_1200:
> + default:
> + return DP_TRAIN_PRE_EMPHASIS_0;
> + }
> + } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_400:
> return DP_TRAIN_PRE_EMPHASIS_6;
> @@ -1577,15 +1591,111 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> }
> }
>
> +static void vlv_set_vswing_pre_emphasis(struct intel_dp *intel_dp, uint8_t v,
> + uint8_t p)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long Demph_reg_value, Preemph_reg_value,
> + Uniqtranscale_reg_value;
> + switch (p) {
> + case DP_TRAIN_PRE_EMPHASIS_0:
> + Preemph_reg_value = 0x0004000;
> + switch (v) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + Demph_reg_value = 0x2B405555;
> + Uniqtranscale_reg_value = 0x552AB83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_600:
> + Demph_reg_value = 0x2B404040;
> + Uniqtranscale_reg_value = 0x5548B83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_800:
> + Demph_reg_value = 0x2B245555;
> + Uniqtranscale_reg_value = 0x5560B83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_1200:
> + Demph_reg_value = 0x2B405555;
> + Uniqtranscale_reg_value = 0x5598DA3A;
> + break;
> + default:
> + return;
> + }
> + break;
> + case DP_TRAIN_PRE_EMPHASIS_3_5:
> + Preemph_reg_value = 0x0002000;
> + switch (v) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + Demph_reg_value = 0x2B404040;
> + Uniqtranscale_reg_value = 0x5552B83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_600:
> + Demph_reg_value = 0x2B404848;
> + Uniqtranscale_reg_value = 0x5580B83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_800:
> + Demph_reg_value = 0x2B404040;
> + Uniqtranscale_reg_value = 0x55ADDA3A;
> + break;
> + default:
> + return;
> + }
> + break;
> + case DP_TRAIN_PRE_EMPHASIS_6:
> + Preemph_reg_value = 0x0000000;
> + switch (v) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + Demph_reg_value = 0x2B305555;
> + Uniqtranscale_reg_value = 0x5570B83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_600:
> + Demph_reg_value = 0x2B2B4040;
> + Uniqtranscale_reg_value = 0x55ADDA3A;
> + break;
> + default:
> + return;
> + }
> + break;
> + case DP_TRAIN_PRE_EMPHASIS_9_5:
> + Preemph_reg_value = 0x0006000;
> + switch (v) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + Demph_reg_value = 0x1B405555;
> + Uniqtranscale_reg_value = 0x55ADDA3A;
> + break;
> + default:
> + return;
> + }
> + break;
> + default:
> + return;
> + }
> +
> + /* eDP is only on port C */
> + mutex_lock(&dev_priv->dpio_lock);
> + intel_dpio_write(dev_priv, 0x8494, 0x00000000);
> + intel_dpio_write(dev_priv, 0x8490, Demph_reg_value);
> + intel_dpio_write(dev_priv, 0x8488, Uniqtranscale_reg_value);
> + intel_dpio_write(dev_priv, 0x848c, 0x0C782040);
> + intel_dpio_write(dev_priv, 0x842c, 0x00030000);
> + intel_dpio_write(dev_priv, 0x8424, Preemph_reg_value);
> + intel_dpio_write(dev_priv, 0x8494, 0x80000000);
> + mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
> static void
> intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
> {
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> uint8_t v = 0;
> uint8_t p = 0;
> int lane;
> uint8_t voltage_max;
> uint8_t preemph_max;
>
> + if (IS_VALLEYVIEW(dev))
> + vlv_set_vswing_pre_emphasis(intel_dp, v, p);
> +
> for (lane = 0; lane < intel_dp->lane_count; lane++) {
> uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8940741..5bee2ea 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -661,6 +661,8 @@ extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
> struct drm_file *file_priv);
>
> extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
> +extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> + u32 val);
>
> /* Power-related functions, located in intel_pm.c */
> extern void intel_init_pm(struct drm_device *dev);
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH] drm/i915: sprite support for ValleyView v4
2013-04-02 18:22 ` [PATCH] drm/i915: sprite support for ValleyView v4 Jesse Barnes
@ 2013-04-02 19:08 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-04-02 19:08 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Tue, Apr 02, 2013 at 11:22:20AM -0700, Jesse Barnes wrote:
> No constant alpha yet though, that needs a new ioctl and/or property to
> get/set.
>
> v2: use drm_plane_format_cpp (Ville)
> fix up vlv_disable_plane, remove IVB bits (Ville)
> remove error path rework (Ville)
> fix component order confusion (Ville)
> clean up platform init (Ville)
> use compute_offset_xtiled (Ville)
> v3: fix up more format confusion (Ville)
> update to new page offset function (Ville)
> v4: remove incorrect formats from framebuffer_init (Ville)
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Ok, I've slurped in a few more patches and droped comments on a few
others. For the not-merged, not-commented-on ones I simply think someone
should grab vlv docs or hw and cross-check.
Cheers, Daniel
> ---
> drivers/gpu/drm/i915/i915_dma.c | 4 +
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 57 +++++++++
> drivers/gpu/drm/i915/intel_display.c | 11 +-
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_sprite.c | 213 ++++++++++++++++++++++++++++++++--
> 6 files changed, 275 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index ebcfe2e..4be58e3 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
> mutex_init(&dev_priv->rps.hw_lock);
> mutex_init(&dev_priv->modeset_restore_lock);
>
> + dev_priv->num_plane = 1;
> + if (IS_VALLEYVIEW(dev))
> + dev_priv->num_plane = 2;
> +
> ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
> if (ret)
> goto out_gem_unload;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1657d873..2832cdb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -914,6 +914,7 @@ typedef struct drm_i915_private {
> bool enable_hotplug_processing;
>
> int num_pch_pll;
> + int num_plane;
>
> unsigned long cfb_size;
> unsigned int cfb_fb;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bceca11..d0f7cb9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3261,6 +3261,63 @@
> #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
> #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>
> +#define _SPACNTR 0x72180
> +#define SP_ENABLE (1<<31)
> +#define SP_GEAMMA_ENABLE (1<<30)
> +#define SP_PIXFORMAT_MASK (0xf<<26)
> +#define SP_FORMAT_YUV422 (0<<26)
> +#define SP_FORMAT_BGR565 (5<<26)
> +#define SP_FORMAT_BGRX8888 (6<<26)
> +#define SP_FORMAT_BGRA8888 (7<<26)
> +#define SP_FORMAT_RGBX1010102 (8<<26)
> +#define SP_FORMAT_RGBA1010102 (9<<26)
> +#define SP_FORMAT_RGBX8888 (0xe<<26)
> +#define SP_FORMAT_RGBA8888 (0xf<<26)
> +#define SP_SOURCE_KEY (1<<22)
> +#define SP_YUV_BYTE_ORDER_MASK (3<<16)
> +#define SP_YUV_ORDER_YUYV (0<<16)
> +#define SP_YUV_ORDER_UYVY (1<<16)
> +#define SP_YUV_ORDER_YVYU (2<<16)
> +#define SP_YUV_ORDER_VYUY (3<<16)
> +#define SP_TILED (1<<10)
> +#define _SPALINOFF 0x72184
> +#define _SPASTRIDE 0x72188
> +#define _SPAPOS 0x7218c
> +#define _SPASIZE 0x72190
> +#define _SPAKEYMINVAL 0x72194
> +#define _SPAKEYMSK 0x72198
> +#define _SPASURF 0x7219c
> +#define _SPAKEYMAXVAL 0x721a0
> +#define _SPATILEOFF 0x721a4
> +#define _SPACONSTALPHA 0x721a8
> +#define _SPAGAMC 0x721f4
> +
> +#define _SPBCNTR 0x72280
> +#define _SPBLINOFF 0x72284
> +#define _SPBSTRIDE 0x72288
> +#define _SPBPOS 0x7228c
> +#define _SPBSIZE 0x72290
> +#define _SPBKEYMINVAL 0x72294
> +#define _SPBKEYMSK 0x72298
> +#define _SPBSURF 0x7229c
> +#define _SPBKEYMAXVAL 0x722a0
> +#define _SPBTILEOFF 0x722a4
> +#define _SPBCONSTALPHA 0x722a8
> +#define _SPBGAMC 0x722f4
> +
> +#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
> +#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
> +#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
> +#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> +#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
> +#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
> +
> /* VBIOS regs */
> #define VGACNTRL 0x71400
> # define VGA_DISP_DISABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7307974..afea89d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8855,7 +8855,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
> void intel_modeset_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int i, ret;
> + int i, j, ret;
>
> drm_mode_config_init(dev);
>
> @@ -8891,9 +8891,12 @@ void intel_modeset_init(struct drm_device *dev)
>
> for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
> intel_crtc_init(dev, i);
> - ret = intel_plane_init(dev, i);
> - if (ret)
> - DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
> + for (j = 0; j < dev_priv->num_plane; j++) {
> + ret = intel_plane_init(dev, i, j);
> + if (ret)
> + DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
> + i, j, ret);
> + }
> }
>
> intel_cpu_pll_init(dev);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 599e978..8940741 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -242,6 +242,7 @@ struct intel_crtc {
>
> struct intel_plane {
> struct drm_plane base;
> + int plane;
> enum pipe pipe;
> struct drm_i915_gem_object *obj;
> bool can_scale;
> @@ -488,7 +489,7 @@ extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
> extern int intel_edp_target_clock(struct intel_encoder *,
> struct drm_display_mode *mode);
> extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
> -extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
> +extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
> extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
> enum plane plane);
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 1b6eb76..2699026 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -37,6 +37,174 @@
> #include "i915_drv.h"
>
> static void
> +vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
> + struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
> + unsigned int crtc_w, unsigned int crtc_h,
> + uint32_t x, uint32_t y,
> + uint32_t src_w, uint32_t src_h)
> +{
> + struct drm_device *dev = dplane->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_plane *intel_plane = to_intel_plane(dplane);
> + int pipe = intel_plane->pipe;
> + int plane = intel_plane->plane;
> + u32 sprctl;
> + unsigned long sprsurf_offset, linear_offset;
> + int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> +
> + sprctl = I915_READ(SPCNTR(pipe, plane));
> +
> + /* Mask out pixel format bits in case we change it */
> + sprctl &= ~SP_PIXFORMAT_MASK;
> + sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
> + sprctl &= ~SP_TILED;
> +
> + switch (fb->pixel_format) {
> + case DRM_FORMAT_YUYV:
> + sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
> + break;
> + case DRM_FORMAT_YVYU:
> + sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
> + break;
> + case DRM_FORMAT_UYVY:
> + sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
> + break;
> + case DRM_FORMAT_VYUY:
> + sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
> + break;
> + case DRM_FORMAT_RGB565:
> + sprctl |= SP_FORMAT_BGR565;
> + break;
> + case DRM_FORMAT_XRGB8888:
> + sprctl |= SP_FORMAT_BGRX8888;
> + break;
> + case DRM_FORMAT_ARGB8888:
> + sprctl |= SP_FORMAT_BGRA8888;
> + break;
> + case DRM_FORMAT_XBGR2101010:
> + sprctl |= SP_FORMAT_RGBX1010102;
> + break;
> + case DRM_FORMAT_ABGR2101010:
> + sprctl |= SP_FORMAT_RGBA1010102;
> + break;
> + case DRM_FORMAT_XBGR8888:
> + sprctl |= SP_FORMAT_RGBX8888;
> + break;
> + case DRM_FORMAT_ABGR8888:
> + sprctl |= SP_FORMAT_RGBA8888;
> + break;
> + default:
> + /*
> + * If we get here one of the upper layers failed to filter
> + * out the unsupported plane formats
> + */
> + BUG();
> + break;
> + }
> +
> + if (obj->tiling_mode != I915_TILING_NONE)
> + sprctl |= SP_TILED;
> +
> + sprctl |= SP_ENABLE;
> +
> + /* Sizes are 0 based */
> + src_w--;
> + src_h--;
> + crtc_w--;
> + crtc_h--;
> +
> + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
> +
> + I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
> + I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
> +
> + linear_offset = y * fb->pitches[0] + x * pixel_size;
> + sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
> + obj->tiling_mode,
> + pixel_size,
> + fb->pitches[0]);
> + linear_offset -= sprsurf_offset;
> +
> + if (obj->tiling_mode != I915_TILING_NONE)
> + I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
> + else
> + I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
> +
> + I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
> + I915_WRITE(SPCNTR(pipe, plane), sprctl);
> + I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset +
> + sprsurf_offset);
> + POSTING_READ(SPSURF(pipe, plane));
> +}
> +
> +static void
> +vlv_disable_plane(struct drm_plane *dplane)
> +{
> + struct drm_device *dev = dplane->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_plane *intel_plane = to_intel_plane(dplane);
> + int pipe = intel_plane->pipe;
> + int plane = intel_plane->plane;
> +
> + I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
> + ~SP_ENABLE);
> + /* Activate double buffered register update */
> + I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
> + POSTING_READ(SPSURF(pipe, plane));
> +}
> +
> +static int
> +vlv_update_colorkey(struct drm_plane *dplane,
> + struct drm_intel_sprite_colorkey *key)
> +{
> + struct drm_device *dev = dplane->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_plane *intel_plane = to_intel_plane(dplane);
> + int pipe = intel_plane->pipe;
> + int plane = intel_plane->plane;
> + u32 sprctl;
> +
> + if (key->flags & I915_SET_COLORKEY_DESTINATION)
> + return -EINVAL;
> +
> + I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
> + I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
> + I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
> +
> + sprctl = I915_READ(SPCNTR(pipe, plane));
> + sprctl &= ~SP_SOURCE_KEY;
> + if (key->flags & I915_SET_COLORKEY_SOURCE)
> + sprctl |= SP_SOURCE_KEY;
> + I915_WRITE(SPCNTR(pipe, plane), sprctl);
> +
> + POSTING_READ(SPKEYMSK(pipe, plane));
> +
> + return 0;
> +}
> +
> +static void
> +vlv_get_colorkey(struct drm_plane *dplane,
> + struct drm_intel_sprite_colorkey *key)
> +{
> + struct drm_device *dev = dplane->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_plane *intel_plane = to_intel_plane(dplane);
> + int pipe = intel_plane->pipe;
> + int plane = intel_plane->plane;
> + u32 sprctl;
> +
> + key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
> + key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
> + key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
> +
> + sprctl = I915_READ(SPCNTR(pipe, plane));
> + if (sprctl & SP_SOURCE_KEY)
> + key->flags = I915_SET_COLORKEY_SOURCE;
> + else
> + key->flags = I915_SET_COLORKEY_NONE;
> +}
> +
> +static void
> ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
> struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
> unsigned int crtc_w, unsigned int crtc_h,
> @@ -670,8 +838,22 @@ static uint32_t snb_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
> +static uint32_t vlv_plane_formats[] = {
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ABGR2101010,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> +};
> +
> int
> -intel_plane_init(struct drm_device *dev, enum pipe pipe)
> +intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
> {
> struct intel_plane *intel_plane;
> unsigned long possible_crtcs;
> @@ -710,14 +892,26 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
> intel_plane->can_scale = false;
> else
> intel_plane->can_scale = true;
> - intel_plane->max_downscale = 2;
> - intel_plane->update_plane = ivb_update_plane;
> - intel_plane->disable_plane = ivb_disable_plane;
> - intel_plane->update_colorkey = ivb_update_colorkey;
> - intel_plane->get_colorkey = ivb_get_colorkey;
> -
> - plane_formats = snb_plane_formats;
> - num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> +
> + if (IS_VALLEYVIEW(dev)) {
> + intel_plane->max_downscale = 1;
> + intel_plane->update_plane = vlv_update_plane;
> + intel_plane->disable_plane = vlv_disable_plane;
> + intel_plane->update_colorkey = vlv_update_colorkey;
> + intel_plane->get_colorkey = vlv_get_colorkey;
> +
> + plane_formats = vlv_plane_formats;
> + num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> + } else {
> + intel_plane->max_downscale = 2;
> + intel_plane->update_plane = ivb_update_plane;
> + intel_plane->disable_plane = ivb_disable_plane;
> + intel_plane->update_colorkey = ivb_update_colorkey;
> + intel_plane->get_colorkey = ivb_get_colorkey;
> +
> + plane_formats = snb_plane_formats;
> + num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> + }
> break;
>
> default:
> @@ -726,6 +920,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
> }
>
> intel_plane->pipe = pipe;
> + intel_plane->plane = plane;
> possible_crtcs = (1 << pipe);
> ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
> &intel_plane_funcs,
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 10/11] drm/i915/dp: program VSwing and Preemphasis control settings on VLV
2013-04-02 19:04 ` Daniel Vetter
@ 2013-04-02 19:13 ` Jesse Barnes
0 siblings, 0 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-04-02 19:13 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, 2 Apr 2013 21:04:29 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Mar 28, 2013 at 09:55:46AM -0700, Jesse Barnes wrote:
> > From: Pallavi G <pallavi.g@intel.com>
> >
> > Program few Tx buffer Swing control settings through DPIO.
> >
> > Signed-off-by: Pallavi G <pallavi.g@intel.com>
> > Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
>
> Grumpy maintainer is more grumpy:
>
> http://lists.freedesktop.org/archives/intel-gfx/2013-March/025831.html
Sorry I did see that mail but must have missed the update. Will fix.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH] drm/i915: turbo & RC6 support for VLV v5
2013-04-02 18:23 ` [PATCH] drm/i915: turbo & RC6 support for VLV v4 Jesse Barnes
@ 2013-04-05 20:09 ` Jesse Barnes
0 siblings, 0 replies; 32+ messages in thread
From: Jesse Barnes @ 2013-04-05 20:09 UTC (permalink / raw)
To: intel-gfx
From: Ben Widawsky <ben@bwidawsk.net>
Uses slightly different interfaces than other platforms.
v2: track actual set freq, not requested (Rohit)
fix debug prints in init code (Jesse)
v3: don't write sleep reg (Jesse)
re-add RC6 wake limit write (Ben)
fixup thresholds to match other platforms (Ben)
clean up mem freq calculation (Ben)
clean up debug prints (Ben)
v4: move defines from punit patch (Ville)
v5: remove writes to nonexistent regs (Jesse)
put RP and RC regs together (Jesse)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
fix up rc6:
- don't write nonexistent regs
- put RP and RC regs together
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 9 +++
drivers/gpu/drm/i915/intel_pm.c | 137 +++++++++++++++++++++++++++++++++++++--
4 files changed, 147 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e4fa36d..d31a11f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1842,6 +1842,7 @@ extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void intel_init_pch_refclk(struct drm_device *dev);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
+extern void valleyview_set_rps(struct drm_device *dev, u8 val);
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
extern int intel_enable_rc6(const struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4c5bdd0..8eda16e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -448,7 +448,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
*/
if (!(new_delay > dev_priv->rps.max_delay ||
new_delay < dev_priv->rps.min_delay)) {
- gen6_set_rps(dev_priv->dev, new_delay);
+ if (IS_VALLEYVIEW(dev_priv->dev))
+ valleyview_set_rps(dev_priv->dev, new_delay);
+ else
+ gen6_set_rps(dev_priv->dev, new_delay);
}
mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 466bfb2..e267aa2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4403,6 +4403,7 @@
#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
+#define GEN7_RC_CTL_TO_MODE (1<<28)
#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
#define GEN6_RC_CTL_HW_ENABLE (1<<31)
#define GEN6_RP_DOWN_TIMEOUT 0xA010
@@ -4499,6 +4500,14 @@
#define PUNIT_OPCODE_REG_READ 6
#define PUNIT_OPCODE_REG_WRITE 7
+#define PUNIT_REG_GPU_LFM 0xd3
+#define PUNIT_REG_GPU_FREQ_REQ 0xd4
+#define PUNIT_REG_GPU_FREQ_STS 0xd8
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
+
+#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+
#define GEN6_GT_CORE_STATUS 0x138060
#define GEN6_CORE_CPD_STATE_MASK (7<<4)
#define GEN6_RCn_MASK 7
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 13a0666..3234d81 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2481,6 +2481,47 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(val * 50);
}
+void valleyview_set_rps(struct drm_device *dev, u8 val)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long timeout = jiffies + msecs_to_jiffies(100);
+ u32 limits = gen6_rps_limits(dev_priv, &val);
+ u32 pval;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+ WARN_ON(val > dev_priv->rps.max_delay);
+ WARN_ON(val < dev_priv->rps.min_delay);
+
+ if (val == dev_priv->rps.cur_delay)
+ return;
+
+ valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+
+ do {
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ if (time_after(jiffies, timeout)) {
+ DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
+ break;
+ }
+ udelay(10);
+ } while (pval & 1);
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ if ((pval >> 8) != val)
+ DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
+ val, pval >> 8);
+
+ /* Make sure we continue to get interrupts
+ * until we hit the minimum or maximum frequencies.
+ */
+ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
+
+ dev_priv->rps.cur_delay = pval >> 8;
+
+ trace_intel_gpu_freq_change(val);
+}
+
+
static void gen6_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2727,6 +2768,89 @@ static void gen6_update_ring_freq(struct drm_device *dev)
}
}
+static void valleyview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, val;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ if ((gtfifodbg = I915_READ(GTFIFODBG))) {
+ DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ gen6_gt_force_wake_get(dev_priv);
+
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+ I915_WRITE(GEN6_RP_UP_EI, 66000);
+ I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+ I915_WRITE(GEN6_RP_CONTROL,
+ GEN6_RP_MEDIA_TURBO |
+ GEN6_RP_MEDIA_HW_NORMAL_MODE |
+ GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE |
+ GEN6_RP_UP_BUSY_AVG |
+ GEN6_RP_DOWN_IDLE_CONT);
+
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
+ I915_WRITE(GEN6_RC_CONTROL,
+ GEN7_RC_CTL_TO_MODE);
+
+ valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
+ DRM_DEBUG_DRIVER("max GPU freq: %d\n", (val >> 16) & 0xff);
+ dev_priv->rps.max_delay = (val >> 16) & 0xff;
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+ DRM_DEBUG_DRIVER("min GPU freq: %d\n", val & 0xff);
+ dev_priv->rps.min_delay = val & 0xff;
+
+ valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS2, &val);
+ DRM_DEBUG_DRIVER("max GPLL freq: %d\n", val);
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
+ dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3);
+ DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
+
+ DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 8 ? "yes" : "no");
+ DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+ DRM_DEBUG_DRIVER("current GPU freq: %x\n", (val >> 8) & 0xff);
+ dev_priv->rps.cur_delay = (val >> 8) & 0xff;
+
+ val = 0xd500;
+ DRM_DEBUG_DRIVER("setting GPU freq to %d\n", (val >> 8) & 0xff);
+
+ valleyview_set_rps(dev_priv->dev, (val >> 8) & 0xff);
+
+ /* requires MSI enabled */
+ I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+ spin_lock_irq(&dev_priv->rps.lock);
+ WARN_ON(dev_priv->rps.pm_iir != 0);
+ I915_WRITE(GEN6_PMIMR, 0);
+ spin_unlock_irq(&dev_priv->rps.lock);
+ /* enable all PM interrupts */
+ I915_WRITE(GEN6_PMINTRMSK, 0);
+
+ gen6_gt_force_wake_put(dev_priv);
+}
+
void ironlake_teardown_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3453,7 +3577,7 @@ void intel_disable_gt_powersave(struct drm_device *dev)
if (IS_IRONLAKE_M(dev)) {
ironlake_disable_drps(dev);
ironlake_disable_rc6(dev);
- } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
+ } else if (INTEL_INFO(dev)->gen >= 6) {
cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
mutex_lock(&dev_priv->rps.hw_lock);
gen6_disable_rps(dev);
@@ -3469,8 +3593,13 @@ static void intel_gen6_powersave_work(struct work_struct *work)
struct drm_device *dev = dev_priv->dev;
mutex_lock(&dev_priv->rps.hw_lock);
- gen6_enable_rps(dev);
- gen6_update_ring_freq(dev);
+
+ if (IS_VALLEYVIEW(dev)) {
+ valleyview_enable_rps(dev);
+ } else {
+ gen6_enable_rps(dev);
+ gen6_update_ring_freq(dev);
+ }
mutex_unlock(&dev_priv->rps.hw_lock);
}
@@ -3482,7 +3611,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
ironlake_enable_drps(dev);
ironlake_enable_rc6(dev);
intel_init_emon(dev);
- } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
+ } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
/*
* PCU communication is slow and this doesn't need to be
* done at any specific time, so do this out of our fast path
--
1.7.10.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
end of thread, other threads:[~2013-04-05 20:09 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-03-28 16:55 [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Jesse Barnes
2013-03-28 16:55 ` [PATCH 02/11] drm/i915: add sprite assertion function for VLV Jesse Barnes
2013-03-28 16:55 ` [PATCH 03/11] drm/i915: update VLV PLL and DPIO code v8 Jesse Barnes
2013-04-02 18:47 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 04/11] drm/i915/dp: fix up VLV DP handling v2 Jesse Barnes
2013-04-02 18:49 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 05/11] drm/i915: panel power sequencing for VLV eDP v2 Jesse Barnes
2013-04-02 18:57 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 06/11] drm/i915: add power context allocation and setup on VLV v4 Jesse Barnes
2013-03-28 16:55 ` [PATCH 07/11] drm/i915: fix VLV limits and m/n/p calculations v2 Jesse Barnes
2013-04-02 18:59 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 08/11] drm/i915: add Punit read/write routines for VLV Jesse Barnes
2013-04-02 11:37 ` Ville Syrjälä
2013-04-02 18:19 ` Jesse Barnes
2013-04-02 18:23 ` [PATCH] drm/i915: add Punit read/write routines for VLV v2 Jesse Barnes
2013-04-02 19:00 ` Daniel Vetter
2013-03-28 16:55 ` [PATCH 09/11] drm/i915: turbo & RC6 support for VLV v3 Jesse Barnes
2013-04-02 18:23 ` [PATCH] drm/i915: turbo & RC6 support for VLV v4 Jesse Barnes
2013-04-05 20:09 ` [PATCH] drm/i915: turbo & RC6 support for VLV v5 Jesse Barnes
2013-03-28 16:55 ` [PATCH 10/11] drm/i915/dp: program VSwing and Preemphasis control settings on VLV Jesse Barnes
2013-04-02 19:04 ` Daniel Vetter
2013-04-02 19:13 ` Jesse Barnes
2013-03-28 16:55 ` [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use " Jesse Barnes
2013-04-02 10:37 ` Ville Syrjälä
2013-04-02 18:09 ` Jesse Barnes
2013-04-02 18:14 ` Ville Syrjälä
2013-04-02 18:20 ` Jesse Barnes
2013-04-02 18:25 ` [PATCH] drm/i915: drop DPFLIPSTAT enables on VLV v3 Jesse Barnes
2013-04-02 10:26 ` [PATCH 01/11] drm/i915: sprite support for ValleyView v3 Ville Syrjälä
2013-04-02 18:12 ` Jesse Barnes
2013-04-02 18:22 ` [PATCH] drm/i915: sprite support for ValleyView v4 Jesse Barnes
2013-04-02 19:08 ` Daniel Vetter
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