* [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT
@ 2013-04-17 21:15 Paulo Zanoni
2013-05-06 20:23 ` Paulo Zanoni
2013-05-07 13:10 ` Damien Lespiau
0 siblings, 2 replies; 8+ messages in thread
From: Paulo Zanoni @ 2013-04-17 21:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
This should prevent mode set failures on LPT.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 413877d..15ff0ac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
I915_WRITE(SOUTH_DSPCLK_GATE_D,
I915_READ(SOUTH_DSPCLK_GATE_D) |
PCH_LP_PARTITION_LEVEL_DISABLE);
+
+ /* WADPOClockGatingDisable */
+ I915_WRITE(_TRANSA_CHICKEN1,
+ I915_READ(_TRANSA_CHICKEN1) |
+ TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
static void haswell_init_clock_gating(struct drm_device *dev)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT
2013-04-17 21:15 [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT Paulo Zanoni
@ 2013-05-06 20:23 ` Paulo Zanoni
2013-05-07 13:10 ` Damien Lespiau
1 sibling, 0 replies; 8+ messages in thread
From: Paulo Zanoni @ 2013-05-06 20:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
2013/4/17 Paulo Zanoni <przanoni@gmail.com>:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This should prevent mode set failures on LPT.
>
Ping?
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 413877d..15ff0ac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> I915_WRITE(SOUTH_DSPCLK_GATE_D,
> I915_READ(SOUTH_DSPCLK_GATE_D) |
> PCH_LP_PARTITION_LEVEL_DISABLE);
> +
> + /* WADPOClockGatingDisable */
> + I915_WRITE(_TRANSA_CHICKEN1,
> + I915_READ(_TRANSA_CHICKEN1) |
> + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> }
>
> static void haswell_init_clock_gating(struct drm_device *dev)
> --
> 1.7.10.4
>
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT
2013-04-17 21:15 [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT Paulo Zanoni
2013-05-06 20:23 ` Paulo Zanoni
@ 2013-05-07 13:10 ` Damien Lespiau
2013-05-07 13:30 ` Damien Lespiau
1 sibling, 1 reply; 8+ messages in thread
From: Damien Lespiau @ 2013-05-07 13:10 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Wed, Apr 17, 2013 at 06:15:49PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This should prevent mode set failures on LPT.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 413877d..15ff0ac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> I915_WRITE(SOUTH_DSPCLK_GATE_D,
> I915_READ(SOUTH_DSPCLK_GATE_D) |
> PCH_LP_PARTITION_LEVEL_DISABLE);
> +
> + /* WADPOClockGatingDisable */
> + I915_WRITE(_TRANSA_CHICKEN1,
> + I915_READ(_TRANSA_CHICKEN1) |
> + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
Don't you need to do that for each pipe? (like the cpt_ version does)?
--
Damien
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT
2013-05-07 13:10 ` Damien Lespiau
@ 2013-05-07 13:30 ` Damien Lespiau
2013-05-07 13:46 ` Paulo Zanoni
0 siblings, 1 reply; 8+ messages in thread
From: Damien Lespiau @ 2013-05-07 13:30 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Tue, May 07, 2013 at 02:10:05PM +0100, Damien Lespiau wrote:
> On Wed, Apr 17, 2013 at 06:15:49PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > This should prevent mode set failures on LPT.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 413877d..15ff0ac 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> > I915_WRITE(SOUTH_DSPCLK_GATE_D,
> > I915_READ(SOUTH_DSPCLK_GATE_D) |
> > PCH_LP_PARTITION_LEVEL_DISABLE);
> > +
> > + /* WADPOClockGatingDisable */
> > + I915_WRITE(_TRANSA_CHICKEN1,
> > + I915_READ(_TRANSA_CHICKEN1) |
> > + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>
> Don't you need to do that for each pipe? (like the cpt_ version does)?
Also it's DP0 (zero), not DPO.
--
Damien
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT
2013-05-07 13:30 ` Damien Lespiau
@ 2013-05-07 13:46 ` Paulo Zanoni
2013-05-07 14:40 ` Damien Lespiau
0 siblings, 1 reply; 8+ messages in thread
From: Paulo Zanoni @ 2013-05-07 13:46 UTC (permalink / raw)
To: Damien Lespiau; +Cc: intel-gfx, Paulo Zanoni
2013/5/7 Damien Lespiau <damien.lespiau@intel.com>:
> On Tue, May 07, 2013 at 02:10:05PM +0100, Damien Lespiau wrote:
>> On Wed, Apr 17, 2013 at 06:15:49PM -0300, Paulo Zanoni wrote:
>> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> >
>> > This should prevent mode set failures on LPT.
>> >
>> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>> > 1 file changed, 5 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index 413877d..15ff0ac 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
>> > I915_WRITE(SOUTH_DSPCLK_GATE_D,
>> > I915_READ(SOUTH_DSPCLK_GATE_D) |
>> > PCH_LP_PARTITION_LEVEL_DISABLE);
>> > +
>> > + /* WADPOClockGatingDisable */
>> > + I915_WRITE(_TRANSA_CHICKEN1,
>> > + I915_READ(_TRANSA_CHICKEN1) |
>> > + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>>
>> Don't you need to do that for each pipe? (like the cpt_ version does)?
It's once per PCH transcoder, but there's just one PCH transcoder on
LPT, so we do it once.
>
> Also it's DP0 (zero), not DPO.
Our documentation is a little inconsistent regarding this, but I guess
the correct name probably has the letter O instead of Zero. The
description inside the LPT TRANS_CHICKEN1 register uses
WADPOClockGatingDisable and the register bit is called "dpounit Gating
Disable". The "BUN" email I got consistently says DPO instead of DP0.
On the CPT/PPT documentation you'll see WADP0ClockGatingDisable but
even the register bit is called "dpounit" and not "dp0unit". So the
only place where I see Zero is on the WA name written inside the CPT
documentation, all the other places use the letter O.
>
> --
> Damien
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT
2013-05-07 13:46 ` Paulo Zanoni
@ 2013-05-07 14:40 ` Damien Lespiau
2013-05-08 12:54 ` Damien Lespiau
0 siblings, 1 reply; 8+ messages in thread
From: Damien Lespiau @ 2013-05-07 14:40 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Tue, May 07, 2013 at 10:46:01AM -0300, Paulo Zanoni wrote:
> 2013/5/7 Damien Lespiau <damien.lespiau@intel.com>:
> > On Tue, May 07, 2013 at 02:10:05PM +0100, Damien Lespiau wrote:
> >> On Wed, Apr 17, 2013 at 06:15:49PM -0300, Paulo Zanoni wrote:
> >> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >> >
> >> > This should prevent mode set failures on LPT.
> >> >
> >> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> >> > 1 file changed, 5 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> > index 413877d..15ff0ac 100644
> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> > @@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> >> > I915_WRITE(SOUTH_DSPCLK_GATE_D,
> >> > I915_READ(SOUTH_DSPCLK_GATE_D) |
> >> > PCH_LP_PARTITION_LEVEL_DISABLE);
> >> > +
> >> > + /* WADPOClockGatingDisable */
> >> > + I915_WRITE(_TRANSA_CHICKEN1,
> >> > + I915_READ(_TRANSA_CHICKEN1) |
> >> > + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> >>
> >> Don't you need to do that for each pipe? (like the cpt_ version does)?
>
> It's once per PCH transcoder, but there's just one PCH transcoder on
> LPT, so we do it once.
Of course, I was looking at the wrong doc.
>
> >
> > Also it's DP0 (zero), not DPO.
>
> Our documentation is a little inconsistent regarding this, but I guess
> the correct name probably has the letter O instead of Zero. The
> description inside the LPT TRANS_CHICKEN1 register uses
> WADPOClockGatingDisable and the register bit is called "dpounit Gating
> Disable". The "BUN" email I got consistently says DPO instead of DP0.
> On the CPT/PPT documentation you'll see WADP0ClockGatingDisable but
> even the register bit is called "dpounit" and not "dp0unit". So the
> only place where I see Zero is on the WA name written inside the CPT
> documentation, all the other places use the letter O.
Conviced (but then we should rename the cpt_ comment for consistency)
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT
2013-05-07 14:40 ` Damien Lespiau
@ 2013-05-08 12:54 ` Damien Lespiau
2013-05-10 19:00 ` Daniel Vetter
0 siblings, 1 reply; 8+ messages in thread
From: Damien Lespiau @ 2013-05-08 12:54 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Tue, May 07, 2013 at 03:40:21PM +0100, Damien Lespiau wrote:
> On Tue, May 07, 2013 at 10:46:01AM -0300, Paulo Zanoni wrote:
> > 2013/5/7 Damien Lespiau <damien.lespiau@intel.com>:
> > > On Tue, May 07, 2013 at 02:10:05PM +0100, Damien Lespiau wrote:
> > >> On Wed, Apr 17, 2013 at 06:15:49PM -0300, Paulo Zanoni wrote:
> > >> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > >> >
> > >> > This should prevent mode set failures on LPT.
> > >> >
> > >> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > >> > ---
> > >> > drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> > >> > 1 file changed, 5 insertions(+)
> > >> >
> > >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > >> > index 413877d..15ff0ac 100644
> > >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > >> > @@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> > >> > I915_WRITE(SOUTH_DSPCLK_GATE_D,
> > >> > I915_READ(SOUTH_DSPCLK_GATE_D) |
> > >> > PCH_LP_PARTITION_LEVEL_DISABLE);
> > >> > +
> > >> > + /* WADPOClockGatingDisable */
> > >> > + I915_WRITE(_TRANSA_CHICKEN1,
> > >> > + I915_READ(_TRANSA_CHICKEN1) |
> > >> > + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
Of course, It'd be good to add the :hsw at the end of
WADPOClockGatingDisable (ammending the patch when applying?) now that
the workaround documentation has been pushed.
(Still Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> of course)
--
Damien
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT
2013-05-08 12:54 ` Damien Lespiau
@ 2013-05-10 19:00 ` Daniel Vetter
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Vetter @ 2013-05-10 19:00 UTC (permalink / raw)
To: Damien Lespiau; +Cc: intel-gfx, Paulo Zanoni
On Wed, May 08, 2013 at 01:54:17PM +0100, Damien Lespiau wrote:
> On Tue, May 07, 2013 at 03:40:21PM +0100, Damien Lespiau wrote:
> > On Tue, May 07, 2013 at 10:46:01AM -0300, Paulo Zanoni wrote:
> > > 2013/5/7 Damien Lespiau <damien.lespiau@intel.com>:
> > > > On Tue, May 07, 2013 at 02:10:05PM +0100, Damien Lespiau wrote:
> > > >> On Wed, Apr 17, 2013 at 06:15:49PM -0300, Paulo Zanoni wrote:
> > > >> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > >> >
> > > >> > This should prevent mode set failures on LPT.
> > > >> >
> > > >> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > >> > ---
> > > >> > drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> > > >> > 1 file changed, 5 insertions(+)
> > > >> >
> > > >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > >> > index 413877d..15ff0ac 100644
> > > >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > >> > @@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> > > >> > I915_WRITE(SOUTH_DSPCLK_GATE_D,
> > > >> > I915_READ(SOUTH_DSPCLK_GATE_D) |
> > > >> > PCH_LP_PARTITION_LEVEL_DISABLE);
> > > >> > +
> > > >> > + /* WADPOClockGatingDisable */
> > > >> > + I915_WRITE(_TRANSA_CHICKEN1,
> > > >> > + I915_READ(_TRANSA_CHICKEN1) |
> > > >> > + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>
>
> Of course, It'd be good to add the :hsw at the end of
> WADPOClockGatingDisable (ammending the patch when applying?) now that
> the workaround documentation has been pushed.
Done and queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2013-05-10 18:57 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-04-17 21:15 [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT Paulo Zanoni
2013-05-06 20:23 ` Paulo Zanoni
2013-05-07 13:10 ` Damien Lespiau
2013-05-07 13:30 ` Damien Lespiau
2013-05-07 13:46 ` Paulo Zanoni
2013-05-07 14:40 ` Damien Lespiau
2013-05-08 12:54 ` Damien Lespiau
2013-05-10 19:00 ` Daniel Vetter
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