* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
Marvell EBU SoCs share some common clock functions that register core
clocks or clock gates from SoC specific data. These clock drivers are
organized by function and over time the drivers filled up with #ifdefs
to separate different SoC specific code.
This patch set first adds a new element to clock gate descriptors to
allow to pass clk flags per clock gate. (Patch 1)
Then it restructures MVEBU clock drivers into common clock setup and
SoC specific files and Kconfig options. The driver's init functions
are also registered to get called with of_clk_init. (Patches 2, 3-6)
It then switches Dove, Kirkwood, and Armada 370/XP to make use of
of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
Finally, all obsolete files and Kconfig options are removed. (Patch 10)
It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
Armada 370 and XP are compile tested only and should get their Tested-by
from Thomas and Gregory, respectively.
@Mike: As this only touches MVEBU related code, I suggest to take it
all through the corresponding ARM branch.
Sebastian Hesselbarth (10):
clk: mvebu: introduce per-clock-gate flags
clk: mvebu: add common clock functions for core clk and clk gating
clk: mvebu: add Dove SoC-centric clock init
clk: mvebu: add Kirkwood SoC-centric clock init
clk: mvebu: add Armada 370 SoC-centric clock init
clk: mvebu: add Armada XP SoC-centric clock init
ARM: dove: move DT boards to SoC-centric clock init
ARM: kirkwood: move DT boards to SoC-centric clock init
ARM: mvebu: move DT boards to SoC-centric clock init
clk: mvebu: desintegrate obsolete file
arch/arm/mach-dove/Kconfig | 3 +-
arch/arm/mach-dove/board-dt.c | 3 +-
arch/arm/mach-dove/common.c | 1 -
arch/arm/mach-kirkwood/Kconfig | 3 +-
arch/arm/mach-kirkwood/board-dt.c | 3 +-
arch/arm/mach-mvebu/Kconfig | 5 +-
arch/arm/mach-mvebu/armada-370-xp.c | 4 +-
drivers/clk/mvebu/Kconfig | 25 +-
drivers/clk/mvebu/Makefile | 8 +-
drivers/clk/mvebu/armada-370.c | 176 +++++++++
drivers/clk/mvebu/armada-xp.c | 204 +++++++++++
drivers/clk/mvebu/clk-core.c | 675 -----------------------------------
drivers/clk/mvebu/clk-core.h | 18 -
drivers/clk/mvebu/clk-gating-ctrl.c | 250 -------------
drivers/clk/mvebu/clk-gating-ctrl.h | 22 --
drivers/clk/mvebu/clk.c | 23 --
drivers/clk/mvebu/common.c | 163 +++++++++
drivers/clk/mvebu/common.h | 48 +++
drivers/clk/mvebu/dove.c | 194 ++++++++++
drivers/clk/mvebu/kirkwood.c | 247 +++++++++++++
include/linux/clk/mvebu.h | 22 --
21 files changed, 1066 insertions(+), 1031 deletions(-)
create mode 100644 drivers/clk/mvebu/armada-370.c
create mode 100644 drivers/clk/mvebu/armada-xp.c
delete mode 100644 drivers/clk/mvebu/clk-core.c
delete mode 100644 drivers/clk/mvebu/clk-core.h
delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
delete mode 100644 drivers/clk/mvebu/clk.c
create mode 100644 drivers/clk/mvebu/common.c
create mode 100644 drivers/clk/mvebu/common.h
create mode 100644 drivers/clk/mvebu/dove.c
create mode 100644 drivers/clk/mvebu/kirkwood.c
delete mode 100644 include/linux/clk/mvebu.h
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
--
1.7.10.4
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
Marvell EBU SoCs share some common clock functions that register core
clocks or clock gates from SoC specific data. These clock drivers are
organized by function and over time the drivers filled up with #ifdefs
to separate different SoC specific code.
This patch set first adds a new element to clock gate descriptors to
allow to pass clk flags per clock gate. (Patch 1)
Then it restructures MVEBU clock drivers into common clock setup and
SoC specific files and Kconfig options. The driver's init functions
are also registered to get called with of_clk_init. (Patches 2, 3-6)
It then switches Dove, Kirkwood, and Armada 370/XP to make use of
of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
Finally, all obsolete files and Kconfig options are removed. (Patch 10)
It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
Armada 370 and XP are compile tested only and should get their Tested-by
from Thomas and Gregory, respectively.
@Mike: As this only touches MVEBU related code, I suggest to take it
all through the corresponding ARM branch.
Sebastian Hesselbarth (10):
clk: mvebu: introduce per-clock-gate flags
clk: mvebu: add common clock functions for core clk and clk gating
clk: mvebu: add Dove SoC-centric clock init
clk: mvebu: add Kirkwood SoC-centric clock init
clk: mvebu: add Armada 370 SoC-centric clock init
clk: mvebu: add Armada XP SoC-centric clock init
ARM: dove: move DT boards to SoC-centric clock init
ARM: kirkwood: move DT boards to SoC-centric clock init
ARM: mvebu: move DT boards to SoC-centric clock init
clk: mvebu: desintegrate obsolete file
arch/arm/mach-dove/Kconfig | 3 +-
arch/arm/mach-dove/board-dt.c | 3 +-
arch/arm/mach-dove/common.c | 1 -
arch/arm/mach-kirkwood/Kconfig | 3 +-
arch/arm/mach-kirkwood/board-dt.c | 3 +-
arch/arm/mach-mvebu/Kconfig | 5 +-
arch/arm/mach-mvebu/armada-370-xp.c | 4 +-
drivers/clk/mvebu/Kconfig | 25 +-
drivers/clk/mvebu/Makefile | 8 +-
drivers/clk/mvebu/armada-370.c | 176 +++++++++
drivers/clk/mvebu/armada-xp.c | 204 +++++++++++
drivers/clk/mvebu/clk-core.c | 675 -----------------------------------
drivers/clk/mvebu/clk-core.h | 18 -
drivers/clk/mvebu/clk-gating-ctrl.c | 250 -------------
drivers/clk/mvebu/clk-gating-ctrl.h | 22 --
drivers/clk/mvebu/clk.c | 23 --
drivers/clk/mvebu/common.c | 163 +++++++++
drivers/clk/mvebu/common.h | 48 +++
drivers/clk/mvebu/dove.c | 194 ++++++++++
drivers/clk/mvebu/kirkwood.c | 247 +++++++++++++
include/linux/clk/mvebu.h | 22 --
21 files changed, 1066 insertions(+), 1031 deletions(-)
create mode 100644 drivers/clk/mvebu/armada-370.c
create mode 100644 drivers/clk/mvebu/armada-xp.c
delete mode 100644 drivers/clk/mvebu/clk-core.c
delete mode 100644 drivers/clk/mvebu/clk-core.h
delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
delete mode 100644 drivers/clk/mvebu/clk.c
create mode 100644 drivers/clk/mvebu/common.c
create mode 100644 drivers/clk/mvebu/common.h
create mode 100644 drivers/clk/mvebu/dove.c
create mode 100644 drivers/clk/mvebu/kirkwood.c
delete mode 100644 include/linux/clk/mvebu.h
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
--
1.7.10.4
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 01/10] clk: mvebu: introduce per-clock-gate flags
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
Clock gates found on MVEBU SoCs get registered by a common function.
To allow specific SoCs to provide tweaks introduce flags to the clock
gate descriptor instead of filling up the common function SoC specific
tweaks.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/clk/mvebu/clk-gating-ctrl.c | 153 +++++++++++++++++------------------
1 file changed, 72 insertions(+), 81 deletions(-)
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index ebf141d..a88e09b 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -28,6 +28,7 @@ struct mvebu_soc_descr {
const char *name;
const char *parent;
int bit_idx;
+ unsigned long flags;
};
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
@@ -88,21 +89,11 @@ static void __init mvebu_clk_gating_setup(
}
for (n = 0; n < ctrl->num_gates; n++) {
- u8 flags = 0;
const char *parent =
(descr[n].parent) ? descr[n].parent : default_parent;
-
- /*
- * On Armada 370, the DDR clock is a special case: it
- * isn't taken by any driver, but should anyway be
- * kept enabled, so we mark it as IGNORE_UNUSED for
- * now.
- */
- if (!strcmp(descr[n].name, "ddr"))
- flags |= CLK_IGNORE_UNUSED;
-
ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
- flags, base, descr[n].bit_idx, 0, &ctrl->lock);
+ descr[n].flags, base, descr[n].bit_idx,
+ 0, &ctrl->lock);
WARN_ON(IS_ERR(ctrl->gates[n]));
}
of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
@@ -114,93 +105,93 @@ static void __init mvebu_clk_gating_setup(
#ifdef CONFIG_MACH_ARMADA_370
static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
- { "audio", NULL, 0 },
- { "pex0_en", NULL, 1 },
- { "pex1_en", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", NULL, 5 },
- { "pex1", NULL, 9 },
- { "sata0", NULL, 15 },
- { "sdio", NULL, 17 },
- { "tdm", NULL, 25 },
- { "ddr", NULL, 28 },
- { "sata1", NULL, 30 },
+ { "audio", NULL, 0, 0 },
+ { "pex0_en", NULL, 1, 0 },
+ { "pex1_en", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", NULL, 5, 0 },
+ { "pex1", NULL, 9, 0 },
+ { "sata0", NULL, 15, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+ { "sata1", NULL, 30, 0 },
{ }
};
#endif
#ifdef CONFIG_MACH_ARMADA_XP
static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
- { "audio", NULL, 0 },
- { "ge3", NULL, 1 },
- { "ge2", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", NULL, 5 },
- { "pex1", NULL, 6 },
- { "pex2", NULL, 7 },
- { "pex3", NULL, 8 },
- { "bp", NULL, 13 },
- { "sata0lnk", NULL, 14 },
- { "sata0", "sata0lnk", 15 },
- { "lcd", NULL, 16 },
- { "sdio", NULL, 17 },
- { "usb0", NULL, 18 },
- { "usb1", NULL, 19 },
- { "usb2", NULL, 20 },
- { "xor0", NULL, 22 },
- { "crypto", NULL, 23 },
- { "tdm", NULL, 25 },
- { "xor1", NULL, 28 },
- { "sata1lnk", NULL, 29 },
- { "sata1", "sata1lnk", 30 },
+ { "audio", NULL, 0, 0 },
+ { "ge3", NULL, 1, 0 },
+ { "ge2", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", NULL, 5, 0 },
+ { "pex1", NULL, 6, 0 },
+ { "pex2", NULL, 7, 0 },
+ { "pex3", NULL, 8, 0 },
+ { "bp", NULL, 13, 0 },
+ { "sata0lnk", NULL, 14, 0 },
+ { "sata0", "sata0lnk", 15, 0 },
+ { "lcd", NULL, 16, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "usb0", NULL, 18, 0 },
+ { "usb1", NULL, 19, 0 },
+ { "usb2", NULL, 20, 0 },
+ { "xor0", NULL, 22, 0 },
+ { "crypto", NULL, 23, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "xor1", NULL, 28, 0 },
+ { "sata1lnk", NULL, 29, 0 },
+ { "sata1", "sata1lnk", 30, 0 },
{ }
};
#endif
#ifdef CONFIG_ARCH_DOVE
static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
- { "usb0", NULL, 0 },
- { "usb1", NULL, 1 },
- { "ge", "gephy", 2 },
- { "sata", NULL, 3 },
- { "pex0", NULL, 4 },
- { "pex1", NULL, 5 },
- { "sdio0", NULL, 8 },
- { "sdio1", NULL, 9 },
- { "nand", NULL, 10 },
- { "camera", NULL, 11 },
- { "i2s0", NULL, 12 },
- { "i2s1", NULL, 13 },
- { "crypto", NULL, 15 },
- { "ac97", NULL, 21 },
- { "pdma", NULL, 22 },
- { "xor0", NULL, 23 },
- { "xor1", NULL, 24 },
- { "gephy", NULL, 30 },
+ { "usb0", NULL, 0, 0 },
+ { "usb1", NULL, 1, 0 },
+ { "ge", "gephy", 2, 0 },
+ { "sata", NULL, 3, 0 },
+ { "pex0", NULL, 4, 0 },
+ { "pex1", NULL, 5, 0 },
+ { "sdio0", NULL, 8, 0 },
+ { "sdio1", NULL, 9, 0 },
+ { "nand", NULL, 10, 0 },
+ { "camera", NULL, 11, 0 },
+ { "i2s0", NULL, 12, 0 },
+ { "i2s1", NULL, 13, 0 },
+ { "crypto", NULL, 15, 0 },
+ { "ac97", NULL, 21, 0 },
+ { "pdma", NULL, 22, 0 },
+ { "xor0", NULL, 23, 0 },
+ { "xor1", NULL, 24, 0 },
+ { "gephy", NULL, 30, 0 },
{ }
};
#endif
#ifdef CONFIG_ARCH_KIRKWOOD
static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
- { "ge0", NULL, 0 },
- { "pex0", NULL, 2 },
- { "usb0", NULL, 3 },
- { "sdio", NULL, 4 },
- { "tsu", NULL, 5 },
- { "runit", NULL, 7 },
- { "xor0", NULL, 8 },
- { "audio", NULL, 9 },
- { "powersave", "cpuclk", 11 },
- { "sata0", NULL, 14 },
- { "sata1", NULL, 15 },
- { "xor1", NULL, 16 },
- { "crypto", NULL, 17 },
- { "pex1", NULL, 18 },
- { "ge1", NULL, 19 },
- { "tdm", NULL, 20 },
+ { "ge0", NULL, 0, 0 },
+ { "pex0", NULL, 2, 0 },
+ { "usb0", NULL, 3, 0 },
+ { "sdio", NULL, 4, 0 },
+ { "tsu", NULL, 5, 0 },
+ { "runit", NULL, 7, 0 },
+ { "xor0", NULL, 8, 0 },
+ { "audio", NULL, 9, 0 },
+ { "powersave", "cpuclk", 11, 0 },
+ { "sata0", NULL, 14, 0 },
+ { "sata1", NULL, 15, 0 },
+ { "xor1", NULL, 16, 0 },
+ { "crypto", NULL, 17, 0 },
+ { "pex1", NULL, 18, 0 },
+ { "ge1", NULL, 19, 0 },
+ { "tdm", NULL, 20, 0 },
{ }
};
#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 01/10] clk: mvebu: introduce per-clock-gate flags
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
Clock gates found on MVEBU SoCs get registered by a common function.
To allow specific SoCs to provide tweaks introduce flags to the clock
gate descriptor instead of filling up the common function SoC specific
tweaks.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/clk/mvebu/clk-gating-ctrl.c | 153 +++++++++++++++++------------------
1 file changed, 72 insertions(+), 81 deletions(-)
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index ebf141d..a88e09b 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -28,6 +28,7 @@ struct mvebu_soc_descr {
const char *name;
const char *parent;
int bit_idx;
+ unsigned long flags;
};
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
@@ -88,21 +89,11 @@ static void __init mvebu_clk_gating_setup(
}
for (n = 0; n < ctrl->num_gates; n++) {
- u8 flags = 0;
const char *parent =
(descr[n].parent) ? descr[n].parent : default_parent;
-
- /*
- * On Armada 370, the DDR clock is a special case: it
- * isn't taken by any driver, but should anyway be
- * kept enabled, so we mark it as IGNORE_UNUSED for
- * now.
- */
- if (!strcmp(descr[n].name, "ddr"))
- flags |= CLK_IGNORE_UNUSED;
-
ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
- flags, base, descr[n].bit_idx, 0, &ctrl->lock);
+ descr[n].flags, base, descr[n].bit_idx,
+ 0, &ctrl->lock);
WARN_ON(IS_ERR(ctrl->gates[n]));
}
of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
@@ -114,93 +105,93 @@ static void __init mvebu_clk_gating_setup(
#ifdef CONFIG_MACH_ARMADA_370
static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
- { "audio", NULL, 0 },
- { "pex0_en", NULL, 1 },
- { "pex1_en", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", NULL, 5 },
- { "pex1", NULL, 9 },
- { "sata0", NULL, 15 },
- { "sdio", NULL, 17 },
- { "tdm", NULL, 25 },
- { "ddr", NULL, 28 },
- { "sata1", NULL, 30 },
+ { "audio", NULL, 0, 0 },
+ { "pex0_en", NULL, 1, 0 },
+ { "pex1_en", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", NULL, 5, 0 },
+ { "pex1", NULL, 9, 0 },
+ { "sata0", NULL, 15, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+ { "sata1", NULL, 30, 0 },
{ }
};
#endif
#ifdef CONFIG_MACH_ARMADA_XP
static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
- { "audio", NULL, 0 },
- { "ge3", NULL, 1 },
- { "ge2", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", NULL, 5 },
- { "pex1", NULL, 6 },
- { "pex2", NULL, 7 },
- { "pex3", NULL, 8 },
- { "bp", NULL, 13 },
- { "sata0lnk", NULL, 14 },
- { "sata0", "sata0lnk", 15 },
- { "lcd", NULL, 16 },
- { "sdio", NULL, 17 },
- { "usb0", NULL, 18 },
- { "usb1", NULL, 19 },
- { "usb2", NULL, 20 },
- { "xor0", NULL, 22 },
- { "crypto", NULL, 23 },
- { "tdm", NULL, 25 },
- { "xor1", NULL, 28 },
- { "sata1lnk", NULL, 29 },
- { "sata1", "sata1lnk", 30 },
+ { "audio", NULL, 0, 0 },
+ { "ge3", NULL, 1, 0 },
+ { "ge2", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", NULL, 5, 0 },
+ { "pex1", NULL, 6, 0 },
+ { "pex2", NULL, 7, 0 },
+ { "pex3", NULL, 8, 0 },
+ { "bp", NULL, 13, 0 },
+ { "sata0lnk", NULL, 14, 0 },
+ { "sata0", "sata0lnk", 15, 0 },
+ { "lcd", NULL, 16, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "usb0", NULL, 18, 0 },
+ { "usb1", NULL, 19, 0 },
+ { "usb2", NULL, 20, 0 },
+ { "xor0", NULL, 22, 0 },
+ { "crypto", NULL, 23, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "xor1", NULL, 28, 0 },
+ { "sata1lnk", NULL, 29, 0 },
+ { "sata1", "sata1lnk", 30, 0 },
{ }
};
#endif
#ifdef CONFIG_ARCH_DOVE
static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
- { "usb0", NULL, 0 },
- { "usb1", NULL, 1 },
- { "ge", "gephy", 2 },
- { "sata", NULL, 3 },
- { "pex0", NULL, 4 },
- { "pex1", NULL, 5 },
- { "sdio0", NULL, 8 },
- { "sdio1", NULL, 9 },
- { "nand", NULL, 10 },
- { "camera", NULL, 11 },
- { "i2s0", NULL, 12 },
- { "i2s1", NULL, 13 },
- { "crypto", NULL, 15 },
- { "ac97", NULL, 21 },
- { "pdma", NULL, 22 },
- { "xor0", NULL, 23 },
- { "xor1", NULL, 24 },
- { "gephy", NULL, 30 },
+ { "usb0", NULL, 0, 0 },
+ { "usb1", NULL, 1, 0 },
+ { "ge", "gephy", 2, 0 },
+ { "sata", NULL, 3, 0 },
+ { "pex0", NULL, 4, 0 },
+ { "pex1", NULL, 5, 0 },
+ { "sdio0", NULL, 8, 0 },
+ { "sdio1", NULL, 9, 0 },
+ { "nand", NULL, 10, 0 },
+ { "camera", NULL, 11, 0 },
+ { "i2s0", NULL, 12, 0 },
+ { "i2s1", NULL, 13, 0 },
+ { "crypto", NULL, 15, 0 },
+ { "ac97", NULL, 21, 0 },
+ { "pdma", NULL, 22, 0 },
+ { "xor0", NULL, 23, 0 },
+ { "xor1", NULL, 24, 0 },
+ { "gephy", NULL, 30, 0 },
{ }
};
#endif
#ifdef CONFIG_ARCH_KIRKWOOD
static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
- { "ge0", NULL, 0 },
- { "pex0", NULL, 2 },
- { "usb0", NULL, 3 },
- { "sdio", NULL, 4 },
- { "tsu", NULL, 5 },
- { "runit", NULL, 7 },
- { "xor0", NULL, 8 },
- { "audio", NULL, 9 },
- { "powersave", "cpuclk", 11 },
- { "sata0", NULL, 14 },
- { "sata1", NULL, 15 },
- { "xor1", NULL, 16 },
- { "crypto", NULL, 17 },
- { "pex1", NULL, 18 },
- { "ge1", NULL, 19 },
- { "tdm", NULL, 20 },
+ { "ge0", NULL, 0, 0 },
+ { "pex0", NULL, 2, 0 },
+ { "usb0", NULL, 3, 0 },
+ { "sdio", NULL, 4, 0 },
+ { "tsu", NULL, 5, 0 },
+ { "runit", NULL, 7, 0 },
+ { "xor0", NULL, 8, 0 },
+ { "audio", NULL, 9, 0 },
+ { "powersave", "cpuclk", 11, 0 },
+ { "sata0", NULL, 14, 0 },
+ { "sata1", NULL, 15, 0 },
+ { "xor1", NULL, 16, 0 },
+ { "crypto", NULL, 17, 0 },
+ { "pex1", NULL, 18, 0 },
+ { "ge1", NULL, 19, 0 },
+ { "tdm", NULL, 20, 0 },
{ }
};
#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 02/10] clk: mvebu: add common clock functions for core clk and clk gating
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
Based on the current common functions for core clocks and clock
gating control, new common functions are joined in a single file.
Given the opportunity, names of functions and structs are unified,
and also a Kconfig entry is added.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 3 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/common.c | 163 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/mvebu/common.h | 48 +++++++++++++
4 files changed, 215 insertions(+)
create mode 100644 drivers/clk/mvebu/common.c
create mode 100644 drivers/clk/mvebu/common.h
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 57323fd..2c3cf95 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -6,3 +6,6 @@ config MVEBU_CLK_CPU
config MVEBU_CLK_GATING
bool
+
+config MVEBU_CLK_COMMON
+ bool
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 58df3dc..2143230 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
new file mode 100644
index 0000000..adaa4a1
--- /dev/null
+++ b/drivers/clk/mvebu/common.c
@@ -0,0 +1,163 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+static struct clk_onecell_data clk_data;
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+ const struct coreclk_soc_desc *desc)
+{
+ const char *tclk_name = "tclk";
+ const char *cpuclk_name = "cpuclk";
+ void __iomem *base;
+ unsigned long rate;
+ int n;
+
+ base = of_iomap(np, 0);
+ if (WARN_ON(!base))
+ return;
+
+ /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
+ clk_data.clk_num = 2 + desc->num_ratios;
+ clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
+ GFP_KERNEL);
+ if (WARN_ON(!clk_data.clks))
+ return;
+
+ /* Register TCLK */
+ of_property_read_string_index(np, "clock-output-names", 0,
+ &tclk_name);
+ rate = desc->get_tclk_freq(base);
+ clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
+ CLK_IS_ROOT, rate);
+ WARN_ON(IS_ERR(clk_data.clks[0]));
+
+ /* Register CPU clock */
+ of_property_read_string_index(np, "clock-output-names", 1,
+ &cpuclk_name);
+ rate = desc->get_cpu_freq(base);
+ clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
+ CLK_IS_ROOT, rate);
+ WARN_ON(IS_ERR(clk_data.clks[1]));
+
+ /* Register fixed-factor clocks derived from CPU clock */
+ for (n = 0; n < desc->num_ratios; n++) {
+ const char *rclk_name = desc->ratios[n].name;
+ int mult, div;
+
+ of_property_read_string_index(np, "clock-output-names",
+ 2+n, &rclk_name);
+ desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
+ clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
+ cpuclk_name, 0, mult, div);
+ WARN_ON(IS_ERR(clk_data.clks[2+n]));
+ };
+
+ /* SAR register isn't needed anymore */
+ iounmap(base);
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+/*
+ * Clock Gating Control
+ */
+
+struct clk_gating_ctrl {
+ spinlock_t lock;
+ struct clk **gates;
+ int num_gates;
+};
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static struct clk *clk_gating_get_src(
+ struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
+ int n;
+
+ if (clkspec->args_count < 1)
+ return ERR_PTR(-EINVAL);
+
+ for (n = 0; n < ctrl->num_gates; n++) {
+ struct clk_gate *gate =
+ to_clk_gate(__clk_get_hw(ctrl->gates[n]));
+ if (clkspec->args[0] == gate->bit_idx)
+ return ctrl->gates[n];
+ }
+ return ERR_PTR(-ENODEV);
+}
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+ const struct clk_gating_soc_desc *desc)
+{
+ struct clk_gating_ctrl *ctrl;
+ struct clk *clk;
+ void __iomem *base;
+ const char *default_parent = NULL;
+ int n;
+
+ base = of_iomap(np, 0);
+ if (WARN_ON(!base))
+ return;
+
+ clk = of_clk_get(np, 0);
+ if (!IS_ERR(clk)) {
+ default_parent = __clk_get_name(clk);
+ clk_put(clk);
+ }
+
+ ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
+ if (WARN_ON(!ctrl))
+ return;
+
+ spin_lock_init(&ctrl->lock);
+
+ /* Count, allocate, and register clock gates */
+ for (n = 0; desc[n].name;)
+ n++;
+
+ ctrl->num_gates = n;
+ ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
+ GFP_KERNEL);
+ if (WARN_ON(!ctrl->gates)) {
+ kfree(ctrl);
+ return;
+ }
+
+ for (n = 0; n < ctrl->num_gates; n++) {
+ const char *parent =
+ (desc[n].parent) ? desc[n].parent : default_parent;
+ ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
+ desc[n].flags, base, desc[n].bit_idx,
+ 0, &ctrl->lock);
+ WARN_ON(IS_ERR(ctrl->gates[n]));
+ }
+
+ of_clk_add_provider(np, clk_gating_get_src, ctrl);
+}
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
new file mode 100644
index 0000000..f968b4d
--- /dev/null
+++ b/drivers/clk/mvebu/common.h
@@ -0,0 +1,48 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __CLK_MVEBU_COMMON_H_
+#define __CLK_MVEBU_COMMON_H_
+
+#include <linux/kernel.h>
+
+struct device_node;
+
+struct coreclk_ratio {
+ int id;
+ const char *name;
+};
+
+struct coreclk_soc_desc {
+ u32 (*get_tclk_freq)(void __iomem *sar);
+ u32 (*get_cpu_freq)(void __iomem *sar);
+ void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
+ const struct coreclk_ratio *ratios;
+ int num_ratios;
+};
+
+struct clk_gating_soc_desc {
+ const char *name;
+ const char *parent;
+ int bit_idx;
+ unsigned long flags;
+};
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+ const struct coreclk_soc_desc *desc);
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+ const struct clk_gating_soc_desc *desc);
+
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 02/10] clk: mvebu: add common clock functions for core clk and clk gating
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
Based on the current common functions for core clocks and clock
gating control, new common functions are joined in a single file.
Given the opportunity, names of functions and structs are unified,
and also a Kconfig entry is added.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 3 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/common.c | 163 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/mvebu/common.h | 48 +++++++++++++
4 files changed, 215 insertions(+)
create mode 100644 drivers/clk/mvebu/common.c
create mode 100644 drivers/clk/mvebu/common.h
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 57323fd..2c3cf95 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -6,3 +6,6 @@ config MVEBU_CLK_CPU
config MVEBU_CLK_GATING
bool
+
+config MVEBU_CLK_COMMON
+ bool
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 58df3dc..2143230 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
new file mode 100644
index 0000000..adaa4a1
--- /dev/null
+++ b/drivers/clk/mvebu/common.c
@@ -0,0 +1,163 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+static struct clk_onecell_data clk_data;
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+ const struct coreclk_soc_desc *desc)
+{
+ const char *tclk_name = "tclk";
+ const char *cpuclk_name = "cpuclk";
+ void __iomem *base;
+ unsigned long rate;
+ int n;
+
+ base = of_iomap(np, 0);
+ if (WARN_ON(!base))
+ return;
+
+ /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
+ clk_data.clk_num = 2 + desc->num_ratios;
+ clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
+ GFP_KERNEL);
+ if (WARN_ON(!clk_data.clks))
+ return;
+
+ /* Register TCLK */
+ of_property_read_string_index(np, "clock-output-names", 0,
+ &tclk_name);
+ rate = desc->get_tclk_freq(base);
+ clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
+ CLK_IS_ROOT, rate);
+ WARN_ON(IS_ERR(clk_data.clks[0]));
+
+ /* Register CPU clock */
+ of_property_read_string_index(np, "clock-output-names", 1,
+ &cpuclk_name);
+ rate = desc->get_cpu_freq(base);
+ clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
+ CLK_IS_ROOT, rate);
+ WARN_ON(IS_ERR(clk_data.clks[1]));
+
+ /* Register fixed-factor clocks derived from CPU clock */
+ for (n = 0; n < desc->num_ratios; n++) {
+ const char *rclk_name = desc->ratios[n].name;
+ int mult, div;
+
+ of_property_read_string_index(np, "clock-output-names",
+ 2+n, &rclk_name);
+ desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
+ clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
+ cpuclk_name, 0, mult, div);
+ WARN_ON(IS_ERR(clk_data.clks[2+n]));
+ };
+
+ /* SAR register isn't needed anymore */
+ iounmap(base);
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+/*
+ * Clock Gating Control
+ */
+
+struct clk_gating_ctrl {
+ spinlock_t lock;
+ struct clk **gates;
+ int num_gates;
+};
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static struct clk *clk_gating_get_src(
+ struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
+ int n;
+
+ if (clkspec->args_count < 1)
+ return ERR_PTR(-EINVAL);
+
+ for (n = 0; n < ctrl->num_gates; n++) {
+ struct clk_gate *gate =
+ to_clk_gate(__clk_get_hw(ctrl->gates[n]));
+ if (clkspec->args[0] == gate->bit_idx)
+ return ctrl->gates[n];
+ }
+ return ERR_PTR(-ENODEV);
+}
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+ const struct clk_gating_soc_desc *desc)
+{
+ struct clk_gating_ctrl *ctrl;
+ struct clk *clk;
+ void __iomem *base;
+ const char *default_parent = NULL;
+ int n;
+
+ base = of_iomap(np, 0);
+ if (WARN_ON(!base))
+ return;
+
+ clk = of_clk_get(np, 0);
+ if (!IS_ERR(clk)) {
+ default_parent = __clk_get_name(clk);
+ clk_put(clk);
+ }
+
+ ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
+ if (WARN_ON(!ctrl))
+ return;
+
+ spin_lock_init(&ctrl->lock);
+
+ /* Count, allocate, and register clock gates */
+ for (n = 0; desc[n].name;)
+ n++;
+
+ ctrl->num_gates = n;
+ ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
+ GFP_KERNEL);
+ if (WARN_ON(!ctrl->gates)) {
+ kfree(ctrl);
+ return;
+ }
+
+ for (n = 0; n < ctrl->num_gates; n++) {
+ const char *parent =
+ (desc[n].parent) ? desc[n].parent : default_parent;
+ ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
+ desc[n].flags, base, desc[n].bit_idx,
+ 0, &ctrl->lock);
+ WARN_ON(IS_ERR(ctrl->gates[n]));
+ }
+
+ of_clk_add_provider(np, clk_gating_get_src, ctrl);
+}
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
new file mode 100644
index 0000000..f968b4d
--- /dev/null
+++ b/drivers/clk/mvebu/common.h
@@ -0,0 +1,48 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __CLK_MVEBU_COMMON_H_
+#define __CLK_MVEBU_COMMON_H_
+
+#include <linux/kernel.h>
+
+struct device_node;
+
+struct coreclk_ratio {
+ int id;
+ const char *name;
+};
+
+struct coreclk_soc_desc {
+ u32 (*get_tclk_freq)(void __iomem *sar);
+ u32 (*get_cpu_freq)(void __iomem *sar);
+ void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
+ const struct coreclk_ratio *ratios;
+ int num_ratios;
+};
+
+struct clk_gating_soc_desc {
+ const char *name;
+ const char *parent;
+ int bit_idx;
+ unsigned long flags;
+};
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+ const struct coreclk_soc_desc *desc);
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+ const struct clk_gating_soc_desc *desc);
+
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 03/10] clk: mvebu: add Dove SoC-centric clock init
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
This is moving core clock and clock gating init for Dove to its own
file and adds a Kconfig option. Also init functions are added and
declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 4 +
drivers/clk/mvebu/Makefile | 2 +
drivers/clk/mvebu/dove.c | 194 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 200 insertions(+)
create mode 100644 drivers/clk/mvebu/dove.c
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 2c3cf95..bc5f05e 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -9,3 +9,7 @@ config MVEBU_CLK_GATING
config MVEBU_CLK_COMMON
bool
+
+config DOVE_CLK
+ bool
+ select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 2143230..bfc3078 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -2,3 +2,5 @@ obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
+
+obj-$(CONFIG_DOVE_CLK) += dove.o
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
new file mode 100644
index 0000000..79d7aed
--- /dev/null
+++ b/drivers/clk/mvebu/dove.c
@@ -0,0 +1,194 @@
+/*
+ * Marvell Dove SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Dove PLL sample-at-reset configuration
+ *
+ * SAR0[8:5] : CPU frequency
+ * 5 = 1000 MHz
+ * 6 = 933 MHz
+ * 7 = 933 MHz
+ * 8 = 800 MHz
+ * 9 = 800 MHz
+ * 10 = 800 MHz
+ * 11 = 1067 MHz
+ * 12 = 667 MHz
+ * 13 = 533 MHz
+ * 14 = 400 MHz
+ * 15 = 333 MHz
+ * others reserved.
+ *
+ * SAR0[11:9] : CPU to L2 Clock divider ratio
+ * 0 = (1/1) * CPU
+ * 2 = (1/2) * CPU
+ * 4 = (1/3) * CPU
+ * 6 = (1/4) * CPU
+ * others reserved.
+ *
+ * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
+ * 0 = (1/1) * CPU
+ * 2 = (1/2) * CPU
+ * 3 = (2/5) * CPU
+ * 4 = (1/3) * CPU
+ * 6 = (1/4) * CPU
+ * 8 = (1/5) * CPU
+ * 10 = (1/6) * CPU
+ * 12 = (1/7) * CPU
+ * 14 = (1/8) * CPU
+ * 15 = (1/10) * CPU
+ * others reserved.
+ *
+ * SAR0[24:23] : TCLK frequency
+ * 0 = 166 MHz
+ * 1 = 125 MHz
+ * others reserved.
+ */
+
+#define SAR_DOVE_CPU_FREQ 5
+#define SAR_DOVE_CPU_FREQ_MASK 0xf
+#define SAR_DOVE_L2_RATIO 9
+#define SAR_DOVE_L2_RATIO_MASK 0x7
+#define SAR_DOVE_DDR_RATIO 12
+#define SAR_DOVE_DDR_RATIO_MASK 0xf
+#define SAR_DOVE_TCLK_FREQ 23
+#define SAR_DOVE_TCLK_FREQ_MASK 0x3
+
+enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst dove_coreclk_ratios[] = {
+ { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
+ { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static const u32 __initconst dove_tclk_freqs[] = {
+ 166666667,
+ 125000000,
+ 0, 0
+};
+
+static u32 __init dove_get_tclk_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
+ SAR_DOVE_TCLK_FREQ_MASK;
+ return dove_tclk_freqs[opt];
+}
+
+static const u32 __initconst dove_cpu_freqs[] = {
+ 0, 0, 0, 0, 0,
+ 1000000000,
+ 933333333, 933333333,
+ 800000000, 800000000, 800000000,
+ 1066666667,
+ 666666667,
+ 533333333,
+ 400000000,
+ 333333333
+};
+
+static u32 __init dove_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
+ SAR_DOVE_CPU_FREQ_MASK;
+ return dove_cpu_freqs[opt];
+}
+
+static const int __initconst dove_cpu_l2_ratios[8][2] = {
+ { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+ { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
+};
+
+static const int __initconst dove_cpu_ddr_ratios[16][2] = {
+ { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
+ { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
+ { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
+ { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
+};
+
+static void __init dove_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ switch (id) {
+ case DOVE_CPU_TO_L2:
+ {
+ u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
+ SAR_DOVE_L2_RATIO_MASK;
+ *mult = dove_cpu_l2_ratios[opt][0];
+ *div = dove_cpu_l2_ratios[opt][1];
+ break;
+ }
+ case DOVE_CPU_TO_DDR:
+ {
+ u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
+ SAR_DOVE_DDR_RATIO_MASK;
+ *mult = dove_cpu_ddr_ratios[opt][0];
+ *div = dove_cpu_ddr_ratios[opt][1];
+ break;
+ }
+ }
+}
+
+static const struct coreclk_soc_desc dove_coreclks = {
+ .get_tclk_freq = dove_get_tclk_freq,
+ .get_cpu_freq = dove_get_cpu_freq,
+ .get_clk_ratio = dove_get_clk_ratio,
+ .ratios = dove_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
+};
+
+static void __init dove_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &dove_coreclks);
+}
+CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst dove_gating_desc[] = {
+ { "usb0", NULL, 0, 0 },
+ { "usb1", NULL, 1, 0 },
+ { "ge", "gephy", 2, 0 },
+ { "sata", NULL, 3, 0 },
+ { "pex0", NULL, 4, 0 },
+ { "pex1", NULL, 5, 0 },
+ { "sdio0", NULL, 8, 0 },
+ { "sdio1", NULL, 9, 0 },
+ { "nand", NULL, 10, 0 },
+ { "camera", NULL, 11, 0 },
+ { "i2s0", NULL, 12, 0 },
+ { "i2s1", NULL, 13, 0 },
+ { "crypto", NULL, 15, 0 },
+ { "ac97", NULL, 21, 0 },
+ { "pdma", NULL, 22, 0 },
+ { "xor0", NULL, 23, 0 },
+ { "xor1", NULL, 24, 0 },
+ { "gephy", NULL, 30, 0 },
+ { }
+};
+
+static void __init dove_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, dove_gating_desc);
+}
+CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock",
+ dove_clk_gating_init);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 03/10] clk: mvebu: add Dove SoC-centric clock init
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
This is moving core clock and clock gating init for Dove to its own
file and adds a Kconfig option. Also init functions are added and
declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 4 +
drivers/clk/mvebu/Makefile | 2 +
drivers/clk/mvebu/dove.c | 194 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 200 insertions(+)
create mode 100644 drivers/clk/mvebu/dove.c
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 2c3cf95..bc5f05e 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -9,3 +9,7 @@ config MVEBU_CLK_GATING
config MVEBU_CLK_COMMON
bool
+
+config DOVE_CLK
+ bool
+ select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 2143230..bfc3078 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -2,3 +2,5 @@ obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
+
+obj-$(CONFIG_DOVE_CLK) += dove.o
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
new file mode 100644
index 0000000..79d7aed
--- /dev/null
+++ b/drivers/clk/mvebu/dove.c
@@ -0,0 +1,194 @@
+/*
+ * Marvell Dove SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Dove PLL sample-at-reset configuration
+ *
+ * SAR0[8:5] : CPU frequency
+ * 5 = 1000 MHz
+ * 6 = 933 MHz
+ * 7 = 933 MHz
+ * 8 = 800 MHz
+ * 9 = 800 MHz
+ * 10 = 800 MHz
+ * 11 = 1067 MHz
+ * 12 = 667 MHz
+ * 13 = 533 MHz
+ * 14 = 400 MHz
+ * 15 = 333 MHz
+ * others reserved.
+ *
+ * SAR0[11:9] : CPU to L2 Clock divider ratio
+ * 0 = (1/1) * CPU
+ * 2 = (1/2) * CPU
+ * 4 = (1/3) * CPU
+ * 6 = (1/4) * CPU
+ * others reserved.
+ *
+ * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
+ * 0 = (1/1) * CPU
+ * 2 = (1/2) * CPU
+ * 3 = (2/5) * CPU
+ * 4 = (1/3) * CPU
+ * 6 = (1/4) * CPU
+ * 8 = (1/5) * CPU
+ * 10 = (1/6) * CPU
+ * 12 = (1/7) * CPU
+ * 14 = (1/8) * CPU
+ * 15 = (1/10) * CPU
+ * others reserved.
+ *
+ * SAR0[24:23] : TCLK frequency
+ * 0 = 166 MHz
+ * 1 = 125 MHz
+ * others reserved.
+ */
+
+#define SAR_DOVE_CPU_FREQ 5
+#define SAR_DOVE_CPU_FREQ_MASK 0xf
+#define SAR_DOVE_L2_RATIO 9
+#define SAR_DOVE_L2_RATIO_MASK 0x7
+#define SAR_DOVE_DDR_RATIO 12
+#define SAR_DOVE_DDR_RATIO_MASK 0xf
+#define SAR_DOVE_TCLK_FREQ 23
+#define SAR_DOVE_TCLK_FREQ_MASK 0x3
+
+enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst dove_coreclk_ratios[] = {
+ { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
+ { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static const u32 __initconst dove_tclk_freqs[] = {
+ 166666667,
+ 125000000,
+ 0, 0
+};
+
+static u32 __init dove_get_tclk_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
+ SAR_DOVE_TCLK_FREQ_MASK;
+ return dove_tclk_freqs[opt];
+}
+
+static const u32 __initconst dove_cpu_freqs[] = {
+ 0, 0, 0, 0, 0,
+ 1000000000,
+ 933333333, 933333333,
+ 800000000, 800000000, 800000000,
+ 1066666667,
+ 666666667,
+ 533333333,
+ 400000000,
+ 333333333
+};
+
+static u32 __init dove_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
+ SAR_DOVE_CPU_FREQ_MASK;
+ return dove_cpu_freqs[opt];
+}
+
+static const int __initconst dove_cpu_l2_ratios[8][2] = {
+ { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+ { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
+};
+
+static const int __initconst dove_cpu_ddr_ratios[16][2] = {
+ { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
+ { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
+ { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
+ { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
+};
+
+static void __init dove_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ switch (id) {
+ case DOVE_CPU_TO_L2:
+ {
+ u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
+ SAR_DOVE_L2_RATIO_MASK;
+ *mult = dove_cpu_l2_ratios[opt][0];
+ *div = dove_cpu_l2_ratios[opt][1];
+ break;
+ }
+ case DOVE_CPU_TO_DDR:
+ {
+ u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
+ SAR_DOVE_DDR_RATIO_MASK;
+ *mult = dove_cpu_ddr_ratios[opt][0];
+ *div = dove_cpu_ddr_ratios[opt][1];
+ break;
+ }
+ }
+}
+
+static const struct coreclk_soc_desc dove_coreclks = {
+ .get_tclk_freq = dove_get_tclk_freq,
+ .get_cpu_freq = dove_get_cpu_freq,
+ .get_clk_ratio = dove_get_clk_ratio,
+ .ratios = dove_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
+};
+
+static void __init dove_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &dove_coreclks);
+}
+CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst dove_gating_desc[] = {
+ { "usb0", NULL, 0, 0 },
+ { "usb1", NULL, 1, 0 },
+ { "ge", "gephy", 2, 0 },
+ { "sata", NULL, 3, 0 },
+ { "pex0", NULL, 4, 0 },
+ { "pex1", NULL, 5, 0 },
+ { "sdio0", NULL, 8, 0 },
+ { "sdio1", NULL, 9, 0 },
+ { "nand", NULL, 10, 0 },
+ { "camera", NULL, 11, 0 },
+ { "i2s0", NULL, 12, 0 },
+ { "i2s1", NULL, 13, 0 },
+ { "crypto", NULL, 15, 0 },
+ { "ac97", NULL, 21, 0 },
+ { "pdma", NULL, 22, 0 },
+ { "xor0", NULL, 23, 0 },
+ { "xor1", NULL, 24, 0 },
+ { "gephy", NULL, 30, 0 },
+ { }
+};
+
+static void __init dove_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, dove_gating_desc);
+}
+CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock",
+ dove_clk_gating_init);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 04/10] clk: mvebu: add Kirkwood SoC-centric clock init
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
This is moving core clock and clock gating init for Kirkwood to its
own file and adds a Kconfig option. Also init functions are added and
declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 4 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/kirkwood.c | 247 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 252 insertions(+)
create mode 100644 drivers/clk/mvebu/kirkwood.c
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index bc5f05e..211695c 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -13,3 +13,7 @@ config MVEBU_CLK_COMMON
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
+
+config KIRKWOOD_CLK
+ bool
+ select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index bfc3078..97d1ab0 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
obj-$(CONFIG_DOVE_CLK) += dove.o
+obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
new file mode 100644
index 0000000..71d2461
--- /dev/null
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -0,0 +1,247 @@
+/*
+ * Marvell Kirkwood SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Kirkwood PLL sample-at-reset configuration
+ * (6180 has different SAR layout than other Kirkwood SoCs)
+ *
+ * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
+ * 4 = 600 MHz
+ * 6 = 800 MHz
+ * 7 = 1000 MHz
+ * 9 = 1200 MHz
+ * 12 = 1500 MHz
+ * 13 = 1600 MHz
+ * 14 = 1800 MHz
+ * 15 = 2000 MHz
+ * others reserved.
+ *
+ * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
+ * 1 = (1/2) * CPU
+ * 3 = (1/3) * CPU
+ * 5 = (1/4) * CPU
+ * others reserved.
+ *
+ * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
+ * 2 = (1/2) * CPU
+ * 4 = (1/3) * CPU
+ * 6 = (1/4) * CPU
+ * 7 = (2/9) * CPU
+ * 8 = (1/5) * CPU
+ * 9 = (1/6) * CPU
+ * others reserved.
+ *
+ * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
+ * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
+ * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
+ * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
+ * others reserved.
+ *
+ * SAR0[21] : TCLK frequency
+ * 0 = 200 MHz
+ * 1 = 166 MHz
+ * others reserved.
+ */
+
+#define SAR_KIRKWOOD_CPU_FREQ(x) \
+ (((x & (1 << 1)) >> 1) | \
+ ((x & (1 << 22)) >> 21) | \
+ ((x & (3 << 3)) >> 1))
+#define SAR_KIRKWOOD_L2_RATIO(x) \
+ (((x & (3 << 9)) >> 9) | \
+ (((x & (1 << 19)) >> 17)))
+#define SAR_KIRKWOOD_DDR_RATIO 5
+#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
+#define SAR_MV88F6180_CLK 2
+#define SAR_MV88F6180_CLK_MASK 0x7
+#define SAR_KIRKWOOD_TCLK_FREQ 21
+#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
+
+enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst kirkwood_coreclk_ratios[] = {
+ { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
+ { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
+ SAR_KIRKWOOD_TCLK_FREQ_MASK;
+ return (opt) ? 166666667 : 200000000;
+}
+
+static const u32 __initconst kirkwood_cpu_freqs[] = {
+ 0, 0, 0, 0,
+ 600000000,
+ 0,
+ 800000000,
+ 1000000000,
+ 0,
+ 1200000000,
+ 0, 0,
+ 1500000000,
+ 1600000000,
+ 1800000000,
+ 2000000000
+};
+
+static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
+ return kirkwood_cpu_freqs[opt];
+}
+
+static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
+ { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
+ { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
+};
+
+static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
+ { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+ { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
+ { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
+ { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
+};
+
+static void __init kirkwood_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ switch (id) {
+ case KIRKWOOD_CPU_TO_L2:
+ {
+ u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
+ *mult = kirkwood_cpu_l2_ratios[opt][0];
+ *div = kirkwood_cpu_l2_ratios[opt][1];
+ break;
+ }
+ case KIRKWOOD_CPU_TO_DDR:
+ {
+ u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
+ SAR_KIRKWOOD_DDR_RATIO_MASK;
+ *mult = kirkwood_cpu_ddr_ratios[opt][0];
+ *div = kirkwood_cpu_ddr_ratios[opt][1];
+ break;
+ }
+ }
+}
+
+static const u32 __initconst mv88f6180_cpu_freqs[] = {
+ 0, 0, 0, 0, 0,
+ 600000000,
+ 800000000,
+ 1000000000
+};
+
+static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
+ return mv88f6180_cpu_freqs[opt];
+}
+
+static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
+ { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
+ { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
+};
+
+static void __init mv88f6180_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ switch (id) {
+ case KIRKWOOD_CPU_TO_L2:
+ {
+ /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
+ *mult = 1;
+ *div = 2;
+ break;
+ }
+ case KIRKWOOD_CPU_TO_DDR:
+ {
+ u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
+ SAR_MV88F6180_CLK_MASK;
+ *mult = mv88f6180_cpu_ddr_ratios[opt][0];
+ *div = mv88f6180_cpu_ddr_ratios[opt][1];
+ break;
+ }
+ }
+}
+
+static const struct coreclk_soc_desc kirkwood_coreclks = {
+ .get_tclk_freq = kirkwood_get_tclk_freq,
+ .get_cpu_freq = kirkwood_get_cpu_freq,
+ .get_clk_ratio = kirkwood_get_clk_ratio,
+ .ratios = kirkwood_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init kirkwood_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &kirkwood_coreclks);
+}
+CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
+ kirkwood_coreclk_init);
+
+static const struct coreclk_soc_desc mv88f6180_coreclks = {
+ .get_tclk_freq = kirkwood_get_tclk_freq,
+ .get_cpu_freq = mv88f6180_get_cpu_freq,
+ .get_clk_ratio = mv88f6180_get_clk_ratio,
+ .ratios = kirkwood_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init mv88f6180_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &mv88f6180_coreclks);
+}
+CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
+ mv88f6180_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst kirkwood_gating_desc[] = {
+ { "ge0", NULL, 0, 0 },
+ { "pex0", NULL, 2, 0 },
+ { "usb0", NULL, 3, 0 },
+ { "sdio", NULL, 4, 0 },
+ { "tsu", NULL, 5, 0 },
+ { "runit", NULL, 7, 0 },
+ { "xor0", NULL, 8, 0 },
+ { "audio", NULL, 9, 0 },
+ { "powersave", "cpuclk", 11, 0 },
+ { "sata0", NULL, 14, 0 },
+ { "sata1", NULL, 15, 0 },
+ { "xor1", NULL, 16, 0 },
+ { "crypto", NULL, 17, 0 },
+ { "pex1", NULL, 18, 0 },
+ { "ge1", NULL, 19, 0 },
+ { "tdm", NULL, 20, 0 },
+ { }
+};
+
+static void __init kirkwood_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, kirkwood_gating_desc);
+}
+CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
+ kirkwood_clk_gating_init);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 04/10] clk: mvebu: add Kirkwood SoC-centric clock init
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
This is moving core clock and clock gating init for Kirkwood to its
own file and adds a Kconfig option. Also init functions are added and
declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 4 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/kirkwood.c | 247 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 252 insertions(+)
create mode 100644 drivers/clk/mvebu/kirkwood.c
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index bc5f05e..211695c 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -13,3 +13,7 @@ config MVEBU_CLK_COMMON
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
+
+config KIRKWOOD_CLK
+ bool
+ select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index bfc3078..97d1ab0 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
obj-$(CONFIG_DOVE_CLK) += dove.o
+obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
new file mode 100644
index 0000000..71d2461
--- /dev/null
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -0,0 +1,247 @@
+/*
+ * Marvell Kirkwood SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Kirkwood PLL sample-at-reset configuration
+ * (6180 has different SAR layout than other Kirkwood SoCs)
+ *
+ * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
+ * 4 = 600 MHz
+ * 6 = 800 MHz
+ * 7 = 1000 MHz
+ * 9 = 1200 MHz
+ * 12 = 1500 MHz
+ * 13 = 1600 MHz
+ * 14 = 1800 MHz
+ * 15 = 2000 MHz
+ * others reserved.
+ *
+ * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
+ * 1 = (1/2) * CPU
+ * 3 = (1/3) * CPU
+ * 5 = (1/4) * CPU
+ * others reserved.
+ *
+ * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
+ * 2 = (1/2) * CPU
+ * 4 = (1/3) * CPU
+ * 6 = (1/4) * CPU
+ * 7 = (2/9) * CPU
+ * 8 = (1/5) * CPU
+ * 9 = (1/6) * CPU
+ * others reserved.
+ *
+ * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
+ * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
+ * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
+ * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
+ * others reserved.
+ *
+ * SAR0[21] : TCLK frequency
+ * 0 = 200 MHz
+ * 1 = 166 MHz
+ * others reserved.
+ */
+
+#define SAR_KIRKWOOD_CPU_FREQ(x) \
+ (((x & (1 << 1)) >> 1) | \
+ ((x & (1 << 22)) >> 21) | \
+ ((x & (3 << 3)) >> 1))
+#define SAR_KIRKWOOD_L2_RATIO(x) \
+ (((x & (3 << 9)) >> 9) | \
+ (((x & (1 << 19)) >> 17)))
+#define SAR_KIRKWOOD_DDR_RATIO 5
+#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
+#define SAR_MV88F6180_CLK 2
+#define SAR_MV88F6180_CLK_MASK 0x7
+#define SAR_KIRKWOOD_TCLK_FREQ 21
+#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
+
+enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst kirkwood_coreclk_ratios[] = {
+ { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
+ { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
+ SAR_KIRKWOOD_TCLK_FREQ_MASK;
+ return (opt) ? 166666667 : 200000000;
+}
+
+static const u32 __initconst kirkwood_cpu_freqs[] = {
+ 0, 0, 0, 0,
+ 600000000,
+ 0,
+ 800000000,
+ 1000000000,
+ 0,
+ 1200000000,
+ 0, 0,
+ 1500000000,
+ 1600000000,
+ 1800000000,
+ 2000000000
+};
+
+static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
+ return kirkwood_cpu_freqs[opt];
+}
+
+static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
+ { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
+ { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
+};
+
+static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
+ { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+ { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
+ { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
+ { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
+};
+
+static void __init kirkwood_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ switch (id) {
+ case KIRKWOOD_CPU_TO_L2:
+ {
+ u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
+ *mult = kirkwood_cpu_l2_ratios[opt][0];
+ *div = kirkwood_cpu_l2_ratios[opt][1];
+ break;
+ }
+ case KIRKWOOD_CPU_TO_DDR:
+ {
+ u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
+ SAR_KIRKWOOD_DDR_RATIO_MASK;
+ *mult = kirkwood_cpu_ddr_ratios[opt][0];
+ *div = kirkwood_cpu_ddr_ratios[opt][1];
+ break;
+ }
+ }
+}
+
+static const u32 __initconst mv88f6180_cpu_freqs[] = {
+ 0, 0, 0, 0, 0,
+ 600000000,
+ 800000000,
+ 1000000000
+};
+
+static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
+ return mv88f6180_cpu_freqs[opt];
+}
+
+static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
+ { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
+ { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
+};
+
+static void __init mv88f6180_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ switch (id) {
+ case KIRKWOOD_CPU_TO_L2:
+ {
+ /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
+ *mult = 1;
+ *div = 2;
+ break;
+ }
+ case KIRKWOOD_CPU_TO_DDR:
+ {
+ u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
+ SAR_MV88F6180_CLK_MASK;
+ *mult = mv88f6180_cpu_ddr_ratios[opt][0];
+ *div = mv88f6180_cpu_ddr_ratios[opt][1];
+ break;
+ }
+ }
+}
+
+static const struct coreclk_soc_desc kirkwood_coreclks = {
+ .get_tclk_freq = kirkwood_get_tclk_freq,
+ .get_cpu_freq = kirkwood_get_cpu_freq,
+ .get_clk_ratio = kirkwood_get_clk_ratio,
+ .ratios = kirkwood_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init kirkwood_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &kirkwood_coreclks);
+}
+CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
+ kirkwood_coreclk_init);
+
+static const struct coreclk_soc_desc mv88f6180_coreclks = {
+ .get_tclk_freq = kirkwood_get_tclk_freq,
+ .get_cpu_freq = mv88f6180_get_cpu_freq,
+ .get_clk_ratio = mv88f6180_get_clk_ratio,
+ .ratios = kirkwood_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init mv88f6180_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &mv88f6180_coreclks);
+}
+CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
+ mv88f6180_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst kirkwood_gating_desc[] = {
+ { "ge0", NULL, 0, 0 },
+ { "pex0", NULL, 2, 0 },
+ { "usb0", NULL, 3, 0 },
+ { "sdio", NULL, 4, 0 },
+ { "tsu", NULL, 5, 0 },
+ { "runit", NULL, 7, 0 },
+ { "xor0", NULL, 8, 0 },
+ { "audio", NULL, 9, 0 },
+ { "powersave", "cpuclk", 11, 0 },
+ { "sata0", NULL, 14, 0 },
+ { "sata1", NULL, 15, 0 },
+ { "xor1", NULL, 16, 0 },
+ { "crypto", NULL, 17, 0 },
+ { "pex1", NULL, 18, 0 },
+ { "ge1", NULL, 19, 0 },
+ { "tdm", NULL, 20, 0 },
+ { }
+};
+
+static void __init kirkwood_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, kirkwood_gating_desc);
+}
+CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
+ kirkwood_clk_gating_init);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 05/10] clk: mvebu: add Armada 370 SoC-centric clock init
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
This is moving core clock and clock gating init for Armada 370 to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 5 ++
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-370.c | 176 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 182 insertions(+)
create mode 100644 drivers/clk/mvebu/armada-370.c
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 211695c..1daf61e 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -10,6 +10,11 @@ config MVEBU_CLK_GATING
config MVEBU_CLK_COMMON
bool
+config ARMADA_370_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 97d1ab0..367b72c 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
+obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
obj-$(CONFIG_DOVE_CLK) += dove.o
obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
new file mode 100644
index 0000000..3c11550
--- /dev/null
+++ b/drivers/clk/mvebu/armada-370.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Armada 370 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_A370_PCLK_FREQ_OPT 11
+#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
+#define SARL_A370_FAB_FREQ_OPT 15
+#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
+#define SARL_A370_TCLK_FREQ_OPT 20
+#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
+
+enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = {
+ { .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = A370_CPU_TO_HCLK, .name = "hclk" },
+ { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+static const u32 __initconst a370_tclk_freqs[] = {
+ 16600000,
+ 20000000,
+};
+
+static u32 __init a370_get_tclk_freq(void __iomem *sar)
+{
+ u8 tclk_freq_select = 0;
+
+ tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
+ SARL_A370_TCLK_FREQ_OPT_MASK);
+ return a370_tclk_freqs[tclk_freq_select];
+}
+
+static const u32 __initconst a370_cpu_freqs[] = {
+ 400000000,
+ 533000000,
+ 667000000,
+ 800000000,
+ 1000000000,
+ 1067000000,
+ 1200000000,
+};
+
+static u32 __init a370_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
+ SARL_A370_PCLK_FREQ_OPT_MASK);
+ if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
+ pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = a370_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst a370_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init a370_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
+ SARL_A370_FAB_FREQ_OPT_MASK);
+
+ switch (id) {
+ case A370_CPU_TO_NBCLK:
+ *mult = a370_nbclk_ratios[opt][0];
+ *div = a370_nbclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_HCLK:
+ *mult = a370_hclk_ratios[opt][0];
+ *div = a370_hclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_DRAMCLK:
+ *mult = a370_dramclk_ratios[opt][0];
+ *div = a370_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc a370_coreclks = {
+ .get_tclk_freq = a370_get_tclk_freq,
+ .get_cpu_freq = a370_get_cpu_freq,
+ .get_clk_ratio = a370_get_clk_ratio,
+ .ratios = a370_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
+};
+
+static void __init a370_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &a370_coreclks);
+}
+CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
+ a370_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "pex0_en", NULL, 1, 0 },
+ { "pex1_en", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", NULL, 5, 0 },
+ { "pex1", NULL, 9, 0 },
+ { "sata0", NULL, 15, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+ { "sata1", NULL, 30, 0 },
+ { }
+};
+
+static void __init a370_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, a370_gating_desc);
+}
+CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
+ a370_clk_gating_init);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 05/10] clk: mvebu: add Armada 370 SoC-centric clock init
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
This is moving core clock and clock gating init for Armada 370 to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 5 ++
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-370.c | 176 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 182 insertions(+)
create mode 100644 drivers/clk/mvebu/armada-370.c
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 211695c..1daf61e 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -10,6 +10,11 @@ config MVEBU_CLK_GATING
config MVEBU_CLK_COMMON
bool
+config ARMADA_370_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 97d1ab0..367b72c 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
+obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
obj-$(CONFIG_DOVE_CLK) += dove.o
obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
new file mode 100644
index 0000000..3c11550
--- /dev/null
+++ b/drivers/clk/mvebu/armada-370.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Armada 370 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_A370_PCLK_FREQ_OPT 11
+#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
+#define SARL_A370_FAB_FREQ_OPT 15
+#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
+#define SARL_A370_TCLK_FREQ_OPT 20
+#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
+
+enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = {
+ { .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = A370_CPU_TO_HCLK, .name = "hclk" },
+ { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+static const u32 __initconst a370_tclk_freqs[] = {
+ 16600000,
+ 20000000,
+};
+
+static u32 __init a370_get_tclk_freq(void __iomem *sar)
+{
+ u8 tclk_freq_select = 0;
+
+ tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
+ SARL_A370_TCLK_FREQ_OPT_MASK);
+ return a370_tclk_freqs[tclk_freq_select];
+}
+
+static const u32 __initconst a370_cpu_freqs[] = {
+ 400000000,
+ 533000000,
+ 667000000,
+ 800000000,
+ 1000000000,
+ 1067000000,
+ 1200000000,
+};
+
+static u32 __init a370_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
+ SARL_A370_PCLK_FREQ_OPT_MASK);
+ if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
+ pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = a370_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst a370_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init a370_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
+ SARL_A370_FAB_FREQ_OPT_MASK);
+
+ switch (id) {
+ case A370_CPU_TO_NBCLK:
+ *mult = a370_nbclk_ratios[opt][0];
+ *div = a370_nbclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_HCLK:
+ *mult = a370_hclk_ratios[opt][0];
+ *div = a370_hclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_DRAMCLK:
+ *mult = a370_dramclk_ratios[opt][0];
+ *div = a370_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc a370_coreclks = {
+ .get_tclk_freq = a370_get_tclk_freq,
+ .get_cpu_freq = a370_get_cpu_freq,
+ .get_clk_ratio = a370_get_clk_ratio,
+ .ratios = a370_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
+};
+
+static void __init a370_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &a370_coreclks);
+}
+CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
+ a370_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "pex0_en", NULL, 1, 0 },
+ { "pex1_en", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", NULL, 5, 0 },
+ { "pex1", NULL, 9, 0 },
+ { "sata0", NULL, 15, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+ { "sata1", NULL, 30, 0 },
+ { }
+};
+
+static void __init a370_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, a370_gating_desc);
+}
+CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
+ a370_clk_gating_init);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 06/10] clk: mvebu: add Armada XP SoC-centric clock init
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
This is moving core clock and clock gating init for Armada XP to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 5 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-xp.c | 204 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 210 insertions(+)
create mode 100644 drivers/clk/mvebu/armada-xp.c
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 1daf61e..8740d34 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -15,6 +15,11 @@ config ARMADA_370_CLK
select MVEBU_CLK_COMMON
select MVEBU_CLK_CPU
+config ARMADA_XP_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 367b72c..13f3d22 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
+obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
obj-$(CONFIG_DOVE_CLK) += dove.o
obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
new file mode 100644
index 0000000..cf7612e
--- /dev/null
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -0,0 +1,204 @@
+/*
+ * Marvell Armada XP SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * register of 32 bits
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_AXP_PCLK_FREQ_OPT 21
+#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
+#define SARL_AXP_FAB_FREQ_OPT 24
+#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
+#define SARH 4 /* High part [32:63] */
+#define SARH_AXP_PCLK_FREQ_OPT (52-32)
+#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
+#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
+#define SARH_AXP_FAB_FREQ_OPT (51-32)
+#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
+#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
+
+enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = {
+ { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
+ { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+/* Armada XP TCLK frequency is fixed to 250MHz */
+static u32 __init axp_get_tclk_freq(void __iomem *sar)
+{
+ return 250000000;
+}
+
+static const u32 __initconst axp_cpu_freqs[] = {
+ 1000000000,
+ 1066000000,
+ 1200000000,
+ 1333000000,
+ 1500000000,
+ 1666000000,
+ 1800000000,
+ 2000000000,
+ 667000000,
+ 0,
+ 800000000,
+ 1600000000,
+};
+
+static u32 __init axp_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
+ SARL_AXP_PCLK_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
+ SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+ if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
+ pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = axp_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst axp_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init axp_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
+ SARL_AXP_FAB_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
+ SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+ switch (id) {
+ case AXP_CPU_TO_NBCLK:
+ *mult = axp_nbclk_ratios[opt][0];
+ *div = axp_nbclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_HCLK:
+ *mult = axp_hclk_ratios[opt][0];
+ *div = axp_hclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_DRAMCLK:
+ *mult = axp_dramclk_ratios[opt][0];
+ *div = axp_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc axp_coreclks = {
+ .get_tclk_freq = axp_get_tclk_freq,
+ .get_cpu_freq = axp_get_cpu_freq,
+ .get_clk_ratio = axp_get_clk_ratio,
+ .ratios = axp_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
+};
+
+static void __init axp_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &axp_coreclks);
+}
+CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
+ axp_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "ge3", NULL, 1, 0 },
+ { "ge2", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", NULL, 5, 0 },
+ { "pex1", NULL, 6, 0 },
+ { "pex2", NULL, 7, 0 },
+ { "pex3", NULL, 8, 0 },
+ { "bp", NULL, 13, 0 },
+ { "sata0lnk", NULL, 14, 0 },
+ { "sata0", "sata0lnk", 15, 0 },
+ { "lcd", NULL, 16, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "usb0", NULL, 18, 0 },
+ { "usb1", NULL, 19, 0 },
+ { "usb2", NULL, 20, 0 },
+ { "xor0", NULL, 22, 0 },
+ { "crypto", NULL, 23, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "xor1", NULL, 28, 0 },
+ { "sata1lnk", NULL, 29, 0 },
+ { "sata1", "sata1lnk", 30, 0 },
+ { }
+};
+
+static void __init axp_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, axp_gating_desc);
+}
+CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
+ axp_clk_gating_init);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 06/10] clk: mvebu: add Armada XP SoC-centric clock init
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
This is moving core clock and clock gating init for Armada XP to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 5 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-xp.c | 204 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 210 insertions(+)
create mode 100644 drivers/clk/mvebu/armada-xp.c
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 1daf61e..8740d34 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -15,6 +15,11 @@ config ARMADA_370_CLK
select MVEBU_CLK_COMMON
select MVEBU_CLK_CPU
+config ARMADA_XP_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 367b72c..13f3d22 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
+obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
obj-$(CONFIG_DOVE_CLK) += dove.o
obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
new file mode 100644
index 0000000..cf7612e
--- /dev/null
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -0,0 +1,204 @@
+/*
+ * Marvell Armada XP SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * register of 32 bits
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_AXP_PCLK_FREQ_OPT 21
+#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
+#define SARL_AXP_FAB_FREQ_OPT 24
+#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
+#define SARH 4 /* High part [32:63] */
+#define SARH_AXP_PCLK_FREQ_OPT (52-32)
+#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
+#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
+#define SARH_AXP_FAB_FREQ_OPT (51-32)
+#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
+#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
+
+enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = {
+ { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
+ { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+/* Armada XP TCLK frequency is fixed to 250MHz */
+static u32 __init axp_get_tclk_freq(void __iomem *sar)
+{
+ return 250000000;
+}
+
+static const u32 __initconst axp_cpu_freqs[] = {
+ 1000000000,
+ 1066000000,
+ 1200000000,
+ 1333000000,
+ 1500000000,
+ 1666000000,
+ 1800000000,
+ 2000000000,
+ 667000000,
+ 0,
+ 800000000,
+ 1600000000,
+};
+
+static u32 __init axp_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
+ SARL_AXP_PCLK_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
+ SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+ if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
+ pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = axp_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst axp_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init axp_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
+ SARL_AXP_FAB_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
+ SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+ switch (id) {
+ case AXP_CPU_TO_NBCLK:
+ *mult = axp_nbclk_ratios[opt][0];
+ *div = axp_nbclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_HCLK:
+ *mult = axp_hclk_ratios[opt][0];
+ *div = axp_hclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_DRAMCLK:
+ *mult = axp_dramclk_ratios[opt][0];
+ *div = axp_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc axp_coreclks = {
+ .get_tclk_freq = axp_get_tclk_freq,
+ .get_cpu_freq = axp_get_cpu_freq,
+ .get_clk_ratio = axp_get_clk_ratio,
+ .ratios = axp_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
+};
+
+static void __init axp_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &axp_coreclks);
+}
+CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
+ axp_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "ge3", NULL, 1, 0 },
+ { "ge2", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", NULL, 5, 0 },
+ { "pex1", NULL, 6, 0 },
+ { "pex2", NULL, 7, 0 },
+ { "pex3", NULL, 8, 0 },
+ { "bp", NULL, 13, 0 },
+ { "sata0lnk", NULL, 14, 0 },
+ { "sata0", "sata0lnk", 15, 0 },
+ { "lcd", NULL, 16, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "usb0", NULL, 18, 0 },
+ { "usb1", NULL, 19, 0 },
+ { "usb2", NULL, 20, 0 },
+ { "xor0", NULL, 22, 0 },
+ { "crypto", NULL, 23, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "xor1", NULL, 28, 0 },
+ { "sata1lnk", NULL, 29, 0 },
+ { "sata1", "sata1lnk", 30, 0 },
+ { }
+};
+
+static void __init axp_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, axp_gating_desc);
+}
+CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
+ axp_clk_gating_init);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 07/10] ARM: dove: move DT boards to SoC-centric clock init
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
SoC centric clock init for Dove can be used by calling of_clk_init.
Use it and get rid of mvebu_clocks_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm/mach-dove/Kconfig | 3 +--
arch/arm/mach-dove/board-dt.c | 3 +--
arch/arm/mach-dove/common.c | 1 -
3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 36469d8..dff7b2f 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -22,8 +22,7 @@ config MACH_CM_A510
config MACH_DOVE_DT
bool "Marvell Dove Flattened Device Tree"
- select MVEBU_CLK_CORE
- select MVEBU_CLK_GATING
+ select DOVE_CLK
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
select USE_OF
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 0b14280..f3755ac 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -10,7 +10,6 @@
#include <linux/init.h>
#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/usb-ehci-orion.h>
@@ -49,7 +48,7 @@ static void __init dove_legacy_clk_init(void)
static void __init dove_of_clk_init(void)
{
- mvebu_clocks_init();
+ of_clk_init(NULL);
dove_legacy_clk_init();
}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da0..2a9443d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -9,7 +9,6 @@
*/
#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/of.h>
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 07/10] ARM: dove: move DT boards to SoC-centric clock init
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
SoC centric clock init for Dove can be used by calling of_clk_init.
Use it and get rid of mvebu_clocks_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/mach-dove/Kconfig | 3 +--
arch/arm/mach-dove/board-dt.c | 3 +--
arch/arm/mach-dove/common.c | 1 -
3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 36469d8..dff7b2f 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -22,8 +22,7 @@ config MACH_CM_A510
config MACH_DOVE_DT
bool "Marvell Dove Flattened Device Tree"
- select MVEBU_CLK_CORE
- select MVEBU_CLK_GATING
+ select DOVE_CLK
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
select USE_OF
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 0b14280..f3755ac 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -10,7 +10,6 @@
#include <linux/init.h>
#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/usb-ehci-orion.h>
@@ -49,7 +48,7 @@ static void __init dove_legacy_clk_init(void)
static void __init dove_of_clk_init(void)
{
- mvebu_clocks_init();
+ of_clk_init(NULL);
dove_legacy_clk_init();
}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da0..2a9443d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -9,7 +9,6 @@
*/
#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/of.h>
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 08/10] ARM: kirkwood: move DT boards to SoC-centric clock init
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
SoC centric clock init for Kirkwood can be used by calling of_clk_init.
Use it and get rid of mvebu_clocks_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm/mach-kirkwood/Kconfig | 3 +--
arch/arm/mach-kirkwood/board-dt.c | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89..79ee9f2 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -134,13 +134,12 @@ comment "Device tree entries"
config ARCH_KIRKWOOD_DT
bool "Marvell Kirkwood Flattened Device Tree"
+ select KIRKWOOD_CLK
select POWER_SUPPLY
select POWER_RESET
select POWER_RESET_GPIO
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
- select MVEBU_CLK_CORE
- select MVEBU_CLK_GATING
select USE_OF
help
Say 'Y' here if you want your kernel to support the
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b8..2f695e5 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -15,7 +15,6 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
#include <linux/kexec.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -77,7 +76,7 @@ static void __init kirkwood_legacy_clk_init(void)
static void __init kirkwood_of_clk_init(void)
{
- mvebu_clocks_init();
+ of_clk_init(NULL);
kirkwood_legacy_clk_init();
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 08/10] ARM: kirkwood: move DT boards to SoC-centric clock init
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
SoC centric clock init for Kirkwood can be used by calling of_clk_init.
Use it and get rid of mvebu_clocks_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/mach-kirkwood/Kconfig | 3 +--
arch/arm/mach-kirkwood/board-dt.c | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89..79ee9f2 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -134,13 +134,12 @@ comment "Device tree entries"
config ARCH_KIRKWOOD_DT
bool "Marvell Kirkwood Flattened Device Tree"
+ select KIRKWOOD_CLK
select POWER_SUPPLY
select POWER_RESET
select POWER_RESET_GPIO
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
- select MVEBU_CLK_CORE
- select MVEBU_CLK_GATING
select USE_OF
help
Say 'Y' here if you want your kernel to support the
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b8..2f695e5 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -15,7 +15,6 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
#include <linux/kexec.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -77,7 +76,7 @@ static void __init kirkwood_legacy_clk_init(void)
static void __init kirkwood_of_clk_init(void)
{
- mvebu_clocks_init();
+ of_clk_init(NULL);
kirkwood_legacy_clk_init();
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 09/10] ARM: mvebu: move DT boards to SoC-centric clock init
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
SoC centric clock init for Armada 370/XP can be used by calling of_clk_init.
Use it and get rid of mvebu_clocks_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm/mach-mvebu/Kconfig | 5 ++---
arch/arm/mach-mvebu/armada-370-xp.c | 4 ++--
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e11acbb..6512837 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -10,9 +10,6 @@ config ARCH_MVEBU
select PLAT_ORION
select SPARSE_IRQ
select CLKDEV_LOOKUP
- select MVEBU_CLK_CORE
- select MVEBU_CLK_CPU
- select MVEBU_CLK_GATING
select MVEBU_MBUS
select ZONE_DMA if ARM_LPAE
@@ -29,6 +26,7 @@ config MACH_ARMADA_370_XP
config MACH_ARMADA_370
bool "Marvell Armada 370 boards"
+ select ARMADA_370_CLK
select MACH_ARMADA_370_XP
select PINCTRL_ARMADA_370
help
@@ -37,6 +35,7 @@ config MACH_ARMADA_370
config MACH_ARMADA_XP
bool "Marvell Armada XP boards"
+ select ARMADA_XP_CLK
select MACH_ARMADA_370_XP
select PINCTRL_ARMADA_XP
help
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 42a4cb3..1d018e4 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -14,10 +14,10 @@
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/clk-provider.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/time-armada-370-xp.h>
-#include <linux/clk/mvebu.h>
#include <linux/dma-mapping.h>
#include <linux/mbus.h>
#include <linux/irqchip.h>
@@ -45,7 +45,7 @@ void __init armada_370_xp_map_io(void)
void __init armada_370_xp_timer_and_clk_init(void)
{
- mvebu_clocks_init();
+ of_clk_init(NULL);
armada_370_xp_timer_init();
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 09/10] ARM: mvebu: move DT boards to SoC-centric clock init
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
SoC centric clock init for Armada 370/XP can be used by calling of_clk_init.
Use it and get rid of mvebu_clocks_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/mach-mvebu/Kconfig | 5 ++---
arch/arm/mach-mvebu/armada-370-xp.c | 4 ++--
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e11acbb..6512837 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -10,9 +10,6 @@ config ARCH_MVEBU
select PLAT_ORION
select SPARSE_IRQ
select CLKDEV_LOOKUP
- select MVEBU_CLK_CORE
- select MVEBU_CLK_CPU
- select MVEBU_CLK_GATING
select MVEBU_MBUS
select ZONE_DMA if ARM_LPAE
@@ -29,6 +26,7 @@ config MACH_ARMADA_370_XP
config MACH_ARMADA_370
bool "Marvell Armada 370 boards"
+ select ARMADA_370_CLK
select MACH_ARMADA_370_XP
select PINCTRL_ARMADA_370
help
@@ -37,6 +35,7 @@ config MACH_ARMADA_370
config MACH_ARMADA_XP
bool "Marvell Armada XP boards"
+ select ARMADA_XP_CLK
select MACH_ARMADA_370_XP
select PINCTRL_ARMADA_XP
help
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 42a4cb3..1d018e4 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -14,10 +14,10 @@
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/clk-provider.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/time-armada-370-xp.h>
-#include <linux/clk/mvebu.h>
#include <linux/dma-mapping.h>
#include <linux/mbus.h>
#include <linux/irqchip.h>
@@ -45,7 +45,7 @@ void __init armada_370_xp_map_io(void)
void __init armada_370_xp_timer_and_clk_init(void)
{
- mvebu_clocks_init();
+ of_clk_init(NULL);
armada_370_xp_timer_init();
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 10/10] clk: mvebu: desintegrate obsolete file
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, Mike Turquette, linux-arm-kernel, linux-kernel
Switch from function-centric to soc-centric clock drivers now makes
a bunch of files obsolete. This deletes all files and Kconfig options
that are not required anymore.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 10 +-
drivers/clk/mvebu/Makefile | 2 -
drivers/clk/mvebu/clk-core.c | 675 -----------------------------------
drivers/clk/mvebu/clk-core.h | 18 -
drivers/clk/mvebu/clk-gating-ctrl.c | 241 -------------
drivers/clk/mvebu/clk-gating-ctrl.h | 22 --
drivers/clk/mvebu/clk.c | 23 --
include/linux/clk/mvebu.h | 22 --
8 files changed, 2 insertions(+), 1011 deletions(-)
delete mode 100644 drivers/clk/mvebu/clk-core.c
delete mode 100644 drivers/clk/mvebu/clk-core.h
delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
delete mode 100644 drivers/clk/mvebu/clk.c
delete mode 100644 include/linux/clk/mvebu.h
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 8740d34..0b0f3e7 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -1,13 +1,7 @@
-config MVEBU_CLK_CORE
- bool
+config MVEBU_CLK_COMMON
+ bool
config MVEBU_CLK_CPU
- bool
-
-config MVEBU_CLK_GATING
- bool
-
-config MVEBU_CLK_COMMON
bool
config ARMADA_370_CLK
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 13f3d22..1c7e70c 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,7 +1,5 @@
obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
-obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
-obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c
deleted file mode 100644
index 0a53edb..0000000
--- a/drivers/clk/mvebu/clk-core.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include "clk-core.h"
-
-struct core_ratio {
- int id;
- const char *name;
-};
-
-struct core_clocks {
- u32 (*get_tclk_freq)(void __iomem *sar);
- u32 (*get_cpu_freq)(void __iomem *sar);
- void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
- const struct core_ratio *ratios;
- int num_ratios;
-};
-
-static struct clk_onecell_data clk_data;
-
-static void __init mvebu_clk_core_setup(struct device_node *np,
- struct core_clocks *coreclk)
-{
- const char *tclk_name = "tclk";
- const char *cpuclk_name = "cpuclk";
- void __iomem *base;
- unsigned long rate;
- int n;
-
- base = of_iomap(np, 0);
- if (WARN_ON(!base))
- return;
-
- /*
- * Allocate struct for TCLK, cpu clk, and core ratio clocks
- */
- clk_data.clk_num = 2 + coreclk->num_ratios;
- clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
- GFP_KERNEL);
- if (WARN_ON(!clk_data.clks))
- return;
-
- /*
- * Register TCLK
- */
- of_property_read_string_index(np, "clock-output-names", 0,
- &tclk_name);
- rate = coreclk->get_tclk_freq(base);
- clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
- CLK_IS_ROOT, rate);
- WARN_ON(IS_ERR(clk_data.clks[0]));
-
- /*
- * Register CPU clock
- */
- of_property_read_string_index(np, "clock-output-names", 1,
- &cpuclk_name);
- rate = coreclk->get_cpu_freq(base);
- clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
- CLK_IS_ROOT, rate);
- WARN_ON(IS_ERR(clk_data.clks[1]));
-
- /*
- * Register fixed-factor clocks derived from CPU clock
- */
- for (n = 0; n < coreclk->num_ratios; n++) {
- const char *rclk_name = coreclk->ratios[n].name;
- int mult, div;
-
- of_property_read_string_index(np, "clock-output-names",
- 2+n, &rclk_name);
- coreclk->get_clk_ratio(base, coreclk->ratios[n].id,
- &mult, &div);
- clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
- cpuclk_name, 0, mult, div);
- WARN_ON(IS_ERR(clk_data.clks[2+n]));
- };
-
- /*
- * SAR register isn't needed anymore
- */
- iounmap(base);
-
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
-
-#ifdef CONFIG_MACH_ARMADA_370_XP
-/*
- * Armada 370/XP Sample At Reset is a 64 bit bitfiled split in two
- * register of 32 bits
- */
-
-#define SARL 0 /* Low part [0:31] */
-#define SARL_AXP_PCLK_FREQ_OPT 21
-#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
-#define SARL_A370_PCLK_FREQ_OPT 11
-#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
-#define SARL_AXP_FAB_FREQ_OPT 24
-#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
-#define SARL_A370_FAB_FREQ_OPT 15
-#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
-#define SARL_A370_TCLK_FREQ_OPT 20
-#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
-#define SARH 4 /* High part [32:63] */
-#define SARH_AXP_PCLK_FREQ_OPT (52-32)
-#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
-#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
-#define SARH_AXP_FAB_FREQ_OPT (51-32)
-#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
-#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
-
-static const u32 __initconst armada_370_tclk_frequencies[] = {
- 16600000,
- 20000000,
-};
-
-static u32 __init armada_370_get_tclk_freq(void __iomem *sar)
-{
- u8 tclk_freq_select = 0;
-
- tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
- SARL_A370_TCLK_FREQ_OPT_MASK);
- return armada_370_tclk_frequencies[tclk_freq_select];
-}
-
-static const u32 __initconst armada_370_cpu_frequencies[] = {
- 400000000,
- 533000000,
- 667000000,
- 800000000,
- 1000000000,
- 1067000000,
- 1200000000,
-};
-
-static u32 __init armada_370_get_cpu_freq(void __iomem *sar)
-{
- u32 cpu_freq;
- u8 cpu_freq_select = 0;
-
- cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
- SARL_A370_PCLK_FREQ_OPT_MASK);
- if (cpu_freq_select >= ARRAY_SIZE(armada_370_cpu_frequencies)) {
- pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
- cpu_freq = 0;
- } else
- cpu_freq = armada_370_cpu_frequencies[cpu_freq_select];
-
- return cpu_freq;
-}
-
-enum { A370_XP_NBCLK, A370_XP_HCLK, A370_XP_DRAMCLK };
-
-static const struct core_ratio __initconst armada_370_xp_core_ratios[] = {
- { .id = A370_XP_NBCLK, .name = "nbclk" },
- { .id = A370_XP_HCLK, .name = "hclk" },
- { .id = A370_XP_DRAMCLK, .name = "dramclk" },
-};
-
-static const int __initconst armada_370_xp_nbclk_ratios[32][2] = {
- {0, 1}, {1, 2}, {2, 2}, {2, 2},
- {1, 2}, {1, 2}, {1, 1}, {2, 3},
- {0, 1}, {1, 2}, {2, 4}, {0, 1},
- {1, 2}, {0, 1}, {0, 1}, {2, 2},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {2, 3}, {0, 1}, {0, 1}, {0, 1},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_hclk_ratios[32][2] = {
- {0, 1}, {1, 2}, {2, 6}, {2, 3},
- {1, 3}, {1, 4}, {1, 2}, {2, 6},
- {0, 1}, {1, 6}, {2, 10}, {0, 1},
- {1, 4}, {0, 1}, {0, 1}, {2, 5},
- {0, 1}, {0, 1}, {0, 1}, {1, 2},
- {2, 6}, {0, 1}, {0, 1}, {0, 1},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_dramclk_ratios[32][2] = {
- {0, 1}, {1, 2}, {2, 3}, {2, 3},
- {1, 3}, {1, 2}, {1, 2}, {2, 6},
- {0, 1}, {1, 3}, {2, 5}, {0, 1},
- {1, 4}, {0, 1}, {0, 1}, {2, 5},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {2, 3}, {0, 1}, {0, 1}, {0, 1},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static void __init armada_370_xp_get_clk_ratio(u32 opt,
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case A370_XP_NBCLK:
- *mult = armada_370_xp_nbclk_ratios[opt][0];
- *div = armada_370_xp_nbclk_ratios[opt][1];
- break;
- case A370_XP_HCLK:
- *mult = armada_370_xp_hclk_ratios[opt][0];
- *div = armada_370_xp_hclk_ratios[opt][1];
- break;
- case A370_XP_DRAMCLK:
- *mult = armada_370_xp_dramclk_ratios[opt][0];
- *div = armada_370_xp_dramclk_ratios[opt][1];
- break;
- }
-}
-
-static void __init armada_370_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
- SARL_A370_FAB_FREQ_OPT_MASK);
-
- armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-
-static const struct core_clocks armada_370_core_clocks = {
- .get_tclk_freq = armada_370_get_tclk_freq,
- .get_cpu_freq = armada_370_get_cpu_freq,
- .get_clk_ratio = armada_370_get_clk_ratio,
- .ratios = armada_370_xp_core_ratios,
- .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-static const u32 __initconst armada_xp_cpu_frequencies[] = {
- 1000000000,
- 1066000000,
- 1200000000,
- 1333000000,
- 1500000000,
- 1666000000,
- 1800000000,
- 2000000000,
- 667000000,
- 0,
- 800000000,
- 1600000000,
-};
-
-/* For Armada XP TCLK frequency is fix: 250MHz */
-static u32 __init armada_xp_get_tclk_freq(void __iomem *sar)
-{
- return 250 * 1000 * 1000;
-}
-
-static u32 __init armada_xp_get_cpu_freq(void __iomem *sar)
-{
- u32 cpu_freq;
- u8 cpu_freq_select = 0;
-
- cpu_freq_select = ((readl(sar) >> SARL_AXP_PCLK_FREQ_OPT) &
- SARL_AXP_PCLK_FREQ_OPT_MASK);
- /*
- * The upper bit is not contiguous to the other ones and
- * located in the high part of the SAR registers
- */
- cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) &
- SARH_AXP_PCLK_FREQ_OPT_MASK)
- << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
- if (cpu_freq_select >= ARRAY_SIZE(armada_xp_cpu_frequencies)) {
- pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
- cpu_freq = 0;
- } else
- cpu_freq = armada_xp_cpu_frequencies[cpu_freq_select];
-
- return cpu_freq;
-}
-
-static void __init armada_xp_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
-
- u32 opt = ((readl(sar) >> SARL_AXP_FAB_FREQ_OPT) &
- SARL_AXP_FAB_FREQ_OPT_MASK);
- /*
- * The upper bit is not contiguous to the other ones and
- * located in the high part of the SAR registers
- */
- opt |= (((readl(sar+4) >> SARH_AXP_FAB_FREQ_OPT) &
- SARH_AXP_FAB_FREQ_OPT_MASK)
- << SARH_AXP_FAB_FREQ_OPT_SHIFT);
-
- armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-static const struct core_clocks armada_xp_core_clocks = {
- .get_tclk_freq = armada_xp_get_tclk_freq,
- .get_cpu_freq = armada_xp_get_cpu_freq,
- .get_clk_ratio = armada_xp_get_clk_ratio,
- .ratios = armada_370_xp_core_ratios,
- .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-#endif /* CONFIG_MACH_ARMADA_370_XP */
-
-/*
- * Dove PLL sample-at-reset configuration
- *
- * SAR0[8:5] : CPU frequency
- * 5 = 1000 MHz
- * 6 = 933 MHz
- * 7 = 933 MHz
- * 8 = 800 MHz
- * 9 = 800 MHz
- * 10 = 800 MHz
- * 11 = 1067 MHz
- * 12 = 667 MHz
- * 13 = 533 MHz
- * 14 = 400 MHz
- * 15 = 333 MHz
- * others reserved.
- *
- * SAR0[11:9] : CPU to L2 Clock divider ratio
- * 0 = (1/1) * CPU
- * 2 = (1/2) * CPU
- * 4 = (1/3) * CPU
- * 6 = (1/4) * CPU
- * others reserved.
- *
- * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
- * 0 = (1/1) * CPU
- * 2 = (1/2) * CPU
- * 3 = (2/5) * CPU
- * 4 = (1/3) * CPU
- * 6 = (1/4) * CPU
- * 8 = (1/5) * CPU
- * 10 = (1/6) * CPU
- * 12 = (1/7) * CPU
- * 14 = (1/8) * CPU
- * 15 = (1/10) * CPU
- * others reserved.
- *
- * SAR0[24:23] : TCLK frequency
- * 0 = 166 MHz
- * 1 = 125 MHz
- * others reserved.
- */
-#ifdef CONFIG_ARCH_DOVE
-#define SAR_DOVE_CPU_FREQ 5
-#define SAR_DOVE_CPU_FREQ_MASK 0xf
-#define SAR_DOVE_L2_RATIO 9
-#define SAR_DOVE_L2_RATIO_MASK 0x7
-#define SAR_DOVE_DDR_RATIO 12
-#define SAR_DOVE_DDR_RATIO_MASK 0xf
-#define SAR_DOVE_TCLK_FREQ 23
-#define SAR_DOVE_TCLK_FREQ_MASK 0x3
-
-static const u32 __initconst dove_tclk_frequencies[] = {
- 166666667,
- 125000000,
- 0, 0
-};
-
-static u32 __init dove_get_tclk_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
- SAR_DOVE_TCLK_FREQ_MASK;
- return dove_tclk_frequencies[opt];
-}
-
-static const u32 __initconst dove_cpu_frequencies[] = {
- 0, 0, 0, 0, 0,
- 1000000000,
- 933333333, 933333333,
- 800000000, 800000000, 800000000,
- 1066666667,
- 666666667,
- 533333333,
- 400000000,
- 333333333
-};
-
-static u32 __init dove_get_cpu_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
- SAR_DOVE_CPU_FREQ_MASK;
- return dove_cpu_frequencies[opt];
-}
-
-enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
-
-static const struct core_ratio __initconst dove_core_ratios[] = {
- { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
- { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static const int __initconst dove_cpu_l2_ratios[8][2] = {
- { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
- { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
-};
-
-static const int __initconst dove_cpu_ddr_ratios[16][2] = {
- { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
- { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
- { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
- { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
-};
-
-static void __init dove_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case DOVE_CPU_TO_L2:
- {
- u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
- SAR_DOVE_L2_RATIO_MASK;
- *mult = dove_cpu_l2_ratios[opt][0];
- *div = dove_cpu_l2_ratios[opt][1];
- break;
- }
- case DOVE_CPU_TO_DDR:
- {
- u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
- SAR_DOVE_DDR_RATIO_MASK;
- *mult = dove_cpu_ddr_ratios[opt][0];
- *div = dove_cpu_ddr_ratios[opt][1];
- break;
- }
- }
-}
-
-static const struct core_clocks dove_core_clocks = {
- .get_tclk_freq = dove_get_tclk_freq,
- .get_cpu_freq = dove_get_cpu_freq,
- .get_clk_ratio = dove_get_clk_ratio,
- .ratios = dove_core_ratios,
- .num_ratios = ARRAY_SIZE(dove_core_ratios),
-};
-#endif /* CONFIG_ARCH_DOVE */
-
-/*
- * Kirkwood PLL sample-at-reset configuration
- * (6180 has different SAR layout than other Kirkwood SoCs)
- *
- * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
- * 4 = 600 MHz
- * 6 = 800 MHz
- * 7 = 1000 MHz
- * 9 = 1200 MHz
- * 12 = 1500 MHz
- * 13 = 1600 MHz
- * 14 = 1800 MHz
- * 15 = 2000 MHz
- * others reserved.
- *
- * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
- * 1 = (1/2) * CPU
- * 3 = (1/3) * CPU
- * 5 = (1/4) * CPU
- * others reserved.
- *
- * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
- * 2 = (1/2) * CPU
- * 4 = (1/3) * CPU
- * 6 = (1/4) * CPU
- * 7 = (2/9) * CPU
- * 8 = (1/5) * CPU
- * 9 = (1/6) * CPU
- * others reserved.
- *
- * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
- * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
- * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
- * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
- * others reserved.
- *
- * SAR0[21] : TCLK frequency
- * 0 = 200 MHz
- * 1 = 166 MHz
- * others reserved.
- */
-#ifdef CONFIG_ARCH_KIRKWOOD
-#define SAR_KIRKWOOD_CPU_FREQ(x) \
- (((x & (1 << 1)) >> 1) | \
- ((x & (1 << 22)) >> 21) | \
- ((x & (3 << 3)) >> 1))
-#define SAR_KIRKWOOD_L2_RATIO(x) \
- (((x & (3 << 9)) >> 9) | \
- (((x & (1 << 19)) >> 17)))
-#define SAR_KIRKWOOD_DDR_RATIO 5
-#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
-#define SAR_MV88F6180_CLK 2
-#define SAR_MV88F6180_CLK_MASK 0x7
-#define SAR_KIRKWOOD_TCLK_FREQ 21
-#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
-
-enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
-
-static const struct core_ratio __initconst kirkwood_core_ratios[] = {
- { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
- { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
- SAR_KIRKWOOD_TCLK_FREQ_MASK;
- return (opt) ? 166666667 : 200000000;
-}
-
-static const u32 __initconst kirkwood_cpu_frequencies[] = {
- 0, 0, 0, 0,
- 600000000,
- 0,
- 800000000,
- 1000000000,
- 0,
- 1200000000,
- 0, 0,
- 1500000000,
- 1600000000,
- 1800000000,
- 2000000000
-};
-
-static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
-{
- u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
- return kirkwood_cpu_frequencies[opt];
-}
-
-static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
- { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
- { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
-};
-
-static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
- { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
- { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
- { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
- { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
-};
-
-static void __init kirkwood_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case KIRKWOOD_CPU_TO_L2:
- {
- u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
- *mult = kirkwood_cpu_l2_ratios[opt][0];
- *div = kirkwood_cpu_l2_ratios[opt][1];
- break;
- }
- case KIRKWOOD_CPU_TO_DDR:
- {
- u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
- SAR_KIRKWOOD_DDR_RATIO_MASK;
- *mult = kirkwood_cpu_ddr_ratios[opt][0];
- *div = kirkwood_cpu_ddr_ratios[opt][1];
- break;
- }
- }
-}
-
-static const struct core_clocks kirkwood_core_clocks = {
- .get_tclk_freq = kirkwood_get_tclk_freq,
- .get_cpu_freq = kirkwood_get_cpu_freq,
- .get_clk_ratio = kirkwood_get_clk_ratio,
- .ratios = kirkwood_core_ratios,
- .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-
-static const u32 __initconst mv88f6180_cpu_frequencies[] = {
- 0, 0, 0, 0, 0,
- 600000000,
- 800000000,
- 1000000000
-};
-
-static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
- return mv88f6180_cpu_frequencies[opt];
-}
-
-static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
- { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
- { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
-};
-
-static void __init mv88f6180_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case KIRKWOOD_CPU_TO_L2:
- {
- /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
- *mult = 1;
- *div = 2;
- break;
- }
- case KIRKWOOD_CPU_TO_DDR:
- {
- u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
- SAR_MV88F6180_CLK_MASK;
- *mult = mv88f6180_cpu_ddr_ratios[opt][0];
- *div = mv88f6180_cpu_ddr_ratios[opt][1];
- break;
- }
- }
-}
-
-static const struct core_clocks mv88f6180_core_clocks = {
- .get_tclk_freq = kirkwood_get_tclk_freq,
- .get_cpu_freq = mv88f6180_get_cpu_freq,
- .get_clk_ratio = mv88f6180_get_clk_ratio,
- .ratios = kirkwood_core_ratios,
- .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-#endif /* CONFIG_ARCH_KIRKWOOD */
-
-static const __initdata struct of_device_id clk_core_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370_XP
- {
- .compatible = "marvell,armada-370-core-clock",
- .data = &armada_370_core_clocks,
- },
- {
- .compatible = "marvell,armada-xp-core-clock",
- .data = &armada_xp_core_clocks,
- },
-#endif
-#ifdef CONFIG_ARCH_DOVE
- {
- .compatible = "marvell,dove-core-clock",
- .data = &dove_core_clocks,
- },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
- {
- .compatible = "marvell,kirkwood-core-clock",
- .data = &kirkwood_core_clocks,
- },
- {
- .compatible = "marvell,mv88f6180-core-clock",
- .data = &mv88f6180_core_clocks,
- },
-#endif
-
- { }
-};
-
-void __init mvebu_core_clk_init(void)
-{
- struct device_node *np;
-
- for_each_matching_node(np, clk_core_match) {
- const struct of_device_id *match =
- of_match_node(clk_core_match, np);
- mvebu_clk_core_setup(np, (struct core_clocks *)match->data);
- }
-}
diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h
deleted file mode 100644
index 28b5e02..0000000
--- a/drivers/clk/mvebu/clk-core.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_CORE_H
-#define __MVEBU_CLK_CORE_H
-
-void __init mvebu_core_clk_init(void);
-
-#endif
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
deleted file mode 100644
index a88e09b..0000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Marvell MVEBU clock gating control.
- *
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-struct mvebu_gating_ctrl {
- spinlock_t lock;
- struct clk **gates;
- int num_gates;
-};
-
-struct mvebu_soc_descr {
- const char *name;
- const char *parent;
- int bit_idx;
- unsigned long flags;
-};
-
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
-
-static struct clk *mvebu_clk_gating_get_src(
- struct of_phandle_args *clkspec, void *data)
-{
- struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data;
- int n;
-
- if (clkspec->args_count < 1)
- return ERR_PTR(-EINVAL);
-
- for (n = 0; n < ctrl->num_gates; n++) {
- struct clk_gate *gate =
- to_clk_gate(__clk_get_hw(ctrl->gates[n]));
- if (clkspec->args[0] == gate->bit_idx)
- return ctrl->gates[n];
- }
- return ERR_PTR(-ENODEV);
-}
-
-static void __init mvebu_clk_gating_setup(
- struct device_node *np, const struct mvebu_soc_descr *descr)
-{
- struct mvebu_gating_ctrl *ctrl;
- struct clk *clk;
- void __iomem *base;
- const char *default_parent = NULL;
- int n;
-
- base = of_iomap(np, 0);
-
- clk = of_clk_get(np, 0);
- if (!IS_ERR(clk)) {
- default_parent = __clk_get_name(clk);
- clk_put(clk);
- }
-
- ctrl = kzalloc(sizeof(struct mvebu_gating_ctrl), GFP_KERNEL);
- if (WARN_ON(!ctrl))
- return;
-
- spin_lock_init(&ctrl->lock);
-
- /*
- * Count, allocate, and register clock gates
- */
- for (n = 0; descr[n].name;)
- n++;
-
- ctrl->num_gates = n;
- ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
- GFP_KERNEL);
- if (WARN_ON(!ctrl->gates)) {
- kfree(ctrl);
- return;
- }
-
- for (n = 0; n < ctrl->num_gates; n++) {
- const char *parent =
- (descr[n].parent) ? descr[n].parent : default_parent;
- ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
- descr[n].flags, base, descr[n].bit_idx,
- 0, &ctrl->lock);
- WARN_ON(IS_ERR(ctrl->gates[n]));
- }
- of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
-}
-
-/*
- * SoC specific clock gating control
- */
-
-#ifdef CONFIG_MACH_ARMADA_370
-static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
- { "audio", NULL, 0, 0 },
- { "pex0_en", NULL, 1, 0 },
- { "pex1_en", NULL, 2, 0 },
- { "ge1", NULL, 3, 0 },
- { "ge0", NULL, 4, 0 },
- { "pex0", NULL, 5, 0 },
- { "pex1", NULL, 9, 0 },
- { "sata0", NULL, 15, 0 },
- { "sdio", NULL, 17, 0 },
- { "tdm", NULL, 25, 0 },
- { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
- { "sata1", NULL, 30, 0 },
- { }
-};
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
-static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
- { "audio", NULL, 0, 0 },
- { "ge3", NULL, 1, 0 },
- { "ge2", NULL, 2, 0 },
- { "ge1", NULL, 3, 0 },
- { "ge0", NULL, 4, 0 },
- { "pex0", NULL, 5, 0 },
- { "pex1", NULL, 6, 0 },
- { "pex2", NULL, 7, 0 },
- { "pex3", NULL, 8, 0 },
- { "bp", NULL, 13, 0 },
- { "sata0lnk", NULL, 14, 0 },
- { "sata0", "sata0lnk", 15, 0 },
- { "lcd", NULL, 16, 0 },
- { "sdio", NULL, 17, 0 },
- { "usb0", NULL, 18, 0 },
- { "usb1", NULL, 19, 0 },
- { "usb2", NULL, 20, 0 },
- { "xor0", NULL, 22, 0 },
- { "crypto", NULL, 23, 0 },
- { "tdm", NULL, 25, 0 },
- { "xor1", NULL, 28, 0 },
- { "sata1lnk", NULL, 29, 0 },
- { "sata1", "sata1lnk", 30, 0 },
- { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
-static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
- { "usb0", NULL, 0, 0 },
- { "usb1", NULL, 1, 0 },
- { "ge", "gephy", 2, 0 },
- { "sata", NULL, 3, 0 },
- { "pex0", NULL, 4, 0 },
- { "pex1", NULL, 5, 0 },
- { "sdio0", NULL, 8, 0 },
- { "sdio1", NULL, 9, 0 },
- { "nand", NULL, 10, 0 },
- { "camera", NULL, 11, 0 },
- { "i2s0", NULL, 12, 0 },
- { "i2s1", NULL, 13, 0 },
- { "crypto", NULL, 15, 0 },
- { "ac97", NULL, 21, 0 },
- { "pdma", NULL, 22, 0 },
- { "xor0", NULL, 23, 0 },
- { "xor1", NULL, 24, 0 },
- { "gephy", NULL, 30, 0 },
- { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
- { "ge0", NULL, 0, 0 },
- { "pex0", NULL, 2, 0 },
- { "usb0", NULL, 3, 0 },
- { "sdio", NULL, 4, 0 },
- { "tsu", NULL, 5, 0 },
- { "runit", NULL, 7, 0 },
- { "xor0", NULL, 8, 0 },
- { "audio", NULL, 9, 0 },
- { "powersave", "cpuclk", 11, 0 },
- { "sata0", NULL, 14, 0 },
- { "sata1", NULL, 15, 0 },
- { "xor1", NULL, 16, 0 },
- { "crypto", NULL, 17, 0 },
- { "pex1", NULL, 18, 0 },
- { "ge1", NULL, 19, 0 },
- { "tdm", NULL, 20, 0 },
- { }
-};
-#endif
-
-static const __initdata struct of_device_id clk_gating_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370
- {
- .compatible = "marvell,armada-370-gating-clock",
- .data = armada_370_gating_descr,
- },
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
- {
- .compatible = "marvell,armada-xp-gating-clock",
- .data = armada_xp_gating_descr,
- },
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
- {
- .compatible = "marvell,dove-gating-clock",
- .data = dove_gating_descr,
- },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
- {
- .compatible = "marvell,kirkwood-gating-clock",
- .data = kirkwood_gating_descr,
- },
-#endif
-
- { }
-};
-
-void __init mvebu_gating_clk_init(void)
-{
- struct device_node *np;
-
- for_each_matching_node(np, clk_gating_match) {
- const struct of_device_id *match =
- of_match_node(clk_gating_match, np);
- mvebu_clk_gating_setup(np,
- (const struct mvebu_soc_descr *)match->data);
- }
-}
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.h b/drivers/clk/mvebu/clk-gating-ctrl.h
deleted file mode 100644
index 9275d1e..0000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Marvell EBU gating clock handling
- *
- * Copyright (C) 2012 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_GATING_H
-#define __MVEBU_CLK_GATING_H
-
-#ifdef CONFIG_MVEBU_CLK_GATING
-void __init mvebu_gating_clk_init(void);
-#else
-void mvebu_gating_clk_init(void) {}
-#endif
-
-#endif
diff --git a/drivers/clk/mvebu/clk.c b/drivers/clk/mvebu/clk.c
deleted file mode 100644
index 29f10fb..0000000
--- a/drivers/clk/mvebu/clk.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Marvell EBU SoC clock handling.
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include "clk-core.h"
-#include "clk-gating-ctrl.h"
-
-void __init mvebu_clocks_init(void)
-{
- mvebu_core_clk_init();
- mvebu_gating_clk_init();
- of_clk_init(NULL);
-}
diff --git a/include/linux/clk/mvebu.h b/include/linux/clk/mvebu.h
deleted file mode 100644
index 8c4ae71..0000000
--- a/include/linux/clk/mvebu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __CLK_MVEBU_H_
-#define __CLK_MVEBU_H_
-
-void __init mvebu_clocks_init(void);
-
-#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 10/10] clk: mvebu: desintegrate obsolete file
@ 2013-05-11 1:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-11 1:08 UTC (permalink / raw)
To: linux-arm-kernel
Switch from function-centric to soc-centric clock drivers now makes
a bunch of files obsolete. This deletes all files and Kconfig options
that are not required anymore.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/clk/mvebu/Kconfig | 10 +-
drivers/clk/mvebu/Makefile | 2 -
drivers/clk/mvebu/clk-core.c | 675 -----------------------------------
drivers/clk/mvebu/clk-core.h | 18 -
drivers/clk/mvebu/clk-gating-ctrl.c | 241 -------------
drivers/clk/mvebu/clk-gating-ctrl.h | 22 --
drivers/clk/mvebu/clk.c | 23 --
include/linux/clk/mvebu.h | 22 --
8 files changed, 2 insertions(+), 1011 deletions(-)
delete mode 100644 drivers/clk/mvebu/clk-core.c
delete mode 100644 drivers/clk/mvebu/clk-core.h
delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
delete mode 100644 drivers/clk/mvebu/clk.c
delete mode 100644 include/linux/clk/mvebu.h
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 8740d34..0b0f3e7 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -1,13 +1,7 @@
-config MVEBU_CLK_CORE
- bool
+config MVEBU_CLK_COMMON
+ bool
config MVEBU_CLK_CPU
- bool
-
-config MVEBU_CLK_GATING
- bool
-
-config MVEBU_CLK_COMMON
bool
config ARMADA_370_CLK
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 13f3d22..1c7e70c 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,7 +1,5 @@
obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
-obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
-obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c
deleted file mode 100644
index 0a53edb..0000000
--- a/drivers/clk/mvebu/clk-core.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include "clk-core.h"
-
-struct core_ratio {
- int id;
- const char *name;
-};
-
-struct core_clocks {
- u32 (*get_tclk_freq)(void __iomem *sar);
- u32 (*get_cpu_freq)(void __iomem *sar);
- void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
- const struct core_ratio *ratios;
- int num_ratios;
-};
-
-static struct clk_onecell_data clk_data;
-
-static void __init mvebu_clk_core_setup(struct device_node *np,
- struct core_clocks *coreclk)
-{
- const char *tclk_name = "tclk";
- const char *cpuclk_name = "cpuclk";
- void __iomem *base;
- unsigned long rate;
- int n;
-
- base = of_iomap(np, 0);
- if (WARN_ON(!base))
- return;
-
- /*
- * Allocate struct for TCLK, cpu clk, and core ratio clocks
- */
- clk_data.clk_num = 2 + coreclk->num_ratios;
- clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
- GFP_KERNEL);
- if (WARN_ON(!clk_data.clks))
- return;
-
- /*
- * Register TCLK
- */
- of_property_read_string_index(np, "clock-output-names", 0,
- &tclk_name);
- rate = coreclk->get_tclk_freq(base);
- clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
- CLK_IS_ROOT, rate);
- WARN_ON(IS_ERR(clk_data.clks[0]));
-
- /*
- * Register CPU clock
- */
- of_property_read_string_index(np, "clock-output-names", 1,
- &cpuclk_name);
- rate = coreclk->get_cpu_freq(base);
- clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
- CLK_IS_ROOT, rate);
- WARN_ON(IS_ERR(clk_data.clks[1]));
-
- /*
- * Register fixed-factor clocks derived from CPU clock
- */
- for (n = 0; n < coreclk->num_ratios; n++) {
- const char *rclk_name = coreclk->ratios[n].name;
- int mult, div;
-
- of_property_read_string_index(np, "clock-output-names",
- 2+n, &rclk_name);
- coreclk->get_clk_ratio(base, coreclk->ratios[n].id,
- &mult, &div);
- clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
- cpuclk_name, 0, mult, div);
- WARN_ON(IS_ERR(clk_data.clks[2+n]));
- };
-
- /*
- * SAR register isn't needed anymore
- */
- iounmap(base);
-
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
-
-#ifdef CONFIG_MACH_ARMADA_370_XP
-/*
- * Armada 370/XP Sample At Reset is a 64 bit bitfiled split in two
- * register of 32 bits
- */
-
-#define SARL 0 /* Low part [0:31] */
-#define SARL_AXP_PCLK_FREQ_OPT 21
-#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
-#define SARL_A370_PCLK_FREQ_OPT 11
-#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
-#define SARL_AXP_FAB_FREQ_OPT 24
-#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
-#define SARL_A370_FAB_FREQ_OPT 15
-#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
-#define SARL_A370_TCLK_FREQ_OPT 20
-#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
-#define SARH 4 /* High part [32:63] */
-#define SARH_AXP_PCLK_FREQ_OPT (52-32)
-#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
-#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
-#define SARH_AXP_FAB_FREQ_OPT (51-32)
-#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
-#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
-
-static const u32 __initconst armada_370_tclk_frequencies[] = {
- 16600000,
- 20000000,
-};
-
-static u32 __init armada_370_get_tclk_freq(void __iomem *sar)
-{
- u8 tclk_freq_select = 0;
-
- tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
- SARL_A370_TCLK_FREQ_OPT_MASK);
- return armada_370_tclk_frequencies[tclk_freq_select];
-}
-
-static const u32 __initconst armada_370_cpu_frequencies[] = {
- 400000000,
- 533000000,
- 667000000,
- 800000000,
- 1000000000,
- 1067000000,
- 1200000000,
-};
-
-static u32 __init armada_370_get_cpu_freq(void __iomem *sar)
-{
- u32 cpu_freq;
- u8 cpu_freq_select = 0;
-
- cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
- SARL_A370_PCLK_FREQ_OPT_MASK);
- if (cpu_freq_select >= ARRAY_SIZE(armada_370_cpu_frequencies)) {
- pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
- cpu_freq = 0;
- } else
- cpu_freq = armada_370_cpu_frequencies[cpu_freq_select];
-
- return cpu_freq;
-}
-
-enum { A370_XP_NBCLK, A370_XP_HCLK, A370_XP_DRAMCLK };
-
-static const struct core_ratio __initconst armada_370_xp_core_ratios[] = {
- { .id = A370_XP_NBCLK, .name = "nbclk" },
- { .id = A370_XP_HCLK, .name = "hclk" },
- { .id = A370_XP_DRAMCLK, .name = "dramclk" },
-};
-
-static const int __initconst armada_370_xp_nbclk_ratios[32][2] = {
- {0, 1}, {1, 2}, {2, 2}, {2, 2},
- {1, 2}, {1, 2}, {1, 1}, {2, 3},
- {0, 1}, {1, 2}, {2, 4}, {0, 1},
- {1, 2}, {0, 1}, {0, 1}, {2, 2},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {2, 3}, {0, 1}, {0, 1}, {0, 1},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_hclk_ratios[32][2] = {
- {0, 1}, {1, 2}, {2, 6}, {2, 3},
- {1, 3}, {1, 4}, {1, 2}, {2, 6},
- {0, 1}, {1, 6}, {2, 10}, {0, 1},
- {1, 4}, {0, 1}, {0, 1}, {2, 5},
- {0, 1}, {0, 1}, {0, 1}, {1, 2},
- {2, 6}, {0, 1}, {0, 1}, {0, 1},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_dramclk_ratios[32][2] = {
- {0, 1}, {1, 2}, {2, 3}, {2, 3},
- {1, 3}, {1, 2}, {1, 2}, {2, 6},
- {0, 1}, {1, 3}, {2, 5}, {0, 1},
- {1, 4}, {0, 1}, {0, 1}, {2, 5},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {2, 3}, {0, 1}, {0, 1}, {0, 1},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static void __init armada_370_xp_get_clk_ratio(u32 opt,
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case A370_XP_NBCLK:
- *mult = armada_370_xp_nbclk_ratios[opt][0];
- *div = armada_370_xp_nbclk_ratios[opt][1];
- break;
- case A370_XP_HCLK:
- *mult = armada_370_xp_hclk_ratios[opt][0];
- *div = armada_370_xp_hclk_ratios[opt][1];
- break;
- case A370_XP_DRAMCLK:
- *mult = armada_370_xp_dramclk_ratios[opt][0];
- *div = armada_370_xp_dramclk_ratios[opt][1];
- break;
- }
-}
-
-static void __init armada_370_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
- SARL_A370_FAB_FREQ_OPT_MASK);
-
- armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-
-static const struct core_clocks armada_370_core_clocks = {
- .get_tclk_freq = armada_370_get_tclk_freq,
- .get_cpu_freq = armada_370_get_cpu_freq,
- .get_clk_ratio = armada_370_get_clk_ratio,
- .ratios = armada_370_xp_core_ratios,
- .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-static const u32 __initconst armada_xp_cpu_frequencies[] = {
- 1000000000,
- 1066000000,
- 1200000000,
- 1333000000,
- 1500000000,
- 1666000000,
- 1800000000,
- 2000000000,
- 667000000,
- 0,
- 800000000,
- 1600000000,
-};
-
-/* For Armada XP TCLK frequency is fix: 250MHz */
-static u32 __init armada_xp_get_tclk_freq(void __iomem *sar)
-{
- return 250 * 1000 * 1000;
-}
-
-static u32 __init armada_xp_get_cpu_freq(void __iomem *sar)
-{
- u32 cpu_freq;
- u8 cpu_freq_select = 0;
-
- cpu_freq_select = ((readl(sar) >> SARL_AXP_PCLK_FREQ_OPT) &
- SARL_AXP_PCLK_FREQ_OPT_MASK);
- /*
- * The upper bit is not contiguous to the other ones and
- * located in the high part of the SAR registers
- */
- cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) &
- SARH_AXP_PCLK_FREQ_OPT_MASK)
- << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
- if (cpu_freq_select >= ARRAY_SIZE(armada_xp_cpu_frequencies)) {
- pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
- cpu_freq = 0;
- } else
- cpu_freq = armada_xp_cpu_frequencies[cpu_freq_select];
-
- return cpu_freq;
-}
-
-static void __init armada_xp_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
-
- u32 opt = ((readl(sar) >> SARL_AXP_FAB_FREQ_OPT) &
- SARL_AXP_FAB_FREQ_OPT_MASK);
- /*
- * The upper bit is not contiguous to the other ones and
- * located in the high part of the SAR registers
- */
- opt |= (((readl(sar+4) >> SARH_AXP_FAB_FREQ_OPT) &
- SARH_AXP_FAB_FREQ_OPT_MASK)
- << SARH_AXP_FAB_FREQ_OPT_SHIFT);
-
- armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-static const struct core_clocks armada_xp_core_clocks = {
- .get_tclk_freq = armada_xp_get_tclk_freq,
- .get_cpu_freq = armada_xp_get_cpu_freq,
- .get_clk_ratio = armada_xp_get_clk_ratio,
- .ratios = armada_370_xp_core_ratios,
- .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-#endif /* CONFIG_MACH_ARMADA_370_XP */
-
-/*
- * Dove PLL sample-at-reset configuration
- *
- * SAR0[8:5] : CPU frequency
- * 5 = 1000 MHz
- * 6 = 933 MHz
- * 7 = 933 MHz
- * 8 = 800 MHz
- * 9 = 800 MHz
- * 10 = 800 MHz
- * 11 = 1067 MHz
- * 12 = 667 MHz
- * 13 = 533 MHz
- * 14 = 400 MHz
- * 15 = 333 MHz
- * others reserved.
- *
- * SAR0[11:9] : CPU to L2 Clock divider ratio
- * 0 = (1/1) * CPU
- * 2 = (1/2) * CPU
- * 4 = (1/3) * CPU
- * 6 = (1/4) * CPU
- * others reserved.
- *
- * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
- * 0 = (1/1) * CPU
- * 2 = (1/2) * CPU
- * 3 = (2/5) * CPU
- * 4 = (1/3) * CPU
- * 6 = (1/4) * CPU
- * 8 = (1/5) * CPU
- * 10 = (1/6) * CPU
- * 12 = (1/7) * CPU
- * 14 = (1/8) * CPU
- * 15 = (1/10) * CPU
- * others reserved.
- *
- * SAR0[24:23] : TCLK frequency
- * 0 = 166 MHz
- * 1 = 125 MHz
- * others reserved.
- */
-#ifdef CONFIG_ARCH_DOVE
-#define SAR_DOVE_CPU_FREQ 5
-#define SAR_DOVE_CPU_FREQ_MASK 0xf
-#define SAR_DOVE_L2_RATIO 9
-#define SAR_DOVE_L2_RATIO_MASK 0x7
-#define SAR_DOVE_DDR_RATIO 12
-#define SAR_DOVE_DDR_RATIO_MASK 0xf
-#define SAR_DOVE_TCLK_FREQ 23
-#define SAR_DOVE_TCLK_FREQ_MASK 0x3
-
-static const u32 __initconst dove_tclk_frequencies[] = {
- 166666667,
- 125000000,
- 0, 0
-};
-
-static u32 __init dove_get_tclk_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
- SAR_DOVE_TCLK_FREQ_MASK;
- return dove_tclk_frequencies[opt];
-}
-
-static const u32 __initconst dove_cpu_frequencies[] = {
- 0, 0, 0, 0, 0,
- 1000000000,
- 933333333, 933333333,
- 800000000, 800000000, 800000000,
- 1066666667,
- 666666667,
- 533333333,
- 400000000,
- 333333333
-};
-
-static u32 __init dove_get_cpu_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
- SAR_DOVE_CPU_FREQ_MASK;
- return dove_cpu_frequencies[opt];
-}
-
-enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
-
-static const struct core_ratio __initconst dove_core_ratios[] = {
- { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
- { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static const int __initconst dove_cpu_l2_ratios[8][2] = {
- { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
- { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
-};
-
-static const int __initconst dove_cpu_ddr_ratios[16][2] = {
- { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
- { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
- { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
- { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
-};
-
-static void __init dove_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case DOVE_CPU_TO_L2:
- {
- u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
- SAR_DOVE_L2_RATIO_MASK;
- *mult = dove_cpu_l2_ratios[opt][0];
- *div = dove_cpu_l2_ratios[opt][1];
- break;
- }
- case DOVE_CPU_TO_DDR:
- {
- u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
- SAR_DOVE_DDR_RATIO_MASK;
- *mult = dove_cpu_ddr_ratios[opt][0];
- *div = dove_cpu_ddr_ratios[opt][1];
- break;
- }
- }
-}
-
-static const struct core_clocks dove_core_clocks = {
- .get_tclk_freq = dove_get_tclk_freq,
- .get_cpu_freq = dove_get_cpu_freq,
- .get_clk_ratio = dove_get_clk_ratio,
- .ratios = dove_core_ratios,
- .num_ratios = ARRAY_SIZE(dove_core_ratios),
-};
-#endif /* CONFIG_ARCH_DOVE */
-
-/*
- * Kirkwood PLL sample-at-reset configuration
- * (6180 has different SAR layout than other Kirkwood SoCs)
- *
- * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
- * 4 = 600 MHz
- * 6 = 800 MHz
- * 7 = 1000 MHz
- * 9 = 1200 MHz
- * 12 = 1500 MHz
- * 13 = 1600 MHz
- * 14 = 1800 MHz
- * 15 = 2000 MHz
- * others reserved.
- *
- * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
- * 1 = (1/2) * CPU
- * 3 = (1/3) * CPU
- * 5 = (1/4) * CPU
- * others reserved.
- *
- * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
- * 2 = (1/2) * CPU
- * 4 = (1/3) * CPU
- * 6 = (1/4) * CPU
- * 7 = (2/9) * CPU
- * 8 = (1/5) * CPU
- * 9 = (1/6) * CPU
- * others reserved.
- *
- * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
- * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
- * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
- * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
- * others reserved.
- *
- * SAR0[21] : TCLK frequency
- * 0 = 200 MHz
- * 1 = 166 MHz
- * others reserved.
- */
-#ifdef CONFIG_ARCH_KIRKWOOD
-#define SAR_KIRKWOOD_CPU_FREQ(x) \
- (((x & (1 << 1)) >> 1) | \
- ((x & (1 << 22)) >> 21) | \
- ((x & (3 << 3)) >> 1))
-#define SAR_KIRKWOOD_L2_RATIO(x) \
- (((x & (3 << 9)) >> 9) | \
- (((x & (1 << 19)) >> 17)))
-#define SAR_KIRKWOOD_DDR_RATIO 5
-#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
-#define SAR_MV88F6180_CLK 2
-#define SAR_MV88F6180_CLK_MASK 0x7
-#define SAR_KIRKWOOD_TCLK_FREQ 21
-#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
-
-enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
-
-static const struct core_ratio __initconst kirkwood_core_ratios[] = {
- { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
- { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
- SAR_KIRKWOOD_TCLK_FREQ_MASK;
- return (opt) ? 166666667 : 200000000;
-}
-
-static const u32 __initconst kirkwood_cpu_frequencies[] = {
- 0, 0, 0, 0,
- 600000000,
- 0,
- 800000000,
- 1000000000,
- 0,
- 1200000000,
- 0, 0,
- 1500000000,
- 1600000000,
- 1800000000,
- 2000000000
-};
-
-static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
-{
- u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
- return kirkwood_cpu_frequencies[opt];
-}
-
-static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
- { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
- { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
-};
-
-static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
- { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
- { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
- { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
- { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
-};
-
-static void __init kirkwood_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case KIRKWOOD_CPU_TO_L2:
- {
- u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
- *mult = kirkwood_cpu_l2_ratios[opt][0];
- *div = kirkwood_cpu_l2_ratios[opt][1];
- break;
- }
- case KIRKWOOD_CPU_TO_DDR:
- {
- u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
- SAR_KIRKWOOD_DDR_RATIO_MASK;
- *mult = kirkwood_cpu_ddr_ratios[opt][0];
- *div = kirkwood_cpu_ddr_ratios[opt][1];
- break;
- }
- }
-}
-
-static const struct core_clocks kirkwood_core_clocks = {
- .get_tclk_freq = kirkwood_get_tclk_freq,
- .get_cpu_freq = kirkwood_get_cpu_freq,
- .get_clk_ratio = kirkwood_get_clk_ratio,
- .ratios = kirkwood_core_ratios,
- .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-
-static const u32 __initconst mv88f6180_cpu_frequencies[] = {
- 0, 0, 0, 0, 0,
- 600000000,
- 800000000,
- 1000000000
-};
-
-static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
- return mv88f6180_cpu_frequencies[opt];
-}
-
-static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
- { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
- { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
-};
-
-static void __init mv88f6180_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case KIRKWOOD_CPU_TO_L2:
- {
- /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
- *mult = 1;
- *div = 2;
- break;
- }
- case KIRKWOOD_CPU_TO_DDR:
- {
- u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
- SAR_MV88F6180_CLK_MASK;
- *mult = mv88f6180_cpu_ddr_ratios[opt][0];
- *div = mv88f6180_cpu_ddr_ratios[opt][1];
- break;
- }
- }
-}
-
-static const struct core_clocks mv88f6180_core_clocks = {
- .get_tclk_freq = kirkwood_get_tclk_freq,
- .get_cpu_freq = mv88f6180_get_cpu_freq,
- .get_clk_ratio = mv88f6180_get_clk_ratio,
- .ratios = kirkwood_core_ratios,
- .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-#endif /* CONFIG_ARCH_KIRKWOOD */
-
-static const __initdata struct of_device_id clk_core_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370_XP
- {
- .compatible = "marvell,armada-370-core-clock",
- .data = &armada_370_core_clocks,
- },
- {
- .compatible = "marvell,armada-xp-core-clock",
- .data = &armada_xp_core_clocks,
- },
-#endif
-#ifdef CONFIG_ARCH_DOVE
- {
- .compatible = "marvell,dove-core-clock",
- .data = &dove_core_clocks,
- },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
- {
- .compatible = "marvell,kirkwood-core-clock",
- .data = &kirkwood_core_clocks,
- },
- {
- .compatible = "marvell,mv88f6180-core-clock",
- .data = &mv88f6180_core_clocks,
- },
-#endif
-
- { }
-};
-
-void __init mvebu_core_clk_init(void)
-{
- struct device_node *np;
-
- for_each_matching_node(np, clk_core_match) {
- const struct of_device_id *match =
- of_match_node(clk_core_match, np);
- mvebu_clk_core_setup(np, (struct core_clocks *)match->data);
- }
-}
diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h
deleted file mode 100644
index 28b5e02..0000000
--- a/drivers/clk/mvebu/clk-core.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_CORE_H
-#define __MVEBU_CLK_CORE_H
-
-void __init mvebu_core_clk_init(void);
-
-#endif
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
deleted file mode 100644
index a88e09b..0000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Marvell MVEBU clock gating control.
- *
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-struct mvebu_gating_ctrl {
- spinlock_t lock;
- struct clk **gates;
- int num_gates;
-};
-
-struct mvebu_soc_descr {
- const char *name;
- const char *parent;
- int bit_idx;
- unsigned long flags;
-};
-
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
-
-static struct clk *mvebu_clk_gating_get_src(
- struct of_phandle_args *clkspec, void *data)
-{
- struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data;
- int n;
-
- if (clkspec->args_count < 1)
- return ERR_PTR(-EINVAL);
-
- for (n = 0; n < ctrl->num_gates; n++) {
- struct clk_gate *gate =
- to_clk_gate(__clk_get_hw(ctrl->gates[n]));
- if (clkspec->args[0] == gate->bit_idx)
- return ctrl->gates[n];
- }
- return ERR_PTR(-ENODEV);
-}
-
-static void __init mvebu_clk_gating_setup(
- struct device_node *np, const struct mvebu_soc_descr *descr)
-{
- struct mvebu_gating_ctrl *ctrl;
- struct clk *clk;
- void __iomem *base;
- const char *default_parent = NULL;
- int n;
-
- base = of_iomap(np, 0);
-
- clk = of_clk_get(np, 0);
- if (!IS_ERR(clk)) {
- default_parent = __clk_get_name(clk);
- clk_put(clk);
- }
-
- ctrl = kzalloc(sizeof(struct mvebu_gating_ctrl), GFP_KERNEL);
- if (WARN_ON(!ctrl))
- return;
-
- spin_lock_init(&ctrl->lock);
-
- /*
- * Count, allocate, and register clock gates
- */
- for (n = 0; descr[n].name;)
- n++;
-
- ctrl->num_gates = n;
- ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
- GFP_KERNEL);
- if (WARN_ON(!ctrl->gates)) {
- kfree(ctrl);
- return;
- }
-
- for (n = 0; n < ctrl->num_gates; n++) {
- const char *parent =
- (descr[n].parent) ? descr[n].parent : default_parent;
- ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
- descr[n].flags, base, descr[n].bit_idx,
- 0, &ctrl->lock);
- WARN_ON(IS_ERR(ctrl->gates[n]));
- }
- of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
-}
-
-/*
- * SoC specific clock gating control
- */
-
-#ifdef CONFIG_MACH_ARMADA_370
-static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
- { "audio", NULL, 0, 0 },
- { "pex0_en", NULL, 1, 0 },
- { "pex1_en", NULL, 2, 0 },
- { "ge1", NULL, 3, 0 },
- { "ge0", NULL, 4, 0 },
- { "pex0", NULL, 5, 0 },
- { "pex1", NULL, 9, 0 },
- { "sata0", NULL, 15, 0 },
- { "sdio", NULL, 17, 0 },
- { "tdm", NULL, 25, 0 },
- { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
- { "sata1", NULL, 30, 0 },
- { }
-};
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
-static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
- { "audio", NULL, 0, 0 },
- { "ge3", NULL, 1, 0 },
- { "ge2", NULL, 2, 0 },
- { "ge1", NULL, 3, 0 },
- { "ge0", NULL, 4, 0 },
- { "pex0", NULL, 5, 0 },
- { "pex1", NULL, 6, 0 },
- { "pex2", NULL, 7, 0 },
- { "pex3", NULL, 8, 0 },
- { "bp", NULL, 13, 0 },
- { "sata0lnk", NULL, 14, 0 },
- { "sata0", "sata0lnk", 15, 0 },
- { "lcd", NULL, 16, 0 },
- { "sdio", NULL, 17, 0 },
- { "usb0", NULL, 18, 0 },
- { "usb1", NULL, 19, 0 },
- { "usb2", NULL, 20, 0 },
- { "xor0", NULL, 22, 0 },
- { "crypto", NULL, 23, 0 },
- { "tdm", NULL, 25, 0 },
- { "xor1", NULL, 28, 0 },
- { "sata1lnk", NULL, 29, 0 },
- { "sata1", "sata1lnk", 30, 0 },
- { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
-static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
- { "usb0", NULL, 0, 0 },
- { "usb1", NULL, 1, 0 },
- { "ge", "gephy", 2, 0 },
- { "sata", NULL, 3, 0 },
- { "pex0", NULL, 4, 0 },
- { "pex1", NULL, 5, 0 },
- { "sdio0", NULL, 8, 0 },
- { "sdio1", NULL, 9, 0 },
- { "nand", NULL, 10, 0 },
- { "camera", NULL, 11, 0 },
- { "i2s0", NULL, 12, 0 },
- { "i2s1", NULL, 13, 0 },
- { "crypto", NULL, 15, 0 },
- { "ac97", NULL, 21, 0 },
- { "pdma", NULL, 22, 0 },
- { "xor0", NULL, 23, 0 },
- { "xor1", NULL, 24, 0 },
- { "gephy", NULL, 30, 0 },
- { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
- { "ge0", NULL, 0, 0 },
- { "pex0", NULL, 2, 0 },
- { "usb0", NULL, 3, 0 },
- { "sdio", NULL, 4, 0 },
- { "tsu", NULL, 5, 0 },
- { "runit", NULL, 7, 0 },
- { "xor0", NULL, 8, 0 },
- { "audio", NULL, 9, 0 },
- { "powersave", "cpuclk", 11, 0 },
- { "sata0", NULL, 14, 0 },
- { "sata1", NULL, 15, 0 },
- { "xor1", NULL, 16, 0 },
- { "crypto", NULL, 17, 0 },
- { "pex1", NULL, 18, 0 },
- { "ge1", NULL, 19, 0 },
- { "tdm", NULL, 20, 0 },
- { }
-};
-#endif
-
-static const __initdata struct of_device_id clk_gating_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370
- {
- .compatible = "marvell,armada-370-gating-clock",
- .data = armada_370_gating_descr,
- },
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
- {
- .compatible = "marvell,armada-xp-gating-clock",
- .data = armada_xp_gating_descr,
- },
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
- {
- .compatible = "marvell,dove-gating-clock",
- .data = dove_gating_descr,
- },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
- {
- .compatible = "marvell,kirkwood-gating-clock",
- .data = kirkwood_gating_descr,
- },
-#endif
-
- { }
-};
-
-void __init mvebu_gating_clk_init(void)
-{
- struct device_node *np;
-
- for_each_matching_node(np, clk_gating_match) {
- const struct of_device_id *match =
- of_match_node(clk_gating_match, np);
- mvebu_clk_gating_setup(np,
- (const struct mvebu_soc_descr *)match->data);
- }
-}
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.h b/drivers/clk/mvebu/clk-gating-ctrl.h
deleted file mode 100644
index 9275d1e..0000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Marvell EBU gating clock handling
- *
- * Copyright (C) 2012 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_GATING_H
-#define __MVEBU_CLK_GATING_H
-
-#ifdef CONFIG_MVEBU_CLK_GATING
-void __init mvebu_gating_clk_init(void);
-#else
-void mvebu_gating_clk_init(void) {}
-#endif
-
-#endif
diff --git a/drivers/clk/mvebu/clk.c b/drivers/clk/mvebu/clk.c
deleted file mode 100644
index 29f10fb..0000000
--- a/drivers/clk/mvebu/clk.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Marvell EBU SoC clock handling.
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include "clk-core.h"
-#include "clk-gating-ctrl.h"
-
-void __init mvebu_clocks_init(void)
-{
- mvebu_core_clk_init();
- mvebu_gating_clk_init();
- of_clk_init(NULL);
-}
diff --git a/include/linux/clk/mvebu.h b/include/linux/clk/mvebu.h
deleted file mode 100644
index 8c4ae71..0000000
--- a/include/linux/clk/mvebu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __CLK_MVEBU_H_
-#define __CLK_MVEBU_H_
-
-void __init mvebu_clocks_init(void);
-
-#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-16 16:46 ` Thomas Petazzoni
-1 siblings, 0 replies; 56+ messages in thread
From: Thomas Petazzoni @ 2013-05-16 16:46 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Andrew Lunn, Russell King, Jason Cooper, linux-kernel,
Gregory Clement, Mike Turquette, linux-arm-kernel
Sebastian, Jason, Andrew, Gregory,
On Sat, 11 May 2013 03:08:00 +0200, Sebastian Hesselbarth wrote:
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
>
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
>
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
>
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
>
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
>
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
>
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
>
> Sebastian Hesselbarth (10):
> clk: mvebu: introduce per-clock-gate flags
> clk: mvebu: add common clock functions for core clk and clk gating
> clk: mvebu: add Dove SoC-centric clock init
> clk: mvebu: add Kirkwood SoC-centric clock init
> clk: mvebu: add Armada 370 SoC-centric clock init
> clk: mvebu: add Armada XP SoC-centric clock init
> ARM: dove: move DT boards to SoC-centric clock init
> ARM: kirkwood: move DT boards to SoC-centric clock init
> ARM: mvebu: move DT boards to SoC-centric clock init
> clk: mvebu: desintegrate obsolete file
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
I've tested on Armada 370 DB (after reverting the ARM core patch that
prevents this platform from booting) and the Armada XP DB. Both boards
boot fine, and detect PCIe devices as they should.
There is some conflict between this set of commits and the two commits
that modify the PCIe clocks in my PCIe series. I've pushed a branch at
https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
which has the mvebu PCIe stuff + Sebastian patches on top of it, with
the conflicts resolved. The tricky thing is that since Sebastian is
adding new clock files, and then removing the old ones, it's pretty
easy to "loose" the changes the two PCIe clock patches are doing. The
branch above works on Armada 370/XP, so you can compare the clock files
if needed.
Of course, I'm willing to do another final test once you've done the
merged to confirm that everything is alright.
I haven't done a detailed review of the patches, but I definitely agree
with the principle, and I trust Sebastian for having done the right
thing in here.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-16 16:46 ` Thomas Petazzoni
0 siblings, 0 replies; 56+ messages in thread
From: Thomas Petazzoni @ 2013-05-16 16:46 UTC (permalink / raw)
To: linux-arm-kernel
Sebastian, Jason, Andrew, Gregory,
On Sat, 11 May 2013 03:08:00 +0200, Sebastian Hesselbarth wrote:
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
>
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
>
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
>
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
>
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
>
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
>
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
>
> Sebastian Hesselbarth (10):
> clk: mvebu: introduce per-clock-gate flags
> clk: mvebu: add common clock functions for core clk and clk gating
> clk: mvebu: add Dove SoC-centric clock init
> clk: mvebu: add Kirkwood SoC-centric clock init
> clk: mvebu: add Armada 370 SoC-centric clock init
> clk: mvebu: add Armada XP SoC-centric clock init
> ARM: dove: move DT boards to SoC-centric clock init
> ARM: kirkwood: move DT boards to SoC-centric clock init
> ARM: mvebu: move DT boards to SoC-centric clock init
> clk: mvebu: desintegrate obsolete file
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
I've tested on Armada 370 DB (after reverting the ARM core patch that
prevents this platform from booting) and the Armada XP DB. Both boards
boot fine, and detect PCIe devices as they should.
There is some conflict between this set of commits and the two commits
that modify the PCIe clocks in my PCIe series. I've pushed a branch at
https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
which has the mvebu PCIe stuff + Sebastian patches on top of it, with
the conflicts resolved. The tricky thing is that since Sebastian is
adding new clock files, and then removing the old ones, it's pretty
easy to "loose" the changes the two PCIe clock patches are doing. The
branch above works on Armada 370/XP, so you can compare the clock files
if needed.
Of course, I'm willing to do another final test once you've done the
merged to confirm that everything is alright.
I haven't done a detailed review of the patches, but I definitely agree
with the principle, and I trust Sebastian for having done the right
thing in here.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-19 20:13 ` Jason Cooper
-1 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-19 20:13 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Thomas Petazzoni, Andrew Lunn, Russell King, linux-kernel,
Gregory Clement, Mike Turquette, linux-arm-kernel
Sebastian,
On Sat, May 11, 2013 at 03:08:00AM +0200, Sebastian Hesselbarth wrote:
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
>
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
>
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
>
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
>
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
>
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
>
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
>
> Sebastian Hesselbarth (10):
> clk: mvebu: introduce per-clock-gate flags
> clk: mvebu: add common clock functions for core clk and clk gating
> clk: mvebu: add Dove SoC-centric clock init
> clk: mvebu: add Kirkwood SoC-centric clock init
> clk: mvebu: add Armada 370 SoC-centric clock init
> clk: mvebu: add Armada XP SoC-centric clock init
> ARM: dove: move DT boards to SoC-centric clock init
> ARM: kirkwood: move DT boards to SoC-centric clock init
> ARM: mvebu: move DT boards to SoC-centric clock init
> clk: mvebu: desintegrate obsolete file
>
> arch/arm/mach-dove/Kconfig | 3 +-
> arch/arm/mach-dove/board-dt.c | 3 +-
> arch/arm/mach-dove/common.c | 1 -
> arch/arm/mach-kirkwood/Kconfig | 3 +-
> arch/arm/mach-kirkwood/board-dt.c | 3 +-
> arch/arm/mach-mvebu/Kconfig | 5 +-
> arch/arm/mach-mvebu/armada-370-xp.c | 4 +-
> drivers/clk/mvebu/Kconfig | 25 +-
> drivers/clk/mvebu/Makefile | 8 +-
> drivers/clk/mvebu/armada-370.c | 176 +++++++++
> drivers/clk/mvebu/armada-xp.c | 204 +++++++++++
> drivers/clk/mvebu/clk-core.c | 675 -----------------------------------
> drivers/clk/mvebu/clk-core.h | 18 -
> drivers/clk/mvebu/clk-gating-ctrl.c | 250 -------------
> drivers/clk/mvebu/clk-gating-ctrl.h | 22 --
> drivers/clk/mvebu/clk.c | 23 --
> drivers/clk/mvebu/common.c | 163 +++++++++
> drivers/clk/mvebu/common.h | 48 +++
> drivers/clk/mvebu/dove.c | 194 ++++++++++
> drivers/clk/mvebu/kirkwood.c | 247 +++++++++++++
> include/linux/clk/mvebu.h | 22 --
> 21 files changed, 1066 insertions(+), 1031 deletions(-)
> create mode 100644 drivers/clk/mvebu/armada-370.c
> create mode 100644 drivers/clk/mvebu/armada-xp.c
> delete mode 100644 drivers/clk/mvebu/clk-core.c
> delete mode 100644 drivers/clk/mvebu/clk-core.h
> delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
> delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
> delete mode 100644 drivers/clk/mvebu/clk.c
> create mode 100644 drivers/clk/mvebu/common.c
> create mode 100644 drivers/clk/mvebu/common.h
> create mode 100644 drivers/clk/mvebu/dove.c
> create mode 100644 drivers/clk/mvebu/kirkwood.c
> delete mode 100644 include/linux/clk/mvebu.h
> ---
I've tentatively applied the whole series to mvebu/seb_clk and merged it
into for-next. This will get it a few rounds of testing in linux-next
until Mike has a chance to review it.
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-19 20:13 ` Jason Cooper
0 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-19 20:13 UTC (permalink / raw)
To: linux-arm-kernel
Sebastian,
On Sat, May 11, 2013 at 03:08:00AM +0200, Sebastian Hesselbarth wrote:
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
>
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
>
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
>
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
>
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
>
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
>
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
>
> Sebastian Hesselbarth (10):
> clk: mvebu: introduce per-clock-gate flags
> clk: mvebu: add common clock functions for core clk and clk gating
> clk: mvebu: add Dove SoC-centric clock init
> clk: mvebu: add Kirkwood SoC-centric clock init
> clk: mvebu: add Armada 370 SoC-centric clock init
> clk: mvebu: add Armada XP SoC-centric clock init
> ARM: dove: move DT boards to SoC-centric clock init
> ARM: kirkwood: move DT boards to SoC-centric clock init
> ARM: mvebu: move DT boards to SoC-centric clock init
> clk: mvebu: desintegrate obsolete file
>
> arch/arm/mach-dove/Kconfig | 3 +-
> arch/arm/mach-dove/board-dt.c | 3 +-
> arch/arm/mach-dove/common.c | 1 -
> arch/arm/mach-kirkwood/Kconfig | 3 +-
> arch/arm/mach-kirkwood/board-dt.c | 3 +-
> arch/arm/mach-mvebu/Kconfig | 5 +-
> arch/arm/mach-mvebu/armada-370-xp.c | 4 +-
> drivers/clk/mvebu/Kconfig | 25 +-
> drivers/clk/mvebu/Makefile | 8 +-
> drivers/clk/mvebu/armada-370.c | 176 +++++++++
> drivers/clk/mvebu/armada-xp.c | 204 +++++++++++
> drivers/clk/mvebu/clk-core.c | 675 -----------------------------------
> drivers/clk/mvebu/clk-core.h | 18 -
> drivers/clk/mvebu/clk-gating-ctrl.c | 250 -------------
> drivers/clk/mvebu/clk-gating-ctrl.h | 22 --
> drivers/clk/mvebu/clk.c | 23 --
> drivers/clk/mvebu/common.c | 163 +++++++++
> drivers/clk/mvebu/common.h | 48 +++
> drivers/clk/mvebu/dove.c | 194 ++++++++++
> drivers/clk/mvebu/kirkwood.c | 247 +++++++++++++
> include/linux/clk/mvebu.h | 22 --
> 21 files changed, 1066 insertions(+), 1031 deletions(-)
> create mode 100644 drivers/clk/mvebu/armada-370.c
> create mode 100644 drivers/clk/mvebu/armada-xp.c
> delete mode 100644 drivers/clk/mvebu/clk-core.c
> delete mode 100644 drivers/clk/mvebu/clk-core.h
> delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
> delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
> delete mode 100644 drivers/clk/mvebu/clk.c
> create mode 100644 drivers/clk/mvebu/common.c
> create mode 100644 drivers/clk/mvebu/common.h
> create mode 100644 drivers/clk/mvebu/dove.c
> create mode 100644 drivers/clk/mvebu/kirkwood.c
> delete mode 100644 include/linux/clk/mvebu.h
> ---
I've tentatively applied the whole series to mvebu/seb_clk and merged it
into for-next. This will get it a few rounds of testing in linux-next
until Mike has a chance to review it.
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-16 16:46 ` Thomas Petazzoni
@ 2013-05-20 17:58 ` Jason Cooper
-1 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-20 17:58 UTC (permalink / raw)
To: Thomas Petazzoni
Cc: Sebastian Hesselbarth, Andrew Lunn, Mike Turquette, linux-kernel,
Gregory Clement, Russell King, linux-arm-kernel
On Thu, May 16, 2013 at 06:46:58PM +0200, Thomas Petazzoni wrote:
> Sebastian, Jason, Andrew, Gregory,
>
> On Sat, 11 May 2013 03:08:00 +0200, Sebastian Hesselbarth wrote:
> > Marvell EBU SoCs share some common clock functions that register core
> > clocks or clock gates from SoC specific data. These clock drivers are
> > organized by function and over time the drivers filled up with #ifdefs
> > to separate different SoC specific code.
> >
> > This patch set first adds a new element to clock gate descriptors to
> > allow to pass clk flags per clock gate. (Patch 1)
> >
> > Then it restructures MVEBU clock drivers into common clock setup and
> > SoC specific files and Kconfig options. The driver's init functions
> > are also registered to get called with of_clk_init. (Patches 2, 3-6)
> >
> > It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> > of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
> >
> > Finally, all obsolete files and Kconfig options are removed. (Patch 10)
> >
> > It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> > Armada 370 and XP are compile tested only and should get their Tested-by
> > from Thomas and Gregory, respectively.
> >
> > @Mike: As this only touches MVEBU related code, I suggest to take it
> > all through the corresponding ARM branch.
> >
> > Sebastian Hesselbarth (10):
> > clk: mvebu: introduce per-clock-gate flags
> > clk: mvebu: add common clock functions for core clk and clk gating
> > clk: mvebu: add Dove SoC-centric clock init
> > clk: mvebu: add Kirkwood SoC-centric clock init
> > clk: mvebu: add Armada 370 SoC-centric clock init
> > clk: mvebu: add Armada XP SoC-centric clock init
> > ARM: dove: move DT boards to SoC-centric clock init
> > ARM: kirkwood: move DT boards to SoC-centric clock init
> > ARM: mvebu: move DT boards to SoC-centric clock init
> > clk: mvebu: desintegrate obsolete file
>
> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>
> I've tested on Armada 370 DB (after reverting the ARM core patch that
> prevents this platform from booting) and the Armada XP DB. Both boards
> boot fine, and detect PCIe devices as they should.
>
> There is some conflict between this set of commits and the two commits
> that modify the PCIe clocks in my PCIe series. I've pushed a branch at
> https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
> which has the mvebu PCIe stuff + Sebastian patches on top of it, with
> the conflicts resolved. The tricky thing is that since Sebastian is
> adding new clock files, and then removing the old ones, it's pretty
> easy to "loose" the changes the two PCIe clock patches are doing. The
> branch above works on Armada 370/XP, so you can compare the clock files
> if needed.
hmm, in my haste yesterday, I did this in the opposite order (clk, then
pcie on top). I'm going to reshuffle them because I don't want pcie
depending on and waiting for this clock series to be ready :)
The good news is everything (except kirkwood-pcie, ran out of time) made
it through linux-next! Also, kisskb is now building mvebu_defconfig in
addition to all the other ones.
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-20 17:58 ` Jason Cooper
0 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-20 17:58 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 16, 2013 at 06:46:58PM +0200, Thomas Petazzoni wrote:
> Sebastian, Jason, Andrew, Gregory,
>
> On Sat, 11 May 2013 03:08:00 +0200, Sebastian Hesselbarth wrote:
> > Marvell EBU SoCs share some common clock functions that register core
> > clocks or clock gates from SoC specific data. These clock drivers are
> > organized by function and over time the drivers filled up with #ifdefs
> > to separate different SoC specific code.
> >
> > This patch set first adds a new element to clock gate descriptors to
> > allow to pass clk flags per clock gate. (Patch 1)
> >
> > Then it restructures MVEBU clock drivers into common clock setup and
> > SoC specific files and Kconfig options. The driver's init functions
> > are also registered to get called with of_clk_init. (Patches 2, 3-6)
> >
> > It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> > of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
> >
> > Finally, all obsolete files and Kconfig options are removed. (Patch 10)
> >
> > It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> > Armada 370 and XP are compile tested only and should get their Tested-by
> > from Thomas and Gregory, respectively.
> >
> > @Mike: As this only touches MVEBU related code, I suggest to take it
> > all through the corresponding ARM branch.
> >
> > Sebastian Hesselbarth (10):
> > clk: mvebu: introduce per-clock-gate flags
> > clk: mvebu: add common clock functions for core clk and clk gating
> > clk: mvebu: add Dove SoC-centric clock init
> > clk: mvebu: add Kirkwood SoC-centric clock init
> > clk: mvebu: add Armada 370 SoC-centric clock init
> > clk: mvebu: add Armada XP SoC-centric clock init
> > ARM: dove: move DT boards to SoC-centric clock init
> > ARM: kirkwood: move DT boards to SoC-centric clock init
> > ARM: mvebu: move DT boards to SoC-centric clock init
> > clk: mvebu: desintegrate obsolete file
>
> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>
> I've tested on Armada 370 DB (after reverting the ARM core patch that
> prevents this platform from booting) and the Armada XP DB. Both boards
> boot fine, and detect PCIe devices as they should.
>
> There is some conflict between this set of commits and the two commits
> that modify the PCIe clocks in my PCIe series. I've pushed a branch at
> https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
> which has the mvebu PCIe stuff + Sebastian patches on top of it, with
> the conflicts resolved. The tricky thing is that since Sebastian is
> adding new clock files, and then removing the old ones, it's pretty
> easy to "loose" the changes the two PCIe clock patches are doing. The
> branch above works on Armada 370/XP, so you can compare the clock files
> if needed.
hmm, in my haste yesterday, I did this in the opposite order (clk, then
pcie on top). I'm going to reshuffle them because I don't want pcie
depending on and waiting for this clock series to be ready :)
The good news is everything (except kirkwood-pcie, ran out of time) made
it through linux-next! Also, kisskb is now building mvebu_defconfig in
addition to all the other ones.
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-20 17:58 ` Jason Cooper
@ 2013-05-20 18:15 ` Thomas Petazzoni
-1 siblings, 0 replies; 56+ messages in thread
From: Thomas Petazzoni @ 2013-05-20 18:15 UTC (permalink / raw)
To: Jason Cooper
Cc: Sebastian Hesselbarth, Andrew Lunn, Mike Turquette, linux-kernel,
Gregory Clement, Russell King, linux-arm-kernel
Dear Jason Cooper,
On Mon, 20 May 2013 13:58:27 -0400, Jason Cooper wrote:
> > I've tested on Armada 370 DB (after reverting the ARM core patch
> > that prevents this platform from booting) and the Armada XP DB.
> > Both boards boot fine, and detect PCIe devices as they should.
> >
> > There is some conflict between this set of commits and the two
> > commits that modify the PCIe clocks in my PCIe series. I've pushed
> > a branch at
> > https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
> > which has the mvebu PCIe stuff + Sebastian patches on top of it,
> > with the conflicts resolved. The tricky thing is that since
> > Sebastian is adding new clock files, and then removing the old
> > ones, it's pretty easy to "loose" the changes the two PCIe clock
> > patches are doing. The branch above works on Armada 370/XP, so you
> > can compare the clock files if needed.
>
> hmm, in my haste yesterday, I did this in the opposite order (clk,
> then pcie on top). I'm going to reshuffle them because I don't want
> pcie depending on and waiting for this clock series to be ready :)
Ok. Either way is fine with me, but it's true that chronologically, the
PCIe stuff has been around for way more time than the clk
restructure patches.
> The good news is everything (except kirkwood-pcie, ran out of time)
> made it through linux-next! Also, kisskb is now building
> mvebu_defconfig in addition to all the other ones.
Ok. Gregory can give more details, but I believe we are also building
daily linux-next and Linus master for the mvebu_defconfig.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-20 18:15 ` Thomas Petazzoni
0 siblings, 0 replies; 56+ messages in thread
From: Thomas Petazzoni @ 2013-05-20 18:15 UTC (permalink / raw)
To: linux-arm-kernel
Dear Jason Cooper,
On Mon, 20 May 2013 13:58:27 -0400, Jason Cooper wrote:
> > I've tested on Armada 370 DB (after reverting the ARM core patch
> > that prevents this platform from booting) and the Armada XP DB.
> > Both boards boot fine, and detect PCIe devices as they should.
> >
> > There is some conflict between this set of commits and the two
> > commits that modify the PCIe clocks in my PCIe series. I've pushed
> > a branch at
> > https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
> > which has the mvebu PCIe stuff + Sebastian patches on top of it,
> > with the conflicts resolved. The tricky thing is that since
> > Sebastian is adding new clock files, and then removing the old
> > ones, it's pretty easy to "loose" the changes the two PCIe clock
> > patches are doing. The branch above works on Armada 370/XP, so you
> > can compare the clock files if needed.
>
> hmm, in my haste yesterday, I did this in the opposite order (clk,
> then pcie on top). I'm going to reshuffle them because I don't want
> pcie depending on and waiting for this clock series to be ready :)
Ok. Either way is fine with me, but it's true that chronologically, the
PCIe stuff has been around for way more time than the clk
restructure patches.
> The good news is everything (except kirkwood-pcie, ran out of time)
> made it through linux-next! Also, kisskb is now building
> mvebu_defconfig in addition to all the other ones.
Ok. Gregory can give more details, but I believe we are also building
daily linux-next and Linus master for the mvebu_defconfig.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-20 18:15 ` Thomas Petazzoni
@ 2013-05-20 18:56 ` Gregory CLEMENT
-1 siblings, 0 replies; 56+ messages in thread
From: Gregory CLEMENT @ 2013-05-20 18:56 UTC (permalink / raw)
To: Thomas Petazzoni
Cc: Jason Cooper, Andrew Lunn, Mike Turquette, linux-kernel,
Russell King, linux-arm-kernel, Sebastian Hesselbarth
On 05/20/2013 08:15 PM, Thomas Petazzoni wrote:
> Dear Jason Cooper,
>
> On Mon, 20 May 2013 13:58:27 -0400, Jason Cooper wrote:
>
>>> I've tested on Armada 370 DB (after reverting the ARM core patch
>>> that prevents this platform from booting) and the Armada XP DB.
>>> Both boards boot fine, and detect PCIe devices as they should.
>>>
>>> There is some conflict between this set of commits and the two
>>> commits that modify the PCIe clocks in my PCIe series. I've pushed
>>> a branch at
>>> https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
>>> which has the mvebu PCIe stuff + Sebastian patches on top of it,
>>> with the conflicts resolved. The tricky thing is that since
>>> Sebastian is adding new clock files, and then removing the old
>>> ones, it's pretty easy to "loose" the changes the two PCIe clock
>>> patches are doing. The branch above works on Armada 370/XP, so you
>>> can compare the clock files if needed.
>>
>> hmm, in my haste yesterday, I did this in the opposite order (clk,
>> then pcie on top). I'm going to reshuffle them because I don't want
>> pcie depending on and waiting for this clock series to be ready :)
>
> Ok. Either way is fine with me, but it's true that chronologically, the
> PCIe stuff has been around for way more time than the clk
> restructure patches.
>
>> The good news is everything (except kirkwood-pcie, ran out of time)
>> made it through linux-next! Also, kisskb is now building
>> mvebu_defconfig in addition to all the other ones.
>
> Ok. Gregory can give more details, but I believe we are also building
> daily linux-next and Linus master for the mvebu_defconfig.
Indeed every day we build linux-next for the mvebu_defconfig and for
multi_v7_defconfig (as mvebu is part of it). You can see the status here:
http://jenkins.free-electrons.com/job/linux-next/
However we don't build Linus master but we could add it.
>
> Best regards,
>
> Thomas
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-20 18:56 ` Gregory CLEMENT
0 siblings, 0 replies; 56+ messages in thread
From: Gregory CLEMENT @ 2013-05-20 18:56 UTC (permalink / raw)
To: linux-arm-kernel
On 05/20/2013 08:15 PM, Thomas Petazzoni wrote:
> Dear Jason Cooper,
>
> On Mon, 20 May 2013 13:58:27 -0400, Jason Cooper wrote:
>
>>> I've tested on Armada 370 DB (after reverting the ARM core patch
>>> that prevents this platform from booting) and the Armada XP DB.
>>> Both boards boot fine, and detect PCIe devices as they should.
>>>
>>> There is some conflict between this set of commits and the two
>>> commits that modify the PCIe clocks in my PCIe series. I've pushed
>>> a branch at
>>> https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-v10-and-seb-clks
>>> which has the mvebu PCIe stuff + Sebastian patches on top of it,
>>> with the conflicts resolved. The tricky thing is that since
>>> Sebastian is adding new clock files, and then removing the old
>>> ones, it's pretty easy to "loose" the changes the two PCIe clock
>>> patches are doing. The branch above works on Armada 370/XP, so you
>>> can compare the clock files if needed.
>>
>> hmm, in my haste yesterday, I did this in the opposite order (clk,
>> then pcie on top). I'm going to reshuffle them because I don't want
>> pcie depending on and waiting for this clock series to be ready :)
>
> Ok. Either way is fine with me, but it's true that chronologically, the
> PCIe stuff has been around for way more time than the clk
> restructure patches.
>
>> The good news is everything (except kirkwood-pcie, ran out of time)
>> made it through linux-next! Also, kisskb is now building
>> mvebu_defconfig in addition to all the other ones.
>
> Ok. Gregory can give more details, but I believe we are also building
> daily linux-next and Linus master for the mvebu_defconfig.
Indeed every day we build linux-next for the mvebu_defconfig and for
multi_v7_defconfig (as mvebu is part of it). You can see the status here:
http://jenkins.free-electrons.com/job/linux-next/
However we don't build Linus master but we could add it.
>
> Best regards,
>
> Thomas
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-28 15:40 ` Jason Cooper
-1 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 15:40 UTC (permalink / raw)
To: Sebastian Hesselbarth, Thomas Petazzoni
Cc: Andrew Lunn, Russell King, linux-kernel, Gregory Clement,
Mike Turquette, linux-arm-kernel
Thomas, Sebastian,
In order to avoid losing changes between this series and mvebu/pcie,
I've rebased this series on top of mvebu/pcie and incorporated the
correct conflict resolution into this series. See below...
On Sat, May 11, 2013 at 03:08:00AM +0200, Sebastian Hesselbarth wrote:
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
>
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
>
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
>
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
>
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
>
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
>
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
>
> Sebastian Hesselbarth (10):
> clk: mvebu: introduce per-clock-gate flags
I updated armada_370_gating_descr[] and armada_xp_gating_descr[] to
incorporate Thomas' pcie changes.
> clk: mvebu: add common clock functions for core clk and clk gating
> clk: mvebu: add Dove SoC-centric clock init
> clk: mvebu: add Kirkwood SoC-centric clock init
> clk: mvebu: add Armada 370 SoC-centric clock init
> clk: mvebu: add Armada XP SoC-centric clock init
I then migrated the changes above to these two commits.
> ARM: dove: move DT boards to SoC-centric clock init
> ARM: kirkwood: move DT boards to SoC-centric clock init
> ARM: mvebu: move DT boards to SoC-centric clock init
> clk: mvebu: desintegrate obsolete file
Obviously, the diffstat changed slightly here.
I'm posting the revised version as replies to patches 1, 5 and 6. Please
let me know if I messed it up. I'd like to send the PR for these
shortly.
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-28 15:40 ` Jason Cooper
0 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 15:40 UTC (permalink / raw)
To: linux-arm-kernel
Thomas, Sebastian,
In order to avoid losing changes between this series and mvebu/pcie,
I've rebased this series on top of mvebu/pcie and incorporated the
correct conflict resolution into this series. See below...
On Sat, May 11, 2013 at 03:08:00AM +0200, Sebastian Hesselbarth wrote:
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
>
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
>
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
>
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
>
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
>
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
>
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
>
> Sebastian Hesselbarth (10):
> clk: mvebu: introduce per-clock-gate flags
I updated armada_370_gating_descr[] and armada_xp_gating_descr[] to
incorporate Thomas' pcie changes.
> clk: mvebu: add common clock functions for core clk and clk gating
> clk: mvebu: add Dove SoC-centric clock init
> clk: mvebu: add Kirkwood SoC-centric clock init
> clk: mvebu: add Armada 370 SoC-centric clock init
> clk: mvebu: add Armada XP SoC-centric clock init
I then migrated the changes above to these two commits.
> ARM: dove: move DT boards to SoC-centric clock init
> ARM: kirkwood: move DT boards to SoC-centric clock init
> ARM: mvebu: move DT boards to SoC-centric clock init
> clk: mvebu: desintegrate obsolete file
Obviously, the diffstat changed slightly here.
I'm posting the revised version as replies to patches 1, 5 and 6. Please
let me know if I messed it up. I'd like to send the PR for these
shortly.
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 01/10] clk: mvebu: introduce per-clock-gate flags
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-28 15:44 ` Jason Cooper
-1 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 15:44 UTC (permalink / raw)
To: Sebastian Hesselbarth, Thomas Petazzoni
Cc: Andrew Lunn, Russell King, linux-kernel, Gregory Clement,
Mike Turquette, linux-arm-kernel
Sebastian, Thomas,
On Sat, May 11, 2013 at 03:08:01AM +0200, Sebastian Hesselbarth wrote:
> Clock gates found on MVEBU SoCs get registered by a common function.
> To allow specific SoCs to provide tweaks introduce flags to the clock
> gate descriptor instead of filling up the common function SoC specific
> tweaks.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
> drivers/clk/mvebu/clk-gating-ctrl.c | 153 +++++++++++++++++------------------
> 1 file changed, 72 insertions(+), 81 deletions(-)
Here's the revised version after rebasing onto mvebu/pcie:
--->8-------
commit 12f8ebff609dc9378a8c121e195ccf6984d5e5c6
Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Date: Sat May 11 03:08:01 2013 +0200
clk: mvebu: introduce per-clock-gate flags
Clock gates found on MVEBU SoCs get registered by a common function.
To allow specific SoCs to provide tweaks introduce flags to the clock
gate descriptor instead of filling up the common function SoC specific
tweaks.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index 2f03723..1df6c4e 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -28,6 +28,7 @@ struct mvebu_soc_descr {
const char *name;
const char *parent;
int bit_idx;
+ unsigned long flags;
};
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
@@ -88,21 +89,11 @@ static void __init mvebu_clk_gating_setup(
}
for (n = 0; n < ctrl->num_gates; n++) {
- u8 flags = 0;
const char *parent =
(descr[n].parent) ? descr[n].parent : default_parent;
-
- /*
- * On Armada 370, the DDR clock is a special case: it
- * isn't taken by any driver, but should anyway be
- * kept enabled, so we mark it as IGNORE_UNUSED for
- * now.
- */
- if (!strcmp(descr[n].name, "ddr"))
- flags |= CLK_IGNORE_UNUSED;
-
ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
- flags, base, descr[n].bit_idx, 0, &ctrl->lock);
+ descr[n].flags, base, descr[n].bit_idx,
+ 0, &ctrl->lock);
WARN_ON(IS_ERR(ctrl->gates[n]));
}
of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
@@ -114,99 +105,99 @@ static void __init mvebu_clk_gating_setup(
#ifdef CONFIG_MACH_ARMADA_370
static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
- { "audio", NULL, 0 },
- { "pex0_en", NULL, 1 },
- { "pex1_en", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", "pex0_en", 5 },
- { "pex1", "pex1_en", 9 },
- { "sata0", NULL, 15 },
- { "sdio", NULL, 17 },
- { "tdm", NULL, 25 },
- { "ddr", NULL, 28 },
- { "sata1", NULL, 30 },
+ { "audio", NULL, 0, 0 },
+ { "pex0_en", NULL, 1, 0 },
+ { "pex1_en", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", "pex0_en", 5, 0 },
+ { "pex1", "pex1_en", 9, 0 },
+ { "sata0", NULL, 15, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+ { "sata1", NULL, 30, 0 },
{ }
};
#endif
#ifdef CONFIG_MACH_ARMADA_XP
static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
- { "audio", NULL, 0 },
- { "ge3", NULL, 1 },
- { "ge2", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex00", NULL, 5 },
- { "pex01", NULL, 6 },
- { "pex02", NULL, 7 },
- { "pex03", NULL, 8 },
- { "pex10", NULL, 9 },
- { "pex11", NULL, 10 },
- { "pex12", NULL, 11 },
- { "pex13", NULL, 12 },
- { "bp", NULL, 13 },
- { "sata0lnk", NULL, 14 },
- { "sata0", "sata0lnk", 15 },
- { "lcd", NULL, 16 },
- { "sdio", NULL, 17 },
- { "usb0", NULL, 18 },
- { "usb1", NULL, 19 },
- { "usb2", NULL, 20 },
- { "xor0", NULL, 22 },
- { "crypto", NULL, 23 },
- { "tdm", NULL, 25 },
- { "pex20", NULL, 26 },
- { "pex30", NULL, 27 },
- { "xor1", NULL, 28 },
- { "sata1lnk", NULL, 29 },
- { "sata1", "sata1lnk", 30 },
+ { "audio", NULL, 0, 0 },
+ { "ge3", NULL, 1, 0 },
+ { "ge2", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex00", NULL, 5, 0 },
+ { "pex01", NULL, 6, 0 },
+ { "pex02", NULL, 7, 0 },
+ { "pex03", NULL, 8, 0 },
+ { "pex10", NULL, 9, 0 },
+ { "pex11", NULL, 10, 0 },
+ { "pex12", NULL, 11, 0 },
+ { "pex13", NULL, 12, 0 },
+ { "bp", NULL, 13, 0 },
+ { "sata0lnk", NULL, 14, 0 },
+ { "sata0", "sata0lnk", 15, 0 },
+ { "lcd", NULL, 16, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "usb0", NULL, 18, 0 },
+ { "usb1", NULL, 19, 0 },
+ { "usb2", NULL, 20, 0 },
+ { "xor0", NULL, 22, 0 },
+ { "crypto", NULL, 23, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "pex20", NULL, 26, 0 },
+ { "pex30", NULL, 27, 0 },
+ { "xor1", NULL, 28, 0 },
+ { "sata1lnk", NULL, 29, 0 },
+ { "sata1", "sata1lnk", 30, 0 },
{ }
};
#endif
#ifdef CONFIG_ARCH_DOVE
static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
- { "usb0", NULL, 0 },
- { "usb1", NULL, 1 },
- { "ge", "gephy", 2 },
- { "sata", NULL, 3 },
- { "pex0", NULL, 4 },
- { "pex1", NULL, 5 },
- { "sdio0", NULL, 8 },
- { "sdio1", NULL, 9 },
- { "nand", NULL, 10 },
- { "camera", NULL, 11 },
- { "i2s0", NULL, 12 },
- { "i2s1", NULL, 13 },
- { "crypto", NULL, 15 },
- { "ac97", NULL, 21 },
- { "pdma", NULL, 22 },
- { "xor0", NULL, 23 },
- { "xor1", NULL, 24 },
- { "gephy", NULL, 30 },
+ { "usb0", NULL, 0, 0 },
+ { "usb1", NULL, 1, 0 },
+ { "ge", "gephy", 2, 0 },
+ { "sata", NULL, 3, 0 },
+ { "pex0", NULL, 4, 0 },
+ { "pex1", NULL, 5, 0 },
+ { "sdio0", NULL, 8, 0 },
+ { "sdio1", NULL, 9, 0 },
+ { "nand", NULL, 10, 0 },
+ { "camera", NULL, 11, 0 },
+ { "i2s0", NULL, 12, 0 },
+ { "i2s1", NULL, 13, 0 },
+ { "crypto", NULL, 15, 0 },
+ { "ac97", NULL, 21, 0 },
+ { "pdma", NULL, 22, 0 },
+ { "xor0", NULL, 23, 0 },
+ { "xor1", NULL, 24, 0 },
+ { "gephy", NULL, 30, 0 },
{ }
};
#endif
#ifdef CONFIG_ARCH_KIRKWOOD
static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
- { "ge0", NULL, 0 },
- { "pex0", NULL, 2 },
- { "usb0", NULL, 3 },
- { "sdio", NULL, 4 },
- { "tsu", NULL, 5 },
- { "runit", NULL, 7 },
- { "xor0", NULL, 8 },
- { "audio", NULL, 9 },
- { "powersave", "cpuclk", 11 },
- { "sata0", NULL, 14 },
- { "sata1", NULL, 15 },
- { "xor1", NULL, 16 },
- { "crypto", NULL, 17 },
- { "pex1", NULL, 18 },
- { "ge1", NULL, 19 },
- { "tdm", NULL, 20 },
+ { "ge0", NULL, 0, 0 },
+ { "pex0", NULL, 2, 0 },
+ { "usb0", NULL, 3, 0 },
+ { "sdio", NULL, 4, 0 },
+ { "tsu", NULL, 5, 0 },
+ { "runit", NULL, 7, 0 },
+ { "xor0", NULL, 8, 0 },
+ { "audio", NULL, 9, 0 },
+ { "powersave", "cpuclk", 11, 0 },
+ { "sata0", NULL, 14, 0 },
+ { "sata1", NULL, 15, 0 },
+ { "xor1", NULL, 16, 0 },
+ { "crypto", NULL, 17, 0 },
+ { "pex1", NULL, 18, 0 },
+ { "ge1", NULL, 19, 0 },
+ { "tdm", NULL, 20, 0 },
{ }
};
#endif
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 01/10] clk: mvebu: introduce per-clock-gate flags
@ 2013-05-28 15:44 ` Jason Cooper
0 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 15:44 UTC (permalink / raw)
To: linux-arm-kernel
Sebastian, Thomas,
On Sat, May 11, 2013 at 03:08:01AM +0200, Sebastian Hesselbarth wrote:
> Clock gates found on MVEBU SoCs get registered by a common function.
> To allow specific SoCs to provide tweaks introduce flags to the clock
> gate descriptor instead of filling up the common function SoC specific
> tweaks.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
> drivers/clk/mvebu/clk-gating-ctrl.c | 153 +++++++++++++++++------------------
> 1 file changed, 72 insertions(+), 81 deletions(-)
Here's the revised version after rebasing onto mvebu/pcie:
--->8-------
commit 12f8ebff609dc9378a8c121e195ccf6984d5e5c6
Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Date: Sat May 11 03:08:01 2013 +0200
clk: mvebu: introduce per-clock-gate flags
Clock gates found on MVEBU SoCs get registered by a common function.
To allow specific SoCs to provide tweaks introduce flags to the clock
gate descriptor instead of filling up the common function SoC specific
tweaks.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index 2f03723..1df6c4e 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -28,6 +28,7 @@ struct mvebu_soc_descr {
const char *name;
const char *parent;
int bit_idx;
+ unsigned long flags;
};
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
@@ -88,21 +89,11 @@ static void __init mvebu_clk_gating_setup(
}
for (n = 0; n < ctrl->num_gates; n++) {
- u8 flags = 0;
const char *parent =
(descr[n].parent) ? descr[n].parent : default_parent;
-
- /*
- * On Armada 370, the DDR clock is a special case: it
- * isn't taken by any driver, but should anyway be
- * kept enabled, so we mark it as IGNORE_UNUSED for
- * now.
- */
- if (!strcmp(descr[n].name, "ddr"))
- flags |= CLK_IGNORE_UNUSED;
-
ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
- flags, base, descr[n].bit_idx, 0, &ctrl->lock);
+ descr[n].flags, base, descr[n].bit_idx,
+ 0, &ctrl->lock);
WARN_ON(IS_ERR(ctrl->gates[n]));
}
of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
@@ -114,99 +105,99 @@ static void __init mvebu_clk_gating_setup(
#ifdef CONFIG_MACH_ARMADA_370
static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
- { "audio", NULL, 0 },
- { "pex0_en", NULL, 1 },
- { "pex1_en", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", "pex0_en", 5 },
- { "pex1", "pex1_en", 9 },
- { "sata0", NULL, 15 },
- { "sdio", NULL, 17 },
- { "tdm", NULL, 25 },
- { "ddr", NULL, 28 },
- { "sata1", NULL, 30 },
+ { "audio", NULL, 0, 0 },
+ { "pex0_en", NULL, 1, 0 },
+ { "pex1_en", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", "pex0_en", 5, 0 },
+ { "pex1", "pex1_en", 9, 0 },
+ { "sata0", NULL, 15, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+ { "sata1", NULL, 30, 0 },
{ }
};
#endif
#ifdef CONFIG_MACH_ARMADA_XP
static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
- { "audio", NULL, 0 },
- { "ge3", NULL, 1 },
- { "ge2", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex00", NULL, 5 },
- { "pex01", NULL, 6 },
- { "pex02", NULL, 7 },
- { "pex03", NULL, 8 },
- { "pex10", NULL, 9 },
- { "pex11", NULL, 10 },
- { "pex12", NULL, 11 },
- { "pex13", NULL, 12 },
- { "bp", NULL, 13 },
- { "sata0lnk", NULL, 14 },
- { "sata0", "sata0lnk", 15 },
- { "lcd", NULL, 16 },
- { "sdio", NULL, 17 },
- { "usb0", NULL, 18 },
- { "usb1", NULL, 19 },
- { "usb2", NULL, 20 },
- { "xor0", NULL, 22 },
- { "crypto", NULL, 23 },
- { "tdm", NULL, 25 },
- { "pex20", NULL, 26 },
- { "pex30", NULL, 27 },
- { "xor1", NULL, 28 },
- { "sata1lnk", NULL, 29 },
- { "sata1", "sata1lnk", 30 },
+ { "audio", NULL, 0, 0 },
+ { "ge3", NULL, 1, 0 },
+ { "ge2", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex00", NULL, 5, 0 },
+ { "pex01", NULL, 6, 0 },
+ { "pex02", NULL, 7, 0 },
+ { "pex03", NULL, 8, 0 },
+ { "pex10", NULL, 9, 0 },
+ { "pex11", NULL, 10, 0 },
+ { "pex12", NULL, 11, 0 },
+ { "pex13", NULL, 12, 0 },
+ { "bp", NULL, 13, 0 },
+ { "sata0lnk", NULL, 14, 0 },
+ { "sata0", "sata0lnk", 15, 0 },
+ { "lcd", NULL, 16, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "usb0", NULL, 18, 0 },
+ { "usb1", NULL, 19, 0 },
+ { "usb2", NULL, 20, 0 },
+ { "xor0", NULL, 22, 0 },
+ { "crypto", NULL, 23, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "pex20", NULL, 26, 0 },
+ { "pex30", NULL, 27, 0 },
+ { "xor1", NULL, 28, 0 },
+ { "sata1lnk", NULL, 29, 0 },
+ { "sata1", "sata1lnk", 30, 0 },
{ }
};
#endif
#ifdef CONFIG_ARCH_DOVE
static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
- { "usb0", NULL, 0 },
- { "usb1", NULL, 1 },
- { "ge", "gephy", 2 },
- { "sata", NULL, 3 },
- { "pex0", NULL, 4 },
- { "pex1", NULL, 5 },
- { "sdio0", NULL, 8 },
- { "sdio1", NULL, 9 },
- { "nand", NULL, 10 },
- { "camera", NULL, 11 },
- { "i2s0", NULL, 12 },
- { "i2s1", NULL, 13 },
- { "crypto", NULL, 15 },
- { "ac97", NULL, 21 },
- { "pdma", NULL, 22 },
- { "xor0", NULL, 23 },
- { "xor1", NULL, 24 },
- { "gephy", NULL, 30 },
+ { "usb0", NULL, 0, 0 },
+ { "usb1", NULL, 1, 0 },
+ { "ge", "gephy", 2, 0 },
+ { "sata", NULL, 3, 0 },
+ { "pex0", NULL, 4, 0 },
+ { "pex1", NULL, 5, 0 },
+ { "sdio0", NULL, 8, 0 },
+ { "sdio1", NULL, 9, 0 },
+ { "nand", NULL, 10, 0 },
+ { "camera", NULL, 11, 0 },
+ { "i2s0", NULL, 12, 0 },
+ { "i2s1", NULL, 13, 0 },
+ { "crypto", NULL, 15, 0 },
+ { "ac97", NULL, 21, 0 },
+ { "pdma", NULL, 22, 0 },
+ { "xor0", NULL, 23, 0 },
+ { "xor1", NULL, 24, 0 },
+ { "gephy", NULL, 30, 0 },
{ }
};
#endif
#ifdef CONFIG_ARCH_KIRKWOOD
static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
- { "ge0", NULL, 0 },
- { "pex0", NULL, 2 },
- { "usb0", NULL, 3 },
- { "sdio", NULL, 4 },
- { "tsu", NULL, 5 },
- { "runit", NULL, 7 },
- { "xor0", NULL, 8 },
- { "audio", NULL, 9 },
- { "powersave", "cpuclk", 11 },
- { "sata0", NULL, 14 },
- { "sata1", NULL, 15 },
- { "xor1", NULL, 16 },
- { "crypto", NULL, 17 },
- { "pex1", NULL, 18 },
- { "ge1", NULL, 19 },
- { "tdm", NULL, 20 },
+ { "ge0", NULL, 0, 0 },
+ { "pex0", NULL, 2, 0 },
+ { "usb0", NULL, 3, 0 },
+ { "sdio", NULL, 4, 0 },
+ { "tsu", NULL, 5, 0 },
+ { "runit", NULL, 7, 0 },
+ { "xor0", NULL, 8, 0 },
+ { "audio", NULL, 9, 0 },
+ { "powersave", "cpuclk", 11, 0 },
+ { "sata0", NULL, 14, 0 },
+ { "sata1", NULL, 15, 0 },
+ { "xor1", NULL, 16, 0 },
+ { "crypto", NULL, 17, 0 },
+ { "pex1", NULL, 18, 0 },
+ { "ge1", NULL, 19, 0 },
+ { "tdm", NULL, 20, 0 },
{ }
};
#endif
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [PATCH 05/10] clk: mvebu: add Armada 370 SoC-centric clock init
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-28 15:46 ` Jason Cooper
-1 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 15:46 UTC (permalink / raw)
To: Sebastian Hesselbarth, Thomas Petazzoni
Cc: Andrew Lunn, Russell King, linux-kernel, Gregory Clement,
Mike Turquette, linux-arm-kernel
Sebastian, Thomas,
On Sat, May 11, 2013 at 03:08:05AM +0200, Sebastian Hesselbarth wrote:
> This is moving core clock and clock gating init for Armada 370 to
> its own file and adds a Kconfig option. Also init functions are added
> and declared so they get called on of_clk_init.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
> drivers/clk/mvebu/Kconfig | 5 ++
> drivers/clk/mvebu/Makefile | 1 +
> drivers/clk/mvebu/armada-370.c | 176 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 182 insertions(+)
> create mode 100644 drivers/clk/mvebu/armada-370.c
Here's the revised version after rebasing onto mvebu/pcie:
---->8------
commit 1bc2c25c3cacce0965d38f3ae2ab7571dffa1b6e
Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Date: Sat May 11 03:08:05 2013 +0200
clk: mvebu: add Armada 370 SoC-centric clock init
This is moving core clock and clock gating init for Armada 370 to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 211695c..1daf61e 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -10,6 +10,11 @@ config MVEBU_CLK_GATING
config MVEBU_CLK_COMMON
bool
+config ARMADA_370_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 97d1ab0..367b72c 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
+obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
obj-$(CONFIG_DOVE_CLK) += dove.o
obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
new file mode 100644
index 0000000..079960e
--- /dev/null
+++ b/drivers/clk/mvebu/armada-370.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Armada 370 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_A370_PCLK_FREQ_OPT 11
+#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
+#define SARL_A370_FAB_FREQ_OPT 15
+#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
+#define SARL_A370_TCLK_FREQ_OPT 20
+#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
+
+enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = {
+ { .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = A370_CPU_TO_HCLK, .name = "hclk" },
+ { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+static const u32 __initconst a370_tclk_freqs[] = {
+ 16600000,
+ 20000000,
+};
+
+static u32 __init a370_get_tclk_freq(void __iomem *sar)
+{
+ u8 tclk_freq_select = 0;
+
+ tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
+ SARL_A370_TCLK_FREQ_OPT_MASK);
+ return a370_tclk_freqs[tclk_freq_select];
+}
+
+static const u32 __initconst a370_cpu_freqs[] = {
+ 400000000,
+ 533000000,
+ 667000000,
+ 800000000,
+ 1000000000,
+ 1067000000,
+ 1200000000,
+};
+
+static u32 __init a370_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
+ SARL_A370_PCLK_FREQ_OPT_MASK);
+ if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
+ pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = a370_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst a370_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init a370_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
+ SARL_A370_FAB_FREQ_OPT_MASK);
+
+ switch (id) {
+ case A370_CPU_TO_NBCLK:
+ *mult = a370_nbclk_ratios[opt][0];
+ *div = a370_nbclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_HCLK:
+ *mult = a370_hclk_ratios[opt][0];
+ *div = a370_hclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_DRAMCLK:
+ *mult = a370_dramclk_ratios[opt][0];
+ *div = a370_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc a370_coreclks = {
+ .get_tclk_freq = a370_get_tclk_freq,
+ .get_cpu_freq = a370_get_cpu_freq,
+ .get_clk_ratio = a370_get_clk_ratio,
+ .ratios = a370_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
+};
+
+static void __init a370_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &a370_coreclks);
+}
+CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
+ a370_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "pex0_en", NULL, 1, 0 },
+ { "pex1_en", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", "pex0_en", 5, 0 },
+ { "pex1", "pex1_en", 9, 0 },
+ { "sata0", NULL, 15, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+ { "sata1", NULL, 30, 0 },
+ { }
+};
+
+static void __init a370_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, a370_gating_desc);
+}
+CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
+ a370_clk_gating_init);
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 05/10] clk: mvebu: add Armada 370 SoC-centric clock init
@ 2013-05-28 15:46 ` Jason Cooper
0 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 15:46 UTC (permalink / raw)
To: linux-arm-kernel
Sebastian, Thomas,
On Sat, May 11, 2013 at 03:08:05AM +0200, Sebastian Hesselbarth wrote:
> This is moving core clock and clock gating init for Armada 370 to
> its own file and adds a Kconfig option. Also init functions are added
> and declared so they get called on of_clk_init.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
> drivers/clk/mvebu/Kconfig | 5 ++
> drivers/clk/mvebu/Makefile | 1 +
> drivers/clk/mvebu/armada-370.c | 176 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 182 insertions(+)
> create mode 100644 drivers/clk/mvebu/armada-370.c
Here's the revised version after rebasing onto mvebu/pcie:
---->8------
commit 1bc2c25c3cacce0965d38f3ae2ab7571dffa1b6e
Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Date: Sat May 11 03:08:05 2013 +0200
clk: mvebu: add Armada 370 SoC-centric clock init
This is moving core clock and clock gating init for Armada 370 to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 211695c..1daf61e 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -10,6 +10,11 @@ config MVEBU_CLK_GATING
config MVEBU_CLK_COMMON
bool
+config ARMADA_370_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 97d1ab0..367b72c 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
+obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
obj-$(CONFIG_DOVE_CLK) += dove.o
obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
new file mode 100644
index 0000000..079960e
--- /dev/null
+++ b/drivers/clk/mvebu/armada-370.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Armada 370 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_A370_PCLK_FREQ_OPT 11
+#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
+#define SARL_A370_FAB_FREQ_OPT 15
+#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
+#define SARL_A370_TCLK_FREQ_OPT 20
+#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
+
+enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = {
+ { .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = A370_CPU_TO_HCLK, .name = "hclk" },
+ { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+static const u32 __initconst a370_tclk_freqs[] = {
+ 16600000,
+ 20000000,
+};
+
+static u32 __init a370_get_tclk_freq(void __iomem *sar)
+{
+ u8 tclk_freq_select = 0;
+
+ tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
+ SARL_A370_TCLK_FREQ_OPT_MASK);
+ return a370_tclk_freqs[tclk_freq_select];
+}
+
+static const u32 __initconst a370_cpu_freqs[] = {
+ 400000000,
+ 533000000,
+ 667000000,
+ 800000000,
+ 1000000000,
+ 1067000000,
+ 1200000000,
+};
+
+static u32 __init a370_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
+ SARL_A370_PCLK_FREQ_OPT_MASK);
+ if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
+ pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = a370_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst a370_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init a370_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
+ SARL_A370_FAB_FREQ_OPT_MASK);
+
+ switch (id) {
+ case A370_CPU_TO_NBCLK:
+ *mult = a370_nbclk_ratios[opt][0];
+ *div = a370_nbclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_HCLK:
+ *mult = a370_hclk_ratios[opt][0];
+ *div = a370_hclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_DRAMCLK:
+ *mult = a370_dramclk_ratios[opt][0];
+ *div = a370_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc a370_coreclks = {
+ .get_tclk_freq = a370_get_tclk_freq,
+ .get_cpu_freq = a370_get_cpu_freq,
+ .get_clk_ratio = a370_get_clk_ratio,
+ .ratios = a370_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
+};
+
+static void __init a370_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &a370_coreclks);
+}
+CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
+ a370_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "pex0_en", NULL, 1, 0 },
+ { "pex1_en", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", "pex0_en", 5, 0 },
+ { "pex1", "pex1_en", 9, 0 },
+ { "sata0", NULL, 15, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+ { "sata1", NULL, 30, 0 },
+ { }
+};
+
+static void __init a370_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, a370_gating_desc);
+}
+CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
+ a370_clk_gating_init);
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [PATCH 06/10] clk: mvebu: add Armada XP SoC-centric clock init
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-28 15:48 ` Jason Cooper
-1 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 15:48 UTC (permalink / raw)
To: Sebastian Hesselbarth, Thomas Petazzoni
Cc: Andrew Lunn, Russell King, linux-kernel, Gregory Clement,
Mike Turquette, linux-arm-kernel
Sebastian, Thomas,
On Sat, May 11, 2013 at 03:08:06AM +0200, Sebastian Hesselbarth wrote:
> This is moving core clock and clock gating init for Armada XP to
> its own file and adds a Kconfig option. Also init functions are added
> and declared so they get called on of_clk_init.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
> drivers/clk/mvebu/Kconfig | 5 +
> drivers/clk/mvebu/Makefile | 1 +
> drivers/clk/mvebu/armada-xp.c | 204 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 210 insertions(+)
> create mode 100644 drivers/clk/mvebu/armada-xp.c
Here's the revised version after rebasing onto mvebu/pcie:
---->8------
commit b45bfc9e9893cf1dc80f5eef6b25d66713fbfeb5
Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Date: Sat May 11 03:08:06 2013 +0200
clk: mvebu: add Armada XP SoC-centric clock init
This is moving core clock and clock gating init for Armada XP to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 1daf61e..8740d34 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -15,6 +15,11 @@ config ARMADA_370_CLK
select MVEBU_CLK_COMMON
select MVEBU_CLK_CPU
+config ARMADA_XP_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 367b72c..13f3d22 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
+obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
obj-$(CONFIG_DOVE_CLK) += dove.o
obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
new file mode 100644
index 0000000..13b62ce
--- /dev/null
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -0,0 +1,210 @@
+/*
+ * Marvell Armada XP SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * register of 32 bits
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_AXP_PCLK_FREQ_OPT 21
+#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
+#define SARL_AXP_FAB_FREQ_OPT 24
+#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
+#define SARH 4 /* High part [32:63] */
+#define SARH_AXP_PCLK_FREQ_OPT (52-32)
+#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
+#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
+#define SARH_AXP_FAB_FREQ_OPT (51-32)
+#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
+#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
+
+enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = {
+ { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
+ { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+/* Armada XP TCLK frequency is fixed to 250MHz */
+static u32 __init axp_get_tclk_freq(void __iomem *sar)
+{
+ return 250000000;
+}
+
+static const u32 __initconst axp_cpu_freqs[] = {
+ 1000000000,
+ 1066000000,
+ 1200000000,
+ 1333000000,
+ 1500000000,
+ 1666000000,
+ 1800000000,
+ 2000000000,
+ 667000000,
+ 0,
+ 800000000,
+ 1600000000,
+};
+
+static u32 __init axp_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
+ SARL_AXP_PCLK_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
+ SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+ if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
+ pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = axp_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst axp_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init axp_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
+ SARL_AXP_FAB_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
+ SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+ switch (id) {
+ case AXP_CPU_TO_NBCLK:
+ *mult = axp_nbclk_ratios[opt][0];
+ *div = axp_nbclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_HCLK:
+ *mult = axp_hclk_ratios[opt][0];
+ *div = axp_hclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_DRAMCLK:
+ *mult = axp_dramclk_ratios[opt][0];
+ *div = axp_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc axp_coreclks = {
+ .get_tclk_freq = axp_get_tclk_freq,
+ .get_cpu_freq = axp_get_cpu_freq,
+ .get_clk_ratio = axp_get_clk_ratio,
+ .ratios = axp_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
+};
+
+static void __init axp_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &axp_coreclks);
+}
+CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
+ axp_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "ge3", NULL, 1, 0 },
+ { "ge2", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex00", NULL, 5, 0 },
+ { "pex01", NULL, 6, 0 },
+ { "pex02", NULL, 7, 0 },
+ { "pex03", NULL, 8, 0 },
+ { "pex10", NULL, 9, 0 },
+ { "pex11", NULL, 10, 0 },
+ { "pex12", NULL, 11, 0 },
+ { "pex13", NULL, 12, 0 },
+ { "bp", NULL, 13, 0 },
+ { "sata0lnk", NULL, 14, 0 },
+ { "sata0", "sata0lnk", 15, 0 },
+ { "lcd", NULL, 16, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "usb0", NULL, 18, 0 },
+ { "usb1", NULL, 19, 0 },
+ { "usb2", NULL, 20, 0 },
+ { "xor0", NULL, 22, 0 },
+ { "crypto", NULL, 23, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "pex20", NULL, 26, 0 },
+ { "pex30", NULL, 27, 0 },
+ { "xor1", NULL, 28, 0 },
+ { "sata1lnk", NULL, 29, 0 },
+ { "sata1", "sata1lnk", 30, 0 },
+ { }
+};
+
+static void __init axp_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, axp_gating_desc);
+}
+CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
+ axp_clk_gating_init);
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH 06/10] clk: mvebu: add Armada XP SoC-centric clock init
@ 2013-05-28 15:48 ` Jason Cooper
0 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 15:48 UTC (permalink / raw)
To: linux-arm-kernel
Sebastian, Thomas,
On Sat, May 11, 2013 at 03:08:06AM +0200, Sebastian Hesselbarth wrote:
> This is moving core clock and clock gating init for Armada XP to
> its own file and adds a Kconfig option. Also init functions are added
> and declared so they get called on of_clk_init.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
> drivers/clk/mvebu/Kconfig | 5 +
> drivers/clk/mvebu/Makefile | 1 +
> drivers/clk/mvebu/armada-xp.c | 204 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 210 insertions(+)
> create mode 100644 drivers/clk/mvebu/armada-xp.c
Here's the revised version after rebasing onto mvebu/pcie:
---->8------
commit b45bfc9e9893cf1dc80f5eef6b25d66713fbfeb5
Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Date: Sat May 11 03:08:06 2013 +0200
clk: mvebu: add Armada XP SoC-centric clock init
This is moving core clock and clock gating init for Armada XP to
its own file and adds a Kconfig option. Also init functions are added
and declared so they get called on of_clk_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 1daf61e..8740d34 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -15,6 +15,11 @@ config ARMADA_370_CLK
select MVEBU_CLK_COMMON
select MVEBU_CLK_CPU
+config ARMADA_XP_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
config DOVE_CLK
bool
select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 367b72c..13f3d22 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
+obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
obj-$(CONFIG_DOVE_CLK) += dove.o
obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
new file mode 100644
index 0000000..13b62ce
--- /dev/null
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -0,0 +1,210 @@
+/*
+ * Marvell Armada XP SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * register of 32 bits
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_AXP_PCLK_FREQ_OPT 21
+#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
+#define SARL_AXP_FAB_FREQ_OPT 24
+#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
+#define SARH 4 /* High part [32:63] */
+#define SARH_AXP_PCLK_FREQ_OPT (52-32)
+#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
+#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
+#define SARH_AXP_FAB_FREQ_OPT (51-32)
+#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
+#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
+
+enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = {
+ { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
+ { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+/* Armada XP TCLK frequency is fixed to 250MHz */
+static u32 __init axp_get_tclk_freq(void __iomem *sar)
+{
+ return 250000000;
+}
+
+static const u32 __initconst axp_cpu_freqs[] = {
+ 1000000000,
+ 1066000000,
+ 1200000000,
+ 1333000000,
+ 1500000000,
+ 1666000000,
+ 1800000000,
+ 2000000000,
+ 667000000,
+ 0,
+ 800000000,
+ 1600000000,
+};
+
+static u32 __init axp_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
+ SARL_AXP_PCLK_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
+ SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+ if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
+ pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = axp_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst axp_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init axp_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
+ SARL_AXP_FAB_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
+ SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+ switch (id) {
+ case AXP_CPU_TO_NBCLK:
+ *mult = axp_nbclk_ratios[opt][0];
+ *div = axp_nbclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_HCLK:
+ *mult = axp_hclk_ratios[opt][0];
+ *div = axp_hclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_DRAMCLK:
+ *mult = axp_dramclk_ratios[opt][0];
+ *div = axp_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc axp_coreclks = {
+ .get_tclk_freq = axp_get_tclk_freq,
+ .get_cpu_freq = axp_get_cpu_freq,
+ .get_clk_ratio = axp_get_clk_ratio,
+ .ratios = axp_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
+};
+
+static void __init axp_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &axp_coreclks);
+}
+CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
+ axp_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "ge3", NULL, 1, 0 },
+ { "ge2", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex00", NULL, 5, 0 },
+ { "pex01", NULL, 6, 0 },
+ { "pex02", NULL, 7, 0 },
+ { "pex03", NULL, 8, 0 },
+ { "pex10", NULL, 9, 0 },
+ { "pex11", NULL, 10, 0 },
+ { "pex12", NULL, 11, 0 },
+ { "pex13", NULL, 12, 0 },
+ { "bp", NULL, 13, 0 },
+ { "sata0lnk", NULL, 14, 0 },
+ { "sata0", "sata0lnk", 15, 0 },
+ { "lcd", NULL, 16, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "usb0", NULL, 18, 0 },
+ { "usb1", NULL, 19, 0 },
+ { "usb2", NULL, 20, 0 },
+ { "xor0", NULL, 22, 0 },
+ { "crypto", NULL, 23, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "pex20", NULL, 26, 0 },
+ { "pex30", NULL, 27, 0 },
+ { "xor1", NULL, 28, 0 },
+ { "sata1lnk", NULL, 29, 0 },
+ { "sata1", "sata1lnk", 30, 0 },
+ { }
+};
+
+static void __init axp_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, axp_gating_desc);
+}
+CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
+ axp_clk_gating_init);
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-28 15:40 ` Jason Cooper
@ 2013-05-28 15:53 ` Thomas Petazzoni
-1 siblings, 0 replies; 56+ messages in thread
From: Thomas Petazzoni @ 2013-05-28 15:53 UTC (permalink / raw)
To: Jason Cooper
Cc: Sebastian Hesselbarth, Andrew Lunn, Russell King, linux-kernel,
Gregory Clement, Mike Turquette, linux-arm-kernel
Dear Jason Cooper,
On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
> In order to avoid losing changes between this series and mvebu/pcie,
> I've rebased this series on top of mvebu/pcie and incorporated the
> correct conflict resolution into this series. See below...
Thanks!
> I'm posting the revised version as replies to patches 1, 5 and 6. Please
> let me know if I messed it up. I'd like to send the PR for these
> shortly.
I had a quick look, and it looks good to me. Let me know to which
branch you've pushed this, and the merge order to follow to "rebuild"
something that works, and I'll try to find some time to test it for
real on hardware.
Thanks again!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-28 15:53 ` Thomas Petazzoni
0 siblings, 0 replies; 56+ messages in thread
From: Thomas Petazzoni @ 2013-05-28 15:53 UTC (permalink / raw)
To: linux-arm-kernel
Dear Jason Cooper,
On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
> In order to avoid losing changes between this series and mvebu/pcie,
> I've rebased this series on top of mvebu/pcie and incorporated the
> correct conflict resolution into this series. See below...
Thanks!
> I'm posting the revised version as replies to patches 1, 5 and 6. Please
> let me know if I messed it up. I'd like to send the PR for these
> shortly.
I had a quick look, and it looks good to me. Let me know to which
branch you've pushed this, and the merge order to follow to "rebuild"
something that works, and I'll try to find some time to test it for
real on hardware.
Thanks again!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-28 15:53 ` Thomas Petazzoni
@ 2013-05-28 15:58 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-28 15:58 UTC (permalink / raw)
To: Thomas Petazzoni
Cc: Jason Cooper, Andrew Lunn, Russell King, linux-kernel,
Gregory Clement, Mike Turquette, linux-arm-kernel
On 05/28/13 17:53, Thomas Petazzoni wrote:
> On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
>> I'm posting the revised version as replies to patches 1, 5 and 6. Please
>> let me know if I messed it up. I'd like to send the PR for these
>> shortly.
>
> I had a quick look, and it looks good to me. Let me know to which
> branch you've pushed this, and the merge order to follow to "rebuild"
> something that works, and I'll try to find some time to test it for
> real on hardware.
I also had a visual check of the files, especially clock_gating_descr.
Didn't find a typo. I will also compile and run on Dove and Kirkwood,
but I guess it should be fine.
Thanks for the effort!
Sebastian
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-28 15:58 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-28 15:58 UTC (permalink / raw)
To: linux-arm-kernel
On 05/28/13 17:53, Thomas Petazzoni wrote:
> On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
>> I'm posting the revised version as replies to patches 1, 5 and 6. Please
>> let me know if I messed it up. I'd like to send the PR for these
>> shortly.
>
> I had a quick look, and it looks good to me. Let me know to which
> branch you've pushed this, and the merge order to follow to "rebuild"
> something that works, and I'll try to find some time to test it for
> real on hardware.
I also had a visual check of the files, especially clock_gating_descr.
Didn't find a typo. I will also compile and run on Dove and Kirkwood,
but I guess it should be fine.
Thanks for the effort!
Sebastian
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-28 15:53 ` Thomas Petazzoni
@ 2013-05-28 16:54 ` Jason Cooper
-1 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 16:54 UTC (permalink / raw)
To: Thomas Petazzoni
Cc: Sebastian Hesselbarth, Andrew Lunn, Russell King, linux-kernel,
Gregory Clement, Mike Turquette, linux-arm-kernel
On Tue, May 28, 2013 at 05:53:43PM +0200, Thomas Petazzoni wrote:
> On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
> > I'm posting the revised version as replies to patches 1, 5 and 6. Please
> > let me know if I messed it up. I'd like to send the PR for these
> > shortly.
>
> I had a quick look, and it looks good to me. Let me know to which
> branch you've pushed this, and the merge order to follow to "rebuild"
> something that works, and I'll try to find some time to test it for
> real on hardware.
$ git checkout v3.10-rc3
$ git merge mvebu/of_pci
$ git merge mvebu/pcie
$ git merge mvebu/seb_clk
test away!
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-28 16:54 ` Jason Cooper
0 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 16:54 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, May 28, 2013 at 05:53:43PM +0200, Thomas Petazzoni wrote:
> On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
> > I'm posting the revised version as replies to patches 1, 5 and 6. Please
> > let me know if I messed it up. I'd like to send the PR for these
> > shortly.
>
> I had a quick look, and it looks good to me. Let me know to which
> branch you've pushed this, and the merge order to follow to "rebuild"
> something that works, and I'll try to find some time to test it for
> real on hardware.
$ git checkout v3.10-rc3
$ git merge mvebu/of_pci
$ git merge mvebu/pcie
$ git merge mvebu/seb_clk
test away!
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-28 16:54 ` Jason Cooper
@ 2013-05-28 20:01 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-28 20:01 UTC (permalink / raw)
To: Jason Cooper
Cc: Thomas Petazzoni, Andrew Lunn, Russell King, linux-kernel,
Gregory Clement, Mike Turquette, linux-arm-kernel
On 05/28/2013 06:54 PM, Jason Cooper wrote:
>> On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
>>> I'm posting the revised version as replies to patches 1, 5 and 6. Please
>>> let me know if I messed it up. I'd like to send the PR for these
>>> shortly.
>
> $ git checkout v3.10-rc3
> $ git merge mvebu/of_pci
> $ git merge mvebu/pcie
> $ git merge mvebu/seb_clk
After manually resolving a merge conflict in arch/arm/mach-mvebu/Kconfig
I can see no obvious regression on neither Dove nor Kirkwood.
Sebastian
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-28 20:01 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-28 20:01 UTC (permalink / raw)
To: linux-arm-kernel
On 05/28/2013 06:54 PM, Jason Cooper wrote:
>> On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
>>> I'm posting the revised version as replies to patches 1, 5 and 6. Please
>>> let me know if I messed it up. I'd like to send the PR for these
>>> shortly.
>
> $ git checkout v3.10-rc3
> $ git merge mvebu/of_pci
> $ git merge mvebu/pcie
> $ git merge mvebu/seb_clk
After manually resolving a merge conflict in arch/arm/mach-mvebu/Kconfig
I can see no obvious regression on neither Dove nor Kirkwood.
Sebastian
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-28 20:01 ` Sebastian Hesselbarth
@ 2013-05-28 20:03 ` Jason Cooper
-1 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 20:03 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Thomas Petazzoni, Andrew Lunn, Russell King, linux-kernel,
Gregory Clement, Mike Turquette, linux-arm-kernel
On Tue, May 28, 2013 at 10:01:19PM +0200, Sebastian Hesselbarth wrote:
> On 05/28/2013 06:54 PM, Jason Cooper wrote:
> >>On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
> >>>I'm posting the revised version as replies to patches 1, 5 and 6. Please
> >>>let me know if I messed it up. I'd like to send the PR for these
> >>>shortly.
> >
> >$ git checkout v3.10-rc3
> >$ git merge mvebu/of_pci
> >$ git merge mvebu/pcie
> >$ git merge mvebu/seb_clk
>
> After manually resolving a merge conflict in arch/arm/mach-mvebu/Kconfig
> I can see no obvious regression on neither Dove nor Kirkwood.
Great, thanks, Sebastian!
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-28 20:03 ` Jason Cooper
0 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-28 20:03 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, May 28, 2013 at 10:01:19PM +0200, Sebastian Hesselbarth wrote:
> On 05/28/2013 06:54 PM, Jason Cooper wrote:
> >>On Tue, 28 May 2013 11:40:47 -0400, Jason Cooper wrote:
> >>>I'm posting the revised version as replies to patches 1, 5 and 6. Please
> >>>let me know if I messed it up. I'd like to send the PR for these
> >>>shortly.
> >
> >$ git checkout v3.10-rc3
> >$ git merge mvebu/of_pci
> >$ git merge mvebu/pcie
> >$ git merge mvebu/seb_clk
>
> After manually resolving a merge conflict in arch/arm/mach-mvebu/Kconfig
> I can see no obvious regression on neither Dove nor Kirkwood.
Great, thanks, Sebastian!
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-11 1:08 ` Sebastian Hesselbarth
@ 2013-05-29 19:02 ` Mike Turquette
-1 siblings, 0 replies; 56+ messages in thread
From: Mike Turquette @ 2013-05-29 19:02 UTC (permalink / raw)
To: Sebastian Hesselbarth, Sebastian Hesselbarth
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, linux-arm-kernel, linux-kernel
Quoting Sebastian Hesselbarth (2013-05-10 18:08:00)
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
>
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
>
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
>
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
>
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
>
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
>
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
>
Sebastian,
Sorry for the tardy response. This cleanup looks really good. If it's
not too late:
Acked-by: Mike Turquette <mturquette@linaro.org>
If the branch is already pulled into arm-soc don't worry about the Ack.
Regards,
Mike
> Sebastian Hesselbarth (10):
> clk: mvebu: introduce per-clock-gate flags
> clk: mvebu: add common clock functions for core clk and clk gating
> clk: mvebu: add Dove SoC-centric clock init
> clk: mvebu: add Kirkwood SoC-centric clock init
> clk: mvebu: add Armada 370 SoC-centric clock init
> clk: mvebu: add Armada XP SoC-centric clock init
> ARM: dove: move DT boards to SoC-centric clock init
> ARM: kirkwood: move DT boards to SoC-centric clock init
> ARM: mvebu: move DT boards to SoC-centric clock init
> clk: mvebu: desintegrate obsolete file
>
> arch/arm/mach-dove/Kconfig | 3 +-
> arch/arm/mach-dove/board-dt.c | 3 +-
> arch/arm/mach-dove/common.c | 1 -
> arch/arm/mach-kirkwood/Kconfig | 3 +-
> arch/arm/mach-kirkwood/board-dt.c | 3 +-
> arch/arm/mach-mvebu/Kconfig | 5 +-
> arch/arm/mach-mvebu/armada-370-xp.c | 4 +-
> drivers/clk/mvebu/Kconfig | 25 +-
> drivers/clk/mvebu/Makefile | 8 +-
> drivers/clk/mvebu/armada-370.c | 176 +++++++++
> drivers/clk/mvebu/armada-xp.c | 204 +++++++++++
> drivers/clk/mvebu/clk-core.c | 675 -----------------------------------
> drivers/clk/mvebu/clk-core.h | 18 -
> drivers/clk/mvebu/clk-gating-ctrl.c | 250 -------------
> drivers/clk/mvebu/clk-gating-ctrl.h | 22 --
> drivers/clk/mvebu/clk.c | 23 --
> drivers/clk/mvebu/common.c | 163 +++++++++
> drivers/clk/mvebu/common.h | 48 +++
> drivers/clk/mvebu/dove.c | 194 ++++++++++
> drivers/clk/mvebu/kirkwood.c | 247 +++++++++++++
> include/linux/clk/mvebu.h | 22 --
> 21 files changed, 1066 insertions(+), 1031 deletions(-)
> create mode 100644 drivers/clk/mvebu/armada-370.c
> create mode 100644 drivers/clk/mvebu/armada-xp.c
> delete mode 100644 drivers/clk/mvebu/clk-core.c
> delete mode 100644 drivers/clk/mvebu/clk-core.h
> delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
> delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
> delete mode 100644 drivers/clk/mvebu/clk.c
> create mode 100644 drivers/clk/mvebu/common.c
> create mode 100644 drivers/clk/mvebu/common.h
> create mode 100644 drivers/clk/mvebu/dove.c
> create mode 100644 drivers/clk/mvebu/kirkwood.c
> delete mode 100644 include/linux/clk/mvebu.h
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> --
> 1.7.10.4
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-29 19:02 ` Mike Turquette
0 siblings, 0 replies; 56+ messages in thread
From: Mike Turquette @ 2013-05-29 19:02 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Sebastian Hesselbarth (2013-05-10 18:08:00)
> Marvell EBU SoCs share some common clock functions that register core
> clocks or clock gates from SoC specific data. These clock drivers are
> organized by function and over time the drivers filled up with #ifdefs
> to separate different SoC specific code.
>
> This patch set first adds a new element to clock gate descriptors to
> allow to pass clk flags per clock gate. (Patch 1)
>
> Then it restructures MVEBU clock drivers into common clock setup and
> SoC specific files and Kconfig options. The driver's init functions
> are also registered to get called with of_clk_init. (Patches 2, 3-6)
>
> It then switches Dove, Kirkwood, and Armada 370/XP to make use of
> of_clk_init instead of mvebu_clocks_init. (Patches 7-9)
>
> Finally, all obsolete files and Kconfig options are removed. (Patch 10)
>
> It has been tested on CuBox (Dove) and Dockstar (Kirkwood) by me.
> Armada 370 and XP are compile tested only and should get their Tested-by
> from Thomas and Gregory, respectively.
>
> @Mike: As this only touches MVEBU related code, I suggest to take it
> all through the corresponding ARM branch.
>
Sebastian,
Sorry for the tardy response. This cleanup looks really good. If it's
not too late:
Acked-by: Mike Turquette <mturquette@linaro.org>
If the branch is already pulled into arm-soc don't worry about the Ack.
Regards,
Mike
> Sebastian Hesselbarth (10):
> clk: mvebu: introduce per-clock-gate flags
> clk: mvebu: add common clock functions for core clk and clk gating
> clk: mvebu: add Dove SoC-centric clock init
> clk: mvebu: add Kirkwood SoC-centric clock init
> clk: mvebu: add Armada 370 SoC-centric clock init
> clk: mvebu: add Armada XP SoC-centric clock init
> ARM: dove: move DT boards to SoC-centric clock init
> ARM: kirkwood: move DT boards to SoC-centric clock init
> ARM: mvebu: move DT boards to SoC-centric clock init
> clk: mvebu: desintegrate obsolete file
>
> arch/arm/mach-dove/Kconfig | 3 +-
> arch/arm/mach-dove/board-dt.c | 3 +-
> arch/arm/mach-dove/common.c | 1 -
> arch/arm/mach-kirkwood/Kconfig | 3 +-
> arch/arm/mach-kirkwood/board-dt.c | 3 +-
> arch/arm/mach-mvebu/Kconfig | 5 +-
> arch/arm/mach-mvebu/armada-370-xp.c | 4 +-
> drivers/clk/mvebu/Kconfig | 25 +-
> drivers/clk/mvebu/Makefile | 8 +-
> drivers/clk/mvebu/armada-370.c | 176 +++++++++
> drivers/clk/mvebu/armada-xp.c | 204 +++++++++++
> drivers/clk/mvebu/clk-core.c | 675 -----------------------------------
> drivers/clk/mvebu/clk-core.h | 18 -
> drivers/clk/mvebu/clk-gating-ctrl.c | 250 -------------
> drivers/clk/mvebu/clk-gating-ctrl.h | 22 --
> drivers/clk/mvebu/clk.c | 23 --
> drivers/clk/mvebu/common.c | 163 +++++++++
> drivers/clk/mvebu/common.h | 48 +++
> drivers/clk/mvebu/dove.c | 194 ++++++++++
> drivers/clk/mvebu/kirkwood.c | 247 +++++++++++++
> include/linux/clk/mvebu.h | 22 --
> 21 files changed, 1066 insertions(+), 1031 deletions(-)
> create mode 100644 drivers/clk/mvebu/armada-370.c
> create mode 100644 drivers/clk/mvebu/armada-xp.c
> delete mode 100644 drivers/clk/mvebu/clk-core.c
> delete mode 100644 drivers/clk/mvebu/clk-core.h
> delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
> delete mode 100644 drivers/clk/mvebu/clk-gating-ctrl.h
> delete mode 100644 drivers/clk/mvebu/clk.c
> create mode 100644 drivers/clk/mvebu/common.c
> create mode 100644 drivers/clk/mvebu/common.h
> create mode 100644 drivers/clk/mvebu/dove.c
> create mode 100644 drivers/clk/mvebu/kirkwood.c
> delete mode 100644 include/linux/clk/mvebu.h
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> --
> 1.7.10.4
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-29 19:02 ` Mike Turquette
@ 2013-05-29 19:05 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-29 19:05 UTC (permalink / raw)
To: Mike Turquette
Cc: Jason Cooper, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, linux-arm-kernel, linux-kernel
On 05/29/2013 09:02 PM, Mike Turquette wrote:
> Quoting Sebastian Hesselbarth (2013-05-10 18:08:00)
>> Marvell EBU SoCs share some common clock functions that register core
>> clocks or clock gates from SoC specific data. These clock drivers are
>> organized by function and over time the drivers filled up with #ifdefs
>> to separate different SoC specific code.
>>
...
>> @Mike: As this only touches MVEBU related code, I suggest to take it
>> all through the corresponding ARM branch.
>>
> Sorry for the tardy response. This cleanup looks really good. If it's
> not too late:
>
> Acked-by: Mike Turquette<mturquette@linaro.org>
>
> If the branch is already pulled into arm-soc don't worry about the Ack.
Mike,
thanks for the Ack, the corresponding pull request has been sent some
hours ago by Jason Cooper. It has not been pulled into arm-soc, so it
is just in time ;)
Sebastian
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-29 19:05 ` Sebastian Hesselbarth
0 siblings, 0 replies; 56+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-29 19:05 UTC (permalink / raw)
To: linux-arm-kernel
On 05/29/2013 09:02 PM, Mike Turquette wrote:
> Quoting Sebastian Hesselbarth (2013-05-10 18:08:00)
>> Marvell EBU SoCs share some common clock functions that register core
>> clocks or clock gates from SoC specific data. These clock drivers are
>> organized by function and over time the drivers filled up with #ifdefs
>> to separate different SoC specific code.
>>
...
>> @Mike: As this only touches MVEBU related code, I suggest to take it
>> all through the corresponding ARM branch.
>>
> Sorry for the tardy response. This cleanup looks really good. If it's
> not too late:
>
> Acked-by: Mike Turquette<mturquette@linaro.org>
>
> If the branch is already pulled into arm-soc don't worry about the Ack.
Mike,
thanks for the Ack, the corresponding pull request has been sent some
hours ago by Jason Cooper. It has not been pulled into arm-soc, so it
is just in time ;)
Sebastian
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
2013-05-29 19:05 ` Sebastian Hesselbarth
@ 2013-05-29 19:17 ` Jason Cooper
-1 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-29 19:17 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Mike Turquette, Andrew Lunn, Russell King, Gregory Clement,
Thomas Petazzoni, linux-arm-kernel, linux-kernel
On Wed, May 29, 2013 at 09:05:41PM +0200, Sebastian Hesselbarth wrote:
> On 05/29/2013 09:02 PM, Mike Turquette wrote:
> >Quoting Sebastian Hesselbarth (2013-05-10 18:08:00)
> >>Marvell EBU SoCs share some common clock functions that register core
> >>clocks or clock gates from SoC specific data. These clock drivers are
> >>organized by function and over time the drivers filled up with #ifdefs
> >>to separate different SoC specific code.
> >>
> ...
> >>@Mike: As this only touches MVEBU related code, I suggest to take it
> >>all through the corresponding ARM branch.
> >>
> >Sorry for the tardy response. This cleanup looks really good. If it's
> >not too late:
> >
> >Acked-by: Mike Turquette<mturquette@linaro.org>
> >
> >If the branch is already pulled into arm-soc don't worry about the Ack.
>
> thanks for the Ack, the corresponding pull request has been sent some
> hours ago by Jason Cooper. It has not been pulled into arm-soc, so it
> is just in time ;)
Just talked to Olof, looks like I can squeeze it in ;-)
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 00/10] clk: mvebu: restructure SoC clock drivers
@ 2013-05-29 19:17 ` Jason Cooper
0 siblings, 0 replies; 56+ messages in thread
From: Jason Cooper @ 2013-05-29 19:17 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 29, 2013 at 09:05:41PM +0200, Sebastian Hesselbarth wrote:
> On 05/29/2013 09:02 PM, Mike Turquette wrote:
> >Quoting Sebastian Hesselbarth (2013-05-10 18:08:00)
> >>Marvell EBU SoCs share some common clock functions that register core
> >>clocks or clock gates from SoC specific data. These clock drivers are
> >>organized by function and over time the drivers filled up with #ifdefs
> >>to separate different SoC specific code.
> >>
> ...
> >>@Mike: As this only touches MVEBU related code, I suggest to take it
> >>all through the corresponding ARM branch.
> >>
> >Sorry for the tardy response. This cleanup looks really good. If it's
> >not too late:
> >
> >Acked-by: Mike Turquette<mturquette@linaro.org>
> >
> >If the branch is already pulled into arm-soc don't worry about the Ack.
>
> thanks for the Ack, the corresponding pull request has been sent some
> hours ago by Jason Cooper. It has not been pulled into arm-soc, so it
> is just in time ;)
Just talked to Olof, looks like I can squeeze it in ;-)
thx,
Jason.
^ permalink raw reply [flat|nested] 56+ messages in thread
end of thread, other threads:[~2013-05-29 19:18 UTC | newest]
Thread overview: 56+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-05-11 1:08 [PATCH 00/10] clk: mvebu: restructure SoC clock drivers Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-11 1:08 ` [PATCH 01/10] clk: mvebu: introduce per-clock-gate flags Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-28 15:44 ` Jason Cooper
2013-05-28 15:44 ` Jason Cooper
2013-05-11 1:08 ` [PATCH 02/10] clk: mvebu: add common clock functions for core clk and clk gating Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-11 1:08 ` [PATCH 03/10] clk: mvebu: add Dove SoC-centric clock init Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-11 1:08 ` [PATCH 04/10] clk: mvebu: add Kirkwood " Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-11 1:08 ` [PATCH 05/10] clk: mvebu: add Armada 370 " Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-28 15:46 ` Jason Cooper
2013-05-28 15:46 ` Jason Cooper
2013-05-11 1:08 ` [PATCH 06/10] clk: mvebu: add Armada XP " Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-28 15:48 ` Jason Cooper
2013-05-28 15:48 ` Jason Cooper
2013-05-11 1:08 ` [PATCH 07/10] ARM: dove: move DT boards to " Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-11 1:08 ` [PATCH 08/10] ARM: kirkwood: " Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-11 1:08 ` [PATCH 09/10] ARM: mvebu: " Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-11 1:08 ` [PATCH 10/10] clk: mvebu: desintegrate obsolete file Sebastian Hesselbarth
2013-05-11 1:08 ` Sebastian Hesselbarth
2013-05-16 16:46 ` [PATCH 00/10] clk: mvebu: restructure SoC clock drivers Thomas Petazzoni
2013-05-16 16:46 ` Thomas Petazzoni
2013-05-20 17:58 ` Jason Cooper
2013-05-20 17:58 ` Jason Cooper
2013-05-20 18:15 ` Thomas Petazzoni
2013-05-20 18:15 ` Thomas Petazzoni
2013-05-20 18:56 ` Gregory CLEMENT
2013-05-20 18:56 ` Gregory CLEMENT
2013-05-19 20:13 ` Jason Cooper
2013-05-19 20:13 ` Jason Cooper
2013-05-28 15:40 ` Jason Cooper
2013-05-28 15:40 ` Jason Cooper
2013-05-28 15:53 ` Thomas Petazzoni
2013-05-28 15:53 ` Thomas Petazzoni
2013-05-28 15:58 ` Sebastian Hesselbarth
2013-05-28 15:58 ` Sebastian Hesselbarth
2013-05-28 16:54 ` Jason Cooper
2013-05-28 16:54 ` Jason Cooper
2013-05-28 20:01 ` Sebastian Hesselbarth
2013-05-28 20:01 ` Sebastian Hesselbarth
2013-05-28 20:03 ` Jason Cooper
2013-05-28 20:03 ` Jason Cooper
2013-05-29 19:02 ` Mike Turquette
2013-05-29 19:02 ` Mike Turquette
2013-05-29 19:05 ` Sebastian Hesselbarth
2013-05-29 19:05 ` Sebastian Hesselbarth
2013-05-29 19:17 ` Jason Cooper
2013-05-29 19:17 ` Jason Cooper
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