* [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes.
2013-05-31 21:01 [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes Anson Huang
@ 2013-05-31 10:37 ` Dirk Behme
2013-05-31 23:08 ` Anson Huang
2013-05-31 21:01 ` [PATCH 2/4] ARM: imx: clk-imx6q: per1_bch's parent is wrong Anson Huang
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Dirk Behme @ 2013-05-31 10:37 UTC (permalink / raw)
To: linux-arm-kernel
On 31.05.2013 23:01, Anson Huang wrote:
> Some clock gates are useful when we try to disable them
> to save power, so we need to add these useful clock gate
> into clock tree.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> ---
> .../devicetree/bindings/clock/imx6q-clock.txt | 13 +++++++++++++
> arch/arm/mach-imx/clk-imx6q.c | 17 ++++++++++++++++-
> 2 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> index 6deb6fd..df68f99 100644
> --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> @@ -208,6 +208,19 @@ clocks and IDs.
> pll4_post_div 193
> pll5_post_div 194
> pll5_video_div 195
> + aips_tz1 196
> + aips_tz2 197
> + caam_mem 198
> + caam_aclk 199
> + caam_ipg 200
> + tzasc1 201
> + tzasc2 202
> + vdoa 203
> + mmdc_ch0_ipg 204
> + mmdc_ch1_ipg 205
> + mx6fast1 206
> + per2_main 207
> + emi_slow 208
>
> Examples:
>
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index dda9a2b..dfb77c1 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -238,7 +238,9 @@ enum mx6q_clks {
> pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
> ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
> sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
> - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
> + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, aips_tz1,
> + aips_tz2, caam_mem, caam_aclk, caam_ipg, tzasc1, tzasc2, vdoa, mmdc_ch0_ipg,
> + mmdc_ch1_ipg, mx6fast1, per2_main, emi_slow, clk_max
> };
>
> static struct clk *clk[clk_max];
> @@ -466,8 +468,13 @@ int __init mx6q_clocks_init(void)
> clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
>
> /* name parent_name reg shift */
> + clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
> + clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
> clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
> clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
> + clk[caam_mem] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
> + clk[caam_aclk] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
> + clk[caam_ipg] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
> clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
> clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
> clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
> @@ -490,6 +497,9 @@ int __init mx6q_clocks_init(void)
> clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
> clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
> clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
> + clk[tzasc1] = imx_clk_gate2("tzasc1", "mmdc_ch0_axi_podf", base + 0x70, 22);
> + clk[tzasc2] = imx_clk_gate2("tzasc2", "mmdc_ch0_axi_podf", base + 0x70, 24);
> + clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
> clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
> clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
> clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
> @@ -502,10 +512,14 @@ int __init mx6q_clocks_init(void)
> clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
> clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
> clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
> + clk[mmdc_ch0_ipg] = imx_clk_gate2("mmdc_ch0_ipg", "ipg", base + 0x74, 24);
> + clk[mmdc_ch1_ipg] = imx_clk_gate2("mmdc_ch1_ipg", "ipg", base + 0x74, 26);
> clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
> clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
> clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
> + clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8);
> clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
> + clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
> clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
> clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
> clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
> @@ -528,6 +542,7 @@ int __init mx6q_clocks_init(void)
> clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
> clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
> clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
> + clk[emi_slow] = imx_clk_gate2("emi_slow", "emi_slow_podf", base + 0x80, 10);
> clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
> clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
> clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
I think we have the emi_slow already:
https://git.linaro.org/gitweb?p=people/shawnguo/linux-2.6.git;a=commitdiff;h=5e569c675297733dec9f5b65aed3fe694c6e6975
Best regards
Dirk
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes.
2013-05-31 10:37 ` Dirk Behme
@ 2013-05-31 23:08 ` Anson Huang
0 siblings, 0 replies; 14+ messages in thread
From: Anson Huang @ 2013-05-31 23:08 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 31, 2013 at 12:37:57PM +0200, Dirk Behme wrote:
> On 31.05.2013 23:01, Anson Huang wrote:
> >Some clock gates are useful when we try to disable them
> >to save power, so we need to add these useful clock gate
> >into clock tree.
> >
> >Signed-off-by: Anson Huang <b20788@freescale.com>
> >---
> > .../devicetree/bindings/clock/imx6q-clock.txt | 13 +++++++++++++
> > arch/arm/mach-imx/clk-imx6q.c | 17 ++++++++++++++++-
> > 2 files changed, 29 insertions(+), 1 deletion(-)
> >
> >diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> >index 6deb6fd..df68f99 100644
> >--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> >+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> >@@ -208,6 +208,19 @@ clocks and IDs.
> > pll4_post_div 193
> > pll5_post_div 194
> > pll5_video_div 195
> >+ aips_tz1 196
> >+ aips_tz2 197
> >+ caam_mem 198
> >+ caam_aclk 199
> >+ caam_ipg 200
> >+ tzasc1 201
> >+ tzasc2 202
> >+ vdoa 203
> >+ mmdc_ch0_ipg 204
> >+ mmdc_ch1_ipg 205
> >+ mx6fast1 206
> >+ per2_main 207
> >+ emi_slow 208
> >
> > Examples:
> >
> >diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> >index dda9a2b..dfb77c1 100644
> >--- a/arch/arm/mach-imx/clk-imx6q.c
> >+++ b/arch/arm/mach-imx/clk-imx6q.c
> >@@ -238,7 +238,9 @@ enum mx6q_clks {
> > pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
> > ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
> > sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
> >- usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
> >+ usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, aips_tz1,
> >+ aips_tz2, caam_mem, caam_aclk, caam_ipg, tzasc1, tzasc2, vdoa, mmdc_ch0_ipg,
> >+ mmdc_ch1_ipg, mx6fast1, per2_main, emi_slow, clk_max
> > };
> >
> > static struct clk *clk[clk_max];
> >@@ -466,8 +468,13 @@ int __init mx6q_clocks_init(void)
> > clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
> >
> > /* name parent_name reg shift */
> >+ clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
> >+ clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
> > clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
> > clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
> >+ clk[caam_mem] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
> >+ clk[caam_aclk] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
> >+ clk[caam_ipg] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
> > clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
> > clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
> > clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
> >@@ -490,6 +497,9 @@ int __init mx6q_clocks_init(void)
> > clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
> > clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
> > clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
> >+ clk[tzasc1] = imx_clk_gate2("tzasc1", "mmdc_ch0_axi_podf", base + 0x70, 22);
> >+ clk[tzasc2] = imx_clk_gate2("tzasc2", "mmdc_ch0_axi_podf", base + 0x70, 24);
> >+ clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
> > clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
> > clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
> > clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
> >@@ -502,10 +512,14 @@ int __init mx6q_clocks_init(void)
> > clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
> > clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
> > clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
> >+ clk[mmdc_ch0_ipg] = imx_clk_gate2("mmdc_ch0_ipg", "ipg", base + 0x74, 24);
> >+ clk[mmdc_ch1_ipg] = imx_clk_gate2("mmdc_ch1_ipg", "ipg", base + 0x74, 26);
> > clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
> > clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
> > clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
> >+ clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8);
> > clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
> >+ clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
> > clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
> > clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
> > clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
> >@@ -528,6 +542,7 @@ int __init mx6q_clocks_init(void)
> > clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
> > clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
> > clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
> >+ clk[emi_slow] = imx_clk_gate2("emi_slow", "emi_slow_podf", base + 0x80, 10);
> > clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
> > clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
> > clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
>
> I think we have the emi_slow already:
>
> https://git.linaro.org/gitweb?p=people/shawnguo/linux-2.6.git;a=commitdiff;h=5e569c675297733dec9f5b65aed3fe694c6e6975
>
Oh, will remove this emi_slow clock, thanks for reminding.
> Best regards
>
> Dirk
>
>
>
>
>
>
>
>
>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/4] ARM: imx: clk-imx6q: per1_bch's parent is wrong
2013-05-31 21:01 [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes Anson Huang
2013-05-31 10:37 ` Dirk Behme
@ 2013-05-31 21:01 ` Anson Huang
2013-06-03 1:29 ` Shawn Guo
2013-05-31 21:01 ` [PATCH 3/4] ARM: imx: clk-imx6q: AXI clock select index is incorrect Anson Huang
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Anson Huang @ 2013-05-31 21:01 UTC (permalink / raw)
To: linux-arm-kernel
per1_bch is sourced from ahb, previous parent
info is incorrect.
Signed-off-by: Anson Huang <b20788@freescale.com>
---
arch/arm/mach-imx/clk-imx6q.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index dfb77c1..c501947 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -518,7 +518,7 @@ int __init mx6q_clocks_init(void)
clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8);
- clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
+ clk[per1_bch] = imx_clk_gate2("per1_bch", "ahb", base + 0x78, 12);
clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 2/4] ARM: imx: clk-imx6q: per1_bch's parent is wrong
2013-05-31 21:01 ` [PATCH 2/4] ARM: imx: clk-imx6q: per1_bch's parent is wrong Anson Huang
@ 2013-06-03 1:29 ` Shawn Guo
2013-06-03 5:46 ` Shawn Guo
0 siblings, 1 reply; 14+ messages in thread
From: Shawn Guo @ 2013-06-03 1:29 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 31, 2013 at 05:01:53PM -0400, Anson Huang wrote:
> per1_bch is sourced from ahb, previous parent
> info is incorrect.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
Applied, thanks.
> ---
> arch/arm/mach-imx/clk-imx6q.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index dfb77c1..c501947 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -518,7 +518,7 @@ int __init mx6q_clocks_init(void)
> clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
> clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
> clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8);
> - clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
> + clk[per1_bch] = imx_clk_gate2("per1_bch", "ahb", base + 0x78, 12);
> clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
> clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
> clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
> --
> 1.7.9.5
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 2/4] ARM: imx: clk-imx6q: per1_bch's parent is wrong
2013-06-03 1:29 ` Shawn Guo
@ 2013-06-03 5:46 ` Shawn Guo
2013-06-10 6:33 ` Dirk Behme
0 siblings, 1 reply; 14+ messages in thread
From: Shawn Guo @ 2013-06-03 5:46 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jun 03, 2013 at 09:29:41AM +0800, Shawn Guo wrote:
> On Fri, May 31, 2013 at 05:01:53PM -0400, Anson Huang wrote:
> > per1_bch is sourced from ahb, previous parent
> > info is incorrect.
> >
> > Signed-off-by: Anson Huang <b20788@freescale.com>
>
> Applied, thanks.
>
I just pulled it out. As Reference Manual does not mention it, we need
to confirm with designer about the correct parent of per1_bch.
Shawn
> > ---
> > arch/arm/mach-imx/clk-imx6q.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> > index dfb77c1..c501947 100644
> > --- a/arch/arm/mach-imx/clk-imx6q.c
> > +++ b/arch/arm/mach-imx/clk-imx6q.c
> > @@ -518,7 +518,7 @@ int __init mx6q_clocks_init(void)
> > clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
> > clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
> > clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8);
> > - clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
> > + clk[per1_bch] = imx_clk_gate2("per1_bch", "ahb", base + 0x78, 12);
> > clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
> > clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
> > clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
> > --
> > 1.7.9.5
> >
> >
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 2/4] ARM: imx: clk-imx6q: per1_bch's parent is wrong
2013-06-03 5:46 ` Shawn Guo
@ 2013-06-10 6:33 ` Dirk Behme
2013-06-10 8:50 ` Shawn Guo
0 siblings, 1 reply; 14+ messages in thread
From: Dirk Behme @ 2013-06-10 6:33 UTC (permalink / raw)
To: linux-arm-kernel
On 03.06.2013 07:46, Shawn Guo wrote:
> On Mon, Jun 03, 2013 at 09:29:41AM +0800, Shawn Guo wrote:
>> On Fri, May 31, 2013 at 05:01:53PM -0400, Anson Huang wrote:
>>> per1_bch is sourced from ahb, previous parent
>>> info is incorrect.
>>>
>>> Signed-off-by: Anson Huang <b20788@freescale.com>
>>
>> Applied, thanks.
>>
> I just pulled it out. As Reference Manual does not mention it, we need
> to confirm with designer about the correct parent of per1_bch.
Any news on this?
Thanks
Dirk
>>> ---
>>> arch/arm/mach-imx/clk-imx6q.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
>>> index dfb77c1..c501947 100644
>>> --- a/arch/arm/mach-imx/clk-imx6q.c
>>> +++ b/arch/arm/mach-imx/clk-imx6q.c
>>> @@ -518,7 +518,7 @@ int __init mx6q_clocks_init(void)
>>> clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
>>> clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
>>> clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8);
>>> - clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
>>> + clk[per1_bch] = imx_clk_gate2("per1_bch", "ahb", base + 0x78, 12);
>>> clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
>>> clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
>>> clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 2/4] ARM: imx: clk-imx6q: per1_bch's parent is wrong
2013-06-10 6:33 ` Dirk Behme
@ 2013-06-10 8:50 ` Shawn Guo
0 siblings, 0 replies; 14+ messages in thread
From: Shawn Guo @ 2013-06-10 8:50 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jun 10, 2013 at 08:33:12AM +0200, Dirk Behme wrote:
> On 03.06.2013 07:46, Shawn Guo wrote:
> >On Mon, Jun 03, 2013 at 09:29:41AM +0800, Shawn Guo wrote:
> >>On Fri, May 31, 2013 at 05:01:53PM -0400, Anson Huang wrote:
> >>>per1_bch is sourced from ahb, previous parent
> >>>info is incorrect.
> >>>
> >>>Signed-off-by: Anson Huang <b20788@freescale.com>
> >>
> >>Applied, thanks.
> >>
> >I just pulled it out. As Reference Manual does not mention it, we need
> >to confirm with designer about the correct parent of per1_bch.
>
> Any news on this?
It turns out that the existing code is correct. So this patch should
just be dropped.
Shawn
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/4] ARM: imx: clk-imx6q: AXI clock select index is incorrect
2013-05-31 21:01 [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes Anson Huang
2013-05-31 10:37 ` Dirk Behme
2013-05-31 21:01 ` [PATCH 2/4] ARM: imx: clk-imx6q: per1_bch's parent is wrong Anson Huang
@ 2013-05-31 21:01 ` Anson Huang
2013-06-03 1:34 ` Shawn Guo
2013-05-31 21:01 ` [PATCH 4/4] ARM: imx: clk-imx6q: correct some clocks' initial enable_count Anson Huang
2013-06-03 1:18 ` [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes Shawn Guo
4 siblings, 1 reply; 14+ messages in thread
From: Anson Huang @ 2013-05-31 21:01 UTC (permalink / raw)
To: linux-arm-kernel
The AXI clock mux should be as below:
00: periph;
01: pll2_pfd2_396m;
10: periph;
11: pll3_pfd1_540m;
So, we need to insert a dummy clock for index 2b'10, otherwise,
if we want to select pll3_pfd1_540m as AXI's parent, it will
still source from periph.
Signed-off-by: Anson Huang <b20788@freescale.com>
---
arch/arm/mach-imx/clk-imx6q.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index c501947..390950e 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -181,7 +181,7 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy",
static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
-static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "dummy", "pll3_pfd1_540m", };
static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
static const char *gpu_axi_sels[] = { "axi", "ahb", };
static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
--
1.7.9.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 3/4] ARM: imx: clk-imx6q: AXI clock select index is incorrect
2013-05-31 21:01 ` [PATCH 3/4] ARM: imx: clk-imx6q: AXI clock select index is incorrect Anson Huang
@ 2013-06-03 1:34 ` Shawn Guo
0 siblings, 0 replies; 14+ messages in thread
From: Shawn Guo @ 2013-06-03 1:34 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 31, 2013 at 05:01:54PM -0400, Anson Huang wrote:
> The AXI clock mux should be as below:
>
> 00: periph;
> 01: pll2_pfd2_396m;
> 10: periph;
> 11: pll3_pfd1_540m;
>
> So, we need to insert a dummy clock for index 2b'10, otherwise,
> if we want to select pll3_pfd1_540m as AXI's parent, it will
> still source from periph.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> ---
> arch/arm/mach-imx/clk-imx6q.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index c501947..390950e 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -181,7 +181,7 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy",
> static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
> static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
> static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
> -static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
> +static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "dummy", "pll3_pfd1_540m", };
As we talked, I replaced "dummy" with "periph", updated the commit log
and applied the patch.
Shawn
> static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
> static const char *gpu_axi_sels[] = { "axi", "ahb", };
> static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
> --
> 1.7.9.5
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/4] ARM: imx: clk-imx6q: correct some clocks' initial enable_count
2013-05-31 21:01 [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes Anson Huang
` (2 preceding siblings ...)
2013-05-31 21:01 ` [PATCH 3/4] ARM: imx: clk-imx6q: AXI clock select index is incorrect Anson Huang
@ 2013-05-31 21:01 ` Anson Huang
2013-05-31 10:44 ` Dirk Behme
2013-06-03 1:18 ` [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes Shawn Guo
4 siblings, 1 reply; 14+ messages in thread
From: Anson Huang @ 2013-05-31 21:01 UTC (permalink / raw)
To: linux-arm-kernel
Those always-on clocks need to be added into init_on array, this
is to avoid confusion when we dump the clock tree, the result
shows that some clocks are on but their enabled_count is 0.
Signed-off-by: Anson Huang <b20788@freescale.com>
---
arch/arm/mach-imx/clk-imx6q.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 390950e..66831a6 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -247,7 +247,7 @@ static struct clk *clk[clk_max];
static struct clk_onecell_data clk_data;
static enum mx6q_clks const clks_init_on[] __initconst = {
- mmdc_ch0_axi, rom, pll1_sys,
+ mmdc_ch0_axi, rom, pll1_sys, ckil, ocram, axi, ipg_per, mx6fast1, per2_main, aips_tz1, aips_tz2, mmdc_ch0_ipg, mmdc_ch1_ipg,
};
static struct clk_div_table clk_enet_ref_table[] = {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 4/4] ARM: imx: clk-imx6q: correct some clocks' initial enable_count
2013-05-31 21:01 ` [PATCH 4/4] ARM: imx: clk-imx6q: correct some clocks' initial enable_count Anson Huang
@ 2013-05-31 10:44 ` Dirk Behme
2013-05-31 23:11 ` Anson Huang
0 siblings, 1 reply; 14+ messages in thread
From: Dirk Behme @ 2013-05-31 10:44 UTC (permalink / raw)
To: linux-arm-kernel
On 31.05.2013 23:01, Anson Huang wrote:
> Those always-on clocks need to be added into init_on array, this
> is to avoid confusion when we dump the clock tree, the result
> shows that some clocks are on but their enabled_count is 0.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> ---
> arch/arm/mach-imx/clk-imx6q.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index 390950e..66831a6 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -247,7 +247,7 @@ static struct clk *clk[clk_max];
> static struct clk_onecell_data clk_data;
>
> static enum mx6q_clks const clks_init_on[] __initconst = {
> - mmdc_ch0_axi, rom, pll1_sys,
> + mmdc_ch0_axi, rom, pll1_sys, ckil, ocram, axi, ipg_per, mx6fast1, per2_main, aips_tz1, aips_tz2, mmdc_ch0_ipg, mmdc_ch1_ipg,
All clocks added with patch 1/4 but not listed here will be disabled by
the kernel, then? Is this intended? I just ask because it might change
the boards behavior in case the boot loader touches one of the clocks
from 1/4 and now they are disabled by the kernel.
Best regards
Dirk
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 4/4] ARM: imx: clk-imx6q: correct some clocks' initial enable_count
2013-05-31 10:44 ` Dirk Behme
@ 2013-05-31 23:11 ` Anson Huang
0 siblings, 0 replies; 14+ messages in thread
From: Anson Huang @ 2013-05-31 23:11 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 31, 2013 at 12:44:23PM +0200, Dirk Behme wrote:
> On 31.05.2013 23:01, Anson Huang wrote:
> >Those always-on clocks need to be added into init_on array, this
> >is to avoid confusion when we dump the clock tree, the result
> >shows that some clocks are on but their enabled_count is 0.
> >
> >Signed-off-by: Anson Huang <b20788@freescale.com>
> >---
> > arch/arm/mach-imx/clk-imx6q.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> >index 390950e..66831a6 100644
> >--- a/arch/arm/mach-imx/clk-imx6q.c
> >+++ b/arch/arm/mach-imx/clk-imx6q.c
> >@@ -247,7 +247,7 @@ static struct clk *clk[clk_max];
> > static struct clk_onecell_data clk_data;
> >
> > static enum mx6q_clks const clks_init_on[] __initconst = {
> >- mmdc_ch0_axi, rom, pll1_sys,
> >+ mmdc_ch0_axi, rom, pll1_sys, ckil, ocram, axi, ipg_per, mx6fast1, per2_main, aips_tz1, aips_tz2, mmdc_ch0_ipg, mmdc_ch1_ipg,
>
>
> All clocks added with patch 1/4 but not listed here will be disabled
> by the kernel, then? Is this intended? I just ask because it might
> change the boards behavior in case the boot loader touches one of
> the clocks from 1/4 and now they are disabled by the kernel.
>
Yes, I think we should only add those necessary clocks during kernel
boot up, other clocks will be disabled by clk framework automatically,
and modules need to enable those clocks they need before active.
> Best regards
>
> Dirk
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes.
2013-05-31 21:01 [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes Anson Huang
` (3 preceding siblings ...)
2013-05-31 21:01 ` [PATCH 4/4] ARM: imx: clk-imx6q: correct some clocks' initial enable_count Anson Huang
@ 2013-06-03 1:18 ` Shawn Guo
4 siblings, 0 replies; 14+ messages in thread
From: Shawn Guo @ 2013-06-03 1:18 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 31, 2013 at 05:01:52PM -0400, Anson Huang wrote:
> Some clock gates are useful when we try to disable them
> to save power, so we need to add these useful clock gate
> into clock tree.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> ---
> .../devicetree/bindings/clock/imx6q-clock.txt | 13 +++++++++++++
> arch/arm/mach-imx/clk-imx6q.c | 17 ++++++++++++++++-
> 2 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> index 6deb6fd..df68f99 100644
> --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> @@ -208,6 +208,19 @@ clocks and IDs.
> pll4_post_div 193
> pll5_post_div 194
> pll5_video_div 195
> + aips_tz1 196
> + aips_tz2 197
> + caam_mem 198
> + caam_aclk 199
> + caam_ipg 200
> + tzasc1 201
> + tzasc2 202
> + vdoa 203
> + mmdc_ch0_ipg 204
> + mmdc_ch1_ipg 205
> + mx6fast1 206
> + per2_main 207
> + emi_slow 208
Be careful when doing this. If you add a gate clk without any user
requesting and using it, the clk_disable_unused() will just shut it
off at late_initcall time. I guess we will have problem if some of the
above clocks like aips_tz1, aips_tz2 get shut off by that late_initcall
call.
Shawn
>
> Examples:
>
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index dda9a2b..dfb77c1 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -238,7 +238,9 @@ enum mx6q_clks {
> pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
> ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
> sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
> - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
> + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, aips_tz1,
> + aips_tz2, caam_mem, caam_aclk, caam_ipg, tzasc1, tzasc2, vdoa, mmdc_ch0_ipg,
> + mmdc_ch1_ipg, mx6fast1, per2_main, emi_slow, clk_max
> };
>
> static struct clk *clk[clk_max];
> @@ -466,8 +468,13 @@ int __init mx6q_clocks_init(void)
> clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
>
> /* name parent_name reg shift */
> + clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
> + clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
> clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
> clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
> + clk[caam_mem] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
> + clk[caam_aclk] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
> + clk[caam_ipg] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
> clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
> clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
> clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
> @@ -490,6 +497,9 @@ int __init mx6q_clocks_init(void)
> clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
> clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
> clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
> + clk[tzasc1] = imx_clk_gate2("tzasc1", "mmdc_ch0_axi_podf", base + 0x70, 22);
> + clk[tzasc2] = imx_clk_gate2("tzasc2", "mmdc_ch0_axi_podf", base + 0x70, 24);
> + clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
> clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
> clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
> clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
> @@ -502,10 +512,14 @@ int __init mx6q_clocks_init(void)
> clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
> clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
> clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
> + clk[mmdc_ch0_ipg] = imx_clk_gate2("mmdc_ch0_ipg", "ipg", base + 0x74, 24);
> + clk[mmdc_ch1_ipg] = imx_clk_gate2("mmdc_ch1_ipg", "ipg", base + 0x74, 26);
> clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
> clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
> clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
> + clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8);
> clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
> + clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
> clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
> clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
> clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
> @@ -528,6 +542,7 @@ int __init mx6q_clocks_init(void)
> clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
> clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
> clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
> + clk[emi_slow] = imx_clk_gate2("emi_slow", "emi_slow_podf", base + 0x80, 10);
> clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
> clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
> clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
> --
> 1.7.9.5
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread