* [PATCH] clk: tegra: pllp_out2 divider is int only
@ 2013-06-05 13:37 ` Peter De Schrijver
0 siblings, 0 replies; 9+ messages in thread
From: Peter De Schrijver @ 2013-06-05 13:37 UTC (permalink / raw)
To: linux-arm-kernel
The pllp_out2 should be integer only, the fractional bit should always be 0.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra114.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index eb27764..5e029fe 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1203,8 +1203,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
/* PLLP_OUT2 */
clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
- TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
- &pll_div_lock);
+ TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
+ 8, 1, &pll_div_lock);
clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
clk_base + PLLP_OUTA, 17, 16,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH] clk: tegra: pllp_out2 divider is int only
@ 2013-06-05 13:37 ` Peter De Schrijver
0 siblings, 0 replies; 9+ messages in thread
From: Peter De Schrijver @ 2013-06-05 13:37 UTC (permalink / raw)
To: Peter De Schrijver
Cc: linux-arm-kernel, mturquette, Stephen Warren, Thierry Reding,
Prashant Gaikwad, linux-tegra, linux-kernel
The pllp_out2 should be integer only, the fractional bit should always be 0.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra114.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index eb27764..5e029fe 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1203,8 +1203,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
/* PLLP_OUT2 */
clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
- TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
- &pll_div_lock);
+ TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
+ 8, 1, &pll_div_lock);
clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
clk_base + PLLP_OUTA, 17, 16,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 9+ messages in thread[parent not found: <1370439442-30852-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH] clk: tegra: pllp_out2 divider is int only
2013-06-05 13:37 ` Peter De Schrijver
(?)
@ 2013-06-05 16:22 ` Stephen Warren
-1 siblings, 0 replies; 9+ messages in thread
From: Stephen Warren @ 2013-06-05 16:22 UTC (permalink / raw)
To: Peter De Schrijver
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
mturquette-QSEj5FYQhm4dnm+yROfE0A, Thierry Reding,
Prashant Gaikwad, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 06/05/2013 07:37 AM, Peter De Schrijver wrote:
> The pllp_out2 should be integer only, the fractional bit should always be 0.
Tested-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] clk: tegra: pllp_out2 divider is int only
@ 2013-06-05 16:22 ` Stephen Warren
0 siblings, 0 replies; 9+ messages in thread
From: Stephen Warren @ 2013-06-05 16:22 UTC (permalink / raw)
To: linux-arm-kernel
On 06/05/2013 07:37 AM, Peter De Schrijver wrote:
> The pllp_out2 should be integer only, the fractional bit should always be 0.
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] clk: tegra: pllp_out2 divider is int only
@ 2013-06-05 16:22 ` Stephen Warren
0 siblings, 0 replies; 9+ messages in thread
From: Stephen Warren @ 2013-06-05 16:22 UTC (permalink / raw)
To: Peter De Schrijver
Cc: linux-arm-kernel, mturquette, Thierry Reding, Prashant Gaikwad,
linux-tegra, linux-kernel
On 06/05/2013 07:37 AM, Peter De Schrijver wrote:
> The pllp_out2 should be integer only, the fractional bit should always be 0.
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] clk: tegra: pllp_out2 divider is int only
2013-06-05 13:37 ` Peter De Schrijver
(?)
@ 2013-06-12 0:26 ` Mike Turquette
-1 siblings, 0 replies; 9+ messages in thread
From: Mike Turquette @ 2013-06-12 0:26 UTC (permalink / raw)
To: Peter De Schrijver
Cc: linux-arm-kernel, Stephen Warren, Thierry Reding,
Prashant Gaikwad, linux-tegra, linux-kernel
Quoting Peter De Schrijver (2013-06-05 06:37:17)
> The pllp_out2 should be integer only, the fractional bit should always be 0.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Taken into clk-next.
Thanks,
Mike
> ---
> drivers/clk/tegra/clk-tegra114.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index eb27764..5e029fe 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -1203,8 +1203,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
> /* PLLP_OUT2 */
> clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
> clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
> - TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
> - &pll_div_lock);
> + TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
> + 8, 1, &pll_div_lock);
> clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
> clk_base + PLLP_OUTA, 17, 16,
> CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
> --
> 1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH] clk: tegra: pllp_out2 divider is int only
@ 2013-06-12 0:26 ` Mike Turquette
0 siblings, 0 replies; 9+ messages in thread
From: Mike Turquette @ 2013-06-12 0:26 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Peter De Schrijver (2013-06-05 06:37:17)
> The pllp_out2 should be integer only, the fractional bit should always be 0.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Taken into clk-next.
Thanks,
Mike
> ---
> drivers/clk/tegra/clk-tegra114.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index eb27764..5e029fe 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -1203,8 +1203,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
> /* PLLP_OUT2 */
> clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
> clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
> - TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
> - &pll_div_lock);
> + TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
> + 8, 1, &pll_div_lock);
> clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
> clk_base + PLLP_OUTA, 17, 16,
> CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
> --
> 1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] clk: tegra: pllp_out2 divider is int only
@ 2013-06-12 0:26 ` Mike Turquette
0 siblings, 0 replies; 9+ messages in thread
From: Mike Turquette @ 2013-06-12 0:26 UTC (permalink / raw)
To: Peter De Schrijver, Peter De Schrijver
Cc: linux-arm-kernel, Stephen Warren, Thierry Reding,
Prashant Gaikwad, linux-tegra, linux-kernel
Quoting Peter De Schrijver (2013-06-05 06:37:17)
> The pllp_out2 should be integer only, the fractional bit should always be 0.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Taken into clk-next.
Thanks,
Mike
> ---
> drivers/clk/tegra/clk-tegra114.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index eb27764..5e029fe 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -1203,8 +1203,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
> /* PLLP_OUT2 */
> clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
> clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
> - TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
> - &pll_div_lock);
> + TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
> + 8, 1, &pll_div_lock);
> clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
> clk_base + PLLP_OUTA, 17, 16,
> CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
> --
> 1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply [flat|nested] 9+ messages in thread