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From: Daniel Vetter <daniel@ffwll.ch>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/6] drm/i915: Optimize the VLV Punit wait a bit
Date: Wed, 26 Jun 2013 12:17:55 +0200	[thread overview]
Message-ID: <20130626101755.GB18285@phenom.ffwll.local> (raw)
In-Reply-To: <1372177266-2665-4-git-send-email-ville.syrjala@linux.intel.com>

On Tue, Jun 25, 2013 at 07:21:03PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Don't do needless udelay() calls if the Punit already completed
> the frequency change.
> 
> Also double check things after the timeout to make sure the timeout
> wasn't just caused by some scheduling delays.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6dbcad7..6b98d45 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3078,14 +3078,20 @@ static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
>  
>  	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>  
> -	do {
> -		pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +
> +	while (pval & 1) {
>  		if (time_after(jiffies, timeout)) {
> -			DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
> +			pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>  			break;
>  		}
> +
>  		udelay(10);
> -	} while (pval & 1);
> +		pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	}
> +
> +	if (pval & 1)
> +		DRM_DEBUG_DRIVER("timed out waiting for Punit\n");

Since we notoriously get these suckers wrong and this check isn't really
in the critical path any more (the punit should have complete the last
change already) and furthermore in a work item: Can we just use one of our
bog-standard wait_for macros here now?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

  parent reply	other threads:[~2013-06-26 10:17 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-25 16:21 [PATCH 0/6] drm/i915: VLV rps stuff ville.syrjala
2013-06-25 16:21 ` [PATCH 1/6] drm/i915: Clean up VLV rps code a bit ville.syrjala
2013-06-25 18:59   ` Jesse Barnes
2013-06-25 16:21 ` [PATCH 2/6] drm/i915: Don't wait for Punit after each freq change on VLV ville.syrjala
2013-06-25 19:02   ` Jesse Barnes
2013-06-25 16:21 ` [PATCH 3/6] drm/i915: Optimize the VLV Punit wait a bit ville.syrjala
2013-06-25 19:03   ` Jesse Barnes
2013-06-26 10:17   ` Daniel Vetter [this message]
2013-06-26 14:43     ` [PATCH] drm/i915: Use wait_for() to wait for Punit to change GPU freq on VLV ville.syrjala
2013-06-26 16:26       ` Jesse Barnes
2013-07-02 13:41         ` Daniel Vetter
2013-07-02 14:01         ` Daniel Vetter
2013-06-25 16:21 ` [PATCH 4/6] drm/i915: Use msecs_to_jiffies_timeout when waiting for Punit freq change ville.syrjala
2013-06-25 19:03   ` Jesse Barnes
2013-06-25 16:21 ` [PATCH 5/6] drm/i915: Make the rps new_delay comparison more readable ville.syrjala
2013-06-25 19:06   ` Jesse Barnes
2013-06-25 16:21 ` [PATCH 6/6] drm/i915: GEN6_RP_INTERRUPT_LIMITS doesn't seem to exist on VLV ville.syrjala
2013-06-25 19:06   ` Jesse Barnes
2013-06-26 10:19     ` Daniel Vetter

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