* ARM Cortex A9: LL counters
@ 2013-07-03 20:32 javier.picorel at epfl.ch
0 siblings, 0 replies; 6+ messages in thread
From: javier.picorel at epfl.ch @ 2013-07-03 20:32 UTC (permalink / raw)
To: linux-arm-kernel
Dear all,
It seems that there is no mapping between any ARM Cortex A9 counter to
the L2 (Last Level) access or misses event.
arch/arm/kernel/perf_event_v7.c
[C(LL)] = {
293 [C(OP_READ)] = {
294 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
295 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
296 },
297 [C(OP_WRITE)] = {
298 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
299 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
300 },
301 [C(OP_PREFETCH)] = {
302 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
303 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
304 },
305 },
Looking at ARM's reference manual and OProfile's event list on A9, I
see the following two counters:
CO_LF_MISS: (counter: 1, 2, 3, 4, 5, 6)
Number of coherent linefill requests which miss in all other
CPUs, meaning that the request
is sent to external memory (min count: 500)
CO_LF_HIT: (counter: 1, 2, 3, 4, 5, 6)
Number of coherent linefill requests which hit in another
CPU, meaning that the linefill
data is fetched directly from the relevant cache (min count: 500)
It seems that the first counter refers to the L2 Misses and the second
one to the L2 Hits (Last Level Cache in this architecture). I'm not sure
whether we should do something about this or nor. Thanks!
Best Regards,
Javier
^ permalink raw reply [flat|nested] 6+ messages in thread
* ARM Cortex A9: LL counters
2013-07-06 20:21 ` Javier Picorel
@ 2013-07-08 8:53 ` Will Deacon
0 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2013-07-08 8:53 UTC (permalink / raw)
To: linux-arm-kernel
[adding Mark]
On Sat, Jul 06, 2013 at 09:21:54PM +0100, Javier Picorel wrote:
> That will be perfect. Is there any way to access these memory mapped counters?
Mark was working on a PMU driver for Perf, which would expose these
counters via the perf system call. Unfortunately, the patches have rotted a
bit since then, so they would need refreshing/rebasing before they can be
reviewed.
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
* ARM Cortex A9: LL counters
2013-07-05 10:12 ` Will Deacon
@ 2013-07-06 20:21 ` Javier Picorel
2013-07-08 8:53 ` Will Deacon
0 siblings, 1 reply; 6+ messages in thread
From: Javier Picorel @ 2013-07-06 20:21 UTC (permalink / raw)
To: linux-arm-kernel
That will be perfect. Is there any way to access these memory mapped counters?
________________________________________
From: Will Deacon [will.deacon at arm.com]
Sent: 05 July 2013 12:12
To: Javier Picorel
Cc: linux-arm-kernel at lists.infradead.org; Mark Rutland
Subject: Re: ARM Cortex A9: LL counters
On Fri, Jul 05, 2013 at 12:44:58AM +0100, Javier Picorel wrote:
> Thanks for the clarification! However, correct me if I'm wrong but, doesn't this mean that the "CO_LF_MISS" counter refers to L2 accesses? Thanks!
It will certainly account for some of them, but I wouldn't be surprised if
you can generate L2 accesses in ways other than missing at coherent L1.
You could look at the L2 counters and compare.
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
* ARM Cortex A9: LL counters
2013-07-04 23:44 ` Javier Picorel
@ 2013-07-05 10:12 ` Will Deacon
2013-07-06 20:21 ` Javier Picorel
0 siblings, 1 reply; 6+ messages in thread
From: Will Deacon @ 2013-07-05 10:12 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 05, 2013 at 12:44:58AM +0100, Javier Picorel wrote:
> Thanks for the clarification! However, correct me if I'm wrong but, doesn't this mean that the "CO_LF_MISS" counter refers to L2 accesses? Thanks!
It will certainly account for some of them, but I wouldn't be surprised if
you can generate L2 accesses in ways other than missing at coherent L1.
You could look at the L2 counters and compare.
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
* ARM Cortex A9: LL counters
2013-07-04 9:45 ` Will Deacon
@ 2013-07-04 23:44 ` Javier Picorel
2013-07-05 10:12 ` Will Deacon
0 siblings, 1 reply; 6+ messages in thread
From: Javier Picorel @ 2013-07-04 23:44 UTC (permalink / raw)
To: linux-arm-kernel
Hello Will,
Thanks for the clarification! However, correct me if I'm wrong but, doesn't this mean that the "CO_LF_MISS" counter refers to L2 accesses? Thanks!
Regards,
Javier
________________________________________
From: Will Deacon [will.deacon at arm.com]
Sent: 04 July 2013 11:45
To: Javier Picorel
Cc: linux-arm-kernel at lists.infradead.org; mark.rutland at arm.com
Subject: Re: ARM Cortex A9: LL counters
On Wed, Jul 03, 2013 at 07:59:14PM +0100, Javier Picorel wrote:
> Dear all,
Hello Javier,
> It seems that there is no mapping between any ARM Cortex A9 counter to the L2 (Last Level) access or misses event.
The L2 cache on Cortex-A9 is external to the CPU core and has its own set of
memory-mapped performance counters. Mark Rutland [CC'd] had something
working for this, but I haven't seen a refresh of the patches for a while.
> Looking at ARM's reference manual and OProfile's event list on A9, I see the following two counters:
>
> CO_LF_MISS: (counter: 1, 2, 3, 4, 5, 6)
> Number of coherent linefill requests which miss in all other CPUs, meaning that the request
> is sent to external memory (min count: 500)
> CO_LF_HIT: (counter: 1, 2, 3, 4, 5, 6)
> Number of coherent linefill requests which hit in another CPU, meaning that the linefill
> data is fetched directly from the relevant cache (min count: 500)
>
> It seems that the first counter refers to the L2 Misses and the second one to the L2 Hits (Last Level Cache in this architecture). I'm not sure
> whether we should do something about this or nor. Thanks!
No, these are all for L1. `sent to external memory' means sent to L2.
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
* ARM Cortex A9: LL counters
[not found] <BFCB49997E59134AAAF17FFE77F8FF06673738BC@REXMD.intranet.epfl.ch>
@ 2013-07-04 9:45 ` Will Deacon
2013-07-04 23:44 ` Javier Picorel
0 siblings, 1 reply; 6+ messages in thread
From: Will Deacon @ 2013-07-04 9:45 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 03, 2013 at 07:59:14PM +0100, Javier Picorel wrote:
> Dear all,
Hello Javier,
> It seems that there is no mapping between any ARM Cortex A9 counter to the L2 (Last Level) access or misses event.
The L2 cache on Cortex-A9 is external to the CPU core and has its own set of
memory-mapped performance counters. Mark Rutland [CC'd] had something
working for this, but I haven't seen a refresh of the patches for a while.
> Looking at ARM's reference manual and OProfile's event list on A9, I see the following two counters:
>
> CO_LF_MISS: (counter: 1, 2, 3, 4, 5, 6)
> Number of coherent linefill requests which miss in all other CPUs, meaning that the request
> is sent to external memory (min count: 500)
> CO_LF_HIT: (counter: 1, 2, 3, 4, 5, 6)
> Number of coherent linefill requests which hit in another CPU, meaning that the linefill
> data is fetched directly from the relevant cache (min count: 500)
>
> It seems that the first counter refers to the L2 Misses and the second one to the L2 Hits (Last Level Cache in this architecture). I'm not sure
> whether we should do something about this or nor. Thanks!
No, these are all for L1. `sent to external memory' means sent to L2.
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-07-08 8:53 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2013-07-03 20:32 ARM Cortex A9: LL counters javier.picorel at epfl.ch
[not found] <BFCB49997E59134AAAF17FFE77F8FF06673738BC@REXMD.intranet.epfl.ch>
2013-07-04 9:45 ` Will Deacon
2013-07-04 23:44 ` Javier Picorel
2013-07-05 10:12 ` Will Deacon
2013-07-06 20:21 ` Javier Picorel
2013-07-08 8:53 ` Will Deacon
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