[PATCH v2 00/02] ARM: shmobile: r8a7790 arch timer frequency update

[PATCH v2 00/02] ARM: shmobile: r8a7790 arch timer frequency update

[Magnus Damm]

ARM: shmobile: r8a7790 arch timer frequency update (v2)

[PATCH v2 01/02] ARM: shmobile: Introduce r8a7790_read_mode_pins()
[PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins

Add code to setup r8a7790 arch timer frequency dynamically at boot time
based on the EXTAL frequency pointed out by the boot mode pins.

Patch 1/2 has been updated with a ioremap() fix.
Patch 2/2 now has reported-by and tested-by.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Built on top of renesas-next-20130711

 arch/arm/mach-shmobile/clock-r8a7790.c        |   11 ----
 arch/arm/mach-shmobile/include/mach/r8a7790.h |    3 +
 arch/arm/mach-shmobile/setup-r8a7790.c        |   63 +++++++++++++++++++++++--
 3 files changed, 63 insertions(+), 14 deletions(-)

[PATCH v2 00/02] ARM: shmobile: r8a7790 arch timer frequency update

[Magnus Damm]

ARM: shmobile: r8a7790 arch timer frequency update (v2)

[PATCH v2 01/02] ARM: shmobile: Introduce r8a7790_read_mode_pins()
[PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins

Add code to setup r8a7790 arch timer frequency dynamically at boot time
based on the EXTAL frequency pointed out by the boot mode pins.

Patch 1/2 has been updated with a ioremap() fix.
Patch 2/2 now has reported-by and tested-by.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Built on top of renesas-next-20130711

 arch/arm/mach-shmobile/clock-r8a7790.c        |   11 ----
 arch/arm/mach-shmobile/include/mach/r8a7790.h |    3 +
 arch/arm/mach-shmobile/setup-r8a7790.c        |   63 +++++++++++++++++++++++--
 3 files changed, 63 insertions(+), 14 deletions(-)

[PATCH v2 01/02] ARM: shmobile: Introduce r8a7790_read_mode_pins()

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Break out the r8a7790 boot mode code into a separate
function so it can be shared by multiple users.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Changes since v1:
 - Don't ioremap() two pages, thanks Sergei!

 arch/arm/mach-shmobile/clock-r8a7790.c        |   11 ++---------
 arch/arm/mach-shmobile/include/mach/r8a7790.h |    3 +++
 arch/arm/mach-shmobile/setup-r8a7790.c        |   14 ++++++++++++++
 3 files changed, 19 insertions(+), 9 deletions(-)

--- 0001/arch/arm/mach-shmobile/clock-r8a7790.c
+++ work/arch/arm/mach-shmobile/clock-r8a7790.c	2013-07-12 01:13:42.000000000 +0900
@@ -24,6 +24,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/r8a7790.h>
 
 /*
  *   MD		EXTAL		PLL0	PLL1	PLL3
@@ -42,8 +43,6 @@
  *	see "p1 / 2" on R8A7790_CLOCK_ROOT() below
  */
 
-#define MD(nr)	(1 << nr)
-
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
@@ -53,7 +52,6 @@
 #define SMSTPCR5 0xe6150144
 #define SMSTPCR7 0xe615014c
 
-#define MODEMR		0xE6160060
 #define SDCKCR		0xE6150074
 #define SD2CKCR		0xE6150078
 #define SD3CKCR		0xE615007C
@@ -288,14 +286,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7790_clock_init(void)
 {
-	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-	u32 mode;
+	u32 mode = r8a7790_read_mode_pins();
 	int k, ret = 0;
 
-	BUG_ON(!modemr);
-	mode = ioread32(modemr);
-	iounmap(modemr);
-
 	switch (mode & (MD(14) | MD(13))) {
 	case 0:
 		R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
--- 0001/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ work/arch/arm/mach-shmobile/include/mach/r8a7790.h	2013-07-12 01:13:42.000000000 +0900
@@ -8,4 +8,7 @@ void r8a7790_pinmux_init(void);
 void r8a7790_init_delay(void);
 void r8a7790_timer_init(void);
 
+#define MD(nr) BIT(nr)
+u32 r8a7790_read_mode_pins(void);
+
 #endif /* __ASM_R8A7790_H__ */
--- 0001/arch/arm/mach-shmobile/setup-r8a7790.c
+++ work/arch/arm/mach-shmobile/setup-r8a7790.c	2013-07-12 01:14:03.000000000 +0900
@@ -201,6 +201,20 @@ void __init r8a7790_add_standard_devices
 	r8a7790_register_thermal();
 }
 
+#define MODEMR 0xe6160060
+
+u32 __init r8a7790_read_mode_pins(void)
+{
+	void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+	u32 mode;
+
+	BUG_ON(!modemr);
+	mode = ioread32(modemr);
+	iounmap(modemr);
+
+	return mode;
+}
+
 void __init r8a7790_timer_init(void)
 {
 	void __iomem *cntcr;

[PATCH v2 01/02] ARM: shmobile: Introduce r8a7790_read_mode_pins()

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Break out the r8a7790 boot mode code into a separate
function so it can be shared by multiple users.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Changes since v1:
 - Don't ioremap() two pages, thanks Sergei!

 arch/arm/mach-shmobile/clock-r8a7790.c        |   11 ++---------
 arch/arm/mach-shmobile/include/mach/r8a7790.h |    3 +++
 arch/arm/mach-shmobile/setup-r8a7790.c        |   14 ++++++++++++++
 3 files changed, 19 insertions(+), 9 deletions(-)

--- 0001/arch/arm/mach-shmobile/clock-r8a7790.c
+++ work/arch/arm/mach-shmobile/clock-r8a7790.c	2013-07-12 01:13:42.000000000 +0900
@@ -24,6 +24,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/r8a7790.h>
 
 /*
  *   MD		EXTAL		PLL0	PLL1	PLL3
@@ -42,8 +43,6 @@
  *	see "p1 / 2" on R8A7790_CLOCK_ROOT() below
  */
 
-#define MD(nr)	(1 << nr)
-
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
@@ -53,7 +52,6 @@
 #define SMSTPCR5 0xe6150144
 #define SMSTPCR7 0xe615014c
 
-#define MODEMR		0xE6160060
 #define SDCKCR		0xE6150074
 #define SD2CKCR		0xE6150078
 #define SD3CKCR		0xE615007C
@@ -288,14 +286,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7790_clock_init(void)
 {
-	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-	u32 mode;
+	u32 mode = r8a7790_read_mode_pins();
 	int k, ret = 0;
 
-	BUG_ON(!modemr);
-	mode = ioread32(modemr);
-	iounmap(modemr);
-
 	switch (mode & (MD(14) | MD(13))) {
 	case 0:
 		R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
--- 0001/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ work/arch/arm/mach-shmobile/include/mach/r8a7790.h	2013-07-12 01:13:42.000000000 +0900
@@ -8,4 +8,7 @@ void r8a7790_pinmux_init(void);
 void r8a7790_init_delay(void);
 void r8a7790_timer_init(void);
 
+#define MD(nr) BIT(nr)
+u32 r8a7790_read_mode_pins(void);
+
 #endif /* __ASM_R8A7790_H__ */
--- 0001/arch/arm/mach-shmobile/setup-r8a7790.c
+++ work/arch/arm/mach-shmobile/setup-r8a7790.c	2013-07-12 01:14:03.000000000 +0900
@@ -201,6 +201,20 @@ void __init r8a7790_add_standard_devices
 	r8a7790_register_thermal();
 }
 
+#define MODEMR 0xe6160060
+
+u32 __init r8a7790_read_mode_pins(void)
+{
+	void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+	u32 mode;
+
+	BUG_ON(!modemr);
+	mode = ioread32(modemr);
+	iounmap(modemr);
+
+	return mode;
+}
+
 void __init r8a7790_timer_init(void)
 {
 	void __iomem *cntcr;

[PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Update the r8a7790 arch timer setup code to configure the
frequency dynamically at boot time. This means that the arch
timer driver will be able to detect a timer frequency that
has been calculated based on the MD pins instead of a fixed
and potentially incorrect 13 MHz.

With this patch applied the Linux kernel will correctly
support the r8a7790 Lager board that uses a 20 Mhz EXTAL.
The arch timer will operate on 10 MHz and the Linux arch
timer driver will be correctly configured to use 10 MHz.

Without this patch the 20 MHz EXTAL will be used to drive
the arch timer at 10 MHz, but the Linux arch timer driver
will believe it is counting at 13 Mhz.

Reported-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Ulrich Hecht <ulrich.hecht@gmail.com>
---

 arch/arm/mach-shmobile/setup-r8a7790.c |   49 ++++++++++++++++++++++++++++----
 1 file changed, 44 insertions(+), 5 deletions(-)

--- 0006/arch/arm/mach-shmobile/setup-r8a7790.c
+++ work/arch/arm/mach-shmobile/setup-r8a7790.c	2013-07-09 21:29:18.000000000 +0900
@@ -215,14 +215,53 @@ u32 __init r8a7790_read_mode_pins(void)
 	return mode;
 }
 
+#define CNTCR 0
+#define CNTFID0 0x20
+
 void __init r8a7790_timer_init(void)
 {
-	void __iomem *cntcr;
+#ifdef CONFIG_ARM_ARCH_TIMER
+	u32 mode = r8a7790_read_mode_pins();
+	void __iomem *base;
+	int extal_mhz = 0;
+	u32 freq;
+
+	/* At Linux boot time the r8a7790 arch timer comes up
+	 * with the counter disabled. Moreover, it may also report
+	 * a potentially incorrect fixed 13 MHz frequency. To be
+	 * correct these registers need to be updated to use the
+	 * frequency EXTAL / 2 which can be determined by the MD pins.
+	 */
+
+	switch (mode & (MD(14) | MD(13))) {
+	case 0:
+		extal_mhz = 15;
+		break;
+	case MD(13):
+		extal_mhz = 20;
+		break;
+	case MD(14):
+		extal_mhz = 26;
+		break;
+	case MD(13) | MD(14):
+		extal_mhz = 30;
+		break;
+	}
+
+	/* The arch timer frequency equals EXTAL / 2 */
+	freq = extal_mhz * (1000000 / 2);
+
+	/* Remap "armgcnt address map" space */
+	base = ioremap(0xe6080000, PAGE_SIZE);
+
+	/* Update registers with correct frequency */
+	iowrite32(freq, base + CNTFID0);
+	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 
-	/* make sure arch timer is started by setting bit 0 of CNTCT */
-	cntcr = ioremap(0xe6080000, PAGE_SIZE);
-	iowrite32(1, cntcr);
-	iounmap(cntcr);
+	/* make sure arch timer is started by setting bit 0 of CNTCR */
+	iowrite32(1, base + CNTCR);
+	iounmap(base);
+#endif /* CONFIG_ARM_ARCH_TIMER */
 
 	shmobile_timer_init();
 }

[PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Update the r8a7790 arch timer setup code to configure the
frequency dynamically at boot time. This means that the arch
timer driver will be able to detect a timer frequency that
has been calculated based on the MD pins instead of a fixed
and potentially incorrect 13 MHz.

With this patch applied the Linux kernel will correctly
support the r8a7790 Lager board that uses a 20 Mhz EXTAL.
The arch timer will operate on 10 MHz and the Linux arch
timer driver will be correctly configured to use 10 MHz.

Without this patch the 20 MHz EXTAL will be used to drive
the arch timer at 10 MHz, but the Linux arch timer driver
will believe it is counting at 13 Mhz.

Reported-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Ulrich Hecht <ulrich.hecht@gmail.com>
---

 arch/arm/mach-shmobile/setup-r8a7790.c |   49 ++++++++++++++++++++++++++++----
 1 file changed, 44 insertions(+), 5 deletions(-)

--- 0006/arch/arm/mach-shmobile/setup-r8a7790.c
+++ work/arch/arm/mach-shmobile/setup-r8a7790.c	2013-07-09 21:29:18.000000000 +0900
@@ -215,14 +215,53 @@ u32 __init r8a7790_read_mode_pins(void)
 	return mode;
 }
 
+#define CNTCR 0
+#define CNTFID0 0x20
+
 void __init r8a7790_timer_init(void)
 {
-	void __iomem *cntcr;
+#ifdef CONFIG_ARM_ARCH_TIMER
+	u32 mode = r8a7790_read_mode_pins();
+	void __iomem *base;
+	int extal_mhz = 0;
+	u32 freq;
+
+	/* At Linux boot time the r8a7790 arch timer comes up
+	 * with the counter disabled. Moreover, it may also report
+	 * a potentially incorrect fixed 13 MHz frequency. To be
+	 * correct these registers need to be updated to use the
+	 * frequency EXTAL / 2 which can be determined by the MD pins.
+	 */
+
+	switch (mode & (MD(14) | MD(13))) {
+	case 0:
+		extal_mhz = 15;
+		break;
+	case MD(13):
+		extal_mhz = 20;
+		break;
+	case MD(14):
+		extal_mhz = 26;
+		break;
+	case MD(13) | MD(14):
+		extal_mhz = 30;
+		break;
+	}
+
+	/* The arch timer frequency equals EXTAL / 2 */
+	freq = extal_mhz * (1000000 / 2);
+
+	/* Remap "armgcnt address map" space */
+	base = ioremap(0xe6080000, PAGE_SIZE);
+
+	/* Update registers with correct frequency */
+	iowrite32(freq, base + CNTFID0);
+	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 
-	/* make sure arch timer is started by setting bit 0 of CNTCT */
-	cntcr = ioremap(0xe6080000, PAGE_SIZE);
-	iowrite32(1, cntcr);
-	iounmap(cntcr);
+	/* make sure arch timer is started by setting bit 0 of CNTCR */
+	iowrite32(1, base + CNTCR);
+	iounmap(base);
+#endif /* CONFIG_ARM_ARCH_TIMER */
 
 	shmobile_timer_init();
 }

Re: [PATCH v2 01/02] ARM: shmobile: Introduce r8a7790_read_mode_pins()

[Simon Horman]

On Fri, Jul 12, 2013 at 01:22:19AM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Break out the r8a7790 boot mode code into a separate
> function so it can be shared by multiple users.
> 
> Signed-off-by: Magnus Damm <damm@opensource.se>

Thanks.

I have queued this up for v3.12 in the soc branch and it
is available in renesas-devel-20130712.

[PATCH v2 01/02] ARM: shmobile: Introduce r8a7790_read_mode_pins()

[Simon Horman]

On Fri, Jul 12, 2013 at 01:22:19AM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Break out the r8a7790 boot mode code into a separate
> function so it can be shared by multiple users.
> 
> Signed-off-by: Magnus Damm <damm@opensource.se>

Thanks.

I have queued this up for v3.12 in the soc branch and it
is available in renesas-devel-20130712.

Re: [PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins

[Simon Horman]

On Fri, Jul 12, 2013 at 01:22:29AM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Update the r8a7790 arch timer setup code to configure the
> frequency dynamically at boot time. This means that the arch
> timer driver will be able to detect a timer frequency that
> has been calculated based on the MD pins instead of a fixed
> and potentially incorrect 13 MHz.
> 
> With this patch applied the Linux kernel will correctly
> support the r8a7790 Lager board that uses a 20 Mhz EXTAL.
> The arch timer will operate on 10 MHz and the Linux arch
> timer driver will be correctly configured to use 10 MHz.
> 
> Without this patch the 20 MHz EXTAL will be used to drive
> the arch timer at 10 MHz, but the Linux arch timer driver
> will believe it is counting at 13 Mhz.
> 
> Reported-by: Ulrich Hecht <ulrich.hecht@gmail.com>
> Signed-off-by: Magnus Damm <damm@opensource.se>
> Tested-by: Ulrich Hecht <ulrich.hecht@gmail.com>

Thanks.

I have queued this up for v3.12 in the soc branch and it
is available in renesas-devel-20130712.

[PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins

[Simon Horman]

On Fri, Jul 12, 2013 at 01:22:29AM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Update the r8a7790 arch timer setup code to configure the
> frequency dynamically at boot time. This means that the arch
> timer driver will be able to detect a timer frequency that
> has been calculated based on the MD pins instead of a fixed
> and potentially incorrect 13 MHz.
> 
> With this patch applied the Linux kernel will correctly
> support the r8a7790 Lager board that uses a 20 Mhz EXTAL.
> The arch timer will operate on 10 MHz and the Linux arch
> timer driver will be correctly configured to use 10 MHz.
> 
> Without this patch the 20 MHz EXTAL will be used to drive
> the arch timer at 10 MHz, but the Linux arch timer driver
> will believe it is counting at 13 Mhz.
> 
> Reported-by: Ulrich Hecht <ulrich.hecht@gmail.com>
> Signed-off-by: Magnus Damm <damm@opensource.se>
> Tested-by: Ulrich Hecht <ulrich.hecht@gmail.com>

Thanks.

I have queued this up for v3.12 in the soc branch and it
is available in renesas-devel-20130712.

Re: [PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins

[Mark Rutland]

On Thu, Jul 11, 2013 at 05:22:29PM +0100, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Update the r8a7790 arch timer setup code to configure the
> frequency dynamically at boot time. This means that the arch
> timer driver will be able to detect a timer frequency that
> has been calculated based on the MD pins instead of a fixed
> and potentially incorrect 13 MHz.
> 
> With this patch applied the Linux kernel will correctly
> support the r8a7790 Lager board that uses a 20 Mhz EXTAL.
> The arch timer will operate on 10 MHz and the Linux arch
> timer driver will be correctly configured to use 10 MHz.
> 
> Without this patch the 20 MHz EXTAL will be used to drive
> the arch timer at 10 MHz, but the Linux arch timer driver
> will believe it is counting at 13 Mhz.

This seems scary to me. The bootloader should be doing this before jumping to
Linux. As CNTCR is only writeable from the secure side, you won't be able to
use KVM unless the bootloader has done this.

Additionally, if you didn't do this in Linux, as far as I can see you wouldn't
need an init_time callback at all...

Thanks,
Mark.

> 
> Reported-by: Ulrich Hecht <ulrich.hecht@gmail.com>
> Signed-off-by: Magnus Damm <damm@opensource.se>
> Tested-by: Ulrich Hecht <ulrich.hecht@gmail.com>
> ---
> 
>  arch/arm/mach-shmobile/setup-r8a7790.c |   49 ++++++++++++++++++++++++++++----
>  1 file changed, 44 insertions(+), 5 deletions(-)
> 
> --- 0006/arch/arm/mach-shmobile/setup-r8a7790.c
> +++ work/arch/arm/mach-shmobile/setup-r8a7790.c	2013-07-09 21:29:18.000000000 +0900
> @@ -215,14 +215,53 @@ u32 __init r8a7790_read_mode_pins(void)
>  	return mode;
>  }
>  
> +#define CNTCR 0
> +#define CNTFID0 0x20
> +
>  void __init r8a7790_timer_init(void)
>  {
> -	void __iomem *cntcr;
> +#ifdef CONFIG_ARM_ARCH_TIMER
> +	u32 mode = r8a7790_read_mode_pins();
> +	void __iomem *base;
> +	int extal_mhz = 0;
> +	u32 freq;
> +
> +	/* At Linux boot time the r8a7790 arch timer comes up
> +	 * with the counter disabled. Moreover, it may also report
> +	 * a potentially incorrect fixed 13 MHz frequency. To be
> +	 * correct these registers need to be updated to use the
> +	 * frequency EXTAL / 2 which can be determined by the MD pins.
> +	 */
> +
> +	switch (mode & (MD(14) | MD(13))) {
> +	case 0:
> +		extal_mhz = 15;
> +		break;
> +	case MD(13):
> +		extal_mhz = 20;
> +		break;
> +	case MD(14):
> +		extal_mhz = 26;
> +		break;
> +	case MD(13) | MD(14):
> +		extal_mhz = 30;
> +		break;
> +	}
> +
> +	/* The arch timer frequency equals EXTAL / 2 */
> +	freq = extal_mhz * (1000000 / 2);
> +
> +	/* Remap "armgcnt address map" space */
> +	base = ioremap(0xe6080000, PAGE_SIZE);
> +
> +	/* Update registers with correct frequency */
> +	iowrite32(freq, base + CNTFID0);
> +	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
>  
> -	/* make sure arch timer is started by setting bit 0 of CNTCT */
> -	cntcr = ioremap(0xe6080000, PAGE_SIZE);
> -	iowrite32(1, cntcr);
> -	iounmap(cntcr);
> +	/* make sure arch timer is started by setting bit 0 of CNTCR */
> +	iowrite32(1, base + CNTCR);
> +	iounmap(base);
> +#endif /* CONFIG_ARM_ARCH_TIMER */
>  
>  	shmobile_timer_init();
>  }
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

[PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins

[Mark Rutland]

On Thu, Jul 11, 2013 at 05:22:29PM +0100, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Update the r8a7790 arch timer setup code to configure the
> frequency dynamically at boot time. This means that the arch
> timer driver will be able to detect a timer frequency that
> has been calculated based on the MD pins instead of a fixed
> and potentially incorrect 13 MHz.
> 
> With this patch applied the Linux kernel will correctly
> support the r8a7790 Lager board that uses a 20 Mhz EXTAL.
> The arch timer will operate on 10 MHz and the Linux arch
> timer driver will be correctly configured to use 10 MHz.
> 
> Without this patch the 20 MHz EXTAL will be used to drive
> the arch timer at 10 MHz, but the Linux arch timer driver
> will believe it is counting at 13 Mhz.

This seems scary to me. The bootloader should be doing this before jumping to
Linux. As CNTCR is only writeable from the secure side, you won't be able to
use KVM unless the bootloader has done this.

Additionally, if you didn't do this in Linux, as far as I can see you wouldn't
need an init_time callback at all...

Thanks,
Mark.

> 
> Reported-by: Ulrich Hecht <ulrich.hecht@gmail.com>
> Signed-off-by: Magnus Damm <damm@opensource.se>
> Tested-by: Ulrich Hecht <ulrich.hecht@gmail.com>
> ---
> 
>  arch/arm/mach-shmobile/setup-r8a7790.c |   49 ++++++++++++++++++++++++++++----
>  1 file changed, 44 insertions(+), 5 deletions(-)
> 
> --- 0006/arch/arm/mach-shmobile/setup-r8a7790.c
> +++ work/arch/arm/mach-shmobile/setup-r8a7790.c	2013-07-09 21:29:18.000000000 +0900
> @@ -215,14 +215,53 @@ u32 __init r8a7790_read_mode_pins(void)
>  	return mode;
>  }
>  
> +#define CNTCR 0
> +#define CNTFID0 0x20
> +
>  void __init r8a7790_timer_init(void)
>  {
> -	void __iomem *cntcr;
> +#ifdef CONFIG_ARM_ARCH_TIMER
> +	u32 mode = r8a7790_read_mode_pins();
> +	void __iomem *base;
> +	int extal_mhz = 0;
> +	u32 freq;
> +
> +	/* At Linux boot time the r8a7790 arch timer comes up
> +	 * with the counter disabled. Moreover, it may also report
> +	 * a potentially incorrect fixed 13 MHz frequency. To be
> +	 * correct these registers need to be updated to use the
> +	 * frequency EXTAL / 2 which can be determined by the MD pins.
> +	 */
> +
> +	switch (mode & (MD(14) | MD(13))) {
> +	case 0:
> +		extal_mhz = 15;
> +		break;
> +	case MD(13):
> +		extal_mhz = 20;
> +		break;
> +	case MD(14):
> +		extal_mhz = 26;
> +		break;
> +	case MD(13) | MD(14):
> +		extal_mhz = 30;
> +		break;
> +	}
> +
> +	/* The arch timer frequency equals EXTAL / 2 */
> +	freq = extal_mhz * (1000000 / 2);
> +
> +	/* Remap "armgcnt address map" space */
> +	base = ioremap(0xe6080000, PAGE_SIZE);
> +
> +	/* Update registers with correct frequency */
> +	iowrite32(freq, base + CNTFID0);
> +	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
>  
> -	/* make sure arch timer is started by setting bit 0 of CNTCT */
> -	cntcr = ioremap(0xe6080000, PAGE_SIZE);
> -	iowrite32(1, cntcr);
> -	iounmap(cntcr);
> +	/* make sure arch timer is started by setting bit 0 of CNTCR */
> +	iowrite32(1, base + CNTCR);
> +	iounmap(base);
> +#endif /* CONFIG_ARM_ARCH_TIMER */
>  
>  	shmobile_timer_init();
>  }
> 
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