From: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> To: Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Cc: Nicolas Pitre <nicolas.pitre-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, Jon Medhurst <tixy-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, Catalin Marinas <Catalin.Marinas-5wv7dgnIgG8@public.gmane.org>, Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>, Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org>, Lennert Buytenhek <kernel-OLH4Qvv75CYX/NnBR394Jw@public.gmane.org>, Kukjin Kim <kgene.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>, Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>, Magnus Damm <magnus.damm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, "grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org" <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, David Brown <davidb-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>, Sekhar Nori <nsekhar-l0cyMroinI0@public.gmane.org>, "devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" <devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org>, "rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org" <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>, Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>, Barry Song <baohua.song-kQvG35nSl+M@public.gmane.org>, "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>, Amit Kucheria <amit.kucheria-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, Vinayak Kale <vkale-qTEPVZfXA3Y@public.gmane.org> Subject: Re: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates Date: Mon, 15 Jul 2013 10:34:06 +0100 [thread overview] Message-ID: <20130715093406.GC15904@e102568-lin.cambridge.arm.com> (raw) In-Reply-To: <CAL_JsqLANi5UoVyRMsa6XoQ+_KnmTQDfTz++shEh-dZ3FQGZaQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote: > On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi > <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote: > > In order to extend the current cpu nodes bindings to newer CPUs > > inclusive of AArch64 and to update support for older ARM CPUs this > > patch updates device tree documentation for the cpu nodes bindings. > > Sorry for the long delay on this, but I'm still not happy with the binding here. I had to ask Russell again to drop the bindings patches from the patch system, and this is not acceptable since two months have passed and the entire series was reviewed, acked and partially merged. I will review these bindings again but I would like to understand who should give the final go ahead to get these patches queued for upstreaming, I can't continue updating this stuff forever. > > Main changes: > > - adds 64-bit bindings > > - define usage of #address-cells > > - define 32/64 dts compatibility settings > > - defines behaviour on pre and post v7 uniprocessor systems > > - adds ARM 11MPcore specific reg property definition > > > > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> > > --- > > Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++--- > > 1 file changed, 412 insertions(+), 47 deletions(-) > > [snip] > > > + # On ARM v8 64-bit systems, where the reg property > > + size can be 1 or 2 cells (as defined by cpus node's > > + #address-cells property), this property is > > + required and matches: > > + > > + - On systems running the OS in AArch32: > > The DTS cannot change based on 32-bit or 64-bit OS. "On systems running the OS in AArch32" implies a dependency on the HW execution state. Since the DT is used to configure OSs I thought that could be a valid sentence. Unfortunately this stuff is not C, so I reiterate my point above, before changing it I would like to understand who should say the wording is ok otherwise we could argue forever. > > + > > + * If the cpus node's #address-cells value is 2: > > + > > + The first reg cell must be set to 0. > > + > > + The second reg cell bits [23:0] must be set to > > + bits [23:0] of MPIDR_EL1. > > + > > + All other bits in the reg cells must be set to 0. > > + > > + * If the cpus node's #address-cells value is 1: > > + > > + Bits [23:0] in the reg cell must be set to > > + bits [23:0] in MPIDR_EL1. > > + > > + All other bits in the reg cell must be 0. > > + > > + - On systems running the OS in AArch64: > > + > > + * If the cpus node's #address-cells value is 2: > > + > > + The first reg cell bits [7:0] must be set to > > + bits [39:32] of MPIDR_EL1. > > + > > + The second reg cell bits [23:0] must be set to > > + bits [23:0] of MPIDR_EL1. > > + > > + All other bits in the reg cells must be set to 0. > > + > > + * If the cpus node's #address-cells value is 1: > > + > > + MPIDR_EL1[63:32] is 0 on all processors in the > > + system. > > Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then > #address-cells can be 1. You could say the upper bits are ignored and > treated as 0. However, you should simplify all this and just mandate > that #address-cells must be 2 for ARMv8 or more generally must match > the size of the MPIDR. If we want to boot a 32-bit kernel, then the > kernel will have to adapt to support this. Fair enough I will see how I can reword it. > > + > > + The reg cell bits [23:0] must be set to > > + bits [23:0] of MPIDR_EL1. > > + > > + All other bits in the reg cell must be set to 0. > > + > > + - compatible: > > + Usage: required > > + Value type: <string> > > + Definition: should be one of: > > + "arm,arm710t" > > + "arm,arm720t" > > + "arm,arm740t" > > + "arm,arm7ej-s" > > + "arm,arm7tdmi" > > + "arm,arm7tdmi-s" > > + "arm,arm9es" > > + "arm,arm9ej-s" > > + "arm,arm920t" > > + "arm,arm922t" > > + "arm,arm925" > > + "arm,arm926e-s" > > + "arm,arm926ej-s" > > + "arm,arm940t" > > + "arm,arm946e-s" > > + "arm,arm966e-s" > > + "arm,arm968e-s" > > + "arm,arm9tdmi" > > + "arm,arm1020e" > > + "arm,arm1020t" > > + "arm,arm1022e" > > + "arm,arm1026ej-s" > > + "arm,arm1136j-s" > > + "arm,arm1136jf-s" > > + "arm,arm1156t2-s" > > + "arm,arm1156t2f-s" > > + "arm,arm1176jzf" > > + "arm,arm1176jz-s" > > + "arm,arm1176jzf-s" > > + "arm,arm11mpcore" > > + "arm,cortex-a5" > > + "arm,cortex-a7" > > + "arm,cortex-a8" > > + "arm,cortex-a9" > > + "arm,cortex-a15" > > + "arm,cortex-a53" > > + "arm,cortex-a57" > > + "arm,cortex-m0" > > + "arm,cortex-m0+" > > + "arm,cortex-m1" > > + "arm,cortex-m3" > > + "arm,cortex-m4" > > + "arm,cortex-r4" > > + "arm,cortex-r5" > > + "arm,cortex-r7" > > + "faraday,fa526" > > + "intel,sa110" > > + "intel,sa1100" > > + "marvell,feroceon" > > + "marvell,mohawk" > > + "marvell,pj4" > > + "marvell,sheeva-v7" > > + "marvell,xsc3" > > + "marvell,xscale" > > + "qcom,krait" > > + "qcom,scorpion" > > + - enable-method > > + Value type: <stringlist> > > + Usage and definition depend on ARM architecture version and > > + configuration: > > + # On ARM v8 64-bit systems running the OS in AArch64, > > Again, the DTS can't depend on the OS type. It was meant to make it dependent on the execution state. > > + this property is required and must be one of: > > + "spin-table" > > + "psci" > > + # On ARM 32-bit systems or ARM v8 systems running > > + the OS in AArch32 this property is prohibited. > > I still don't get the distinction between 32 and 64 bit here. On > 32-bit, you have 3 choices: psci, spin-table, or SoC specific. So make > this property optional for 32-bit and mandatory for 64-bit. Ok. > > + > > + - cpu-release-addr > > + Usage: required for systems that have an "enable-method" > > + property value of "spin-table". > > + Value type: <prop-encoded-array> > > + Definition: > > + # On ARM v8 64-bit systems must be a two cell > > + property identifying a 64-bit zero-initialised > > + memory location. > > As I mentioned previously, isn't some wake-up method needed? Most > systems will be in wfi or wfe rather than continuously spinning. Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some thought. Thanks, Lorenzo
WARNING: multiple messages have this Message-ID (diff)
From: lorenzo.pieralisi@arm.com (Lorenzo Pieralisi) To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates Date: Mon, 15 Jul 2013 10:34:06 +0100 [thread overview] Message-ID: <20130715093406.GC15904@e102568-lin.cambridge.arm.com> (raw) In-Reply-To: <CAL_JsqLANi5UoVyRMsa6XoQ+_KnmTQDfTz++shEh-dZ3FQGZaQ@mail.gmail.com> On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote: > On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi > <lorenzo.pieralisi@arm.com> wrote: > > In order to extend the current cpu nodes bindings to newer CPUs > > inclusive of AArch64 and to update support for older ARM CPUs this > > patch updates device tree documentation for the cpu nodes bindings. > > Sorry for the long delay on this, but I'm still not happy with the binding here. I had to ask Russell again to drop the bindings patches from the patch system, and this is not acceptable since two months have passed and the entire series was reviewed, acked and partially merged. I will review these bindings again but I would like to understand who should give the final go ahead to get these patches queued for upstreaming, I can't continue updating this stuff forever. > > Main changes: > > - adds 64-bit bindings > > - define usage of #address-cells > > - define 32/64 dts compatibility settings > > - defines behaviour on pre and post v7 uniprocessor systems > > - adds ARM 11MPcore specific reg property definition > > > > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> > > --- > > Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++--- > > 1 file changed, 412 insertions(+), 47 deletions(-) > > [snip] > > > + # On ARM v8 64-bit systems, where the reg property > > + size can be 1 or 2 cells (as defined by cpus node's > > + #address-cells property), this property is > > + required and matches: > > + > > + - On systems running the OS in AArch32: > > The DTS cannot change based on 32-bit or 64-bit OS. "On systems running the OS in AArch32" implies a dependency on the HW execution state. Since the DT is used to configure OSs I thought that could be a valid sentence. Unfortunately this stuff is not C, so I reiterate my point above, before changing it I would like to understand who should say the wording is ok otherwise we could argue forever. > > + > > + * If the cpus node's #address-cells value is 2: > > + > > + The first reg cell must be set to 0. > > + > > + The second reg cell bits [23:0] must be set to > > + bits [23:0] of MPIDR_EL1. > > + > > + All other bits in the reg cells must be set to 0. > > + > > + * If the cpus node's #address-cells value is 1: > > + > > + Bits [23:0] in the reg cell must be set to > > + bits [23:0] in MPIDR_EL1. > > + > > + All other bits in the reg cell must be 0. > > + > > + - On systems running the OS in AArch64: > > + > > + * If the cpus node's #address-cells value is 2: > > + > > + The first reg cell bits [7:0] must be set to > > + bits [39:32] of MPIDR_EL1. > > + > > + The second reg cell bits [23:0] must be set to > > + bits [23:0] of MPIDR_EL1. > > + > > + All other bits in the reg cells must be set to 0. > > + > > + * If the cpus node's #address-cells value is 1: > > + > > + MPIDR_EL1[63:32] is 0 on all processors in the > > + system. > > Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then > #address-cells can be 1. You could say the upper bits are ignored and > treated as 0. However, you should simplify all this and just mandate > that #address-cells must be 2 for ARMv8 or more generally must match > the size of the MPIDR. If we want to boot a 32-bit kernel, then the > kernel will have to adapt to support this. Fair enough I will see how I can reword it. > > + > > + The reg cell bits [23:0] must be set to > > + bits [23:0] of MPIDR_EL1. > > + > > + All other bits in the reg cell must be set to 0. > > + > > + - compatible: > > + Usage: required > > + Value type: <string> > > + Definition: should be one of: > > + "arm,arm710t" > > + "arm,arm720t" > > + "arm,arm740t" > > + "arm,arm7ej-s" > > + "arm,arm7tdmi" > > + "arm,arm7tdmi-s" > > + "arm,arm9es" > > + "arm,arm9ej-s" > > + "arm,arm920t" > > + "arm,arm922t" > > + "arm,arm925" > > + "arm,arm926e-s" > > + "arm,arm926ej-s" > > + "arm,arm940t" > > + "arm,arm946e-s" > > + "arm,arm966e-s" > > + "arm,arm968e-s" > > + "arm,arm9tdmi" > > + "arm,arm1020e" > > + "arm,arm1020t" > > + "arm,arm1022e" > > + "arm,arm1026ej-s" > > + "arm,arm1136j-s" > > + "arm,arm1136jf-s" > > + "arm,arm1156t2-s" > > + "arm,arm1156t2f-s" > > + "arm,arm1176jzf" > > + "arm,arm1176jz-s" > > + "arm,arm1176jzf-s" > > + "arm,arm11mpcore" > > + "arm,cortex-a5" > > + "arm,cortex-a7" > > + "arm,cortex-a8" > > + "arm,cortex-a9" > > + "arm,cortex-a15" > > + "arm,cortex-a53" > > + "arm,cortex-a57" > > + "arm,cortex-m0" > > + "arm,cortex-m0+" > > + "arm,cortex-m1" > > + "arm,cortex-m3" > > + "arm,cortex-m4" > > + "arm,cortex-r4" > > + "arm,cortex-r5" > > + "arm,cortex-r7" > > + "faraday,fa526" > > + "intel,sa110" > > + "intel,sa1100" > > + "marvell,feroceon" > > + "marvell,mohawk" > > + "marvell,pj4" > > + "marvell,sheeva-v7" > > + "marvell,xsc3" > > + "marvell,xscale" > > + "qcom,krait" > > + "qcom,scorpion" > > + - enable-method > > + Value type: <stringlist> > > + Usage and definition depend on ARM architecture version and > > + configuration: > > + # On ARM v8 64-bit systems running the OS in AArch64, > > Again, the DTS can't depend on the OS type. It was meant to make it dependent on the execution state. > > + this property is required and must be one of: > > + "spin-table" > > + "psci" > > + # On ARM 32-bit systems or ARM v8 systems running > > + the OS in AArch32 this property is prohibited. > > I still don't get the distinction between 32 and 64 bit here. On > 32-bit, you have 3 choices: psci, spin-table, or SoC specific. So make > this property optional for 32-bit and mandatory for 64-bit. Ok. > > + > > + - cpu-release-addr > > + Usage: required for systems that have an "enable-method" > > + property value of "spin-table". > > + Value type: <prop-encoded-array> > > + Definition: > > + # On ARM v8 64-bit systems must be a two cell > > + property identifying a 64-bit zero-initialised > > + memory location. > > As I mentioned previously, isn't some wake-up method needed? Most > systems will be in wfi or wfe rather than continuously spinning. Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some thought. Thanks, Lorenzo
next prev parent reply other threads:[~2013-07-15 9:34 UTC|newest] Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-05-17 15:20 [RFC PATCH v4 00/18] ARM: DT cpu bindings updates Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi [not found] ` <1368804061-4421-4-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> 2013-05-17 16:07 ` Nicolas Pitre 2013-05-17 16:07 ` Nicolas Pitre 2013-07-12 14:47 ` Rob Herring 2013-07-12 14:47 ` Rob Herring [not found] ` <CAL_JsqLANi5UoVyRMsa6XoQ+_KnmTQDfTz++shEh-dZ3FQGZaQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2013-07-15 9:34 ` Lorenzo Pieralisi [this message] 2013-07-15 9:34 ` Lorenzo Pieralisi [not found] ` <20130715093406.GC15904-7AyDDHkRsp3ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org> 2013-07-15 18:50 ` Rob Herring 2013-07-15 18:50 ` Rob Herring [not found] ` <51E44486.7050806-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2013-07-16 9:45 ` Lorenzo Pieralisi 2013-07-16 9:45 ` Lorenzo Pieralisi [not found] ` <20130716094508.GA28503-7AyDDHkRsp3ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org> 2013-07-17 3:22 ` Rob Herring 2013-07-17 3:22 ` Rob Herring 2013-07-16 11:25 ` Dave Martin 2013-07-16 11:25 ` Dave Martin [not found] ` <1368804061-4421-1-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> 2013-05-17 15:20 ` [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi [not found] ` <1368804061-4421-2-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> 2013-05-17 15:49 ` Nicolas Pitre 2013-05-17 15:49 ` Nicolas Pitre 2013-05-17 16:31 ` Rob Herring 2013-05-17 16:31 ` Rob Herring [not found] ` <CAL_JsqLdbbsBeEaUT5BcxjZnbjEiu=qsPsynxCXdgi1J=ejzTg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2013-05-17 17:04 ` Lorenzo Pieralisi 2013-05-17 17:04 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default initialization Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi [not found] ` <1368804061-4421-3-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> 2013-05-17 15:46 ` Nicolas Pitre 2013-05-17 15:46 ` Nicolas Pitre 2013-05-17 15:20 ` [RFC PATCH v4 04/18] ARM: dts: am33xx: cpus/cpu nodes dts updates Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi [not found] ` <1368804061-4421-6-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> 2013-05-17 17:16 ` Gregory CLEMENT 2013-05-17 17:16 ` Gregory CLEMENT 2013-05-17 15:20 ` [RFC PATCH v4 06/18] ARM: dts: at91: " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 07/18] ARM: dts: exynos5440: cpus/cpu nodes " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 08/18] ARM: dts: imx: " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 09/18] ARM: dts: lpc32xx: " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 10/18] ARM: dts: omap: " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 11/18] ARM: dts: picoxcell: " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 12/18] ARM: dts: prima2: cpus/cpu node " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 13/18] ARM: dts: pxa2xx: cpus/cpu nodes " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 14/18] ARM: dts: r8a7740: " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 15/18] ARM: dts: sh7372: " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:20 ` [RFC PATCH v4 16/18] ARM: dts: spear: " Lorenzo Pieralisi 2013-05-17 15:20 ` Lorenzo Pieralisi 2013-05-17 15:21 ` [RFC PATCH v4 17/18] ARM: dts: sunxi: " Lorenzo Pieralisi 2013-05-17 15:21 ` Lorenzo Pieralisi 2013-05-17 15:21 ` [RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings update Lorenzo Pieralisi 2013-05-17 15:21 ` Lorenzo Pieralisi [not found] ` <1368804061-4421-19-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> 2013-05-17 16:22 ` Nicolas Pitre 2013-05-17 16:22 ` Nicolas Pitre
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