* [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest
@ 2013-07-24 16:01 Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 01/14] hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h Michael S. Tsirkin
` (15 more replies)
0 siblings, 16 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:01 UTC (permalink / raw)
To: qemu-devel, Anthony Liguori
This code can also be found here:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi
Please review, and consider for 1.6.
Changes from v2 repost:
- address comment by Anthony - convert to use APIs implemented
using QOM
- address comment by Anthony - avoid tricky pointer path,
use GArray from glib instead
- Address lots of comments by Hu Tao and Laszlo Ersek
- rebase to latest bits
Changes from v2:
- added missing patches to make it actually build
Changes from v1 RFC:
- added code to address cross version compatibility
- rebased to latest bits
- updated seabios code to latest bits (added pvpanic device)
This patchset moves all generation of ACPI tables
from guest BIOS to the hypervisor.
Although ACPI tables come from a system BIOS on real hw,
it makes sense that the ACPI tables are coupled with the
virtual machine, since they have to abstract the x86 machine to
the OS's.
This is widely desired as a way to avoid the churn
and proliferation of QEMU-specific interfaces
associated with ACPI tables in bios code.
There's a bit of code duplication where we
already declare similar acpi structures in qemu.
I think it's best to do it in this order: port
code directly, and apply cleanups and reduce duplication
that results, on top.
This way it's much easier to see that we don't introduce
regressions.
In particular, I booted a guest on qemu with and without the
change, and verified that ACPI tables are
unchanged except for trivial pointer address changes.
Such binary compatibility makes it easier to be
confident that this change won't break things.
Michael S. Tsirkin (14):
hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h
i386: add ACPI table files from seabios
acpi: add rules to compile ASL source
acpi: pre-compiled ASL files
loader: use file path size from fw_cfg.h
i386: add bios linker/loader
loader: support for unmapped ROM blobs
loader: allow adding ROMs in done callbacks
i386: define pc guest info
ich9: APIs for pc guest info
piix: APIs for pc guest info
pvpanic: add API to access io port
hpet: add API to find it
i386: ACPI table generation code from seabios
configure | 9 +-
hw/acpi/ich9.c | 6 +
hw/acpi/piix4.c | 29 +-
hw/core/loader.c | 40 +-
hw/i386/Makefile.objs | 27 +
hw/i386/acpi-build.c | 907 +++++
hw/i386/acpi-defs.h | 327 ++
hw/i386/acpi-dsdt-cpu-hotplug.dsl | 93 +
hw/i386/acpi-dsdt-dbug.dsl | 41 +
hw/i386/acpi-dsdt-hpet.dsl | 51 +
hw/i386/acpi-dsdt-isa.dsl | 117 +
hw/i386/acpi-dsdt-pci-crs.dsl | 105 +
hw/i386/acpi-dsdt.dsl | 343 ++
hw/i386/acpi-dsdt.hex.generated | 4409 ++++++++++++++++++++
hw/i386/bios-linker-loader.c | 156 +
hw/i386/pc.c | 37 +-
hw/i386/pc_piix.c | 5 +
hw/i386/pc_q35.c | 3 +
hw/i386/q35-acpi-dsdt.dsl | 452 +++
hw/i386/q35-acpi-dsdt.hex.generated | 7346 ++++++++++++++++++++++++++++++++++
hw/i386/ssdt-misc.dsl | 119 +
hw/i386/ssdt-misc.hex.generated | 190 +
hw/i386/ssdt-pcihp.dsl | 51 +
hw/i386/ssdt-pcihp.hex.generated | 108 +
hw/i386/ssdt-proc.dsl | 63 +
hw/i386/ssdt-proc.hex.generated | 134 +
hw/isa/lpc_ich9.c | 19 +
hw/lm32/lm32_hwsetup.h | 2 +-
hw/mips/mips_malta.c | 2 +-
hw/misc/pvpanic.c | 11 +
hw/pci-host/piix.c | 8 +
hw/pci-host/q35.c | 10 +
hw/timer/hpet.c | 5 +
include/hw/acpi/ich9.h | 2 +
include/hw/i386/acpi-build.h | 9 +
include/hw/i386/apic.h | 2 +
include/hw/i386/bios-linker-loader.h | 26 +
include/hw/i386/ich9.h | 3 +
include/hw/i386/pc.h | 34 +
include/hw/loader.h | 5 +-
include/hw/nvram/fw_cfg.h | 4 +-
include/hw/pci-host/q35.h | 2 +
include/hw/timer/hpet.h | 2 +
include/qemu/typedefs.h | 2 +
scripts/acpi_extract.py | 362 ++
scripts/acpi_extract_preprocess.py | 51 +
scripts/update-acpi.sh | 4 +
vl.c | 3 +
48 files changed, 15721 insertions(+), 15 deletions(-)
create mode 100644 hw/i386/acpi-build.c
create mode 100644 hw/i386/acpi-defs.h
create mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl
create mode 100644 hw/i386/acpi-dsdt-dbug.dsl
create mode 100644 hw/i386/acpi-dsdt-hpet.dsl
create mode 100644 hw/i386/acpi-dsdt-isa.dsl
create mode 100644 hw/i386/acpi-dsdt-pci-crs.dsl
create mode 100644 hw/i386/acpi-dsdt.dsl
create mode 100644 hw/i386/acpi-dsdt.hex.generated
create mode 100644 hw/i386/bios-linker-loader.c
create mode 100644 hw/i386/q35-acpi-dsdt.dsl
create mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
create mode 100644 hw/i386/ssdt-misc.dsl
create mode 100644 hw/i386/ssdt-misc.hex.generated
create mode 100644 hw/i386/ssdt-pcihp.dsl
create mode 100644 hw/i386/ssdt-pcihp.hex.generated
create mode 100644 hw/i386/ssdt-proc.dsl
create mode 100644 hw/i386/ssdt-proc.hex.generated
create mode 100644 include/hw/i386/acpi-build.h
create mode 100644 include/hw/i386/bios-linker-loader.h
create mode 100755 scripts/acpi_extract.py
create mode 100755 scripts/acpi_extract_preprocess.py
create mode 100644 scripts/update-acpi.sh
--
MST
^ permalink raw reply [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 01/14] hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
@ 2013-07-24 16:01 ` Michael S. Tsirkin
2013-07-25 12:05 ` Gerd Hoffmann
2013-07-28 0:44 ` Andreas Färber
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 02/14] i386: add ACPI table files from seabios Michael S. Tsirkin
` (14 subsequent siblings)
15 siblings, 2 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori, Laszlo Ersek
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
hw/i386/pc.c | 2 --
include/hw/i386/apic.h | 2 ++
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2a87563..b0b98a8 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -75,8 +75,6 @@
#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
-#define IO_APIC_DEFAULT_ADDRESS 0xfec00000
-
#define E820_NR_ENTRIES 16
struct e820_entry {
diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h
index 1d48e02..edbb37f 100644
--- a/include/hw/i386/apic.h
+++ b/include/hw/i386/apic.h
@@ -26,6 +26,8 @@ void apic_designate_bsp(DeviceState *d);
/* pc.c */
DeviceState *cpu_get_current_apic(void);
+#define IO_APIC_DEFAULT_ADDRESS 0xfec00000
+
/* cpu.c */
bool cpu_is_bsp(X86CPU *cpu);
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 02/14] i386: add ACPI table files from seabios
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 01/14] hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h Michael S. Tsirkin
@ 2013-07-24 16:01 ` Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 03/14] acpi: add rules to compile ASL source Michael S. Tsirkin
` (13 subsequent siblings)
15 siblings, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:01 UTC (permalink / raw)
To: qemu-devel
This adds ASL code as well as scripts for processing it,
imported from seabios git tree
commit 51684b7ced75fb76776e8ee84833fcfb6ecf12dd
Will be used for runtime acpi table generation.
Note:
This patch reuses some code from SeaBIOS, which was originally under
LGPLv2 and then relicensed to GPLv3 or LGPLv3, in QEMU under GPLv2+. This
relicensing has been acked by all contributors that had contributed to the
code since the v2->v3 relicense. ACKs approving the v2+ relicensing are
listed below. The list might include ACKs from people not holding
copyright on any parts of the reused code, but it's better to err on the
side of caution and include them.
Affected SeaBIOS files (GPLv2+ license headers added)
<http://thread.gmane.org/gmane.comp.bios.coreboot.seabios/5949>:
src/acpi-dsdt-cpu-hotplug.dsl
src/acpi-dsdt-dbug.dsl
src/acpi-dsdt-hpet.dsl
src/acpi-dsdt-isa.dsl
src/acpi-dsdt-pci-crs.dsl
src/acpi.c
src/acpi.h
src/ssdt-misc.dsl
src/ssdt-pcihp.dsl
src/ssdt-proc.dsl
tools/acpi_extract.py
tools/acpi_extract_preprocess.py
Each one of the listed people agreed to the following:
> If you allow the use of your contribution in QEMU under the
> terms of GPLv2 or later as proposed by this patch,
> please respond to this mail including the line:
>
> Acked-by: Name <email address>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Jason Baron <jbaron@akamai.com>
Acked-by: David Woodhouse <David.Woodhouse@intel.com>
Acked-by: Gleb Natapov <gleb@redhat.com>
Acked-by: Marcelo Tosatti <mtosatti@redhat.com>
Acked-by: Dave Frodin <dave.frodin@se-eng.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Acked-by: Isaku Yamahata <yamahata@valinux.co.jp>
Acked-by: Magnus Christensson <magnus.christensson@intel.com>
Acked-by: Hu Tao <hutao@cn.fujitsu.com>
Acked-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/acpi-dsdt-cpu-hotplug.dsl | 93 ++++++++
hw/i386/acpi-dsdt-dbug.dsl | 41 ++++
hw/i386/acpi-dsdt-hpet.dsl | 51 +++++
hw/i386/acpi-dsdt-isa.dsl | 117 ++++++++++
hw/i386/acpi-dsdt-pci-crs.dsl | 105 +++++++++
hw/i386/acpi-dsdt.dsl | 343 ++++++++++++++++++++++++++++
hw/i386/q35-acpi-dsdt.dsl | 452 +++++++++++++++++++++++++++++++++++++
hw/i386/ssdt-misc.dsl | 119 ++++++++++
hw/i386/ssdt-pcihp.dsl | 51 +++++
hw/i386/ssdt-proc.dsl | 63 ++++++
| 362 +++++++++++++++++++++++++++++
| 51 +++++
12 files changed, 1848 insertions(+)
create mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl
create mode 100644 hw/i386/acpi-dsdt-dbug.dsl
create mode 100644 hw/i386/acpi-dsdt-hpet.dsl
create mode 100644 hw/i386/acpi-dsdt-isa.dsl
create mode 100644 hw/i386/acpi-dsdt-pci-crs.dsl
create mode 100644 hw/i386/acpi-dsdt.dsl
create mode 100644 hw/i386/q35-acpi-dsdt.dsl
create mode 100644 hw/i386/ssdt-misc.dsl
create mode 100644 hw/i386/ssdt-pcihp.dsl
create mode 100644 hw/i386/ssdt-proc.dsl
create mode 100755 scripts/acpi_extract.py
create mode 100755 scripts/acpi_extract_preprocess.py
diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
new file mode 100644
index 0000000..c96ac42
--- /dev/null
+++ b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
@@ -0,0 +1,93 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/****************************************************************
+ * CPU hotplug
+ ****************************************************************/
+
+Scope(\_SB) {
+ /* Objects filled in by run-time generated SSDT */
+ External(NTFY, MethodObj)
+ External(CPON, PkgObj)
+
+ /* Methods called by run-time generated SSDT Processor objects */
+ Method(CPMA, 1, NotSerialized) {
+ // _MAT method - create an madt apic buffer
+ // Arg0 = Processor ID = Local APIC ID
+ // Local0 = CPON flag for this cpu
+ Store(DerefOf(Index(CPON, Arg0)), Local0)
+ // Local1 = Buffer (in madt apic form) to return
+ Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
+ // Update the processor id, lapic id, and enable/disable status
+ Store(Arg0, Index(Local1, 2))
+ Store(Arg0, Index(Local1, 3))
+ Store(Local0, Index(Local1, 4))
+ Return (Local1)
+ }
+ Method(CPST, 1, NotSerialized) {
+ // _STA method - return ON status of cpu
+ // Arg0 = Processor ID = Local APIC ID
+ // Local0 = CPON flag for this cpu
+ Store(DerefOf(Index(CPON, Arg0)), Local0)
+ If (Local0) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ Method(CPEJ, 2, NotSerialized) {
+ // _EJ0 method - eject callback
+ Sleep(200)
+ }
+
+ /* CPU hotplug notify method */
+ OperationRegion(PRST, SystemIO, 0xaf00, 32)
+ Field(PRST, ByteAcc, NoLock, Preserve) {
+ PRS, 256
+ }
+ Method(PRSC, 0) {
+ // Local5 = active cpu bitmap
+ Store(PRS, Local5)
+ // Local2 = last read byte from bitmap
+ Store(Zero, Local2)
+ // Local0 = Processor ID / APIC ID iterator
+ Store(Zero, Local0)
+ While (LLess(Local0, SizeOf(CPON))) {
+ // Local1 = CPON flag for this cpu
+ Store(DerefOf(Index(CPON, Local0)), Local1)
+ If (And(Local0, 0x07)) {
+ // Shift down previously read bitmap byte
+ ShiftRight(Local2, 1, Local2)
+ } Else {
+ // Read next byte from cpu bitmap
+ Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
+ }
+ // Local3 = active state for this cpu
+ Store(And(Local2, 1), Local3)
+
+ If (LNotEqual(Local1, Local3)) {
+ // State change - update CPON with new state
+ Store(Local3, Index(CPON, Local0))
+ // Do CPU notify
+ If (LEqual(Local3, 1)) {
+ NTFY(Local0, 1)
+ } Else {
+ NTFY(Local0, 3)
+ }
+ }
+ Increment(Local0)
+ }
+ }
+}
diff --git a/hw/i386/acpi-dsdt-dbug.dsl b/hw/i386/acpi-dsdt-dbug.dsl
new file mode 100644
index 0000000..86230f7
--- /dev/null
+++ b/hw/i386/acpi-dsdt-dbug.dsl
@@ -0,0 +1,41 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/****************************************************************
+ * Debugging
+ ****************************************************************/
+
+Scope(\) {
+ /* Debug Output */
+ OperationRegion(DBG, SystemIO, 0x0402, 0x01)
+ Field(DBG, ByteAcc, NoLock, Preserve) {
+ DBGB, 8,
+ }
+
+ /* Debug method - use this method to send output to the QEMU
+ * BIOS debug port. This method handles strings, integers,
+ * and buffers. For example: DBUG("abc") DBUG(0x123) */
+ Method(DBUG, 1) {
+ ToHexString(Arg0, Local0)
+ ToBuffer(Local0, Local0)
+ Subtract(SizeOf(Local0), 1, Local1)
+ Store(Zero, Local2)
+ While (LLess(Local2, Local1)) {
+ Store(DerefOf(Index(Local0, Local2)), DBGB)
+ Increment(Local2)
+ }
+ Store(0x0A, DBGB)
+ }
+}
diff --git a/hw/i386/acpi-dsdt-hpet.dsl b/hw/i386/acpi-dsdt-hpet.dsl
new file mode 100644
index 0000000..dfde174
--- /dev/null
+++ b/hw/i386/acpi-dsdt-hpet.dsl
@@ -0,0 +1,51 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/****************************************************************
+ * HPET
+ ****************************************************************/
+
+Scope(\_SB) {
+ Device(HPET) {
+ Name(_HID, EISAID("PNP0103"))
+ Name(_UID, 0)
+ OperationRegion(HPTM, SystemMemory, 0xFED00000, 0x400)
+ Field(HPTM, DWordAcc, Lock, Preserve) {
+ VEND, 32,
+ PRD, 32,
+ }
+ Method(_STA, 0, NotSerialized) {
+ Store(VEND, Local0)
+ Store(PRD, Local1)
+ ShiftRight(Local0, 16, Local0)
+ If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) {
+ Return (0x0)
+ }
+ If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) {
+ Return (0x0)
+ }
+ Return (0x0F)
+ }
+ Name(_CRS, ResourceTemplate() {
+#if 0 /* This makes WinXP BSOD for not yet figured reasons. */
+ IRQNoFlags() {2, 8}
+#endif
+ Memory32Fixed(ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+}
diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl
new file mode 100644
index 0000000..89caa16
--- /dev/null
+++ b/hw/i386/acpi-dsdt-isa.dsl
@@ -0,0 +1,117 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Common legacy ISA style devices. */
+Scope(\_SB.PCI0.ISA) {
+
+ Device(RTC) {
+ Name(_HID, EisaId("PNP0B00"))
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0070, 0x0070, 0x10, 0x02)
+ IRQNoFlags() { 8 }
+ IO(Decode16, 0x0072, 0x0072, 0x02, 0x06)
+ })
+ }
+
+ Device(KBD) {
+ Name(_HID, EisaId("PNP0303"))
+ Method(_STA, 0, NotSerialized) {
+ Return (0x0f)
+ }
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO(Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags() { 1 }
+ })
+ }
+
+ Device(MOU) {
+ Name(_HID, EisaId("PNP0F13"))
+ Method(_STA, 0, NotSerialized) {
+ Return (0x0f)
+ }
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags() { 12 }
+ })
+ }
+
+ Device(FDC0) {
+ Name(_HID, EisaId("PNP0700"))
+ Method(_STA, 0, NotSerialized) {
+ Store(FDEN, Local0)
+ If (LEqual(Local0, 0)) {
+ Return (0x00)
+ } Else {
+ Return (0x0F)
+ }
+ }
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+ IO(Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+ IRQNoFlags() { 6 }
+ DMA(Compatibility, NotBusMaster, Transfer8) { 2 }
+ })
+ }
+
+ Device(LPT) {
+ Name(_HID, EisaId("PNP0400"))
+ Method(_STA, 0, NotSerialized) {
+ Store(LPEN, Local0)
+ If (LEqual(Local0, 0)) {
+ Return (0x00)
+ } Else {
+ Return (0x0F)
+ }
+ }
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0378, 0x0378, 0x08, 0x08)
+ IRQNoFlags() { 7 }
+ })
+ }
+
+ Device(COM1) {
+ Name(_HID, EisaId("PNP0501"))
+ Name(_UID, 0x01)
+ Method(_STA, 0, NotSerialized) {
+ Store(CAEN, Local0)
+ If (LEqual(Local0, 0)) {
+ Return (0x00)
+ } Else {
+ Return (0x0F)
+ }
+ }
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
+ IRQNoFlags() { 4 }
+ })
+ }
+
+ Device(COM2) {
+ Name(_HID, EisaId("PNP0501"))
+ Name(_UID, 0x02)
+ Method(_STA, 0, NotSerialized) {
+ Store(CBEN, Local0)
+ If (LEqual(Local0, 0)) {
+ Return (0x00)
+ } Else {
+ Return (0x0F)
+ }
+ }
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
+ IRQNoFlags() { 3 }
+ })
+ }
+}
diff --git a/hw/i386/acpi-dsdt-pci-crs.dsl b/hw/i386/acpi-dsdt-pci-crs.dsl
new file mode 100644
index 0000000..b375a19
--- /dev/null
+++ b/hw/i386/acpi-dsdt-pci-crs.dsl
@@ -0,0 +1,105 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* PCI CRS (current resources) definition. */
+Scope(\_SB.PCI0) {
+
+ Name(CRES, ResourceTemplate() {
+ WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x00FF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0100, // Address Length
+ ,, )
+ IO(Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0CF8, // Address Length
+ ,, , TypeStatic)
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0D00, // Address Range Minimum
+ 0xFFFF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0xF300, // Address Length
+ ,, , TypeStatic)
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x000A0000, // Address Range Minimum
+ 0x000BFFFF, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00020000, // Address Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0xE0000000, // Address Range Minimum
+ 0xFEBFFFFF, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x1EC00000, // Address Length
+ ,, PW32, AddressRangeMemory, TypeStatic)
+ })
+
+ Name(CR64, ResourceTemplate() {
+ QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x8000000000, // Address Range Minimum
+ 0xFFFFFFFFFF, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x8000000000, // Address Length
+ ,, PW64, AddressRangeMemory, TypeStatic)
+ })
+
+ Method(_CRS, 0) {
+ /* Fields provided by dynamically created ssdt */
+ External(P0S, IntObj)
+ External(P0E, IntObj)
+ External(P1V, IntObj)
+ External(P1S, BuffObj)
+ External(P1E, BuffObj)
+ External(P1L, BuffObj)
+
+ /* fixup 32bit pci io window */
+ CreateDWordField(CRES, \_SB.PCI0.PW32._MIN, PS32)
+ CreateDWordField(CRES, \_SB.PCI0.PW32._MAX, PE32)
+ CreateDWordField(CRES, \_SB.PCI0.PW32._LEN, PL32)
+ Store(P0S, PS32)
+ Store(P0E, PE32)
+ Store(Add(Subtract(P0E, P0S), 1), PL32)
+
+ If (LEqual(P1V, Zero)) {
+ Return (CRES)
+ }
+
+ /* fixup 64bit pci io window */
+ CreateQWordField(CR64, \_SB.PCI0.PW64._MIN, PS64)
+ CreateQWordField(CR64, \_SB.PCI0.PW64._MAX, PE64)
+ CreateQWordField(CR64, \_SB.PCI0.PW64._LEN, PL64)
+ Store(P1S, PS64)
+ Store(P1E, PE64)
+ Store(P1L, PL64)
+ /* add window and return result */
+ ConcatenateResTemplate(CRES, CR64, Local0)
+ Return (Local0)
+ }
+}
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
new file mode 100644
index 0000000..90efce0
--- /dev/null
+++ b/hw/i386/acpi-dsdt.dsl
@@ -0,0 +1,343 @@
+/*
+ * Bochs/QEMU ACPI DSDT ASL definition
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+ACPI_EXTRACT_ALL_CODE AcpiDsdtAmlCode
+
+DefinitionBlock (
+ "acpi-dsdt.aml", // Output Filename
+ "DSDT", // Signature
+ 0x01, // DSDT Compliance Revision
+ "BXPC", // OEMID
+ "BXDSDT", // TABLE ID
+ 0x1 // OEM Revision
+ )
+{
+
+#include "acpi-dsdt-dbug.dsl"
+
+
+/****************************************************************
+ * PCI Bus definition
+ ****************************************************************/
+
+ Scope(\_SB) {
+ Device(PCI0) {
+ Name(_HID, EisaId("PNP0A03"))
+ Name(_ADR, 0x00)
+ Name(_UID, 1)
+ }
+ }
+
+#include "acpi-dsdt-pci-crs.dsl"
+#include "acpi-dsdt-hpet.dsl"
+
+
+/****************************************************************
+ * VGA
+ ****************************************************************/
+
+ Scope(\_SB.PCI0) {
+ Device(VGA) {
+ Name(_ADR, 0x00020000)
+ OperationRegion(PCIC, PCI_Config, Zero, 0x4)
+ Field(PCIC, DWordAcc, NoLock, Preserve) {
+ VEND, 32
+ }
+ Method(_S1D, 0, NotSerialized) {
+ Return (0x00)
+ }
+ Method(_S2D, 0, NotSerialized) {
+ Return (0x00)
+ }
+ Method(_S3D, 0, NotSerialized) {
+ If (LEqual(VEND, 0x1001b36)) {
+ Return (0x03) // QXL
+ } Else {
+ Return (0x00)
+ }
+ }
+ }
+ }
+
+
+/****************************************************************
+ * PIIX4 PM
+ ****************************************************************/
+
+ Scope(\_SB.PCI0) {
+ Device(PX13) {
+ Name(_ADR, 0x00010003)
+ OperationRegion(P13C, PCI_Config, 0x00, 0xff)
+ }
+ }
+
+
+/****************************************************************
+ * PIIX3 ISA bridge
+ ****************************************************************/
+
+ Scope(\_SB.PCI0) {
+ Device(ISA) {
+ Name(_ADR, 0x00010000)
+
+ /* PIIX PCI to ISA irq remapping */
+ OperationRegion(P40C, PCI_Config, 0x60, 0x04)
+
+ /* enable bits */
+ Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) {
+ Offset(0x5f),
+ , 7,
+ LPEN, 1, // LPT
+ Offset(0x67),
+ , 3,
+ CAEN, 1, // COM1
+ , 3,
+ CBEN, 1, // COM2
+ }
+ Name(FDEN, 1)
+ }
+ }
+
+#include "acpi-dsdt-isa.dsl"
+
+
+/****************************************************************
+ * PCI hotplug
+ ****************************************************************/
+
+ Scope(\_SB.PCI0) {
+ OperationRegion(PCST, SystemIO, 0xae00, 0x08)
+ Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
+ PCIU, 32,
+ PCID, 32,
+ }
+
+ OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
+ Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
+ B0EJ, 32,
+ }
+
+ /* Methods called by bulk generated PCI devices below */
+
+ /* Methods called by hotplug devices */
+ Method(PCEJ, 1, NotSerialized) {
+ // _EJ0 method - eject callback
+ Store(ShiftLeft(1, Arg0), B0EJ)
+ Return (0x0)
+ }
+
+ /* Hotplug notification method supplied by SSDT */
+ External(\_SB.PCI0.PCNT, MethodObj)
+
+ /* PCI hotplug notify method */
+ Method(PCNF, 0) {
+ // Local0 = iterator
+ Store(Zero, Local0)
+ While (LLess(Local0, 31)) {
+ Increment(Local0)
+ If (And(PCIU, ShiftLeft(1, Local0))) {
+ PCNT(Local0, 1)
+ }
+ If (And(PCID, ShiftLeft(1, Local0))) {
+ PCNT(Local0, 3)
+ }
+ }
+ }
+ }
+
+
+/****************************************************************
+ * PCI IRQs
+ ****************************************************************/
+
+ Scope(\_SB) {
+ Scope(PCI0) {
+ Name(_PRT, Package() {
+ /* PCI IRQ routing table, example from ACPI 2.0a specification,
+ section 6.2.8.1 */
+ /* Note: we provide the same info as the PCI routing
+ table of the Bochs BIOS */
+
+#define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \
+ Package() { nr##ffff, 0, lnk0, 0 }, \
+ Package() { nr##ffff, 1, lnk1, 0 }, \
+ Package() { nr##ffff, 2, lnk2, 0 }, \
+ Package() { nr##ffff, 3, lnk3, 0 }
+
+#define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
+#define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
+#define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
+#define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
+
+ prt_slot0(0x0000),
+ /* Device 1 is power mgmt device, and can only use irq 9 */
+ prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD),
+ prt_slot2(0x0002),
+ prt_slot3(0x0003),
+ prt_slot0(0x0004),
+ prt_slot1(0x0005),
+ prt_slot2(0x0006),
+ prt_slot3(0x0007),
+ prt_slot0(0x0008),
+ prt_slot1(0x0009),
+ prt_slot2(0x000a),
+ prt_slot3(0x000b),
+ prt_slot0(0x000c),
+ prt_slot1(0x000d),
+ prt_slot2(0x000e),
+ prt_slot3(0x000f),
+ prt_slot0(0x0010),
+ prt_slot1(0x0011),
+ prt_slot2(0x0012),
+ prt_slot3(0x0013),
+ prt_slot0(0x0014),
+ prt_slot1(0x0015),
+ prt_slot2(0x0016),
+ prt_slot3(0x0017),
+ prt_slot0(0x0018),
+ prt_slot1(0x0019),
+ prt_slot2(0x001a),
+ prt_slot3(0x001b),
+ prt_slot0(0x001c),
+ prt_slot1(0x001d),
+ prt_slot2(0x001e),
+ prt_slot3(0x001f),
+ })
+ }
+
+ Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
+
+ Method(IQST, 1, NotSerialized) {
+ // _STA method - get status
+ If (And(0x80, Arg0)) {
+ Return (0x09)
+ }
+ Return (0x0B)
+ }
+ Method(IQCR, 1, NotSerialized) {
+ // _CRS method - get current settings
+ Name(PRR0, ResourceTemplate() {
+ Interrupt(, Level, ActiveHigh, Shared) { 0 }
+ })
+ CreateDWordField(PRR0, 0x05, PRRI)
+ If (LLess(Arg0, 0x80)) {
+ Store(Arg0, PRRI)
+ }
+ Return (PRR0)
+ }
+
+#define define_link(link, uid, reg) \
+ Device(link) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, uid) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(, Level, ActiveHigh, Shared) { \
+ 5, 10, 11 \
+ } \
+ }) \
+ Method(_STA, 0, NotSerialized) { \
+ Return (IQST(reg)) \
+ } \
+ Method(_DIS, 0, NotSerialized) { \
+ Or(reg, 0x80, reg) \
+ } \
+ Method(_CRS, 0, NotSerialized) { \
+ Return (IQCR(reg)) \
+ } \
+ Method(_SRS, 1, NotSerialized) { \
+ CreateDWordField(Arg0, 0x05, PRRI) \
+ Store(PRRI, reg) \
+ } \
+ }
+
+ define_link(LNKA, 0, PRQ0)
+ define_link(LNKB, 1, PRQ1)
+ define_link(LNKC, 2, PRQ2)
+ define_link(LNKD, 3, PRQ3)
+
+ Device(LNKS) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+ Name(_PRS, ResourceTemplate() {
+ Interrupt(, Level, ActiveHigh, Shared) { 9 }
+ })
+
+ // The SCI cannot be disabled and is always attached to GSI 9,
+ // so these are no-ops. We only need this link to override the
+ // polarity to active high and match the content of the MADT.
+ Method(_STA, 0, NotSerialized) { Return (0x0b) }
+ Method(_DIS, 0, NotSerialized) { }
+ Method(_CRS, 0, NotSerialized) { Return (_PRS) }
+ Method(_SRS, 1, NotSerialized) { }
+ }
+ }
+
+#include "acpi-dsdt-cpu-hotplug.dsl"
+
+
+/****************************************************************
+ * General purpose events
+ ****************************************************************/
+
+ Scope(\_GPE) {
+ Name(_HID, "ACPI0006")
+
+ Method(_L00) {
+ }
+ Method(_E01) {
+ // PCI hotplug event
+ \_SB.PCI0.PCNF()
+ }
+ Method(_E02) {
+ // CPU hotplug event
+ \_SB.PRSC()
+ }
+ Method(_L03) {
+ }
+ Method(_L04) {
+ }
+ Method(_L05) {
+ }
+ Method(_L06) {
+ }
+ Method(_L07) {
+ }
+ Method(_L08) {
+ }
+ Method(_L09) {
+ }
+ Method(_L0A) {
+ }
+ Method(_L0B) {
+ }
+ Method(_L0C) {
+ }
+ Method(_L0D) {
+ }
+ Method(_L0E) {
+ }
+ Method(_L0F) {
+ }
+ }
+}
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
new file mode 100644
index 0000000..21c89b0
--- /dev/null
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -0,0 +1,452 @@
+/*
+ * Bochs/QEMU ACPI DSDT ASL definition
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+/*
+ * Copyright (c) 2010 Isaku Yamahata
+ * yamahata at valinux co jp
+ * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
+ */
+
+ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
+
+DefinitionBlock (
+ "q35-acpi-dsdt.aml",// Output Filename
+ "DSDT", // Signature
+ 0x01, // DSDT Compliance Revision
+ "BXPC", // OEMID
+ "BXDSDT", // TABLE ID
+ 0x2 // OEM Revision
+ )
+{
+
+#include "acpi-dsdt-dbug.dsl"
+
+ Scope(\_SB) {
+ OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
+ OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
+ Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
+ PCIB, 8,
+ }
+ }
+
+
+/****************************************************************
+ * PCI Bus definition
+ ****************************************************************/
+
+ Scope(\_SB) {
+ Device(PCI0) {
+ Name(_HID, EisaId("PNP0A08"))
+ Name(_CID, EisaId("PNP0A03"))
+ Name(_ADR, 0x00)
+ Name(_UID, 1)
+
+ // _OSC: based on sample of ACPI3.0b spec
+ Name(SUPP, 0) // PCI _OSC Support Field value
+ Name(CTRL, 0) // PCI _OSC Control Field value
+ Method(_OSC, 4) {
+ // Create DWORD-addressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3, 0, CDW1)
+
+ // Check for proper UUID
+ If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWORD-addressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3, 4, CDW2)
+ CreateDWordField(Arg3, 8, CDW3)
+
+ // Save Capabilities DWORD2 & 3
+ Store(CDW2, SUPP)
+ Store(CDW3, CTRL)
+
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL, 0x1D, CTRL)
+
+#if 0 // For now, nothing to do
+ If (Not(And(CDW1, 1))) { // Query flag clear?
+ // Disable GPEs for features granted native control.
+ If (And(CTRL, 0x01)) { // Hot plug control granted?
+ Store(0, HPCE) // clear the hot plug SCI enable bit
+ Store(1, HPCS) // clear the hot plug SCI status bit
+ }
+ If (And(CTRL, 0x04)) { // PME control granted?
+ Store(0, PMCE) // clear the PME SCI enable bit
+ Store(1, PMCS) // clear the PME SCI status bit
+ }
+ If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
+ // Set status to not restore PCI Express cap structure
+ // upon resume from S3
+ Store(1, S3CR)
+ }
+ }
+#endif
+ If (LNotEqual(Arg1, One)) {
+ // Unknown revision
+ Or(CDW1, 0x08, CDW1)
+ }
+ If (LNotEqual(CDW3, CTRL)) {
+ // Capabilities bits were masked
+ Or(CDW1, 0x10, CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL, CDW3)
+ } Else {
+ Or(CDW1, 4, CDW1) // Unrecognized UUID
+ }
+ Return (Arg3)
+ }
+ }
+ }
+
+#include "acpi-dsdt-pci-crs.dsl"
+#include "acpi-dsdt-hpet.dsl"
+
+
+/****************************************************************
+ * VGA
+ ****************************************************************/
+
+ Scope(\_SB.PCI0) {
+ Device(VGA) {
+ Name(_ADR, 0x00010000)
+ Method(_S1D, 0, NotSerialized) {
+ Return (0x00)
+ }
+ Method(_S2D, 0, NotSerialized) {
+ Return (0x00)
+ }
+ Method(_S3D, 0, NotSerialized) {
+ Return (0x00)
+ }
+ }
+ }
+
+
+/****************************************************************
+ * LPC ISA bridge
+ ****************************************************************/
+
+ Scope(\_SB.PCI0) {
+ /* PCI D31:f0 LPC ISA bridge */
+ Device(ISA) {
+ /* PCI D31:f0 */
+ Name(_ADR, 0x001f0000)
+
+ /* ICH9 PCI to ISA irq remapping */
+ OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
+
+ OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
+ Field(LPCD, AnyAcc, NoLock, Preserve) {
+ COMA, 3,
+ , 1,
+ COMB, 3,
+
+ Offset(0x01),
+ LPTD, 2,
+ , 2,
+ FDCD, 2
+ }
+ OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
+ Field(LPCE, AnyAcc, NoLock, Preserve) {
+ CAEN, 1,
+ CBEN, 1,
+ LPEN, 1,
+ FDEN, 1
+ }
+ }
+ }
+
+#include "acpi-dsdt-isa.dsl"
+
+
+/****************************************************************
+ * PCI IRQs
+ ****************************************************************/
+
+ /* Zero => PIC mode, One => APIC Mode */
+ Name(\PICF, Zero)
+ Method(\_PIC, 1, NotSerialized) {
+ Store(Arg0, \PICF)
+ }
+
+ Scope(\_SB) {
+ Scope(PCI0) {
+#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
+ Package() { nr##ffff, 0, lnk0, 0 }, \
+ Package() { nr##ffff, 1, lnk1, 0 }, \
+ Package() { nr##ffff, 2, lnk2, 0 }, \
+ Package() { nr##ffff, 3, lnk3, 0 }
+
+#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
+#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
+#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
+#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
+
+#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
+#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
+#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
+#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
+
+ Name(PRTP, package() {
+ prt_slot_lnkE(0x0000),
+ prt_slot_lnkF(0x0001),
+ prt_slot_lnkG(0x0002),
+ prt_slot_lnkH(0x0003),
+ prt_slot_lnkE(0x0004),
+ prt_slot_lnkF(0x0005),
+ prt_slot_lnkG(0x0006),
+ prt_slot_lnkH(0x0007),
+ prt_slot_lnkE(0x0008),
+ prt_slot_lnkF(0x0009),
+ prt_slot_lnkG(0x000a),
+ prt_slot_lnkH(0x000b),
+ prt_slot_lnkE(0x000c),
+ prt_slot_lnkF(0x000d),
+ prt_slot_lnkG(0x000e),
+ prt_slot_lnkH(0x000f),
+ prt_slot_lnkE(0x0010),
+ prt_slot_lnkF(0x0011),
+ prt_slot_lnkG(0x0012),
+ prt_slot_lnkH(0x0013),
+ prt_slot_lnkE(0x0014),
+ prt_slot_lnkF(0x0015),
+ prt_slot_lnkG(0x0016),
+ prt_slot_lnkH(0x0017),
+ prt_slot_lnkE(0x0018),
+
+ /* INTA -> PIRQA for slot 25 - 31
+ see the default value of D<N>IR */
+ prt_slot_lnkA(0x0019),
+ prt_slot_lnkA(0x001a),
+ prt_slot_lnkA(0x001b),
+ prt_slot_lnkA(0x001c),
+ prt_slot_lnkA(0x001d),
+
+ /* PCIe->PCI bridge. use PIRQ[E-H] */
+ prt_slot_lnkE(0x001e),
+
+ prt_slot_lnkA(0x001f)
+ })
+
+#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
+ Package() { nr##ffff, 0, gsi0, 0 }, \
+ Package() { nr##ffff, 1, gsi1, 0 }, \
+ Package() { nr##ffff, 2, gsi2, 0 }, \
+ Package() { nr##ffff, 3, gsi3, 0 }
+
+#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
+#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
+#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
+#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
+
+#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
+#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
+#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
+#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
+
+ Name(PRTA, package() {
+ prt_slot_gsiE(0x0000),
+ prt_slot_gsiF(0x0001),
+ prt_slot_gsiG(0x0002),
+ prt_slot_gsiH(0x0003),
+ prt_slot_gsiE(0x0004),
+ prt_slot_gsiF(0x0005),
+ prt_slot_gsiG(0x0006),
+ prt_slot_gsiH(0x0007),
+ prt_slot_gsiE(0x0008),
+ prt_slot_gsiF(0x0009),
+ prt_slot_gsiG(0x000a),
+ prt_slot_gsiH(0x000b),
+ prt_slot_gsiE(0x000c),
+ prt_slot_gsiF(0x000d),
+ prt_slot_gsiG(0x000e),
+ prt_slot_gsiH(0x000f),
+ prt_slot_gsiE(0x0010),
+ prt_slot_gsiF(0x0011),
+ prt_slot_gsiG(0x0012),
+ prt_slot_gsiH(0x0013),
+ prt_slot_gsiE(0x0014),
+ prt_slot_gsiF(0x0015),
+ prt_slot_gsiG(0x0016),
+ prt_slot_gsiH(0x0017),
+ prt_slot_gsiE(0x0018),
+
+ /* INTA -> PIRQA for slot 25 - 31, but 30
+ see the default value of D<N>IR */
+ prt_slot_gsiA(0x0019),
+ prt_slot_gsiA(0x001a),
+ prt_slot_gsiA(0x001b),
+ prt_slot_gsiA(0x001c),
+ prt_slot_gsiA(0x001d),
+
+ /* PCIe->PCI bridge. use PIRQ[E-H] */
+ prt_slot_gsiE(0x001e),
+
+ prt_slot_gsiA(0x001f)
+ })
+
+ Method(_PRT, 0, NotSerialized) {
+ /* PCI IRQ routing table, example from ACPI 2.0a specification,
+ section 6.2.8.1 */
+ /* Note: we provide the same info as the PCI routing
+ table of the Bochs BIOS */
+ If (LEqual(\PICF, Zero)) {
+ Return (PRTP)
+ } Else {
+ Return (PRTA)
+ }
+ }
+ }
+
+ Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+
+ Offset(0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method(IQST, 1, NotSerialized) {
+ // _STA method - get status
+ If (And(0x80, Arg0)) {
+ Return (0x09)
+ }
+ Return (0x0B)
+ }
+ Method(IQCR, 1, NotSerialized) {
+ // _CRS method - get current settings
+ Name(PRR0, ResourceTemplate() {
+ Interrupt(, Level, ActiveHigh, Shared) { 0 }
+ })
+ CreateDWordField(PRR0, 0x05, PRRI)
+ Store(And(Arg0, 0x0F), PRRI)
+ Return (PRR0)
+ }
+
+#define define_link(link, uid, reg) \
+ Device(link) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, uid) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(, Level, ActiveHigh, Shared) { \
+ 5, 10, 11 \
+ } \
+ }) \
+ Method(_STA, 0, NotSerialized) { \
+ Return (IQST(reg)) \
+ } \
+ Method(_DIS, 0, NotSerialized) { \
+ Or(reg, 0x80, reg) \
+ } \
+ Method(_CRS, 0, NotSerialized) { \
+ Return (IQCR(reg)) \
+ } \
+ Method(_SRS, 1, NotSerialized) { \
+ CreateDWordField(Arg0, 0x05, PRRI) \
+ Store(PRRI, reg) \
+ } \
+ }
+
+ define_link(LNKA, 0, PRQA)
+ define_link(LNKB, 1, PRQB)
+ define_link(LNKC, 2, PRQC)
+ define_link(LNKD, 3, PRQD)
+ define_link(LNKE, 4, PRQE)
+ define_link(LNKF, 5, PRQF)
+ define_link(LNKG, 6, PRQG)
+ define_link(LNKH, 7, PRQH)
+
+#define define_gsi_link(link, uid, gsi) \
+ Device(link) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, uid) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(, Level, ActiveHigh, Shared) { \
+ gsi \
+ } \
+ }) \
+ Name(_CRS, ResourceTemplate() { \
+ Interrupt(, Level, ActiveHigh, Shared) { \
+ gsi \
+ } \
+ }) \
+ Method(_SRS, 1, NotSerialized) { \
+ } \
+ }
+
+ define_gsi_link(GSIA, 0, 0x10)
+ define_gsi_link(GSIB, 0, 0x11)
+ define_gsi_link(GSIC, 0, 0x12)
+ define_gsi_link(GSID, 0, 0x13)
+ define_gsi_link(GSIE, 0, 0x14)
+ define_gsi_link(GSIF, 0, 0x15)
+ define_gsi_link(GSIG, 0, 0x16)
+ define_gsi_link(GSIH, 0, 0x17)
+ }
+
+#include "acpi-dsdt-cpu-hotplug.dsl"
+
+
+/****************************************************************
+ * General purpose events
+ ****************************************************************/
+
+ Scope(\_GPE) {
+ Name(_HID, "ACPI0006")
+
+ Method(_L00) {
+ }
+ Method(_L01) {
+ // CPU hotplug event
+ \_SB.PRSC()
+ }
+ Method(_L02) {
+ }
+ Method(_L03) {
+ }
+ Method(_L04) {
+ }
+ Method(_L05) {
+ }
+ Method(_L06) {
+ }
+ Method(_L07) {
+ }
+ Method(_L08) {
+ }
+ Method(_L09) {
+ }
+ Method(_L0A) {
+ }
+ Method(_L0B) {
+ }
+ Method(_L0C) {
+ }
+ Method(_L0D) {
+ }
+ Method(_L0E) {
+ }
+ Method(_L0F) {
+ }
+ }
+}
diff --git a/hw/i386/ssdt-misc.dsl b/hw/i386/ssdt-misc.dsl
new file mode 100644
index 0000000..a4484b8
--- /dev/null
+++ b/hw/i386/ssdt-misc.dsl
@@ -0,0 +1,119 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+ACPI_EXTRACT_ALL_CODE ssdp_misc_aml
+
+DefinitionBlock ("ssdt-misc.aml", "SSDT", 0x01, "BXPC", "BXSSDTSUSP", 0x1)
+{
+
+/****************************************************************
+ * PCI memory ranges
+ ****************************************************************/
+
+ Scope(\) {
+ ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_start
+ Name(P0S, 0x12345678)
+ ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_end
+ Name(P0E, 0x12345678)
+ ACPI_EXTRACT_NAME_BYTE_CONST acpi_pci64_valid
+ Name(P1V, 0x12)
+ ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_start
+ Name(P1S, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+ ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_end
+ Name(P1E, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+ ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_length
+ Name(P1L, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+ }
+
+
+/****************************************************************
+ * Suspend
+ ****************************************************************/
+
+ Scope(\) {
+ /*
+ * S3 (suspend-to-ram), S4 (suspend-to-disk) and S5 (power-off) type codes:
+ * must match piix4 emulation.
+ */
+
+ ACPI_EXTRACT_NAME_STRING acpi_s3_name
+ Name(_S3, Package(0x04) {
+ One, /* PM1a_CNT.SLP_TYP */
+ One, /* PM1b_CNT.SLP_TYP */
+ Zero, /* reserved */
+ Zero /* reserved */
+ })
+ ACPI_EXTRACT_NAME_STRING acpi_s4_name
+ ACPI_EXTRACT_PKG_START acpi_s4_pkg
+ Name(_S4, Package(0x04) {
+ 0x2, /* PM1a_CNT.SLP_TYP */
+ 0x2, /* PM1b_CNT.SLP_TYP */
+ Zero, /* reserved */
+ Zero /* reserved */
+ })
+ Name(_S5, Package(0x04) {
+ Zero, /* PM1a_CNT.SLP_TYP */
+ Zero, /* PM1b_CNT.SLP_TYP */
+ Zero, /* reserved */
+ Zero /* reserved */
+ })
+ }
+
+ External(\_SB.PCI0, DeviceObj)
+ External(\_SB.PCI0.ISA, DeviceObj)
+
+ Scope(\_SB.PCI0.ISA) {
+ Device(PEVT) {
+ Name(_HID, "QEMU0001")
+ /* PEST will be patched to be Zero if no such device */
+ ACPI_EXTRACT_NAME_WORD_CONST ssdt_isa_pest
+ Name(PEST, 0xFFFF)
+ OperationRegion(PEOR, SystemIO, PEST, 0x01)
+ Field(PEOR, ByteAcc, NoLock, Preserve) {
+ PEPT, 8,
+ }
+
+ Method(_STA, 0, NotSerialized) {
+ Store(PEST, Local0)
+ If (LEqual(Local0, Zero)) {
+ Return (0x00)
+ } Else {
+ Return (0x0F)
+ }
+ }
+
+ Method(RDPT, 0, NotSerialized) {
+ Store(PEPT, Local0)
+ Return (Local0)
+ }
+
+ Method(WRPT, 1, NotSerialized) {
+ Store(Arg0, PEPT)
+ }
+
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00, 0x00, 0x01, 0x01, IO)
+ })
+
+ CreateWordField(_CRS, IO._MIN, IOMN)
+ CreateWordField(_CRS, IO._MAX, IOMX)
+
+ Method(_INI, 0, NotSerialized) {
+ Store(PEST, IOMN)
+ Store(PEST, IOMX)
+ }
+ }
+ }
+}
diff --git a/hw/i386/ssdt-pcihp.dsl b/hw/i386/ssdt-pcihp.dsl
new file mode 100644
index 0000000..d29a5b9
--- /dev/null
+++ b/hw/i386/ssdt-pcihp.dsl
@@ -0,0 +1,51 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml
+
+DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
+{
+
+/****************************************************************
+ * PCI hotplug
+ ****************************************************************/
+
+ /* Objects supplied by DSDT */
+ External(\_SB.PCI0, DeviceObj)
+ External(\_SB.PCI0.PCEJ, MethodObj)
+
+ Scope(\_SB.PCI0) {
+
+ /* Bulk generated PCI hotplug devices */
+ ACPI_EXTRACT_DEVICE_START ssdt_pcihp_start
+ ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end
+ ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name
+
+ // Method _EJ0 can be patched by BIOS to EJ0_
+ // at runtime, if the slot is detected to not support hotplug.
+ // Extract the offset of the address dword and the
+ // _EJ0 name to allow this patching.
+ Device(SAA) {
+ ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id
+ Name(_SUN, 0xAA)
+ ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr
+ Name(_ADR, 0xAA0000)
+ ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0
+ Method(_EJ0, 1) {
+ Return (PCEJ(_SUN))
+ }
+ }
+ }
+}
diff --git a/hw/i386/ssdt-proc.dsl b/hw/i386/ssdt-proc.dsl
new file mode 100644
index 0000000..58333c7
--- /dev/null
+++ b/hw/i386/ssdt-proc.dsl
@@ -0,0 +1,63 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* This file is the basis for the ssdt table generated in src/acpi.c.
+ * It defines the contents of the per-cpu Processor() object. At
+ * runtime, a dynamically generated SSDT will contain one copy of this
+ * AML snippet for every possible cpu in the system. The objects will
+ * be placed in the \_SB_ namespace.
+ *
+ * In addition to the aml code generated from this file, the
+ * src/acpi.c file creates a NTFY method with an entry for each cpu:
+ * Method(NTFY, 2) {
+ * If (LEqual(Arg0, 0x00)) { Notify(CP00, Arg1) }
+ * If (LEqual(Arg0, 0x01)) { Notify(CP01, Arg1) }
+ * ...
+ * }
+ * and a CPON array with the list of active and inactive cpus:
+ * Name(CPON, Package() { One, One, ..., Zero, Zero, ... })
+ */
+
+ACPI_EXTRACT_ALL_CODE ssdp_proc_aml
+
+DefinitionBlock ("ssdt-proc.aml", "SSDT", 0x01, "BXPC", "BXSSDT", 0x1)
+{
+ ACPI_EXTRACT_PROCESSOR_START ssdt_proc_start
+ ACPI_EXTRACT_PROCESSOR_END ssdt_proc_end
+ ACPI_EXTRACT_PROCESSOR_STRING ssdt_proc_name
+ Processor(CPAA, 0xAA, 0x0000b010, 0x06) {
+ ACPI_EXTRACT_NAME_BYTE_CONST ssdt_proc_id
+ Name(ID, 0xAA)
+/*
+ * The src/acpi.c code requires the above ACP_EXTRACT tags so that it can update
+ * CPAA and 0xAA with the appropriate CPU id (see
+ * SD_OFFSET_CPUHEX/CPUID1/CPUID2). Don't change the above without
+ * also updating the C code.
+ */
+ Name(_HID, "ACPI0007")
+ External(CPMA, MethodObj)
+ External(CPST, MethodObj)
+ External(CPEJ, MethodObj)
+ Method(_MAT, 0) {
+ Return (CPMA(ID))
+ }
+ Method(_STA, 0) {
+ Return (CPST(ID))
+ }
+ Method(_EJ0, 1, NotSerialized) {
+ CPEJ(ID, Arg0)
+ }
+ }
+}
--git a/scripts/acpi_extract.py b/scripts/acpi_extract.py
new file mode 100755
index 0000000..22ea468
--- /dev/null
+++ b/scripts/acpi_extract.py
@@ -0,0 +1,362 @@
+#!/usr/bin/python
+# Copyright (C) 2011 Red Hat, Inc., Michael S. Tsirkin <mst@redhat.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, see <http://www.gnu.org/licenses/>.
+
+# Process mixed ASL/AML listing (.lst file) produced by iasl -l
+# Locate and execute ACPI_EXTRACT directives, output offset info
+#
+# Documentation of ACPI_EXTRACT_* directive tags:
+#
+# These directive tags output offset information from AML for BIOS runtime
+# table generation.
+# Each directive is of the form:
+# ACPI_EXTRACT_<TYPE> <array_name> <Operator> (...)
+# and causes the extractor to create an array
+# named <array_name> with offset, in the generated AML,
+# of an object of a given type in the following <Operator>.
+#
+# A directive must fit on a single code line.
+#
+# Object type in AML is verified, a mismatch causes a build failure.
+#
+# Directives and operators currently supported are:
+# ACPI_EXTRACT_NAME_DWORD_CONST - extract a Dword Const object from Name()
+# ACPI_EXTRACT_NAME_WORD_CONST - extract a Word Const object from Name()
+# ACPI_EXTRACT_NAME_BYTE_CONST - extract a Byte Const object from Name()
+# ACPI_EXTRACT_METHOD_STRING - extract a NameString from Method()
+# ACPI_EXTRACT_NAME_STRING - extract a NameString from Name()
+# ACPI_EXTRACT_PROCESSOR_START - start of Processor() block
+# ACPI_EXTRACT_PROCESSOR_STRING - extract a NameString from Processor()
+# ACPI_EXTRACT_PROCESSOR_END - offset at last byte of Processor() + 1
+# ACPI_EXTRACT_PKG_START - start of Package block
+#
+# ACPI_EXTRACT_ALL_CODE - create an array storing the generated AML bytecode
+#
+# ACPI_EXTRACT is not allowed anywhere else in code, except in comments.
+
+import re;
+import sys;
+import fileinput;
+
+aml = []
+asl = []
+output = {}
+debug = ""
+
+class asl_line:
+ line = None
+ lineno = None
+ aml_offset = None
+
+def die(diag):
+ sys.stderr.write("Error: %s; %s\n" % (diag, debug))
+ sys.exit(1)
+
+#Store an ASL command, matching AML offset, and input line (for debugging)
+def add_asl(lineno, line):
+ l = asl_line()
+ l.line = line
+ l.lineno = lineno
+ l.aml_offset = len(aml)
+ asl.append(l)
+
+#Store an AML byte sequence
+#Verify that offset output by iasl matches # of bytes so far
+def add_aml(offset, line):
+ o = int(offset, 16);
+ # Sanity check: offset must match size of code so far
+ if (o != len(aml)):
+ die("Offset 0x%x != 0x%x" % (o, len(aml)))
+ # Strip any trailing dots and ASCII dump after "
+ line = re.sub(r'\s*\.*\s*".*$',"", line)
+ # Strip traling whitespace
+ line = re.sub(r'\s+$',"", line)
+ # Strip leading whitespace
+ line = re.sub(r'^\s+',"", line)
+ # Split on whitespace
+ code = re.split(r'\s+', line)
+ for c in code:
+ # Require a legal hex number, two digits
+ if (not(re.search(r'^[0-9A-Fa-f][0-9A-Fa-f]$', c))):
+ die("Unexpected octet %s" % c);
+ aml.append(int(c, 16));
+
+# Process aml bytecode array, decoding AML
+def aml_pkglen_bytes(offset):
+ # PkgLength can be multibyte. Bits 8-7 give the # of extra bytes.
+ pkglenbytes = aml[offset] >> 6;
+ return pkglenbytes + 1
+
+def aml_pkglen(offset):
+ pkgstart = offset
+ pkglenbytes = aml_pkglen_bytes(offset)
+ pkglen = aml[offset] & 0x3F
+ # If multibyte, first nibble only uses bits 0-3
+ if ((pkglenbytes > 1) and (pkglen & 0x30)):
+ die("PkgLen bytes 0x%x but first nibble 0x%x expected 0x0X" %
+ (pkglen, pkglen))
+ offset += 1
+ pkglenbytes -= 1
+ for i in range(pkglenbytes):
+ pkglen |= aml[offset + i] << (i * 8 + 4)
+ if (len(aml) < pkgstart + pkglen):
+ die("PckgLen 0x%x at offset 0x%x exceeds AML size 0x%x" %
+ (pkglen, offset, len(aml)))
+ return pkglen
+
+# Given method offset, find its NameString offset
+def aml_method_string(offset):
+ #0x14 MethodOp PkgLength NameString MethodFlags TermList
+ if (aml[offset] != 0x14):
+ die( "Method offset 0x%x: expected 0x14 actual 0x%x" %
+ (offset, aml[offset]));
+ offset += 1;
+ pkglenbytes = aml_pkglen_bytes(offset)
+ offset += pkglenbytes;
+ return offset;
+
+# Given name offset, find its NameString offset
+def aml_name_string(offset):
+ #0x08 NameOp NameString DataRef
+ if (aml[offset] != 0x08):
+ die( "Name offset 0x%x: expected 0x08 actual 0x%x" %
+ (offset, aml[offset]));
+ offset += 1
+ # Block Name Modifier. Skip it.
+ if (aml[offset] == 0x5c or aml[offset] == 0x5e):
+ offset += 1
+ return offset;
+
+# Given data offset, find 8 byte buffer offset
+def aml_data_buffer8(offset):
+ #0x08 NameOp NameString DataRef
+ expect = [0x11, 0x0B, 0x0A, 0x08]
+ if (aml[offset:offset+4] != expect):
+ die( "Name offset 0x%x: expected %s actual %s" %
+ (offset, aml[offset:offset+4], expect))
+ return offset + len(expect)
+
+# Given data offset, find dword const offset
+def aml_data_dword_const(offset):
+ #0x08 NameOp NameString DataRef
+ if (aml[offset] != 0x0C):
+ die( "Name offset 0x%x: expected 0x0C actual 0x%x" %
+ (offset, aml[offset]));
+ return offset + 1;
+
+# Given data offset, find word const offset
+def aml_data_word_const(offset):
+ #0x08 NameOp NameString DataRef
+ if (aml[offset] != 0x0B):
+ die( "Name offset 0x%x: expected 0x0B actual 0x%x" %
+ (offset, aml[offset]));
+ return offset + 1;
+
+# Given data offset, find byte const offset
+def aml_data_byte_const(offset):
+ #0x08 NameOp NameString DataRef
+ if (aml[offset] != 0x0A):
+ die( "Name offset 0x%x: expected 0x0A actual 0x%x" %
+ (offset, aml[offset]));
+ return offset + 1;
+
+# Find name'd buffer8
+def aml_name_buffer8(offset):
+ return aml_data_buffer8(aml_name_string(offset) + 4)
+
+# Given name offset, find dword const offset
+def aml_name_dword_const(offset):
+ return aml_data_dword_const(aml_name_string(offset) + 4)
+
+# Given name offset, find word const offset
+def aml_name_word_const(offset):
+ return aml_data_word_const(aml_name_string(offset) + 4)
+
+# Given name offset, find byte const offset
+def aml_name_byte_const(offset):
+ return aml_data_byte_const(aml_name_string(offset) + 4)
+
+def aml_device_start(offset):
+ #0x5B 0x82 DeviceOp PkgLength NameString
+ if ((aml[offset] != 0x5B) or (aml[offset + 1] != 0x82)):
+ die( "Name offset 0x%x: expected 0x5B 0x82 actual 0x%x 0x%x" %
+ (offset, aml[offset], aml[offset + 1]));
+ return offset
+
+def aml_device_string(offset):
+ #0x5B 0x82 DeviceOp PkgLength NameString
+ start = aml_device_start(offset)
+ offset += 2
+ pkglenbytes = aml_pkglen_bytes(offset)
+ offset += pkglenbytes
+ return offset
+
+def aml_device_end(offset):
+ start = aml_device_start(offset)
+ offset += 2
+ pkglenbytes = aml_pkglen_bytes(offset)
+ pkglen = aml_pkglen(offset)
+ return offset + pkglen
+
+def aml_processor_start(offset):
+ #0x5B 0x83 ProcessorOp PkgLength NameString ProcID
+ if ((aml[offset] != 0x5B) or (aml[offset + 1] != 0x83)):
+ die( "Name offset 0x%x: expected 0x5B 0x83 actual 0x%x 0x%x" %
+ (offset, aml[offset], aml[offset + 1]));
+ return offset
+
+def aml_processor_string(offset):
+ #0x5B 0x83 ProcessorOp PkgLength NameString ProcID
+ start = aml_processor_start(offset)
+ offset += 2
+ pkglenbytes = aml_pkglen_bytes(offset)
+ offset += pkglenbytes
+ return offset
+
+def aml_processor_end(offset):
+ start = aml_processor_start(offset)
+ offset += 2
+ pkglenbytes = aml_pkglen_bytes(offset)
+ pkglen = aml_pkglen(offset)
+ return offset + pkglen
+
+def aml_package_start(offset):
+ offset = aml_name_string(offset) + 4
+ # 0x12 PkgLength NumElements PackageElementList
+ if (aml[offset] != 0x12):
+ die( "Name offset 0x%x: expected 0x12 actual 0x%x" %
+ (offset, aml[offset]));
+ offset += 1
+ return offset + aml_pkglen_bytes(offset) + 1
+
+lineno = 0
+for line in fileinput.input():
+ # Strip trailing newline
+ line = line.rstrip();
+ # line number and debug string to output in case of errors
+ lineno = lineno + 1
+ debug = "input line %d: %s" % (lineno, line)
+ #ASL listing: space, then line#, then ...., then code
+ pasl = re.compile('^\s+([0-9]+)(:\s\s|\.\.\.\.)\s*')
+ m = pasl.search(line)
+ if (m):
+ add_asl(lineno, pasl.sub("", line));
+ # AML listing: offset in hex, then ...., then code
+ paml = re.compile('^([0-9A-Fa-f]+)(:\s\s|\.\.\.\.)\s*')
+ m = paml.search(line)
+ if (m):
+ add_aml(m.group(1), paml.sub("", line))
+
+# Now go over code
+# Track AML offset of a previous non-empty ASL command
+prev_aml_offset = -1
+for i in range(len(asl)):
+ debug = "input line %d: %s" % (asl[i].lineno, asl[i].line)
+
+ l = asl[i].line
+
+ # skip if not an extract directive
+ a = len(re.findall(r'ACPI_EXTRACT', l))
+ if (not a):
+ # If not empty, store AML offset. Will be used for sanity checks
+ # IASL seems to put {}. at random places in the listing.
+ # Ignore any non-words for the purpose of this test.
+ m = re.search(r'\w+', l)
+ if (m):
+ prev_aml_offset = asl[i].aml_offset
+ continue
+
+ if (a > 1):
+ die("Expected at most one ACPI_EXTRACT per line, actual %d" % a)
+
+ mext = re.search(r'''
+ ^\s* # leading whitespace
+ /\*\s* # start C comment
+ (ACPI_EXTRACT_\w+) # directive: group(1)
+ \s+ # whitspace separates directive from array name
+ (\w+) # array name: group(2)
+ \s*\*/ # end of C comment
+ \s*$ # trailing whitespace
+ ''', l, re.VERBOSE)
+ if (not mext):
+ die("Stray ACPI_EXTRACT in input")
+
+ # previous command must have produced some AML,
+ # otherwise we are in a middle of a block
+ if (prev_aml_offset == asl[i].aml_offset):
+ die("ACPI_EXTRACT directive in the middle of a block")
+
+ directive = mext.group(1)
+ array = mext.group(2)
+ offset = asl[i].aml_offset
+
+ if (directive == "ACPI_EXTRACT_ALL_CODE"):
+ if array in output:
+ die("%s directive used more than once" % directive)
+ output[array] = aml
+ continue
+ if (directive == "ACPI_EXTRACT_NAME_BUFFER8"):
+ offset = aml_name_buffer8(offset)
+ elif (directive == "ACPI_EXTRACT_NAME_DWORD_CONST"):
+ offset = aml_name_dword_const(offset)
+ elif (directive == "ACPI_EXTRACT_NAME_WORD_CONST"):
+ offset = aml_name_word_const(offset)
+ elif (directive == "ACPI_EXTRACT_NAME_BYTE_CONST"):
+ offset = aml_name_byte_const(offset)
+ elif (directive == "ACPI_EXTRACT_NAME_STRING"):
+ offset = aml_name_string(offset)
+ elif (directive == "ACPI_EXTRACT_METHOD_STRING"):
+ offset = aml_method_string(offset)
+ elif (directive == "ACPI_EXTRACT_DEVICE_START"):
+ offset = aml_device_start(offset)
+ elif (directive == "ACPI_EXTRACT_DEVICE_STRING"):
+ offset = aml_device_string(offset)
+ elif (directive == "ACPI_EXTRACT_DEVICE_END"):
+ offset = aml_device_end(offset)
+ elif (directive == "ACPI_EXTRACT_PROCESSOR_START"):
+ offset = aml_processor_start(offset)
+ elif (directive == "ACPI_EXTRACT_PROCESSOR_STRING"):
+ offset = aml_processor_string(offset)
+ elif (directive == "ACPI_EXTRACT_PROCESSOR_END"):
+ offset = aml_processor_end(offset)
+ elif (directive == "ACPI_EXTRACT_PKG_START"):
+ offset = aml_package_start(offset)
+ else:
+ die("Unsupported directive %s" % directive)
+
+ if array not in output:
+ output[array] = []
+ output[array].append(offset)
+
+debug = "at end of file"
+
+def get_value_type(maxvalue):
+ #Use type large enough to fit the table
+ if (maxvalue >= 0x10000):
+ return "int"
+ elif (maxvalue >= 0x100):
+ return "short"
+ else:
+ return "char"
+
+# Pretty print output
+for array in output.keys():
+ otype = get_value_type(max(output[array]))
+ odata = []
+ for value in output[array]:
+ odata.append("0x%x" % value)
+ sys.stdout.write("static unsigned %s %s[] = {\n" % (otype, array))
+ sys.stdout.write(",\n".join(odata))
+ sys.stdout.write('\n};\n');
--git a/scripts/acpi_extract_preprocess.py b/scripts/acpi_extract_preprocess.py
new file mode 100755
index 0000000..69d10d6
--- /dev/null
+++ b/scripts/acpi_extract_preprocess.py
@@ -0,0 +1,51 @@
+#!/usr/bin/python
+# Copyright (C) 2011 Red Hat, Inc., Michael S. Tsirkin <mst@redhat.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, see <http://www.gnu.org/licenses/>.
+
+# Read a preprocessed ASL listing and put each ACPI_EXTRACT
+# directive in a comment, to make iasl skip it.
+# We also put each directive on a new line, the machinery
+# in tools/acpi_extract.py requires this.
+
+import re;
+import sys;
+import fileinput;
+
+def die(diag):
+ sys.stderr.write("Error: %s\n" % (diag))
+ sys.exit(1)
+
+# Note: () around pattern make split return matched string as part of list
+psplit = re.compile(r''' (
+ \b # At word boundary
+ ACPI_EXTRACT_\w+ # directive
+ \s+ # some whitespace
+ \w+ # array name
+ )''', re.VERBOSE);
+
+lineno = 0
+for line in fileinput.input():
+ # line number and debug string to output in case of errors
+ lineno = lineno + 1
+ debug = "input line %d: %s" % (lineno, line.rstrip())
+
+ s = psplit.split(line);
+ # The way split works, each odd item is the matching ACPI_EXTRACT directive.
+ # Put each in a comment, and on a line by itself.
+ for i in range(len(s)):
+ if (i % 2):
+ sys.stdout.write("\n/* %s */\n" % s[i])
+ else:
+ sys.stdout.write(s[i])
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 03/14] acpi: add rules to compile ASL source
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 01/14] hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 02/14] i386: add ACPI table files from seabios Michael S. Tsirkin
@ 2013-07-24 16:01 ` Michael S. Tsirkin
2013-07-25 12:09 ` Gerd Hoffmann
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 04/14] acpi: pre-compiled ASL files Michael S. Tsirkin
` (12 subsequent siblings)
15 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:01 UTC (permalink / raw)
To: qemu-devel
Detect presence of IASL compiler and use it
to process ASL source. If not there, use pre-compiled
files in-tree. Add script to update the in-tree files.
Note: distros are known to silently update iasl
so detect correct iasl flags for the installed version on each run as
opposed to at configure time.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
configure | 9 ++++++++-
hw/i386/Makefile.objs | 22 ++++++++++++++++++++++
scripts/update-acpi.sh | 4 ++++
3 files changed, 34 insertions(+), 1 deletion(-)
create mode 100644 scripts/update-acpi.sh
diff --git a/configure b/configure
index 877a821..9f3236f 100755
--- a/configure
+++ b/configure
@@ -119,6 +119,7 @@ path_of() {
# default parameters
source_path=`dirname "$0"`
cpu=""
+iasl="iasl"
interp_prefix="/usr/gnemul/qemu-%M"
static="no"
cross_prefix=""
@@ -253,6 +254,8 @@ for opt do
;;
--cc=*) CC="$optarg"
;;
+ --iasl=*) iasl="$optarg"
+ ;;
--source-path=*) source_path="$optarg"
;;
--cpu=*) cpu="$optarg"
@@ -1026,6 +1029,7 @@ echo "Advanced options (experts only):"
echo " --source-path=PATH path of source code [$source_path]"
echo " --cross-prefix=PREFIX use PREFIX for compile tools [$cross_prefix]"
echo " --cc=CC use C compiler CC [$cc]"
+echo " --iasl=IASL use ACPI compiler IASL [$iasl]"
echo " --host-cc=CC use C compiler CC [$host_cc] for code run at"
echo " build time"
echo " --objcc=OBJCC use Objective-C compiler OBJCC [$objcc]"
@@ -4110,6 +4114,9 @@ else
fi
echo "PYTHON=$python" >> $config_host_mak
echo "CC=$cc" >> $config_host_mak
+if $iasl -h > /dev/null 2>&1; then
+ echo "IASL=$iasl" >> $config_host_mak
+fi
echo "CC_I386=$cc_i386" >> $config_host_mak
echo "HOST_CC=$host_cc" >> $config_host_mak
echo "OBJCC=$objcc" >> $config_host_mak
@@ -4570,7 +4577,7 @@ for rom in seabios vgabios ; do
echo "BCC=bcc" >> $config_mak
echo "CPP=$cpp" >> $config_mak
echo "OBJCOPY=objcopy" >> $config_mak
- echo "IASL=iasl" >> $config_mak
+ echo "IASL=$iasl" >> $config_mak
echo "LD=$ld" >> $config_mak
done
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 205d22e..013d250 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -4,3 +4,25 @@ obj-y += pc.o pc_piix.o pc_q35.o
obj-$(CONFIG_XEN) += xen_domainbuild.o xen_machine_pv.o
obj-y += kvmvapic.o
+
+iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \
+ ; then echo "$(2)"; else echo "$(3)"; fi ;)
+
+ifdef IASL
+#IASL Present. Generate hex files from .dsl
+hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.dsl $(SRC_PATH)/scripts/acpi_extract_preprocess.py $(SRC_PATH)/scripts/acpi_extract.py
+ $(call quiet-command, cpp -P $< -o $*.dsl.i.orig, " CPP $(TARGET_DIR)$*.dsl.i.orig")
+ $(call quiet-command, $(PYTHON) $(SRC_PATH)/scripts/acpi_extract_preprocess.py $*.dsl.i.orig > $*.dsl.i, " ACPI_PREPROCESS $(TARGET_DIR)$*.dsl.i")
+ $(call quiet-command, $(IASL) $(call iasl-option,$(IASL),-Pn,) -vs -l -tc -p $* $*.dsl.i $(if $(V), , > /dev/null) 2>&1 ," IASL $(TARGET_DIR)$*.dsl.i")
+ $(call quiet-command, $(SRC_PATH)/scripts/acpi_extract.py $*.lst > $*.off, " ACPI_EXTRACT $(TARGET_DIR)$*.off")
+ $(call quiet-command, cat $*.off > $@, " CAT $(TARGET_DIR)$@")
+else
+#IASL Not present. Restore pre-generated hex files.
+hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.hex.generated
+ $(call quiet-command, cp -f $< $@, " CP $(TARGET_DIR)$@")
+endif
+
+.PHONY: cleanhex
+cleanhex:
+ rm -f hw/i386/*hex
+clean: cleanhex
diff --git a/scripts/update-acpi.sh b/scripts/update-acpi.sh
new file mode 100644
index 0000000..b5f05ff
--- /dev/null
+++ b/scripts/update-acpi.sh
@@ -0,0 +1,4 @@
+cd x86_64-softmmu
+for file in hw/i386/*.hex; do
+ cp -f $file ../$file.generated
+done
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 04/14] acpi: pre-compiled ASL files
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (2 preceding siblings ...)
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 03/14] acpi: add rules to compile ASL source Michael S. Tsirkin
@ 2013-07-24 16:01 ` Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 05/14] loader: use file path size from fw_cfg.h Michael S. Tsirkin
` (11 subsequent siblings)
15 siblings, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:01 UTC (permalink / raw)
To: qemu-devel
Add pre-compiled ASL files. Useful for systems that
do not have IASL.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/acpi-dsdt.hex.generated | 4409 +++++++++++++++++++++
hw/i386/q35-acpi-dsdt.hex.generated | 7346 +++++++++++++++++++++++++++++++++++
hw/i386/ssdt-misc.hex.generated | 190 +
hw/i386/ssdt-pcihp.hex.generated | 108 +
hw/i386/ssdt-proc.hex.generated | 134 +
5 files changed, 12187 insertions(+)
create mode 100644 hw/i386/acpi-dsdt.hex.generated
create mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
create mode 100644 hw/i386/ssdt-misc.hex.generated
create mode 100644 hw/i386/ssdt-pcihp.hex.generated
create mode 100644 hw/i386/ssdt-proc.hex.generated
diff --git a/hw/i386/acpi-dsdt.hex.generated b/hw/i386/acpi-dsdt.hex.generated
new file mode 100644
index 0000000..68cab3e
--- /dev/null
+++ b/hw/i386/acpi-dsdt.hex.generated
@@ -0,0 +1,4409 @@
+static unsigned char AcpiDsdtAmlCode[] = {
+0x44,
+0x53,
+0x44,
+0x54,
+0x37,
+0x11,
+0x0,
+0x0,
+0x1,
+0xe1,
+0x42,
+0x58,
+0x50,
+0x43,
+0x0,
+0x0,
+0x42,
+0x58,
+0x44,
+0x53,
+0x44,
+0x54,
+0x0,
+0x0,
+0x1,
+0x0,
+0x0,
+0x0,
+0x49,
+0x4e,
+0x54,
+0x4c,
+0x28,
+0x5,
+0x10,
+0x20,
+0x10,
+0x49,
+0x4,
+0x5c,
+0x0,
+0x5b,
+0x80,
+0x44,
+0x42,
+0x47,
+0x5f,
+0x1,
+0xb,
+0x2,
+0x4,
+0x1,
+0x5b,
+0x81,
+0xb,
+0x44,
+0x42,
+0x47,
+0x5f,
+0x1,
+0x44,
+0x42,
+0x47,
+0x42,
+0x8,
+0x14,
+0x2c,
+0x44,
+0x42,
+0x55,
+0x47,
+0x1,
+0x98,
+0x68,
+0x60,
+0x96,
+0x60,
+0x60,
+0x74,
+0x87,
+0x60,
+0x1,
+0x61,
+0x70,
+0x0,
+0x62,
+0xa2,
+0x10,
+0x95,
+0x62,
+0x61,
+0x70,
+0x83,
+0x88,
+0x60,
+0x62,
+0x0,
+0x44,
+0x42,
+0x47,
+0x42,
+0x75,
+0x62,
+0x70,
+0xa,
+0xa,
+0x44,
+0x42,
+0x47,
+0x42,
+0x10,
+0x22,
+0x5f,
+0x53,
+0x42,
+0x5f,
+0x5b,
+0x82,
+0x1b,
+0x50,
+0x43,
+0x49,
+0x30,
+0x8,
+0x5f,
+0x48,
+0x49,
+0x44,
+0xc,
+0x41,
+0xd0,
+0xa,
+0x3,
+0x8,
+0x5f,
+0x41,
+0x44,
+0x52,
+0x0,
+0x8,
+0x5f,
+0x55,
+0x49,
+0x44,
+0x1,
+0x10,
+0x4e,
+0x15,
+0x2e,
+0x5f,
+0x53,
+0x42,
+0x5f,
+0x50,
+0x43,
+0x49,
+0x30,
+0x8,
+0x43,
+0x52,
+0x45,
+0x53,
+0x11,
+0x42,
+0x7,
+0xa,
+0x6e,
+0x88,
+0xd,
+0x0,
+0x2,
+0xc,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0xff,
+0x0,
+0x0,
+0x0,
+0x0,
+0x1,
+0x47,
+0x1,
+0xf8,
+0xc,
+0xf8,
+0xc,
+0x1,
+0x8,
+0x88,
+0xd,
+0x0,
+0x1,
+0xc,
+0x3,
+0x0,
+0x0,
+0x0,
+0x0,
+0xf7,
+0xc,
+0x0,
+0x0,
+0xf8,
+0xc,
+0x88,
+0xd,
+0x0,
+0x1,
+0xc,
+0x3,
+0x0,
+0x0,
+0x0,
+0xd,
+0xff,
+0xff,
+0x0,
+0x0,
+0x0,
+0xf3,
+0x87,
+0x17,
+0x0,
+0x0,
+0xc,
+0x3,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0xa,
+0x0,
+0xff,
+0xff,
+0xb,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x2,
+0x0,
+0x87,
+0x17,
+0x0,
+0x0,
+0xc,
+0x1,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0xe0,
+0xff,
+0xff,
+0xbf,
+0xfe,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0xc0,
+0x1e,
+0x79,
+0x0,
+0x8,
+0x43,
+0x52,
+0x36,
+0x34,
+0x11,
+0x33,
+0xa,
+0x30,
+0x8a,
+0x2b,
+0x0,
+0x0,
+0xc,
+0x3,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x80,
+0x0,
+0x0,
+0x0,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x80,
+0x0,
+0x0,
+0x0,
+0x79,
+0x0,
+0x14,
+0x41,
+0xa,
+0x5f,
+0x43,
+0x52,
+0x53,
+0x0,
+0x8a,
+0x43,
+0x52,
+0x45,
+0x53,
+0xa,
+0x5c,
+0x50,
+0x53,
+0x33,
+0x32,
+0x8a,
+0x43,
+0x52,
+0x45,
+0x53,
+0xa,
+0x60,
+0x50,
+0x45,
+0x33,
+0x32,
+0x8a,
+0x43,
+0x52,
+0x45,
+0x53,
+0xa,
+0x68,
+0x50,
+0x4c,
+0x33,
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+};
diff --git a/hw/i386/q35-acpi-dsdt.hex.generated b/hw/i386/q35-acpi-dsdt.hex.generated
new file mode 100644
index 0000000..3a6168d
--- /dev/null
+++ b/hw/i386/q35-acpi-dsdt.hex.generated
@@ -0,0 +1,7346 @@
+static unsigned char Q35AcpiDsdtAmlCode[] = {
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+0x30,
+0x46,
+0x0
+};
diff --git a/hw/i386/ssdt-misc.hex.generated b/hw/i386/ssdt-misc.hex.generated
new file mode 100644
index 0000000..33a5266
--- /dev/null
+++ b/hw/i386/ssdt-misc.hex.generated
@@ -0,0 +1,190 @@
+static unsigned char acpi_pci64_length[] = {
+0x6f
+};
+static unsigned char acpi_s4_pkg[] = {
+0x8f
+};
+static unsigned char acpi_s3_name[] = {
+0x7c
+};
+static unsigned char acpi_pci32_start[] = {
+0x2f
+};
+static unsigned char acpi_pci64_valid[] = {
+0x43
+};
+static unsigned char ssdp_misc_aml[] = {
+0x53,
+0x53,
+0x44,
+0x54,
+0xa1,
+0x0,
+0x0,
+0x0,
+0x1,
+0x19,
+0x42,
+0x58,
+0x50,
+0x43,
+0x0,
+0x0,
+0x42,
+0x58,
+0x53,
+0x53,
+0x44,
+0x54,
+0x53,
+0x55,
+0x1,
+0x0,
+0x0,
+0x0,
+0x49,
+0x4e,
+0x54,
+0x4c,
+0x28,
+0x5,
+0x10,
+0x20,
+0x10,
+0x42,
+0x5,
+0x5c,
+0x0,
+0x8,
+0x50,
+0x30,
+0x53,
+0x5f,
+0xc,
+0x78,
+0x56,
+0x34,
+0x12,
+0x8,
+0x50,
+0x30,
+0x45,
+0x5f,
+0xc,
+0x78,
+0x56,
+0x34,
+0x12,
+0x8,
+0x50,
+0x31,
+0x56,
+0x5f,
+0xa,
+0x12,
+0x8,
+0x50,
+0x31,
+0x53,
+0x5f,
+0x11,
+0xb,
+0xa,
+0x8,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x8,
+0x50,
+0x31,
+0x45,
+0x5f,
+0x11,
+0xb,
+0xa,
+0x8,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x8,
+0x50,
+0x31,
+0x4c,
+0x5f,
+0x11,
+0xb,
+0xa,
+0x8,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x10,
+0x29,
+0x5c,
+0x0,
+0x8,
+0x5f,
+0x53,
+0x33,
+0x5f,
+0x12,
+0x6,
+0x4,
+0x1,
+0x1,
+0x0,
+0x0,
+0x8,
+0x5f,
+0x53,
+0x34,
+0x5f,
+0x12,
+0x8,
+0x4,
+0xa,
+0x2,
+0xa,
+0x2,
+0x0,
+0x0,
+0x8,
+0x5f,
+0x53,
+0x35,
+0x5f,
+0x12,
+0x6,
+0x4,
+0x0,
+0x0,
+0x0,
+0x0
+};
+static unsigned char acpi_s4_name[] = {
+0x88
+};
+static unsigned char acpi_pci64_start[] = {
+0x4d
+};
+static unsigned char acpi_pci64_end[] = {
+0x5e
+};
+static unsigned char acpi_pci32_end[] = {
+0x39
+};
diff --git a/hw/i386/ssdt-pcihp.hex.generated b/hw/i386/ssdt-pcihp.hex.generated
new file mode 100644
index 0000000..0d32a27
--- /dev/null
+++ b/hw/i386/ssdt-pcihp.hex.generated
@@ -0,0 +1,108 @@
+static unsigned char ssdt_pcihp_name[] = {
+0x33
+};
+static unsigned char ssdt_pcihp_adr[] = {
+0x44
+};
+static unsigned char ssdt_pcihp_end[] = {
+0x58
+};
+static unsigned char ssdp_pcihp_aml[] = {
+0x53,
+0x53,
+0x44,
+0x54,
+0x58,
+0x0,
+0x0,
+0x0,
+0x1,
+0x77,
+0x42,
+0x58,
+0x50,
+0x43,
+0x0,
+0x0,
+0x42,
+0x58,
+0x53,
+0x53,
+0x44,
+0x54,
+0x50,
+0x43,
+0x1,
+0x0,
+0x0,
+0x0,
+0x49,
+0x4e,
+0x54,
+0x4c,
+0x28,
+0x5,
+0x10,
+0x20,
+0x10,
+0x33,
+0x5c,
+0x2e,
+0x5f,
+0x53,
+0x42,
+0x5f,
+0x50,
+0x43,
+0x49,
+0x30,
+0x5b,
+0x82,
+0x26,
+0x53,
+0x41,
+0x41,
+0x5f,
+0x8,
+0x5f,
+0x53,
+0x55,
+0x4e,
+0xa,
+0xaa,
+0x8,
+0x5f,
+0x41,
+0x44,
+0x52,
+0xc,
+0x0,
+0x0,
+0xaa,
+0x0,
+0x14,
+0xf,
+0x5f,
+0x45,
+0x4a,
+0x30,
+0x1,
+0xa4,
+0x50,
+0x43,
+0x45,
+0x4a,
+0x5f,
+0x53,
+0x55,
+0x4e
+};
+static unsigned char ssdt_pcihp_start[] = {
+0x30
+};
+static unsigned char ssdt_pcihp_id[] = {
+0x3d
+};
+static unsigned char ssdt_pcihp_ej0[] = {
+0x4a
+};
diff --git a/hw/i386/ssdt-proc.hex.generated b/hw/i386/ssdt-proc.hex.generated
new file mode 100644
index 0000000..a28172e
--- /dev/null
+++ b/hw/i386/ssdt-proc.hex.generated
@@ -0,0 +1,134 @@
+static unsigned char ssdt_proc_name[] = {
+0x28
+};
+static unsigned char ssdp_proc_aml[] = {
+0x53,
+0x53,
+0x44,
+0x54,
+0x78,
+0x0,
+0x0,
+0x0,
+0x1,
+0xb3,
+0x42,
+0x58,
+0x50,
+0x43,
+0x0,
+0x0,
+0x42,
+0x58,
+0x53,
+0x53,
+0x44,
+0x54,
+0x0,
+0x0,
+0x1,
+0x0,
+0x0,
+0x0,
+0x49,
+0x4e,
+0x54,
+0x4c,
+0x28,
+0x5,
+0x10,
+0x20,
+0x5b,
+0x83,
+0x42,
+0x5,
+0x43,
+0x50,
+0x41,
+0x41,
+0xaa,
+0x10,
+0xb0,
+0x0,
+0x0,
+0x6,
+0x8,
+0x49,
+0x44,
+0x5f,
+0x5f,
+0xa,
+0xaa,
+0x8,
+0x5f,
+0x48,
+0x49,
+0x44,
+0xd,
+0x41,
+0x43,
+0x50,
+0x49,
+0x30,
+0x30,
+0x30,
+0x37,
+0x0,
+0x14,
+0xf,
+0x5f,
+0x4d,
+0x41,
+0x54,
+0x0,
+0xa4,
+0x43,
+0x50,
+0x4d,
+0x41,
+0x49,
+0x44,
+0x5f,
+0x5f,
+0x14,
+0xf,
+0x5f,
+0x53,
+0x54,
+0x41,
+0x0,
+0xa4,
+0x43,
+0x50,
+0x53,
+0x54,
+0x49,
+0x44,
+0x5f,
+0x5f,
+0x14,
+0xf,
+0x5f,
+0x45,
+0x4a,
+0x30,
+0x1,
+0x43,
+0x50,
+0x45,
+0x4a,
+0x49,
+0x44,
+0x5f,
+0x5f,
+0x68
+};
+static unsigned char ssdt_proc_id[] = {
+0x38
+};
+static unsigned char ssdt_proc_end[] = {
+0x78
+};
+static unsigned char ssdt_proc_start[] = {
+0x24
+};
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 05/14] loader: use file path size from fw_cfg.h
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (3 preceding siblings ...)
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 04/14] acpi: pre-compiled ASL files Michael S. Tsirkin
@ 2013-07-24 16:01 ` Michael S. Tsirkin
2013-07-24 23:42 ` Andreas Färber
2013-07-25 12:10 ` Gerd Hoffmann
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 06/14] i386: add bios linker/loader Michael S. Tsirkin
` (10 subsequent siblings)
15 siblings, 2 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:01 UTC (permalink / raw)
To: qemu-devel
Avoid a bit of code duplication, make
max file path constant reusable.
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/core/loader.c | 2 +-
include/hw/nvram/fw_cfg.h | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index c3c28cf..c4dd665 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -645,7 +645,7 @@ int rom_add_file(const char *file, const char *fw_dir,
rom_insert(rom);
if (rom->fw_file && fw_cfg) {
const char *basename;
- char fw_file_name[56];
+ char fw_file_name[FW_CFG_MAX_FILE_PATH];
basename = strrchr(rom->fw_file, '/');
if (basename) {
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index f60dd67..fa5c8c6 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -46,12 +46,14 @@
#define FW_CFG_INVALID 0xffff
+#define FW_CFG_MAX_FILE_PATH 56
+
#ifndef NO_QEMU_PROTOS
typedef struct FWCfgFile {
uint32_t size; /* file size */
uint16_t select; /* write this to 0x510 to read it */
uint16_t reserved;
- char name[56];
+ char name[FW_CFG_MAX_FILE_PATH];
} FWCfgFile;
typedef struct FWCfgFiles {
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 06/14] i386: add bios linker/loader
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (4 preceding siblings ...)
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 05/14] loader: use file path size from fw_cfg.h Michael S. Tsirkin
@ 2013-07-24 16:01 ` Michael S. Tsirkin
2013-07-25 12:11 ` Gerd Hoffmann
2013-07-26 9:42 ` Gerd Hoffmann
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs Michael S. Tsirkin
` (9 subsequent siblings)
15 siblings, 2 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:01 UTC (permalink / raw)
To: qemu-devel
This adds a dynamic bios linker/loader.
This will be used by acpi table generation
code to:
- load each table in the appropriate memory segment
- link tables to each other
- fix up checksums after said linking
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/Makefile.objs | 1 +
hw/i386/bios-linker-loader.c | 156 +++++++++++++++++++++++++++++++++++
include/hw/i386/bios-linker-loader.h | 26 ++++++
3 files changed, 183 insertions(+)
create mode 100644 hw/i386/bios-linker-loader.c
create mode 100644 include/hw/i386/bios-linker-loader.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 013d250..71be2da 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -4,6 +4,7 @@ obj-y += pc.o pc_piix.o pc_q35.o
obj-$(CONFIG_XEN) += xen_domainbuild.o xen_machine_pv.o
obj-y += kvmvapic.o
+obj-y += bios-linker-loader.o
iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \
; then echo "$(2)"; else echo "$(3)"; fi ;)
diff --git a/hw/i386/bios-linker-loader.c b/hw/i386/bios-linker-loader.c
new file mode 100644
index 0000000..644016b
--- /dev/null
+++ b/hw/i386/bios-linker-loader.c
@@ -0,0 +1,156 @@
+/* Dynamic linker/loader of ACPI tables
+ *
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/i386/bios-linker-loader.h"
+#include "hw/nvram/fw_cfg.h"
+
+#include <string.h>
+#include <assert.h>
+#include "qemu/bswap.h"
+
+#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
+
+struct BiosLinkerLoaderEntry {
+ uint32_t command;
+ union {
+ /*
+ * COMMAND_ALLOCATE - allocate a table from @alloc_file
+ * subject to @alloc_align alignment (must be power of 2)
+ * and @alloc_zone (can be HIGH or FSEG) requirements.
+ *
+ * Must appear exactly once for each file, and before
+ * this file is referenced by any other command.
+ */
+ struct {
+ char alloc_file[BIOS_LINKER_LOADER_FILESZ];
+ uint32_t alloc_align;
+ uint8_t alloc_zone;
+ };
+
+ /*
+ * COMMAND_ADD_POINTER - patch the table (originating from
+ * @dest_file) at @pointer_offset, by adding a pointer to the table
+ * originating from @src_file. 1,2,4 or 8 byte unsigned
+ * addition is used depending on @pointer_size.
+ */
+ struct {
+ char pointer_dest_file[BIOS_LINKER_LOADER_FILESZ];
+ char pointer_src_file[BIOS_LINKER_LOADER_FILESZ];
+ uint32_t pointer_offset;
+ uint8_t pointer_size;
+ };
+
+ /*
+ * COMMAND_ADD_CHECKSUM - calculate checksum of the range specified by
+ * @cksum_start and @cksum_length fields,
+ * and then add the value at @cksum_offset.
+ * Checksum simply sums -X for each byte X in the range
+ * using 8-bit math.
+ */
+ struct {
+ char cksum_file[BIOS_LINKER_LOADER_FILESZ];
+ uint32_t cksum_offset;
+ uint32_t cksum_start;
+ uint32_t cksum_length;
+ };
+
+ /* padding */
+ char pad[124];
+ };
+} QEMU_PACKED;
+typedef struct BiosLinkerLoaderEntry BiosLinkerLoaderEntry;
+
+enum {
+ BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1,
+ BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2,
+ BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
+};
+
+enum {
+ BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
+ BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
+};
+
+GArray *bios_linker_init(void)
+{
+ return g_array_new(false, true /* clear */, sizeof(BiosLinkerLoaderEntry));
+}
+
+/* Free linker wrapper and return the linker array. */
+void *bios_linker_cleanup(GArray *linker)
+{
+ return g_array_free(linker, false);
+}
+
+void bios_linker_alloc(GArray *linker,
+ const char *file,
+ uint32_t alloc_align,
+ bool alloc_fseg)
+{
+ BiosLinkerLoaderEntry entry;
+
+ memset(&entry, 0, sizeof entry);
+ strncpy(entry.alloc_file, file, sizeof entry.alloc_file - 1);
+ entry.command = cpu_to_le32(BIOS_LINKER_LOADER_COMMAND_ALLOCATE);
+ entry.alloc_align = cpu_to_le32(alloc_align);
+ entry.alloc_zone = cpu_to_le32(alloc_fseg ?
+ BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG :
+ BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH);
+
+ /* Alloc entries must come first, so prepend them */
+ g_array_prepend_val(linker, entry);
+}
+
+void bios_linker_add_checksum(GArray *linker, const char *file, void *table,
+ void *start, unsigned size, uint8_t *checksum)
+{
+ BiosLinkerLoaderEntry entry;
+
+ memset(&entry, 0, sizeof entry);
+ strncpy(entry.cksum_file, file, sizeof entry.cksum_file - 1);
+ entry.command = cpu_to_le32(BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM);
+ entry.cksum_offset = cpu_to_le32(checksum - (uint8_t *)table);
+ entry.cksum_start = cpu_to_le32((uint8_t *)start - (uint8_t *)table);
+ entry.cksum_length = cpu_to_le32(size);
+
+ g_array_append_val(linker, entry);
+}
+
+void bios_linker_add_pointer(GArray *linker,
+ const char *dest_file,
+ const char *src_file,
+ GArray *table, void *pointer,
+ uint8_t pointer_size)
+{
+ BiosLinkerLoaderEntry entry;
+
+ memset(&entry, 0, sizeof entry);
+ strncpy(entry.pointer_dest_file, dest_file,
+ sizeof entry.pointer_dest_file - 1);
+ strncpy(entry.pointer_src_file, src_file,
+ sizeof entry.pointer_src_file - 1);
+ entry.command = cpu_to_le32(BIOS_LINKER_LOADER_COMMAND_ADD_POINTER);
+ entry.pointer_offset = cpu_to_le32((gchar *)pointer - table->data);
+ entry.pointer_size = pointer_size;
+ assert(pointer_size == 1 || pointer_size == 2 ||
+ pointer_size == 4 || pointer_size == 8);
+
+ g_array_append_val(linker, entry);
+}
diff --git a/include/hw/i386/bios-linker-loader.h b/include/hw/i386/bios-linker-loader.h
new file mode 100644
index 0000000..18c3868
--- /dev/null
+++ b/include/hw/i386/bios-linker-loader.h
@@ -0,0 +1,26 @@
+#ifndef BIOS_LINKER_LOADER_H
+#define BIOS_LINKER_LOADER_H
+
+#include <glib.h>
+#include <stdbool.h>
+#include <inttypes.h>
+
+GArray *bios_linker_init(void);
+
+void bios_linker_alloc(GArray *linker,
+ const char *file,
+ uint32_t alloc_align,
+ bool alloc_fseg);
+
+void bios_linker_add_checksum(GArray *linker, const char *file, void *table,
+ void *start, unsigned size, uint8_t *checksum);
+
+
+void bios_linker_add_pointer(GArray *linker,
+ const char *dest_file,
+ const char *src_file,
+ GArray *table, void *pointer,
+ uint8_t pointer_size);
+
+void *bios_linker_cleanup(GArray *linker);
+#endif
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (5 preceding siblings ...)
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 06/14] i386: add bios linker/loader Michael S. Tsirkin
@ 2013-07-24 16:01 ` Michael S. Tsirkin
2013-07-25 12:14 ` Gerd Hoffmann
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 08/14] loader: allow adding ROMs in done callbacks Michael S. Tsirkin
` (8 subsequent siblings)
15 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Michael Walle
Support ROM blobs not mapped into guest memory:
let user pass in MR for memory serving as the backing store.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
hw/core/loader.c | 32 +++++++++++++++++++++++++++++---
hw/lm32/lm32_hwsetup.h | 2 +-
include/hw/loader.h | 4 ++--
3 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index c4dd665..c2309e6 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -576,6 +576,7 @@ struct Rom {
size_t datasize;
uint8_t *data;
+ MemoryRegion *mr;
int isrom;
char *fw_dir;
char *fw_file;
@@ -675,7 +676,7 @@ err:
}
int rom_add_blob(const char *name, const void *blob, size_t len,
- hwaddr addr)
+ hwaddr addr, MemoryRegion *mr)
{
Rom *rom;
@@ -685,6 +686,11 @@ int rom_add_blob(const char *name, const void *blob, size_t len,
rom->romsize = len;
rom->datasize = len;
rom->data = g_malloc0(rom->datasize);
+ rom->mr = mr;
+ if (mr) {
+ assert(memory_region_is_ram(mr));
+ rom->isrom = memory_region_is_rom(mr);
+ }
memcpy(rom->data, blob, len);
rom_insert(rom);
return 0;
@@ -725,13 +731,21 @@ static void rom_reset(void *unused)
Rom *rom;
QTAILQ_FOREACH(rom, &roms, next) {
+ if (rom->mr) {
+ continue;
+ }
if (rom->fw_file) {
continue;
}
if (rom->data == NULL) {
continue;
}
- cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
+ if (rom->mr) {
+ void *host = memory_region_get_ram_ptr(rom->mr);
+ memcpy(host, rom->data, rom->datasize);
+ } else {
+ cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
+ }
if (rom->isrom) {
/* rom needs to be written only once */
g_free(rom->data);
@@ -781,6 +795,9 @@ static Rom *find_rom(hwaddr addr)
if (rom->fw_file) {
continue;
}
+ if (rom->mr) {
+ continue;
+ }
if (rom->addr > addr) {
continue;
}
@@ -808,6 +825,9 @@ int rom_copy(uint8_t *dest, hwaddr addr, size_t size)
if (rom->fw_file) {
continue;
}
+ if (rom->mr) {
+ continue;
+ }
if (rom->addr + rom->romsize < addr) {
continue;
}
@@ -867,7 +887,13 @@ void do_info_roms(Monitor *mon, const QDict *qdict)
Rom *rom;
QTAILQ_FOREACH(rom, &roms, next) {
- if (!rom->fw_file) {
+ if (rom->mr) {
+ monitor_printf(mon, "%s"
+ " size=0x%06zx name=\"%s\"\n",
+ rom->mr->name,
+ rom->romsize,
+ rom->name);
+ } else if (!rom->fw_file) {
monitor_printf(mon, "addr=" TARGET_FMT_plx
" size=0x%06zx mem=%s name=\"%s\"\n",
rom->addr, rom->romsize,
diff --git a/hw/lm32/lm32_hwsetup.h b/hw/lm32/lm32_hwsetup.h
index 3449bd8..d6914d6 100644
--- a/hw/lm32/lm32_hwsetup.h
+++ b/hw/lm32/lm32_hwsetup.h
@@ -73,7 +73,7 @@ static inline void hwsetup_free(HWSetup *hw)
static inline void hwsetup_create_rom(HWSetup *hw,
hwaddr base)
{
- rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base);
+ rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base, NULL);
}
static inline void hwsetup_add_u8(HWSetup *hw, uint8_t u)
diff --git a/include/hw/loader.h b/include/hw/loader.h
index eb9c9a3..cdb7b4b 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -40,7 +40,7 @@ void pstrcpy_targphys(const char *name,
int rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex);
int rom_add_blob(const char *name, const void *blob, size_t len,
- hwaddr addr);
+ hwaddr addr, MemoryRegion *mr);
int rom_add_elf_program(const char *name, void *data, size_t datasize,
size_t romsize, hwaddr addr);
int rom_load_all(void);
@@ -52,7 +52,7 @@ void do_info_roms(Monitor *mon, const QDict *qdict);
#define rom_add_file_fixed(_f, _a, _i) \
rom_add_file(_f, NULL, _a, _i)
#define rom_add_blob_fixed(_f, _b, _l, _a) \
- rom_add_blob(_f, _b, _l, _a)
+ rom_add_blob(_f, _b, _l, _a, NULL)
#define PC_ROM_MIN_VGA 0xc0000
#define PC_ROM_MIN_OPTION 0xc8000
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 08/14] loader: allow adding ROMs in done callbacks
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (6 preceding siblings ...)
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs Michael S. Tsirkin
@ 2013-07-24 16:02 ` Michael S. Tsirkin
2013-07-25 12:15 ` Gerd Hoffmann
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 09/14] i386: define pc guest info Michael S. Tsirkin
` (7 subsequent siblings)
15 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
Don't abort if machine done callbacks add ROMs.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/core/loader.c | 6 +++++-
include/hw/loader.h | 1 +
vl.c | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index c2309e6..c68f757 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -778,10 +778,14 @@ int rom_load_all(void)
memory_region_unref(section.mr);
}
qemu_register_reset(rom_reset, NULL);
- roms_loaded = 1;
return 0;
}
+void rom_load_done(void)
+{
+ roms_loaded = 1;
+}
+
void rom_set_fw(FWCfgState *f)
{
fw_cfg = f;
diff --git a/include/hw/loader.h b/include/hw/loader.h
index cdb7b4b..8f0d142 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -44,6 +44,7 @@ int rom_add_blob(const char *name, const void *blob, size_t len,
int rom_add_elf_program(const char *name, void *data, size_t datasize,
size_t romsize, hwaddr addr);
int rom_load_all(void);
+void rom_load_done(void);
void rom_set_fw(FWCfgState *f);
int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
void *rom_ptr(hwaddr addr);
diff --git a/vl.c b/vl.c
index 25b8f2f..3d56ec0 100644
--- a/vl.c
+++ b/vl.c
@@ -4408,6 +4408,9 @@ int main(int argc, char **argv, char **envp)
qemu_register_reset(qbus_reset_all_fn, sysbus_get_default());
qemu_run_machine_init_done_notifiers();
+ /* Done notifiers can load ROMs */
+ rom_load_done();
+
qemu_system_reset(VMRESET_SILENT);
if (loadvm) {
if (load_vmstate(loadvm) < 0) {
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 09/14] i386: define pc guest info
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (7 preceding siblings ...)
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 08/14] loader: allow adding ROMs in done callbacks Michael S. Tsirkin
@ 2013-07-24 16:02 ` Michael S. Tsirkin
2013-07-25 12:31 ` Gerd Hoffmann
2013-07-28 0:41 ` Andreas Färber
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 10/14] ich9: APIs for " Michael S. Tsirkin
` (6 subsequent siblings)
15 siblings, 2 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
This defines a structure that will be used to fill in guest info table.
This structure will be filled in in follow-up patches, using QOM. Fill
in NUMA node info is not available in QOM so it is filled in directly.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
hw/i386/pc.c | 33 +++++++++++++++++++++++++++++++++
include/hw/i386/pc.h | 31 +++++++++++++++++++++++++++++++
include/qemu/typedefs.h | 1 +
3 files changed, 65 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index b0b98a8..b9b8f92 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1017,6 +1017,27 @@ static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
}
+static void pc_set_cpu_guest_info(CPUState *cpu, void *arg)
+{
+ PcGuestInfo *guest_info = arg;
+ CPUClass *klass = CPU_GET_CLASS(cpu);
+ uint64_t apic_id = klass->get_arch_id(cpu);
+ int j;
+
+ assert(apic_id <= MAX_CPUMASK_BITS);
+ assert(apic_id < guest_info->apic_id_limit);
+
+ set_bit(apic_id, guest_info->found_cpus);
+
+ for (j = 0; j < guest_info->numa_nodes; j++) {
+ assert(cpu->cpu_index < max_cpus);
+ if (test_bit(cpu->cpu_index, node_cpumask[j])) {
+ guest_info->node_cpu[apic_id] = cpu_to_le64(j);
+ break;
+ }
+ }
+}
+
typedef struct PcGuestInfoState {
PcGuestInfo info;
Notifier machine_done;
@@ -1037,6 +1058,18 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
PcGuestInfo *guest_info = &guest_info_state->info;
+ guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
+ guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
+ guest_info->apic_xrupt_override = kvm_allows_irq0_override();
+ guest_info->numa_nodes = nb_numa_nodes;
+ guest_info->node_mem = g_memdup(node_mem, guest_info->numa_nodes *
+ sizeof *guest_info->node_mem);
+ guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
+ sizeof *guest_info->node_cpu);
+
+ memset(&guest_info->found_cpus, 0, sizeof guest_info->found_cpus);
+ qemu_for_each_cpu(pc_set_cpu_guest_info, guest_info);
+
guest_info->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
if (sizeof(hwaddr) == 4) {
guest_info->pci_info.w64.begin = 0;
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 7fb97b0..7c0bd50 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -9,6 +9,9 @@
#include "hw/i386/ioapic.h"
#include "qemu/range.h"
+#include "qemu/bitmap.h"
+#include "sysemu/sysemu.h"
+#include "hw/pci/pci.h"
/* PC-style peripherals (also used by other machines). */
@@ -17,9 +20,37 @@ typedef struct PcPciInfo {
Range w64;
} PcPciInfo;
+/* Matches the value hard-coded in BIOS */
+#define PC_GUEST_PORT_ACPI_PM_BASE 0xb000
+
+struct AcpiPmInfo {
+ bool s3_disabled;
+ bool s4_disabled;
+ uint8_t s4_val;
+ uint16_t sci_int;
+ uint8_t acpi_enable_cmd;
+ uint8_t acpi_disable_cmd;
+ uint32_t gpe0_blk;
+ uint32_t gpe0_blk_len;
+};
+
struct PcGuestInfo {
PcPciInfo pci_info;
bool has_pci_info;
+ hwaddr ram_size;
+ unsigned apic_id_limit;
+ bool apic_xrupt_override;
+ bool has_hpet;
+ uint64_t numa_nodes;
+ uint64_t *node_mem;
+ uint64_t *node_cpu;
+ DECLARE_BITMAP(found_cpus, MAX_CPUMASK_BITS + 1);
+ DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
+ AcpiPmInfo pm;
+ uint64_t mcfg_base;
+ const unsigned char *dsdt_code;
+ unsigned dsdt_size;
+ uint16_t pvpanic_port;
FWCfgState *fw_cfg;
};
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index ac9f8d4..cb66e19 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -65,5 +65,6 @@ typedef struct QEMUSGList QEMUSGList;
typedef struct SHPCDevice SHPCDevice;
typedef struct FWCfgState FWCfgState;
typedef struct PcGuestInfo PcGuestInfo;
+typedef struct AcpiPmInfo AcpiPmInfo;
#endif /* QEMU_TYPEDEFS_H */
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 10/14] ich9: APIs for pc guest info
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (8 preceding siblings ...)
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 09/14] i386: define pc guest info Michael S. Tsirkin
@ 2013-07-24 16:02 ` Michael S. Tsirkin
2013-07-25 12:33 ` Gerd Hoffmann
2013-07-28 0:37 ` Andreas Färber
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 11/14] piix: " Michael S. Tsirkin
` (5 subsequent siblings)
15 siblings, 2 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:02 UTC (permalink / raw)
To: qemu-devel
This adds APIs that will be used to fill in
guest info table, implemented using QOM,
to various ich9 components.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/ich9.c | 6 ++++++
hw/isa/lpc_ich9.c | 19 +++++++++++++++++++
hw/pci-host/q35.c | 10 ++++++++++
include/hw/acpi/ich9.h | 2 ++
include/hw/i386/ich9.h | 3 +++
include/hw/pci-host/q35.h | 2 ++
6 files changed, 42 insertions(+)
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 3fb443d..7ea55e1 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -228,3 +228,9 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
pm->powerdown_notifier.notify = pm_powerdown_req;
qemu_register_powerdown_notifier(&pm->powerdown_notifier);
}
+
+void ich9_pm_get_acpi_pm_info(ICH9LPCPMRegs *pm, AcpiPmInfo *info)
+{
+ info->gpe0_blk = PC_GUEST_PORT_ACPI_PM_BASE + ICH9_PMIO_GPE0_STS;
+ info->gpe0_blk_len = ICH9_PMIO_GPE0_LEN;
+}
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index d1921aa..12d4a23 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -562,6 +562,25 @@ static bool ich9_rst_cnt_needed(void *opaque)
return (lpc->rst_cnt != 0);
}
+ICH9LPCState *ich9_lpc_find(void)
+{
+ bool ambig;
+ Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig);
+
+ if (ambig) {
+ return NULL;
+ }
+ return ICH9_LPC_DEVICE(o);
+}
+
+void ich9_lpc_get_acpi_pm_info(ICH9LPCState *lpc, AcpiPmInfo *info)
+{
+ info->sci_int = 9;
+ info->acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
+ info->acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
+ ich9_pm_get_acpi_pm_info(&lpc->pm, info);
+}
+
static const VMStateDescription vmstate_ich9_rst_cnt = {
.name = "ICH9LPC/rst_cnt",
.version_id = 1,
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 6b1b3b7..ca6f495 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -298,6 +298,16 @@ static int mch_init(PCIDevice *d)
return 0;
}
+uint64_t mch_mcfg_base(void)
+{
+ bool ambiguous;
+ Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
+ if (!o) {
+ return 0;
+ }
+ return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
+}
+
static void mch_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
index b1fe71f..f5e8a88 100644
--- a/include/hw/acpi/ich9.h
+++ b/include/hw/acpi/ich9.h
@@ -49,4 +49,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
extern const VMStateDescription vmstate_ich9_pm;
+void ich9_pm_get_acpi_pm_info(ICH9LPCPMRegs *, AcpiPmInfo *);
+
#endif /* HW_ACPI_ICH9_H */
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index c5f637b..6528dc0 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -66,6 +66,9 @@ typedef struct ICH9LPCState {
qemu_irq *ioapic;
} ICH9LPCState;
+ICH9LPCState *ich9_lpc_find(void);
+void ich9_lpc_get_acpi_pm_info(ICH9LPCState *, AcpiPmInfo *);
+
#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 3cb631e..6337dcf 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -154,4 +154,6 @@ typedef struct Q35PCIHost {
#define MCH_PCIE_DEV 1
#define MCH_PCIE_FUNC 0
+uint64_t mch_mcfg_base(void);
+
#endif /* HW_Q35_H */
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (9 preceding siblings ...)
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 10/14] ich9: APIs for " Michael S. Tsirkin
@ 2013-07-24 16:02 ` Michael S. Tsirkin
2013-07-25 9:32 ` Michael S. Tsirkin
2013-07-25 12:34 ` Gerd Hoffmann
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port Michael S. Tsirkin
` (4 subsequent siblings)
15 siblings, 2 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
This adds APIs that will be used to fill in guest info table,
implemented using QOM, to various piix components.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/piix4.c | 29 +++++++++++++++++++++++++++--
hw/mips/mips_malta.c | 2 +-
hw/pci-host/piix.c | 8 ++++++++
include/hw/i386/pc.h | 1 +
include/qemu/typedefs.h | 1 +
5 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index c885690..2128f13 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -29,6 +29,7 @@
#include "exec/ioport.h"
#include "hw/nvram/fw_cfg.h"
#include "exec/address-spaces.h"
+#include "hw/acpi/piix4.h"
//#define DEBUG
@@ -63,7 +64,7 @@ typedef struct CPUStatus {
uint8_t sts[PIIX4_PROC_LEN];
} CPUStatus;
-typedef struct PIIX4PMState {
+struct PIIX4PMState {
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
@@ -96,7 +97,7 @@ typedef struct PIIX4PMState {
CPUStatus gpe_cpu;
Notifier cpu_added_notifier;
-} PIIX4PMState;
+};
#define TYPE_PIIX4_PM "PIIX4_PM"
@@ -458,6 +459,30 @@ static int piix4_pm_initfn(PCIDevice *dev)
return 0;
}
+PIIX4PMState *piix4_pm_find(void)
+{
+ bool ambig;
+ Object *o = object_resolve_path_type("", "PIIX4_PM", &ambig);
+
+ if (ambig || !o) {
+ return NULL;
+ }
+ return OBJECT_CHECK(PIIX4PMState, o, "PIIX4_PM");
+}
+
+void piix4_pm_get_acpi_pm_info(PIIX4PMState *s, AcpiPmInfo *info)
+{
+ info->s3_disabled = s->disable_s3;
+ info->s4_disabled = s->disable_s4;
+ info->s4_val = s->s4_val;
+
+ info->acpi_enable_cmd = ACPI_ENABLE;
+ info->acpi_disable_cmd = ACPI_DISABLE;
+ info->gpe0_blk = GPE_BASE;
+ info->gpe0_blk_len = GPE_LEN;
+ info->sci_int = 9;
+}
+
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int kvm_enabled, FWCfgState *fw_cfg)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index de87241..14573ab 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -965,7 +965,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
- isa_get_irq(NULL, 9), NULL, 0, NULL);
+ isa_get_irq(NULL, 9), NULL, 0, NULL, NULL);
/* TODO: Populate SPD eeprom data. */
smbus_eeprom_init(smbus, 8, NULL, 0);
pit = pit_init(isa_bus, 0x40, 0, NULL);
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3908860..daefdfb 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -349,6 +349,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
return b;
}
+PCIBus *find_i440fx(void)
+{
+ PCIHostState *s = OBJECT_CHECK(PCIHostState,
+ object_resolve_path("/machine/i440fx", NULL),
+ TYPE_PCI_HOST_BRIDGE);
+ return s ? s->bus : NULL;
+}
+
/* PIIX3 PCI to ISA bridge */
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 7c0bd50..76af5cd 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -186,6 +186,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
+PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index cb66e19..7d42693 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -65,6 +65,7 @@ typedef struct QEMUSGList QEMUSGList;
typedef struct SHPCDevice SHPCDevice;
typedef struct FWCfgState FWCfgState;
typedef struct PcGuestInfo PcGuestInfo;
+typedef struct PIIX4PMState PIIX4PMState;
typedef struct AcpiPmInfo AcpiPmInfo;
#endif /* QEMU_TYPEDEFS_H */
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (10 preceding siblings ...)
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 11/14] piix: " Michael S. Tsirkin
@ 2013-07-24 16:02 ` Michael S. Tsirkin
2013-07-25 10:29 ` Gerd Hoffmann
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 13/14] hpet: add API to find it Michael S. Tsirkin
` (3 subsequent siblings)
15 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:02 UTC (permalink / raw)
To: qemu-devel
Add API to find pvpanic device and get its io port.
Will be used to fill in guest info structure.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/misc/pvpanic.c | 11 +++++++++++
include/hw/i386/pc.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index 7bb49a5..bb403e9 100644
--- a/hw/misc/pvpanic.c
+++ b/hw/misc/pvpanic.c
@@ -122,6 +122,17 @@ void pvpanic_init(ISABus *bus)
pvpanic_fw_cfg(dev, fw_cfg);
}
+uint16_t pvpanic_port(void)
+{
+ Object *o = object_resolve_path_type("", TYPE_ISA_PVPANIC_DEVICE, NULL);
+ PVPanicState *s;
+ if (!o) {
+ return 0;
+ }
+ s = ISA_PVPANIC_DEVICE(o);
+ return s->ioport;
+}
+
static Property pvpanic_isa_properties[] = {
DEFINE_PROP_UINT16("ioport", PVPanicState, ioport, 0x505),
DEFINE_PROP_END_OF_LIST(),
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 76af5cd..e718a59 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -228,6 +228,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory);
/* pvpanic.c */
void pvpanic_init(ISABus *bus);
+uint16_t pvpanic_port(void);
/* e820 types */
#define E820_RAM 1
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 13/14] hpet: add API to find it
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (11 preceding siblings ...)
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port Michael S. Tsirkin
@ 2013-07-24 16:02 ` Michael S. Tsirkin
2013-07-25 12:36 ` Gerd Hoffmann
2013-07-27 23:38 ` Andreas Färber
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios Michael S. Tsirkin
` (2 subsequent siblings)
15 siblings, 2 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:02 UTC (permalink / raw)
To: qemu-devel
Add API to find HPET using QOM.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/timer/hpet.c | 5 +++++
include/hw/timer/hpet.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index 648b383..11bf401 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -757,6 +757,11 @@ static void hpet_device_class_init(ObjectClass *klass, void *data)
dc->props = hpet_device_properties;
}
+bool hpet_find(void)
+{
+ return object_resolve_path_type("", "hpet", NULL);
+}
+
static const TypeInfo hpet_device_info = {
.name = TYPE_HPET,
.parent = TYPE_SYS_BUS_DEVICE,
diff --git a/include/hw/timer/hpet.h b/include/hw/timer/hpet.h
index 757f79f..ab44bd3 100644
--- a/include/hw/timer/hpet.h
+++ b/include/hw/timer/hpet.h
@@ -71,4 +71,6 @@ struct hpet_fw_config
} QEMU_PACKED;
extern struct hpet_fw_config hpet_cfg;
+
+bool hpet_find(void);
#endif
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (12 preceding siblings ...)
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 13/14] hpet: add API to find it Michael S. Tsirkin
@ 2013-07-24 16:02 ` Michael S. Tsirkin
2013-07-25 13:06 ` Gerd Hoffmann
2013-07-25 15:50 ` [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Andreas Färber
2013-07-29 15:27 ` Anthony Liguori
15 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-24 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
This adds C code for generating ACPI tables at runtime,
imported from seabios git tree
commit 51684b7ced75fb76776e8ee84833fcfb6ecf12dd
Although ACPI tables come from a system BIOS on real hw,
it makes sense that the ACPI tables are coupled with the
virtual machine, since they have to abstract the x86 machine to
the OS's.
This is widely desired as a way to avoid the churn
and proliferation of QEMU-specific interfaces
associated with ACPI tables in bios code.
Notes:
The code structure was intentionally kept as close
to the seabios original as possible, to simplify
comparison and making sure we didn't lose anything
in translation.
Minor code duplication results, to help ensure there are no functional
regressions, I think it's better to merge it like this and do more code
changes in follow-up patches.
Cross-version compatibility concerns have been addressed:
ACPI tables are exposed to guest as FW_CFG entries.
When running with -M 1.5 and older, this patch disables ACPI
table generation, and doesn't expose ACPI
tables to guest.
As table content is likely to change over time,
the following measures are taken to simplify
cross-version migration:
- All tables besides the RSDP are packed in a single FW CFG entry.
This entry size is currently 23K. We round it up to 64K
to avoid too much churn there.
- Tables are placed in special ROM blob (not mapped into guest memory)
which is automatically migrated together with the guest, same
as BIOS code.
This patch reuses some code from SeaBIOS, which was originally under
LGPLv2 and then relicensed to GPLv3 or LGPLv3, in QEMU under GPLv2+. This
relicensing has been acked by all contributors that had contributed to the
code since the v2->v3 relicense. ACKs approving the v2+ relicensing are
listed below. The list might include ACKs from people not holding
copyright on any parts of the reused code, but it's better to err on the
side of caution and include them.
Affected SeaBIOS files (GPLv2+ license headers added)
<http://thread.gmane.org/gmane.comp.bios.coreboot.seabios/5949>:
src/acpi-dsdt-cpu-hotplug.dsl
src/acpi-dsdt-dbug.dsl
src/acpi-dsdt-hpet.dsl
src/acpi-dsdt-isa.dsl
src/acpi-dsdt-pci-crs.dsl
src/acpi.c
src/acpi.h
src/ssdt-misc.dsl
src/ssdt-pcihp.dsl
src/ssdt-proc.dsl
tools/acpi_extract.py
tools/acpi_extract_preprocess.py
Each one of the listed people agreed to the following:
> If you allow the use of your contribution in QEMU under the
> terms of GPLv2 or later as proposed by this patch,
> please respond to this mail including the line:
>
> Acked-by: Name <email address>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Jason Baron <jbaron@akamai.com>
Acked-by: David Woodhouse <David.Woodhouse@intel.com>
Acked-by: Gleb Natapov <gleb@redhat.com>
Acked-by: Marcelo Tosatti <mtosatti@redhat.com>
Acked-by: Dave Frodin <dave.frodin@se-eng.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Acked-by: Isaku Yamahata <yamahata@valinux.co.jp>
Acked-by: Magnus Christensson <magnus.christensson@intel.com>
Acked-by: Hu Tao <hutao@cn.fujitsu.com>
Acked-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/Makefile.objs | 4 +
hw/i386/acpi-build.c | 907 +++++++++++++++++++++++++++++++++++++++++++
hw/i386/acpi-defs.h | 327 ++++++++++++++++
hw/i386/pc.c | 2 +
hw/i386/pc_piix.c | 5 +
hw/i386/pc_q35.c | 3 +
include/hw/i386/acpi-build.h | 9 +
include/hw/i386/pc.h | 1 +
8 files changed, 1258 insertions(+)
create mode 100644 hw/i386/acpi-build.c
create mode 100644 hw/i386/acpi-defs.h
create mode 100644 include/hw/i386/acpi-build.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 71be2da..6754fd5 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -4,7 +4,11 @@ obj-y += pc.o pc_piix.o pc_q35.o
obj-$(CONFIG_XEN) += xen_domainbuild.o xen_machine_pv.o
obj-y += kvmvapic.o
+obj-y += acpi-build.o
obj-y += bios-linker-loader.o
+hw/i386/acpi-build.o: hw/i386/acpi-build.c hw/i386/acpi-dsdt.hex \
+ hw/i386/ssdt-proc.hex hw/i386/ssdt-pcihp.hex hw/i386/ssdt-misc.hex \
+ hw/i386/acpi-dsdt.hex hw/i386/q35-acpi-dsdt.hex
iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \
; then echo "$(2)"; else echo "$(3)"; fi ;)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
new file mode 100644
index 0000000..e6933f5
--- /dev/null
+++ b/hw/i386/acpi-build.c
@@ -0,0 +1,907 @@
+/* Support for generating ACPI tables and passing them to Guests
+ *
+ * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
+ * Copyright (C) 2006 Fabrice Bellard
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/i386/acpi-build.h"
+#include <stddef.h>
+#include <glib.h>
+#include "qemu/bitmap.h"
+#include "qemu/range.h"
+#include "hw/pci/pci.h"
+#include "qom/cpu.h"
+#include "hw/i386/pc.h"
+#include "target-i386/cpu.h"
+#include "hw/timer/hpet.h"
+#include "hw/i386/acpi-defs.h"
+#include "hw/acpi/acpi.h"
+#include "hw/nvram/fw_cfg.h"
+#include "hw/i386/bios-linker-loader.h"
+#include "hw/loader.h"
+
+/* Supported chipsets: */
+#include "hw/acpi/piix4.h"
+#include "hw/i386/ich9.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci-host/q35.h"
+
+#include "hw/i386/q35-acpi-dsdt.hex"
+#include "hw/i386/acpi-dsdt.hex"
+
+static void acpi_get_pm_info(PcGuestInfo *guest_info)
+{
+ PIIX4PMState *piix = piix4_pm_find();
+ ICH9LPCState *lpc = ich9_lpc_find();
+ assert(!!piix != !!lpc);
+
+ if (piix) {
+ piix4_pm_get_acpi_pm_info(piix, &guest_info->pm);
+ guest_info->dsdt_code = AcpiDsdtAmlCode;
+ guest_info->dsdt_size = sizeof AcpiDsdtAmlCode;
+ }
+ if (lpc) {
+ ich9_lpc_get_acpi_pm_info(lpc, &guest_info->pm);
+ guest_info->dsdt_code = Q35AcpiDsdtAmlCode;
+ guest_info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
+ }
+}
+
+static void acpi_get_hotplug_info(PcGuestInfo *guest_info)
+{
+ int i;
+ PCIBus *bus = find_i440fx();
+
+ if (!bus) {
+ return;
+ }
+
+ memset(guest_info->slot_hotplug_enable, 0xff,
+ DIV_ROUND_UP(PCI_SLOT_MAX, BITS_PER_BYTE));
+
+ for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
+ PCIDeviceClass *pc;
+ PCIDevice *pdev = bus->devices[i];
+
+ if (!pdev) {
+ continue;
+ }
+
+ pc = PCI_DEVICE_GET_CLASS(pdev);
+
+ if (pc->no_hotplug) {
+ int slot = PCI_SLOT(i);
+
+ clear_bit(slot, guest_info->slot_hotplug_enable);
+ }
+ }
+}
+
+static void acpi_get_misc_info(PcGuestInfo *guest_info)
+{
+ guest_info->mcfg_base = mch_mcfg_base();
+ guest_info->has_hpet = hpet_find();
+ guest_info->pvpanic_port = pvpanic_port();
+}
+
+#define ACPI_BUILD_APPNAME "Bochs"
+#define ACPI_BUILD_APPNAME6 "BOCHS "
+#define ACPI_BUILD_APPNAME4 "BXPC"
+
+#define ACPI_BUILD_DPRINTF(level, fmt, ...) do {} while(0)
+
+#define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
+#define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
+
+static void
+build_header(GArray *linker, GArray *table_data,
+ AcpiTableHeader *h, uint32_t sig, int len, uint8_t rev)
+{
+ h->signature = cpu_to_le32(sig);
+ h->length = cpu_to_le32(len);
+ h->revision = rev;
+ memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
+ memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
+ memcpy(h->oem_table_id + 4, (void*)&sig, 4);
+ h->oem_revision = cpu_to_le32(1);
+ memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
+ h->asl_compiler_revision = cpu_to_le32(1);
+ h->checksum = 0;
+ /* Checksum to be filled in by Guest linker */
+ bios_linker_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
+ table_data->data, h, len, &h->checksum);
+}
+
+static inline GArray *build_alloc_array(void)
+{
+ return g_array_new(false, true /* clear */, 1);
+}
+
+static inline void build_free_array(GArray *array)
+{
+ g_array_free(array, true);
+}
+
+static inline void build_prepend_byte(GArray *array, uint8_t val)
+{
+ g_array_prepend_val(array, val);
+}
+
+static inline void build_append_byte(GArray *array, uint8_t val)
+{
+ g_array_append_val(array, val);
+}
+
+static inline void build_prepend_array(GArray *array, GArray *val)
+{
+ g_array_prepend_vals(array, val->data, val->len);
+}
+
+static inline void build_append_array(GArray *array, GArray *val)
+{
+ g_array_append_vals(array, val->data, val->len);
+}
+
+static void build_append_nameseg(GArray *array, const char *format, ...)
+{
+ GString *s = g_string_new("");
+ va_list args;
+
+ va_start(args, format);
+ g_string_vprintf(s, format, args);
+ va_end(args);
+
+ assert(s->len == 4);
+ g_array_append_vals(array, s->str, s->len);
+ g_string_free(s, true);
+}
+
+/* 5.4 Definition Block Encoding */
+enum {
+ PACKAGE_LENGTH_1BYTE_SHIFT = 6, /* Up to 63 - use extra 2 bits. */
+ PACKAGE_LENGTH_2BYTE_SHIFT = 4,
+ PACKAGE_LENGTH_3BYTE_SHIFT = 12,
+ PACKAGE_LENGTH_4BYTE_SHIFT = 20,
+};
+
+static void build_prepend_package_length(GArray *package)
+{
+ uint8_t byte;
+ unsigned length = package->len;
+ unsigned length_bytes;
+
+ if (length + 1 < (1 << PACKAGE_LENGTH_1BYTE_SHIFT)) {
+ length_bytes = 1;
+ } else if (length + 2 < (1 << PACKAGE_LENGTH_3BYTE_SHIFT)) {
+ length_bytes = 2;
+ } else if (length + 3 < (1 << PACKAGE_LENGTH_4BYTE_SHIFT)) {
+ length_bytes = 3;
+ } else {
+ length_bytes = 4;
+ }
+
+ /* PkgLength is the length of the inclusive length of the data. */
+ length += length_bytes;
+
+ switch (length_bytes) {
+ case 1:
+ byte = length;
+ build_prepend_byte(package, byte);
+ return;
+ case 4:
+ byte = length >> PACKAGE_LENGTH_4BYTE_SHIFT;
+ build_prepend_byte(package, byte);
+ length &= (1 << PACKAGE_LENGTH_4BYTE_SHIFT) - 1;
+ /* fall through */
+ case 3:
+ byte = length >> PACKAGE_LENGTH_3BYTE_SHIFT;
+ build_prepend_byte(package, byte);
+ length &= (1 << PACKAGE_LENGTH_3BYTE_SHIFT) - 1;
+ /* fall through */
+ case 2:
+ byte = length >> PACKAGE_LENGTH_2BYTE_SHIFT;
+ build_prepend_byte(package, byte);
+ length &= (1 << PACKAGE_LENGTH_2BYTE_SHIFT) - 1;
+ /* fall through */
+ }
+ /*
+ * Most significant two bits of byte zero indicate how many following bytes
+ * are in PkgLength encoding.
+ */
+ byte = ((length_bytes - 1) << PACKAGE_LENGTH_1BYTE_SHIFT) | length;
+ build_prepend_byte(package, byte);
+}
+
+static void build_package(GArray *package, uint8_t op)
+{
+ build_prepend_package_length(package);
+ build_prepend_byte(package, op);
+}
+
+static void build_append_value(GArray *table, uint32_t value, int size)
+{
+ uint8_t prefix;
+ int i;
+
+ switch (size) {
+ case 1:
+ prefix = 0x0A; /* BytePrefix */
+ break;
+ case 2:
+ prefix = 0x0B; /* WordPrefix */
+ break;
+ case 4:
+ prefix = 0x0C; /* DWordPrefix */
+ default:
+ assert(0);
+ return;
+ }
+ build_append_byte(table, prefix);
+ for (i = 0; i < size; ++i) {
+ build_append_byte(table, value & 0xFF);
+ value = value >> 8;
+ }
+}
+
+static void build_append_notify_target(GArray *method, GArray *target_name,
+ uint32_t value, int size)
+{
+ GArray *notify = build_alloc_array();
+ uint8_t op = 0xA0; /* IfOp */
+
+ build_append_byte(notify, 0x93); /* LEqualOp */
+ build_append_byte(notify, 0x68); /* Arg0Op */
+ build_append_value(notify, value, size);
+ build_append_byte(notify, 0x86); /* NotifyOp */
+ build_append_array(notify, target_name);
+ build_append_byte(notify, 0x69); /* Arg1Op */
+
+ /* Pack it up */
+ build_package(notify, op);
+
+ build_append_array(method, notify);
+
+ build_free_array(notify);
+}
+
+#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
+#define ACPI_PORT_PM_BASE 0xb000
+
+static inline void *acpi_data_push(GArray *table_data, unsigned size)
+{
+ unsigned off = table_data->len;
+ g_array_set_size(table_data, off + size);
+ return table_data->data + off;
+}
+
+static unsigned acpi_data_len(GArray *table)
+{
+ return table->len * g_array_get_element_size(table);
+}
+
+static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
+{
+ uint32_t offset = cpu_to_le32(table_data->len);
+ g_array_append_val(table_offsets, offset);
+}
+
+/* FACS */
+static void
+build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
+{
+ AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
+ facs->signature = cpu_to_le32(ACPI_FACS_SIGNATURE);
+ facs->length = cpu_to_le32(sizeof(*facs));
+}
+
+/* Load chipset information into FADT */
+static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, PcGuestInfo *guest_info)
+{
+ fadt->model = 1;
+ fadt->reserved1 = 0;
+ fadt->sci_int = cpu_to_le16(guest_info->pm.sci_int);
+ fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
+ fadt->acpi_enable = guest_info->pm.acpi_enable_cmd;
+ fadt->acpi_disable = guest_info->pm.acpi_disable_cmd;
+ fadt->pm1a_evt_blk = cpu_to_le32(ACPI_PORT_PM_BASE);
+ fadt->pm1a_cnt_blk = cpu_to_le32(ACPI_PORT_PM_BASE + 0x04);
+ fadt->pm_tmr_blk = cpu_to_le32(ACPI_PORT_PM_BASE + 0x08);
+ fadt->gpe0_blk = cpu_to_le32(guest_info->pm.gpe0_blk);
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = guest_info->pm.gpe0_blk_len;
+ fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
+ fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
+ fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
+ (1 << ACPI_FADT_F_PROC_C1) |
+ (1 << ACPI_FADT_F_SLP_BUTTON) |
+ (1 << ACPI_FADT_F_RTC_S4));
+ fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
+}
+
+
+/* FADT */
+static void
+build_fadt(GArray *table_data, GArray *linker, PcGuestInfo *guest_info,
+ unsigned facs, unsigned dsdt)
+{
+ AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
+
+ fadt->firmware_ctrl = cpu_to_le32(facs);
+ /* FACS address to be filled by Guest linker */
+ bios_linker_add_pointer(linker, ACPI_BUILD_TABLE_FILE, ACPI_BUILD_TABLE_FILE,
+ table_data, &fadt->firmware_ctrl,
+ sizeof fadt->firmware_ctrl);
+
+ fadt->dsdt = cpu_to_le32(dsdt);
+ /* DSDT address to be filled by Guest linker */
+ bios_linker_add_pointer(linker, ACPI_BUILD_TABLE_FILE, ACPI_BUILD_TABLE_FILE,
+ table_data, &fadt->dsdt,
+ sizeof fadt->dsdt);
+
+ fadt_setup(fadt, guest_info);
+
+ build_header(linker, table_data,
+ (void*)fadt, ACPI_FACP_SIGNATURE, sizeof(*fadt), 1);
+}
+
+static void
+build_madt(GArray *table_data, GArray *linker, FWCfgState *fw_cfg, PcGuestInfo *guest_info)
+{
+ int madt_start = table_data->len;
+
+ AcpiMultipleApicTable *madt;
+ AcpiMadtProcessorApic *apic;
+ AcpiMadtIoApic *io_apic;
+ AcpiMadtIntsrcovr *intsrcovr;
+ AcpiMadtLocalNmi *local_nmi;
+ int i;
+
+ madt = acpi_data_push(table_data, sizeof *madt);
+ madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
+ madt->flags = cpu_to_le32(1);
+
+ for (i = 0; i < guest_info->apic_id_limit; i++) {
+ apic = acpi_data_push(table_data, sizeof *apic);
+ apic->type = ACPI_APIC_PROCESSOR;
+ apic->length = sizeof(*apic);
+ apic->processor_id = i;
+ apic->local_apic_id = i;
+ if (test_bit(i, guest_info->found_cpus))
+ apic->flags = cpu_to_le32(1);
+ else
+ apic->flags = cpu_to_le32(0);
+ apic++;
+ }
+ io_apic = acpi_data_push(table_data, sizeof *io_apic);
+ io_apic->type = ACPI_APIC_IO;
+ io_apic->length = sizeof(*io_apic);
+#define ACPI_BUILD_IOAPIC_ID 0x0
+ io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
+ io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
+ io_apic->interrupt = cpu_to_le32(0);
+
+ if (guest_info->apic_xrupt_override) {
+ intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
+ intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
+ intsrcovr->length = sizeof(*intsrcovr);
+ intsrcovr->source = 0;
+ intsrcovr->gsi = cpu_to_le32(2);
+ intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
+ }
+ for (i = 1; i < 16; i++) {
+#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
+ if (!(ACPI_BUILD_PCI_IRQS & (1 << i)))
+ /* No need for a INT source override structure. */
+ continue;
+ intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
+ intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
+ intsrcovr->length = sizeof(*intsrcovr);
+ intsrcovr->source = i;
+ intsrcovr->gsi = cpu_to_le32(i);
+ intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
+ }
+
+ local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
+ local_nmi->type = ACPI_APIC_LOCAL_NMI;
+ local_nmi->length = sizeof(*local_nmi);
+ local_nmi->processor_id = 0xff; /* all processors */
+ local_nmi->flags = cpu_to_le16(0);
+ local_nmi->lint = 1; /* ACPI_LINT1 */
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + madt_start), ACPI_APIC_SIGNATURE,
+ table_data->len - madt_start, 1);
+}
+
+/* Encode a hex value */
+static inline char acpi_get_hex(uint32_t val) {
+ val &= 0x0f;
+ return (val <= 9) ? ('0' + val) : ('A' + val - 10);
+}
+
+#include "hw/i386/ssdt-proc.hex"
+
+/* 0x5B 0x83 ProcessorOp PkgLength NameString ProcID */
+#define ACPI_PROC_OFFSET_CPUHEX (*ssdt_proc_name - *ssdt_proc_start + 2)
+#define ACPI_PROC_OFFSET_CPUID1 (*ssdt_proc_name - *ssdt_proc_start + 4)
+#define ACPI_PROC_OFFSET_CPUID2 (*ssdt_proc_id - *ssdt_proc_start)
+#define ACPI_PROC_SIZEOF (*ssdt_proc_end - *ssdt_proc_start)
+#define ACPI_PROC_AML (ssdp_proc_aml + *ssdt_proc_start)
+
+/* 0x5B 0x82 DeviceOp PkgLength NameString */
+#define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
+#define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
+#define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
+#define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
+#define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
+#define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
+
+#define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */
+#define ACPI_SSDT_HEADER_LENGTH 36
+
+#include "hw/i386/ssdt-misc.hex"
+#include "hw/i386/ssdt-pcihp.hex"
+
+static void
+build_append_notify(GArray *device, const char *name,
+ const char *format, int skip, int count)
+{
+ int i;
+ GArray *method = build_alloc_array();
+ uint8_t op = 0x14; /* MethodOp */
+
+ build_append_nameseg(method, name);
+ build_append_byte(method, 0x02); /* MethodFlags: ArgCount */
+ for (i = skip; i < count; i++) {
+ GArray *target = build_alloc_array();
+ build_append_nameseg(target, format, i);
+ assert(i < 256); /* Fits in 1 byte */
+ build_append_notify_target(method, target, i, 1);
+ build_free_array(target);
+ }
+ build_package(method, op);
+
+ build_append_array(device, method);
+ build_free_array(method);
+}
+
+static void patch_pcihp(int slot, uint8_t *ssdt_ptr, uint32_t eject)
+{
+ ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(slot >> 4);
+ ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(slot);
+ ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot;
+ ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot;
+
+ /* Runtime patching of ACPI_EJ0: to disable hotplug for a slot,
+ * replace the method name: _EJ0 by ACPI_EJ0_. */
+ /* Sanity check */
+ assert (!memcmp(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "_EJ0", 4));
+
+ if (!eject) {
+ memcpy(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "EJ0_", 4);
+ }
+}
+
+static void
+build_ssdt(GArray *table_data, GArray *linker,
+ FWCfgState *fw_cfg, PcGuestInfo *guest_info)
+{
+ int acpi_cpus = MIN(0xff, guest_info->apic_id_limit);
+ int ssdt_start = table_data->len;
+ uint8_t *ssdt_ptr;
+ int i;
+
+ /* Copy header and patch values in the S3_ / S4_ / S5_ packages */
+ ssdt_ptr = acpi_data_push(table_data, sizeof(ssdp_misc_aml));
+ memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml));
+ if (guest_info->pm.s3_disabled) {
+ ssdt_ptr[acpi_s3_name[0]] = 'X';
+ }
+ if (guest_info->pm.s4_disabled) {
+ ssdt_ptr[acpi_s4_name[0]] = 'X';
+ } else {
+ ssdt_ptr[acpi_s4_pkg[0] + 1] = ssdt_ptr[acpi_s4_pkg[0] + 3] =
+ guest_info->pm.s4_val;
+ }
+
+ *(uint32_t*)&ssdt_ptr[acpi_pci32_start[0]] =
+ cpu_to_le32(guest_info->pci_info.w32.begin);
+ *(uint32_t*)&ssdt_ptr[acpi_pci32_end[0]] =
+ cpu_to_le32(guest_info->pci_info.w32.end - 1);
+
+ if (guest_info->pci_info.w64.end > guest_info->pci_info.w64.begin) {
+ ssdt_ptr[acpi_pci64_valid[0]] = 1;
+ *(uint64_t*)&ssdt_ptr[acpi_pci64_start[0]] =
+ cpu_to_le64(guest_info->pci_info.w64.begin);
+ *(uint64_t*)&ssdt_ptr[acpi_pci64_end[0]] =
+ cpu_to_le64(guest_info->pci_info.w64.end - 1);
+ *(uint64_t*)&ssdt_ptr[acpi_pci64_length[0]] =
+ cpu_to_le64(guest_info->pci_info.w64.end -
+ guest_info->pci_info.w64.begin);
+ } else {
+ ssdt_ptr[acpi_pci64_valid[0]] = 0;
+ }
+
+ *(uint16_t *)(ssdt_ptr + *ssdt_isa_pest) =
+ cpu_to_le16(guest_info->pvpanic_port);
+
+ {
+ GArray *sb_scope = build_alloc_array();
+ uint8_t op = 0x10; /* ScopeOp */
+
+ build_append_nameseg(sb_scope, "_SB_");
+
+ /* build Processor object for each processor */
+ for (i = 0; i < acpi_cpus; i++) {
+ uint8_t *proc = acpi_data_push(sb_scope, ACPI_PROC_SIZEOF);
+ memcpy(proc, ACPI_PROC_AML, ACPI_PROC_SIZEOF);
+ proc[ACPI_PROC_OFFSET_CPUHEX] = acpi_get_hex(i >> 4);
+ proc[ACPI_PROC_OFFSET_CPUHEX+1] = acpi_get_hex(i);
+ proc[ACPI_PROC_OFFSET_CPUID1] = i;
+ proc[ACPI_PROC_OFFSET_CPUID2] = i;
+ }
+
+ /* build "Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}" */
+ /* Arg0 = Processor ID = APIC ID */
+ build_append_notify(sb_scope, "NTFY", "CP%0.02X", 0, acpi_cpus);
+
+ /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" */
+ build_append_byte(sb_scope, 0x08); /* NameOp */
+ build_append_nameseg(sb_scope, "CPON");
+
+ {
+ GArray *package = build_alloc_array();
+ uint8_t op = 0x12; /* PackageOp */
+
+ build_append_byte(package, acpi_cpus); /* NumElements */
+ for (i = 0; i < acpi_cpus; i++) {
+ uint8_t b = test_bit(i, guest_info->found_cpus) ? 0x01 : 0x00;
+ build_append_byte(package, b);
+ }
+
+ build_package(package, op);
+ build_append_array(sb_scope, package);
+ build_free_array(package);
+ }
+
+ {
+ GArray *pci0 = build_alloc_array();
+ uint8_t op = 0x10; /* ScopeOp */;
+
+ build_append_nameseg(pci0, "PCI0");
+
+ /* build Device object for each slot */
+ for (i = 1; i < PCI_SLOT_MAX; i++) {
+ bool eject = test_bit(i, guest_info->slot_hotplug_enable);
+ void *pcihp = acpi_data_push(pci0, ACPI_PCIHP_SIZEOF);
+
+ memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
+ patch_pcihp(i, pcihp, eject);
+ }
+
+ build_append_notify(pci0, "PCNT", "S%0.02X_", 1, PCI_SLOT_MAX);
+ build_package(pci0, op);
+ build_append_array(sb_scope, pci0);
+ build_free_array(pci0);
+ }
+
+ build_package(sb_scope, op);
+ build_append_array(table_data, sb_scope);
+ build_free_array(sb_scope);
+ }
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + ssdt_start),
+ ACPI_SSDT_SIGNATURE, table_data->len - ssdt_start, 1);
+}
+
+static void
+build_hpet(GArray *table_data, GArray *linker)
+{
+ Acpi20Hpet *hpet;
+
+ hpet = acpi_data_push(table_data, sizeof(*hpet));
+ /* Note timer_block_id value must be kept in sync with value advertised by
+ * emulated hpet
+ */
+ hpet->timer_block_id = cpu_to_le32(0x8086a201);
+ hpet->addr.address = cpu_to_le64(HPET_BASE);
+ build_header(linker, table_data,
+ (void*)hpet, ACPI_HPET_SIGNATURE, sizeof(*hpet), 1);
+}
+
+static void
+acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem,
+ uint64_t base, uint64_t len, int node, int enabled)
+{
+ numamem->type = ACPI_SRAT_MEMORY;
+ numamem->length = sizeof(*numamem);
+ memset(numamem->proximity, 0, 4);
+ numamem->proximity[0] = node;
+ numamem->flags = cpu_to_le32(!!enabled);
+ numamem->base_addr = cpu_to_le64(base);
+ numamem->range_length = cpu_to_le64(len);
+}
+
+static void
+build_srat(GArray *table_data, GArray *linker,
+ FWCfgState *fw_cfg, PcGuestInfo *guest_info)
+{
+ AcpiSystemResourceAffinityTable *srat;
+ AcpiSratProcessorAffinity *core;
+ AcpiSratMemoryAffinity *numamem;
+
+ int i;
+ uint64_t curnode;
+ int srat_start, numa_start, slots;
+ uint64_t mem_len, mem_base, next_base;
+
+ srat_start = table_data->len;
+
+ srat = acpi_data_push(table_data, sizeof *srat);
+ srat->reserved1 = cpu_to_le32(1);
+ core = (void*)(srat + 1);
+
+ for (i = 0; i < guest_info->apic_id_limit; ++i) {
+ core = acpi_data_push(table_data, sizeof *core);
+ core->type = ACPI_SRAT_PROCESSOR;
+ core->length = sizeof(*core);
+ core->local_apic_id = i;
+ curnode = guest_info->node_cpu[i];
+ core->proximity_lo = curnode;
+ memset(core->proximity_hi, 0, 3);
+ core->local_sapic_eid = 0;
+ if (test_bit(i, guest_info->found_cpus))
+ core->flags = cpu_to_le32(1);
+ else
+ core->flags = cpu_to_le32(0);
+ }
+
+
+ /* the memory map is a bit tricky, it contains at least one hole
+ * from 640k-1M and possibly another one from 3.5G-4G.
+ */
+ next_base = 0;
+ numa_start = table_data->len;
+
+ numamem = acpi_data_push(table_data, sizeof *numamem);
+ acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
+ next_base = 1024 * 1024;
+ for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
+ mem_base = next_base;
+ mem_len = guest_info->node_mem[i - 1];
+ if (i == 1)
+ mem_len -= 1024 * 1024;
+ next_base = mem_base + mem_len;
+
+ /* Cut out the ACPI_PCI hole */
+ if (mem_base <= guest_info->ram_size &&
+ next_base > guest_info->ram_size) {
+ mem_len -= next_base - guest_info->ram_size;
+ if (mem_len > 0) {
+ numamem = acpi_data_push(table_data, sizeof *numamem);
+ acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
+ }
+ mem_base = 1ULL << 32;
+ mem_len = next_base - guest_info->ram_size;
+ next_base += (1ULL << 32) - guest_info->ram_size;
+ }
+ numamem = acpi_data_push(table_data, sizeof *numamem);
+ acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1);
+ }
+ slots = (table_data->len - numa_start) / sizeof *numamem;
+ for (; slots < guest_info->numa_nodes + 2; slots++) {
+ numamem = acpi_data_push(table_data, sizeof *numamem);
+ acpi_build_srat_memory(numamem, 0, 0, 0, 0);
+ }
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + srat_start),
+ ACPI_SRAT_SIGNATURE,
+ table_data->len - srat_start, 1);
+}
+
+static void
+build_mcfg_q35(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
+{
+ AcpiTableMcfg *mcfg;
+
+ int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
+ mcfg = acpi_data_push(table_data, len);
+ mcfg->allocation[0].address = cpu_to_le64(guest_info->mcfg_base);
+ /* Only a single allocation so no need to play with segments */
+ mcfg->allocation[0].pci_segment = cpu_to_le16(0);
+ mcfg->allocation[0].start_bus_number = 0;
+ mcfg->allocation[0].end_bus_number = 0xFF;
+
+ build_header(linker, table_data, (void *)mcfg, ACPI_MCFG_SIGNATURE, len, 1);
+}
+
+static void
+build_dsdt(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
+{
+ void *dsdt;
+ assert(guest_info->dsdt_code && guest_info->dsdt_size);
+ dsdt = acpi_data_push(table_data, guest_info->dsdt_size);
+ memcpy(dsdt, guest_info->dsdt_code, guest_info->dsdt_size);
+}
+
+/* Build final rsdt table */
+static void
+build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
+{
+ AcpiRsdtDescriptorRev1 *rsdt;
+ size_t rsdt_len;
+ int i;
+
+ rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
+ rsdt = acpi_data_push(table_data, rsdt_len);
+ memcpy(rsdt->table_offset_entry, table_offsets->data,
+ sizeof(uint32_t) * table_offsets->len);
+ for (i = 0; i < table_offsets->len; ++i) {
+ /* rsdt->table_offset_entry to be filled by Guest linker */
+ bios_linker_add_pointer(linker,
+ ACPI_BUILD_TABLE_FILE, ACPI_BUILD_TABLE_FILE,
+ table_data, &rsdt->table_offset_entry[i],
+ sizeof(uint32_t));
+ }
+ build_header(linker, table_data,
+ (void*)rsdt, ACPI_RSDT_SIGNATURE, rsdt_len, 1);
+}
+
+static GArray *
+build_rsdp(GArray *linker, unsigned rsdt)
+{
+ GArray *rsdp_table;
+ AcpiRsdpDescriptor *rsdp;
+
+ rsdp_table = g_array_new(false, true /* clear */, sizeof *rsdp);
+ g_array_set_size(rsdp_table, 1);
+ rsdp = (void *)rsdp_table->data;
+
+ bios_linker_alloc(linker, ACPI_BUILD_RSDP_FILE, 1, true /* fseg memory */);
+
+ rsdp->signature = cpu_to_le64(ACPI_RSDP_SIGNATURE);
+ memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
+ rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
+ /* Address to be filled by Guest linker */
+ bios_linker_add_pointer(linker, ACPI_BUILD_RSDP_FILE, ACPI_BUILD_TABLE_FILE,
+ rsdp_table, &rsdp->rsdt_physical_address,
+ sizeof rsdp->rsdt_physical_address);
+ rsdp->checksum = 0;
+ /* Checksum to be filled by Guest linker */
+ bios_linker_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
+ rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
+
+ return rsdp_table;
+}
+
+static void acpi_add_rom_blob(PcGuestInfo *guest_info, GArray *blob,
+ const char *name, unsigned align)
+{
+ MemoryRegion *mr = g_malloc(sizeof(*mr));
+
+ /* Align size to multiple of given size. This reduces the chance
+ * we need to change size in the future (breaking cross version migration).
+ */
+ g_array_set_size(blob, (ROUND_UP(acpi_data_len(blob), align) +
+ g_array_get_element_size(blob) - 1) /
+ g_array_get_element_size(blob));
+ memory_region_init_ram_ptr(mr, NULL, name,
+ acpi_data_len(blob), blob->data);
+ memory_region_set_readonly(mr, true);
+ vmstate_register_ram_global(mr);
+ rom_add_blob(ACPI_BUILD_TABLE_FILE, blob->data, acpi_data_len(blob),
+ -1, mr);
+
+ fw_cfg_add_file(guest_info->fw_cfg, name,
+ blob->data, acpi_data_len(blob));
+}
+
+#define ACPI_MAX_ACPI_TABLES 20
+void acpi_setup(PcGuestInfo *guest_info)
+{
+ GArray *table_data, *table_offsets, *rsdp, *linker;
+ unsigned facs, dsdt, rsdt;
+
+ if (!guest_info->fw_cfg) {
+ ACPI_BUILD_DPRINTF(3, "No fw cfg. Boiling out.\n");
+ return;
+ }
+
+ if (!guest_info->has_acpi_build) {
+ ACPI_BUILD_DPRINTF(3, "ACPI build disabled. Boiling out.\n");
+ return;
+ }
+
+ acpi_get_pm_info(guest_info);
+ acpi_get_hotplug_info(guest_info);
+ acpi_get_misc_info(guest_info);
+
+ table_data = g_array_new(false, true /* clear */, 1);
+ table_offsets = g_array_new(false, true /* clear */,
+ sizeof(uint32_t));
+ linker = bios_linker_init();
+
+ ACPI_BUILD_DPRINTF(3, "init ACPI tables\n");
+
+ bios_linker_alloc(linker, ACPI_BUILD_TABLE_FILE, 64 /* Ensure FACS is aligned */,
+ false /* high memory */);
+
+ /*
+ * FACS is pointed to by FADT.
+ * We place it first since it's the only table that has alignment
+ * requirements.
+ */
+ facs = table_data->len;
+ build_facs(table_data, linker, guest_info);
+
+ /* DSDT is pointed to by FADT */
+ dsdt = table_data->len;
+ build_dsdt(table_data, linker, guest_info);
+
+ /* ACPI tables pointed to by RSDT */
+ acpi_add_table(table_offsets, table_data);
+ build_fadt(table_data, linker, guest_info, facs, dsdt);
+ acpi_add_table(table_offsets, table_data);
+ build_ssdt(table_data, linker, guest_info->fw_cfg, guest_info);
+ acpi_add_table(table_offsets, table_data);
+ build_madt(table_data, linker, guest_info->fw_cfg, guest_info);
+ acpi_add_table(table_offsets, table_data);
+ if (guest_info->has_hpet) {
+ build_hpet(table_data, linker);
+ }
+ if (guest_info->numa_nodes) {
+ acpi_add_table(table_offsets, table_data);
+ build_srat(table_data, linker, guest_info->fw_cfg, guest_info);
+ }
+ if (guest_info->mcfg_base) {
+ acpi_add_table(table_offsets, table_data);
+ build_mcfg_q35(table_data, linker, guest_info);
+ }
+
+ /* RSDT is pointed to by RSDP */
+ rsdt = table_data->len;
+ build_rsdt(table_data, linker, table_offsets);
+
+ /* RSDP is in FSEG memory, so allocate it separately */
+ rsdp = build_rsdp(linker, rsdt);
+
+ /* Now expose it all to Guest */
+ acpi_add_rom_blob(guest_info, table_data,
+ ACPI_BUILD_TABLE_FILE, 0x10000);
+
+ acpi_add_rom_blob(guest_info, linker,
+ "etc/linker-script", TARGET_PAGE_SIZE);
+
+ /*
+ * RSDP is small so it's easy to keep it immutable, no need to
+ * bother with ROM blobs.
+ */
+ fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
+ rsdp->data, acpi_data_len(rsdp));
+
+ /* Cleanup GArray wrappers and memory if no longer used. */
+ bios_linker_cleanup(linker);
+ g_array_free(table_offsets, true);
+ g_array_free(rsdp, false);
+ g_array_free(table_data, false);
+}
diff --git a/hw/i386/acpi-defs.h b/hw/i386/acpi-defs.h
new file mode 100644
index 0000000..e920229
--- /dev/null
+++ b/hw/i386/acpi-defs.h
@@ -0,0 +1,327 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef QEMU_ACPI_DEFS_H
+#define QEMU_ACPI_DEFS_H
+
+enum {
+ ACPI_FADT_F_WBINVD,
+ ACPI_FADT_F_WBINVD_FLUSH,
+ ACPI_FADT_F_PROC_C1,
+ ACPI_FADT_F_P_LVL2_UP,
+ ACPI_FADT_F_PWR_BUTTON,
+ ACPI_FADT_F_SLP_BUTTON,
+ ACPI_FADT_F_FIX_RTC,
+ ACPI_FADT_F_RTC_S4,
+ ACPI_FADT_F_TMR_VAL_EXT,
+ ACPI_FADT_F_DCK_CAP,
+ ACPI_FADT_F_RESET_REG_SUP,
+ ACPI_FADT_F_SEALED_CASE,
+ ACPI_FADT_F_HEADLESS,
+ ACPI_FADT_F_CPU_SW_SLP,
+ ACPI_FADT_F_PCI_EXP_WAK,
+ ACPI_FADT_F_USE_PLATFORM_CLOCK,
+ ACPI_FADT_F_S4_RTC_STS_VALID,
+ ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE,
+ ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL,
+ ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE,
+ ACPI_FADT_F_HW_REDUCED_ACPI,
+ ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
+};
+
+/*
+ * ACPI 2.0 Generic Address Space definition.
+ */
+struct Acpi20GenericAddress {
+ uint8_t address_space_id;
+ uint8_t register_bit_width;
+ uint8_t register_bit_offset;
+ uint8_t reserved;
+ uint64_t address;
+} QEMU_PACKED;
+typedef struct Acpi20GenericAddress Acpi20GenericAddress;
+
+#define ACPI_RSDP_SIGNATURE 0x2052545020445352LL // "RSD PTR "
+
+struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */
+ uint64_t signature; /* ACPI signature, contains "RSD PTR " */
+ uint8_t checksum; /* To make sum of struct == 0 */
+ uint8_t oem_id [6]; /* OEM identification */
+ uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
+ uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
+ uint32_t length; /* XSDT Length in bytes including hdr */
+ uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
+ uint8_t extended_checksum; /* Checksum of entire table */
+ uint8_t reserved [3]; /* Reserved field must be 0 */
+} QEMU_PACKED;
+typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor;
+
+/* Table structure from Linux kernel (the ACPI tables are under the
+ BSD license) */
+
+
+#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
+ uint32_t signature; /* ACPI signature (4 ASCII characters) */ \
+ uint32_t length; /* Length of table, in bytes, including header */ \
+ uint8_t revision; /* ACPI Specification minor version # */ \
+ uint8_t checksum; /* To make sum of entire table == 0 */ \
+ uint8_t oem_id [6]; /* OEM identification */ \
+ uint8_t oem_table_id [8]; /* OEM table identification */ \
+ uint32_t oem_revision; /* OEM revision number */ \
+ uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */ \
+ uint32_t asl_compiler_revision; /* ASL compiler revision number */
+
+
+struct AcpiTableHeader /* ACPI common table header */
+{
+ ACPI_TABLE_HEADER_DEF
+} QEMU_PACKED;
+typedef struct AcpiTableHeader AcpiTableHeader;
+
+/*
+ * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ */
+#define ACPI_FACP_SIGNATURE 0x50434146 // FACP
+struct AcpiFadtDescriptorRev1
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t firmware_ctrl; /* Physical address of FACS */
+ uint32_t dsdt; /* Physical address of DSDT */
+ uint8_t model; /* System Interrupt Model */
+ uint8_t reserved1; /* Reserved */
+ uint16_t sci_int; /* System vector of SCI interrupt */
+ uint32_t smi_cmd; /* Port address of SMI command port */
+ uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
+ uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
+ uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
+ uint8_t reserved2; /* Reserved - must be zero */
+ uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
+ uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
+ uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
+ uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
+ uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
+ uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
+ uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
+ uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
+ uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
+ uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
+ uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
+ uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
+ uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
+ uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
+ uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
+ uint8_t reserved3; /* Reserved */
+ uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
+ uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
+ uint16_t flush_size; /* Size of area read to flush caches */
+ uint16_t flush_stride; /* Stride used in flushing caches */
+ uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
+ uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
+ uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
+ uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
+ uint8_t century; /* Index to century in RTC CMOS RAM */
+ uint8_t reserved4; /* Reserved */
+ uint8_t reserved4a; /* Reserved */
+ uint8_t reserved4b; /* Reserved */
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
+
+/*
+ * ACPI 1.0 Root System Description Table (RSDT)
+ */
+#define ACPI_RSDT_SIGNATURE 0x54445352 // RSDT
+struct AcpiRsdtDescriptorRev1
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t table_offset_entry[0]; /* Array of pointers to other */
+ /* ACPI tables */
+} QEMU_PACKED;
+typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
+
+/*
+ * ACPI 1.0 Firmware ACPI Control Structure (FACS)
+ */
+#define ACPI_FACS_SIGNATURE 0x53434146 // FACS
+struct AcpiFacsDescriptorRev1
+{
+ uint32_t signature; /* ACPI Signature */
+ uint32_t length; /* Length of structure, in bytes */
+ uint32_t hardware_signature; /* Hardware configuration signature */
+ uint32_t firmware_waking_vector; /* ACPI OS waking vector */
+ uint32_t global_lock; /* Global Lock */
+ uint32_t flags;
+ uint8_t resverved3 [40]; /* Reserved - must be zero */
+} QEMU_PACKED;
+typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
+
+/*
+ * Differentiated System Description Table (DSDT)
+ */
+#define ACPI_DSDT_SIGNATURE 0x54445344 // DSDT
+
+/*
+ * MADT values and structures
+ */
+
+/* Values for MADT PCATCompat */
+
+#define ACPI_DUAL_PIC 0
+#define ACPI_MULTIPLE_APIC 1
+
+/* Master MADT */
+
+#define ACPI_APIC_SIGNATURE 0x43495041 // APIC
+struct AcpiMultipleApicTable
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t local_apic_address; /* Physical address of local APIC */
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
+
+/* Values for Type in APIC sub-headers */
+
+#define ACPI_APIC_PROCESSOR 0
+#define ACPI_APIC_IO 1
+#define ACPI_APIC_XRUPT_OVERRIDE 2
+#define ACPI_APIC_NMI 3
+#define ACPI_APIC_LOCAL_NMI 4
+#define ACPI_APIC_ADDRESS_OVERRIDE 5
+#define ACPI_APIC_IO_SAPIC 6
+#define ACPI_APIC_LOCAL_SAPIC 7
+#define ACPI_APIC_XRUPT_SOURCE 8
+#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
+
+/*
+ * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
+ */
+#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
+ uint8_t type; \
+ uint8_t length;
+
+/* Sub-structures for MADT */
+
+struct AcpiMadtProcessorApic
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t processor_id; /* ACPI processor id */
+ uint8_t local_apic_id; /* Processor's local APIC id */
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
+
+struct AcpiMadtIoApic
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t io_apic_id; /* I/O APIC ID */
+ uint8_t reserved; /* Reserved - must be zero */
+ uint32_t address; /* APIC physical address */
+ uint32_t interrupt; /* Global system interrupt where INTI
+ * lines start */
+} QEMU_PACKED;
+typedef struct AcpiMadtIoApic AcpiMadtIoApic;
+
+struct AcpiMadtIntsrcovr {
+ ACPI_SUB_HEADER_DEF
+ uint8_t bus;
+ uint8_t source;
+ uint32_t gsi;
+ uint16_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
+
+struct AcpiMadtLocalNmi {
+ ACPI_SUB_HEADER_DEF
+ uint8_t processor_id; /* ACPI processor id */
+ uint16_t flags; /* MPS INTI flags */
+ uint8_t lint; /* Local APIC LINT# */
+} QEMU_PACKED;
+typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
+
+/*
+ * HPET Description Table
+ */
+#define ACPI_HPET_SIGNATURE 0x54455048 // HPET
+struct Acpi20Hpet {
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t timer_block_id;
+ Acpi20GenericAddress addr;
+ uint8_t hpet_number;
+ uint16_t min_tick;
+ uint8_t page_protect;
+} QEMU_PACKED;
+typedef struct Acpi20Hpet Acpi20Hpet;
+
+/*
+ * SRAT (NUMA topology description) table
+ */
+
+#define ACPI_SRAT_SIGNATURE 0x54415253 // SRAT
+struct AcpiSystemResourceAffinityTable
+{
+ ACPI_TABLE_HEADER_DEF
+ uint32_t reserved1;
+ uint32_t reserved2[2];
+} QEMU_PACKED;
+typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
+
+#define ACPI_SRAT_PROCESSOR 0
+#define ACPI_SRAT_MEMORY 1
+
+struct AcpiSratProcessorAffinity
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t proximity_lo;
+ uint8_t local_apic_id;
+ uint32_t flags;
+ uint8_t local_sapic_eid;
+ uint8_t proximity_hi[3];
+ uint32_t reserved;
+} QEMU_PACKED;
+typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
+
+struct AcpiSratMemoryAffinity
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t proximity[4];
+ uint16_t reserved1;
+ uint64_t base_addr;
+ uint64_t range_length;
+ uint32_t reserved2;
+ uint32_t flags;
+ uint32_t reserved3[2];
+} QEMU_PACKED;
+typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
+
+/* PCI fw r3.0 MCFG table. */
+/* Subtable */
+struct AcpiMcfgAllocation {
+ uint64_t address; /* Base address, processor-relative */
+ uint16_t pci_segment; /* PCI segment group number */
+ uint8_t start_bus_number; /* Starting PCI Bus number */
+ uint8_t end_bus_number; /* Final PCI Bus number */
+ uint32_t reserved;
+} QEMU_PACKED;
+typedef struct AcpiMcfgAllocation AcpiMcfgAllocation;
+
+#define ACPI_MCFG_SIGNATURE 0x4746434d // MCFG
+struct AcpiTableMcfg {
+ ACPI_TABLE_HEADER_DEF;
+ uint8_t reserved[8];
+ AcpiMcfgAllocation allocation[0];
+} QEMU_PACKED;
+typedef struct AcpiTableMcfg AcpiTableMcfg;
+
+#endif
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index b9b8f92..edd49e5 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -55,6 +55,7 @@
#include "hw/acpi/acpi.h"
#include "hw/cpu/icc_bus.h"
#include "hw/boards.h"
+#include "hw/i386/acpi-build.h"
/* debug PC/ISA interrupts */
//#define DEBUG_IRQ
@@ -1050,6 +1051,7 @@ void pc_guest_info_machine_done(Notifier *notifier, void *data)
PcGuestInfoState,
machine_done);
pc_fw_cfg_guest_info(&guest_info_state->info);
+ acpi_setup(&guest_info_state->info);
}
PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index b58c255..f365e6e 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -58,6 +58,7 @@ static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
static bool has_pvpanic = true;
static bool has_pci_info = true;
+static bool has_acpi_build = true;
/* PC hardware initialisation */
static void pc_init1(MemoryRegion *system_memory,
@@ -127,6 +128,9 @@ static void pc_init1(MemoryRegion *system_memory,
}
guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
+
+ guest_info->has_acpi_build = has_acpi_build;
+
guest_info->has_pci_info = has_pci_info;
/* Set PCI window size the way seabios has always done it. */
@@ -264,6 +268,7 @@ static void pc_init_pci(QEMUMachineInitArgs *args)
static void pc_init_pci_1_5(QEMUMachineInitArgs *args)
{
has_pci_info = false;
+ has_acpi_build = false;
pc_init_pci(args);
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 0b1d2e3..0edd408 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -48,6 +48,7 @@
static bool has_pvpanic = true;
static bool has_pci_info = true;
+static bool has_acpi_build = true;
/* PC hardware initialisation */
static void pc_q35_init(QEMUMachineInitArgs *args)
@@ -110,6 +111,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
guest_info->has_pci_info = has_pci_info;
+ guest_info->has_acpi_build = has_acpi_build;
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
@@ -219,6 +221,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
static void pc_q35_init_1_5(QEMUMachineInitArgs *args)
{
has_pci_info = false;
+ has_acpi_build = false;
pc_q35_init(args);
}
diff --git a/include/hw/i386/acpi-build.h b/include/hw/i386/acpi-build.h
new file mode 100644
index 0000000..e57b1aa
--- /dev/null
+++ b/include/hw/i386/acpi-build.h
@@ -0,0 +1,9 @@
+
+#ifndef HW_I386_ACPI_BUILD_H
+#define HW_I386_ACPI_BUILD_H
+
+#include "qemu/typedefs.h"
+
+void acpi_setup(PcGuestInfo *);
+
+#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index e718a59..0020332 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -52,6 +52,7 @@ struct PcGuestInfo {
unsigned dsdt_size;
uint16_t pvpanic_port;
FWCfgState *fw_cfg;
+ bool has_acpi_build;
};
/* parallel.c */
--
MST
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 05/14] loader: use file path size from fw_cfg.h
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 05/14] loader: use file path size from fw_cfg.h Michael S. Tsirkin
@ 2013-07-24 23:42 ` Andreas Färber
2013-07-25 12:10 ` Gerd Hoffmann
1 sibling, 0 replies; 69+ messages in thread
From: Andreas Färber @ 2013-07-24 23:42 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
Am 24.07.2013 18:01, schrieb Michael S. Tsirkin:
> Avoid a bit of code duplication, make
> max file path constant reusable.
>
> Suggested-by: Laszlo Ersek <lersek@redhat.com>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 11/14] piix: " Michael S. Tsirkin
@ 2013-07-25 9:32 ` Michael S. Tsirkin
2013-07-28 0:12 ` Andreas Färber
2013-07-25 12:34 ` Gerd Hoffmann
1 sibling, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 9:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
On Wed, Jul 24, 2013 at 07:02:13PM +0300, Michael S. Tsirkin wrote:
> This adds APIs that will be used to fill in guest info table,
> implemented using QOM, to various piix components.
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/piix4.c | 29 +++++++++++++++++++++++++++--
> hw/mips/mips_malta.c | 2 +-
> hw/pci-host/piix.c | 8 ++++++++
> include/hw/i386/pc.h | 1 +
> include/qemu/typedefs.h | 1 +
> 5 files changed, 38 insertions(+), 3 deletions(-)
Ouch, forgot to git add a file, so it's missing.
include/hw/acpi/piix4.h below.
Corrected patch with this chunk added below.
It's trivial so not reposting.
--->
Subject: piix: APIs for pc guest info
This adds APIs that will be used to fill in guest info table,
implemented using QOM, to various piix components.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index c885690..2128f13 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -29,6 +29,7 @@
#include "exec/ioport.h"
#include "hw/nvram/fw_cfg.h"
#include "exec/address-spaces.h"
+#include "hw/acpi/piix4.h"
//#define DEBUG
@@ -63,7 +64,7 @@ typedef struct CPUStatus {
uint8_t sts[PIIX4_PROC_LEN];
} CPUStatus;
-typedef struct PIIX4PMState {
+struct PIIX4PMState {
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
@@ -96,7 +97,7 @@ typedef struct PIIX4PMState {
CPUStatus gpe_cpu;
Notifier cpu_added_notifier;
-} PIIX4PMState;
+};
#define TYPE_PIIX4_PM "PIIX4_PM"
@@ -458,6 +459,30 @@ static int piix4_pm_initfn(PCIDevice *dev)
return 0;
}
+PIIX4PMState *piix4_pm_find(void)
+{
+ bool ambig;
+ Object *o = object_resolve_path_type("", "PIIX4_PM", &ambig);
+
+ if (ambig || !o) {
+ return NULL;
+ }
+ return OBJECT_CHECK(PIIX4PMState, o, "PIIX4_PM");
+}
+
+void piix4_pm_get_acpi_pm_info(PIIX4PMState *s, AcpiPmInfo *info)
+{
+ info->s3_disabled = s->disable_s3;
+ info->s4_disabled = s->disable_s4;
+ info->s4_val = s->s4_val;
+
+ info->acpi_enable_cmd = ACPI_ENABLE;
+ info->acpi_disable_cmd = ACPI_DISABLE;
+ info->gpe0_blk = GPE_BASE;
+ info->gpe0_blk_len = GPE_LEN;
+ info->sci_int = 9;
+}
+
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int kvm_enabled, FWCfgState *fw_cfg)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index de87241..14573ab 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -965,7 +965,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
- isa_get_irq(NULL, 9), NULL, 0, NULL);
+ isa_get_irq(NULL, 9), NULL, 0, NULL, NULL);
/* TODO: Populate SPD eeprom data. */
smbus_eeprom_init(smbus, 8, NULL, 0);
pit = pit_init(isa_bus, 0x40, 0, NULL);
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3908860..daefdfb 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -349,6 +349,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
return b;
}
+PCIBus *find_i440fx(void)
+{
+ PCIHostState *s = OBJECT_CHECK(PCIHostState,
+ object_resolve_path("/machine/i440fx", NULL),
+ TYPE_PCI_HOST_BRIDGE);
+ return s ? s->bus : NULL;
+}
+
/* PIIX3 PCI to ISA bridge */
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
new file mode 100644
index 0000000..2876428
--- /dev/null
+++ b/include/hw/acpi/piix4.h
@@ -0,0 +1,10 @@
+#ifndef HW_ACPI_PIIX4_H
+#define HW_ACPI_PIIX4_H
+
+#include "qemu/typedefs.h"
+
+PIIX4PMState *piix4_pm_find(void);
+
+void piix4_pm_get_acpi_pm_info(PIIX4PMState *, AcpiPmInfo *);
+
+#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 7c0bd50..76af5cd 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -186,6 +186,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
+PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index cb66e19..7d42693 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -65,6 +65,7 @@ typedef struct QEMUSGList QEMUSGList;
typedef struct SHPCDevice SHPCDevice;
typedef struct FWCfgState FWCfgState;
typedef struct PcGuestInfo PcGuestInfo;
+typedef struct PIIX4PMState PIIX4PMState;
typedef struct AcpiPmInfo AcpiPmInfo;
#endif /* QEMU_TYPEDEFS_H */
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port Michael S. Tsirkin
@ 2013-07-25 10:29 ` Gerd Hoffmann
2013-07-25 10:55 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 10:29 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
On 07/24/13 18:02, Michael S. Tsirkin wrote:
> Add API to find pvpanic device and get its io port.
> Will be used to fill in guest info structure.
> +uint16_t pvpanic_port(void)
> +{
> + Object *o = object_resolve_path_type("", TYPE_ISA_PVPANIC_DEVICE, NULL);
> + PVPanicState *s;
> + if (!o) {
> + return 0;
> + }
return object_property_get_int(o, "ioport");
}
Then you don't need PVPanicState access and can place the code into
acpi-build.c.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port
2013-07-25 10:29 ` Gerd Hoffmann
@ 2013-07-25 10:55 ` Michael S. Tsirkin
2013-07-25 10:58 ` Michael S. Tsirkin
2013-07-25 11:05 ` Gerd Hoffmann
0 siblings, 2 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 10:55 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel
On Thu, Jul 25, 2013 at 12:29:52PM +0200, Gerd Hoffmann wrote:
> On 07/24/13 18:02, Michael S. Tsirkin wrote:
> > Add API to find pvpanic device and get its io port.
> > Will be used to fill in guest info structure.
>
> > +uint16_t pvpanic_port(void)
> > +{
> > + Object *o = object_resolve_path_type("", TYPE_ISA_PVPANIC_DEVICE, NULL);
> > + PVPanicState *s;
> > + if (!o) {
> > + return 0;
> > + }
>
> return object_property_get_int(o, "ioport");
> }
>
> Then you don't need PVPanicState access and can place the code into
> acpi-build.c.
>
> cheers,
> Gerd
I can change the implementation but I don't think it's
a good idea to copy property names around:
it's too fragile, compiler won't warn us if we
change the name or value semantics, or make
a mistake in acpi-build.c
Same applies to TYPE_ISA_PVPANIC_DEVICE: better
to expose an API than expose the type externally.
--
MST
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port
2013-07-25 10:55 ` Michael S. Tsirkin
@ 2013-07-25 10:58 ` Michael S. Tsirkin
2013-07-25 11:05 ` Gerd Hoffmann
1 sibling, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 10:58 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel
On Thu, Jul 25, 2013 at 01:55:26PM +0300, Michael S. Tsirkin wrote:
> On Thu, Jul 25, 2013 at 12:29:52PM +0200, Gerd Hoffmann wrote:
> > On 07/24/13 18:02, Michael S. Tsirkin wrote:
> > > Add API to find pvpanic device and get its io port.
> > > Will be used to fill in guest info structure.
> >
> > > +uint16_t pvpanic_port(void)
> > > +{
> > > + Object *o = object_resolve_path_type("", TYPE_ISA_PVPANIC_DEVICE, NULL);
> > > + PVPanicState *s;
> > > + if (!o) {
> > > + return 0;
> > > + }
> >
> > return object_property_get_int(o, "ioport");
> > }
> >
> > Then you don't need PVPanicState access and can place the code into
> > acpi-build.c.
> >
> > cheers,
> > Gerd
>
> I can change the implementation but I don't think it's
> a good idea to copy property names around:
> it's too fragile, compiler won't warn us if we
> change the name or value semantics, or make
> a mistake in acpi-build.c
And even within pvpanic.c, this will make me copy-paste
the "ioport" string or create yet another macro.
s = ISA_PVPANIC_DEVICE(o);
return s->ioport;
seems nicer.
> Same applies to TYPE_ISA_PVPANIC_DEVICE: better
> to expose an API than expose the type externally.
> --
> MST
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port
2013-07-25 10:55 ` Michael S. Tsirkin
2013-07-25 10:58 ` Michael S. Tsirkin
@ 2013-07-25 11:05 ` Gerd Hoffmann
2013-07-25 11:22 ` Michael S. Tsirkin
1 sibling, 1 reply; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 11:05 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
Hi,
> I can change the implementation but I don't think it's
> a good idea to copy property names around:
> it's too fragile, compiler won't warn us if we
> change the name or value semantics,
I'm not worried. Changing the strings will break the command line
interface too (qemu -device pvpanic,ioport=...), so that isn't going to
happen.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port
2013-07-25 11:05 ` Gerd Hoffmann
@ 2013-07-25 11:22 ` Michael S. Tsirkin
2013-07-25 12:03 ` Gerd Hoffmann
0 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 11:22 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel
On Thu, Jul 25, 2013 at 01:05:12PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> > I can change the implementation but I don't think it's
> > a good idea to copy property names around:
> > it's too fragile, compiler won't warn us if we
> > change the name or value semantics,
>
> I'm not worried. Changing the strings will break the command line
> interface too (qemu -device pvpanic,ioport=...), so that isn't going to
> happen.
>
> cheers,
> Gerd
What will catch this breakage?
There are 0 users actually tweaking the port
number so I'm sure no one will notice this.
In any case, catching errors at compile time
is much better than at runtime.
What exactly are advantages of duplicating
property names in this way? I don't see any.
--
MST
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port
2013-07-25 11:22 ` Michael S. Tsirkin
@ 2013-07-25 12:03 ` Gerd Hoffmann
2013-07-25 12:23 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:03 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
On 07/25/13 13:22, Michael S. Tsirkin wrote:
> On Thu, Jul 25, 2013 at 01:05:12PM +0200, Gerd Hoffmann wrote:
>> Hi,
>>
>>> I can change the implementation but I don't think it's
>>> a good idea to copy property names around:
>>> it's too fragile, compiler won't warn us if we
>>> change the name or value semantics,
>>
>> I'm not worried. Changing the strings will break the command line
>> interface too (qemu -device pvpanic,ioport=...), so that isn't going to
>> happen.
>>
>> cheers,
>> Gerd
>
> What will catch this breakage?
> There are 0 users actually tweaking the port
> number so I'm sure no one will notice this.
>
> In any case, catching errors at compile time
> is much better than at runtime.
>
> What exactly are advantages of duplicating
> property names in this way? I don't see any.
You don't need access to pvpanic internals then and thus the code can be
moved over to the acpi generator. At least in this case where all info
needed is already available via properties.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 01/14] hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 01/14] hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h Michael S. Tsirkin
@ 2013-07-25 12:05 ` Gerd Hoffmann
2013-07-28 0:44 ` Andreas Färber
1 sibling, 0 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:05 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Anthony Liguori, Laszlo Ersek, qemu-devel
On 07/24/13 18:01, Michael S. Tsirkin wrote:
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> Signed-off-by: Laszlo Ersek <lersek@redhat.com>
> ---
> hw/i386/pc.c | 2 --
> include/hw/i386/apic.h | 2 ++
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 03/14] acpi: add rules to compile ASL source
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 03/14] acpi: add rules to compile ASL source Michael S. Tsirkin
@ 2013-07-25 12:09 ` Gerd Hoffmann
0 siblings, 0 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:09 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
On 07/24/13 18:01, Michael S. Tsirkin wrote:
> Detect presence of IASL compiler and use it
> to process ASL source. If not there, use pre-compiled
> files in-tree. Add script to update the in-tree files.
>
> Note: distros are known to silently update iasl
> so detect correct iasl flags for the installed version on each run as
> opposed to at configure time.
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 05/14] loader: use file path size from fw_cfg.h
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 05/14] loader: use file path size from fw_cfg.h Michael S. Tsirkin
2013-07-24 23:42 ` Andreas Färber
@ 2013-07-25 12:10 ` Gerd Hoffmann
1 sibling, 0 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:10 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
On 07/24/13 18:01, Michael S. Tsirkin wrote:
> Avoid a bit of code duplication, make
> max file path constant reusable.
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 06/14] i386: add bios linker/loader
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 06/14] i386: add bios linker/loader Michael S. Tsirkin
@ 2013-07-25 12:11 ` Gerd Hoffmann
2013-07-26 9:42 ` Gerd Hoffmann
1 sibling, 0 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:11 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
On 07/24/13 18:01, Michael S. Tsirkin wrote:
> This adds a dynamic bios linker/loader.
> This will be used by acpi table generation
> code to:
> - load each table in the appropriate memory segment
> - link tables to each other
> - fix up checksums after said linking
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs Michael S. Tsirkin
@ 2013-07-25 12:14 ` Gerd Hoffmann
2013-07-25 12:28 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:14 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Michael Walle, qemu-devel
On 07/24/13 18:01, Michael S. Tsirkin wrote:
> QTAILQ_FOREACH(rom, &roms, next) {
> + if (rom->mr) {
> + continue;
> + }
> if (rom->fw_file) {
> continue;
> }
> if (rom->data == NULL) {
> continue;
> }
> - cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
> + if (rom->mr) {
> + void *host = memory_region_get_ram_ptr(rom->mr);
> + memcpy(host, rom->data, rom->datasize);
I think this code never ever runs ...
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 08/14] loader: allow adding ROMs in done callbacks
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 08/14] loader: allow adding ROMs in done callbacks Michael S. Tsirkin
@ 2013-07-25 12:15 ` Gerd Hoffmann
0 siblings, 0 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:15 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Anthony Liguori, qemu-devel
On 07/24/13 18:02, Michael S. Tsirkin wrote:
> Don't abort if machine done callbacks add ROMs.
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port
2013-07-25 12:03 ` Gerd Hoffmann
@ 2013-07-25 12:23 ` Michael S. Tsirkin
2013-07-27 23:58 ` Andreas Färber
0 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 12:23 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel
On Thu, Jul 25, 2013 at 02:03:33PM +0200, Gerd Hoffmann wrote:
> On 07/25/13 13:22, Michael S. Tsirkin wrote:
> > On Thu, Jul 25, 2013 at 01:05:12PM +0200, Gerd Hoffmann wrote:
> >> Hi,
> >>
> >>> I can change the implementation but I don't think it's
> >>> a good idea to copy property names around:
> >>> it's too fragile, compiler won't warn us if we
> >>> change the name or value semantics,
> >>
> >> I'm not worried. Changing the strings will break the command line
> >> interface too (qemu -device pvpanic,ioport=...), so that isn't going to
> >> happen.
> >>
> >> cheers,
> >> Gerd
> >
> > What will catch this breakage?
> > There are 0 users actually tweaking the port
> > number so I'm sure no one will notice this.
> >
> > In any case, catching errors at compile time
> > is much better than at runtime.
> >
> > What exactly are advantages of duplicating
> > property names in this way? I don't see any.
>
> You don't need access to pvpanic internals then and thus the code can be
> moved over to the acpi generator. At least in this case where all info
> needed is already available via properties.
>
> cheers,
> Gerd
We'll have to disagree here.
There's no access to internals with an API.
I prefer using APIs, since they are compiler-checked.
--
MST
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs
2013-07-25 12:14 ` Gerd Hoffmann
@ 2013-07-25 12:28 ` Michael S. Tsirkin
2013-07-25 12:43 ` Gerd Hoffmann
0 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 12:28 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Michael Walle, qemu-devel
On Thu, Jul 25, 2013 at 02:14:40PM +0200, Gerd Hoffmann wrote:
> On 07/24/13 18:01, Michael S. Tsirkin wrote:
> > QTAILQ_FOREACH(rom, &roms, next) {
> > + if (rom->mr) {
> > + continue;
> > + }
> > if (rom->fw_file) {
> > continue;
> > }
> > if (rom->data == NULL) {
> > continue;
> > }
> > - cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
> > + if (rom->mr) {
> > + void *host = memory_region_get_ram_ptr(rom->mr);
> > + memcpy(host, rom->data, rom->datasize);
>
> I think this code never ever runs ...
>
> cheers,
> Gerd
>
Could you be clearer please? This chunk is in rom_reset,
I think it runs on reset.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 09/14] i386: define pc guest info
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 09/14] i386: define pc guest info Michael S. Tsirkin
@ 2013-07-25 12:31 ` Gerd Hoffmann
2013-07-28 0:41 ` Andreas Färber
1 sibling, 0 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:31 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Anthony Liguori, qemu-devel
On 07/24/13 18:02, Michael S. Tsirkin wrote:
> This defines a structure that will be used to fill in guest info table.
> This structure will be filled in in follow-up patches, using QOM. Fill
> in NUMA node info is not available in QOM so it is filled in directly.
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 10/14] ich9: APIs for pc guest info
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 10/14] ich9: APIs for " Michael S. Tsirkin
@ 2013-07-25 12:33 ` Gerd Hoffmann
2013-07-28 0:37 ` Andreas Färber
1 sibling, 0 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:33 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
On 07/24/13 18:02, Michael S. Tsirkin wrote:
> This adds APIs that will be used to fill in
> guest info table, implemented using QOM,
> to various ich9 components.
Uses QOM to lookup the device state without needing nasty hooks in
machine creation. Then goes copy info directly from device state as the
bits needed are not exported as properties. Looks reasonable to me.
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 11/14] piix: " Michael S. Tsirkin
2013-07-25 9:32 ` Michael S. Tsirkin
@ 2013-07-25 12:34 ` Gerd Hoffmann
1 sibling, 0 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:34 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Aurelien Jarno
On 07/24/13 18:02, Michael S. Tsirkin wrote:
> This adds APIs that will be used to fill in guest info table,
> implemented using QOM, to various piix components.
Like ich9.
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 13/14] hpet: add API to find it
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 13/14] hpet: add API to find it Michael S. Tsirkin
@ 2013-07-25 12:36 ` Gerd Hoffmann
2013-07-27 23:38 ` Andreas Färber
1 sibling, 0 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:36 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
On 07/24/13 18:02, Michael S. Tsirkin wrote:
> +bool hpet_find(void)
given this returns just a bool hpet_present() would be a better name I
think.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs
2013-07-25 12:28 ` Michael S. Tsirkin
@ 2013-07-25 12:43 ` Gerd Hoffmann
2013-07-25 13:03 ` Michael S. Tsirkin
2013-07-25 19:57 ` Michael S. Tsirkin
0 siblings, 2 replies; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 12:43 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Michael Walle, qemu-devel
On 07/25/13 14:28, Michael S. Tsirkin wrote:
> On Thu, Jul 25, 2013 at 02:14:40PM +0200, Gerd Hoffmann wrote:
>> On 07/24/13 18:01, Michael S. Tsirkin wrote:
>>> QTAILQ_FOREACH(rom, &roms, next) {
>>> + if (rom->mr) {
>>> + continue;
>>> + }
>>> if (rom->fw_file) {
>>> continue;
>>> }
>>> if (rom->data == NULL) {
>>> continue;
>>> }
>>> - cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
>>> + if (rom->mr) {
>>> + void *host = memory_region_get_ram_ptr(rom->mr);
>>> + memcpy(host, rom->data, rom->datasize);
>>
>> I think this code never ever runs ...
>>
>> cheers,
>> Gerd
>>
>
>
> Could you be clearer please? This chunk is in rom_reset,
> I think it runs on reset.
You have the "if (rom->mr)" twice in the loop. The first does continue
so the second will never ever evaluate to true, thereby making the
memcpy dead code.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs
2013-07-25 12:43 ` Gerd Hoffmann
@ 2013-07-25 13:03 ` Michael S. Tsirkin
2013-07-25 19:57 ` Michael S. Tsirkin
1 sibling, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 13:03 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Michael Walle, qemu-devel
On Thu, Jul 25, 2013 at 02:43:53PM +0200, Gerd Hoffmann wrote:
> On 07/25/13 14:28, Michael S. Tsirkin wrote:
> > On Thu, Jul 25, 2013 at 02:14:40PM +0200, Gerd Hoffmann wrote:
> >> On 07/24/13 18:01, Michael S. Tsirkin wrote:
> >>> QTAILQ_FOREACH(rom, &roms, next) {
> >>> + if (rom->mr) {
> >>> + continue;
> >>> + }
> >>> if (rom->fw_file) {
> >>> continue;
> >>> }
> >>> if (rom->data == NULL) {
> >>> continue;
> >>> }
> >>> - cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
> >>> + if (rom->mr) {
> >>> + void *host = memory_region_get_ram_ptr(rom->mr);
> >>> + memcpy(host, rom->data, rom->datasize);
> >>
> >> I think this code never ever runs ...
> >>
> >> cheers,
> >> Gerd
> >>
> >
> >
> > Could you be clearer please? This chunk is in rom_reset,
> > I think it runs on reset.
>
> You have the "if (rom->mr)" twice in the loop. The first does continue
> so the second will never ever evaluate to true, thereby making the
> memcpy dead code.
>
> cheers,
> Gerd
Hmm that's a bugt I think. Thanks!
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios Michael S. Tsirkin
@ 2013-07-25 13:06 ` Gerd Hoffmann
2013-07-25 13:23 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 13:06 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Anthony Liguori, qemu-devel
Hi,
> As table content is likely to change over time,
> the following measures are taken to simplify
> cross-version migration:
> - All tables besides the RSDP are packed in a single FW CFG entry.
> This entry size is currently 23K. We round it up to 64K
> to avoid too much churn there.
Does it need to be that way? I'd prefer to have one fw_cfg entry per table.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios
2013-07-25 13:06 ` Gerd Hoffmann
@ 2013-07-25 13:23 ` Michael S. Tsirkin
2013-07-25 14:58 ` Gerd Hoffmann
0 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 13:23 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Anthony Liguori, qemu-devel
On Thu, Jul 25, 2013 at 03:06:25PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> > As table content is likely to change over time,
> > the following measures are taken to simplify
> > cross-version migration:
> > - All tables besides the RSDP are packed in a single FW CFG entry.
> > This entry size is currently 23K. We round it up to 64K
> > to avoid too much churn there.
>
> Does it need to be that way? I'd prefer to have one fw_cfg entry per table.
>
> cheers,
> Gerd
>
It's better I think. The advantages are:
- when we add more tables we don't break cross-version
migration compatibility
- we have limited number of files, this way we won't
run out of them
what are advantages of file per table?
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios
2013-07-25 13:23 ` Michael S. Tsirkin
@ 2013-07-25 14:58 ` Gerd Hoffmann
2013-07-25 15:14 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-25 14:58 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Anthony Liguori, qemu-devel
On 07/25/13 15:23, Michael S. Tsirkin wrote:
> On Thu, Jul 25, 2013 at 03:06:25PM +0200, Gerd Hoffmann wrote:
>> Hi,
>>
>>> As table content is likely to change over time,
>>> the following measures are taken to simplify
>>> cross-version migration:
>>> - All tables besides the RSDP are packed in a single FW CFG entry.
>>> This entry size is currently 23K. We round it up to 64K
>>> to avoid too much churn there.
>>
>> Does it need to be that way? I'd prefer to have one fw_cfg entry per table.
>>
>> cheers,
>> Gerd
>>
>
> It's better I think. The advantages are:
> - when we add more tables we don't break cross-version
> migration compatibility
New tables are a guest-visible change, so I think we have to turn them
off for old machine types via compat properties anyway. This will also
solve the migration issue.
> - we have limited number of files, this way we won't
> run out of them
Anything which prevents us from raising that number?
> what are advantages of file per table?
You can look at the tables without doing a full linker pass first, so
the firmware can easily initialize the hardware according to what it
finds in specific acpi tables. Check FADT for pm_base. Check MCFG for
mmconf xbar location.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios
2013-07-25 14:58 ` Gerd Hoffmann
@ 2013-07-25 15:14 ` Michael S. Tsirkin
2013-07-26 9:06 ` Gerd Hoffmann
0 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 15:14 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Anthony Liguori, qemu-devel
On Thu, Jul 25, 2013 at 04:58:20PM +0200, Gerd Hoffmann wrote:
> On 07/25/13 15:23, Michael S. Tsirkin wrote:
> > On Thu, Jul 25, 2013 at 03:06:25PM +0200, Gerd Hoffmann wrote:
> >> Hi,
> >>
> >>> As table content is likely to change over time,
> >>> the following measures are taken to simplify
> >>> cross-version migration:
> >>> - All tables besides the RSDP are packed in a single FW CFG entry.
> >>> This entry size is currently 23K. We round it up to 64K
> >>> to avoid too much churn there.
> >>
> >> Does it need to be that way? I'd prefer to have one fw_cfg entry per table.
> >>
> >> cheers,
> >> Gerd
> >>
> >
> > It's better I think. The advantages are:
> > - when we add more tables we don't break cross-version
> > migration compatibility
>
> New tables are a guest-visible change, so I think we have to turn them
> off for old machine types via compat properties anyway. This will also
> solve the migration issue.
ACPI is really part of bios.
We *do* make guest visible changes to bios rom, so
I'm not so sure we should take a hard-line stance on this.
> > - we have limited number of files, this way we won't
> > run out of them
>
> Anything which prevents us from raising that number?
There's a static array so we can extend it a bit,
but making it large and dynamic is hard.
I *really* want to keep the number of moving parts to
minimum, this is a huge patchset as it is.
So please, let's keep it simple, and have everything in one file,
and we can move things around later any number of times
if/when the need arises.
> > what are advantages of file per table?
>
> You can look at the tables without doing a full linker pass first, so
> the firmware can easily initialize the hardware according to what it
> finds in specific acpi tables. Check FADT for pm_base. Check MCFG for
> mmconf xbar location.
>
> cheers,
> Gerd
That's something I think that it's best for firmware to avoid.
Much better to load tables in memory and use standard ACPI
methods to find specific tables.
It's a general thing: paravirtualization is often easier
but let's use standard interfaces where possible.
Sticking everything in one file will serve to keep firmware
honest and not let it cut corners.
--
MST
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (13 preceding siblings ...)
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios Michael S. Tsirkin
@ 2013-07-25 15:50 ` Andreas Färber
2013-07-25 16:19 ` Michael S. Tsirkin
2013-07-25 17:18 ` Michael S. Tsirkin
2013-07-29 15:27 ` Anthony Liguori
15 siblings, 2 replies; 69+ messages in thread
From: Andreas Färber @ 2013-07-25 15:50 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Anthony Liguori
Am 24.07.2013 18:01, schrieb Michael S. Tsirkin:
> This code can also be found here:
> git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi
>
> Please review, and consider for 1.6.
Quite frankly, this is still not looking the way I imagined it based on
the KVM call discussion and Anthony's comments that I remember:
I believe Anthony asked to extract the information from the QOM tree,
originally from the SeaBIOS side, then later agreeing to do it on the
QEMU side.
However here I am still seeing *functions* added in device code to check
device existence and to extract individual fields. I was assuming (and
clearly prefer) such code to live in a central place, be it acpi-build.c
or something else, and to use QOM *API*s to obtain information when
needed rather than building up lots of new structs duplicating that
data. That would at the same time be a test case for how useful the QOM
tree is
I'm not sure if there was a misunderstanding or whether the PC QOM model
still sucks^W is incomplete? Anthony and Ping Fang(?) had both posted
patches to improve the composition tree once. If there's properties
missing that you need to access for ACPI, we should simply add them.
For i440fx we have /machine/i440fx.
For q35 I encountered an mch child on q35-pcihost, but what's trivially
missing apparently is to add q35-pcihost as a child to /machine, e.g.
/machine/q35.
Then you'll end up doing
Object *obj = object_resolve_path_component(qdev_get_machine(), "q35/mch");
object_property_get_int(obj, "foo", &err);
object_property_get_string(obj, "bar", &err);
and so on. No need to do the TYPE_... based search for everything.
User-added -devices will show up in /machine/peripheral or
/machine/peripheral-anon depending on whether id= is used, so there a
type-based search probably makes sense. And there is nothing wrong with
moving the TYPE_* constants to a device header where not yet the case,
to allow that from generic code.
Similarly, please don't open-code OBJECT_CHECK()s, do a trivial patch
with a macro that we can then reuse elsewhere. I'd be happy to review
such QOM patches and help fast-track them into master.
Will take a closer look at the implementation later.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest
2013-07-25 15:50 ` [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Andreas Färber
@ 2013-07-25 16:19 ` Michael S. Tsirkin
2013-07-26 12:19 ` Andreas Färber
2013-07-25 17:18 ` Michael S. Tsirkin
1 sibling, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 16:19 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Anthony Liguori
On Thu, Jul 25, 2013 at 05:50:55PM +0200, Andreas Färber wrote:
> Am 24.07.2013 18:01, schrieb Michael S. Tsirkin:
> > This code can also be found here:
> > git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi
> >
> > Please review, and consider for 1.6.
>
> Quite frankly, this is still not looking the way I imagined it based on
> the KVM call discussion and Anthony's comments that I remember:
>
> I believe Anthony asked to extract the information from the QOM tree,
> originally from the SeaBIOS side, then later agreeing to do it on the
> QEMU side.
>
> However here I am still seeing *functions* added in device code to check
> device existence and to extract individual fields. I was assuming (and
> clearly prefer) such code to live in a central place, be it acpi-build.c
> or something else, and to use QOM *API*s to obtain information when
> needed rather than building up lots of new structs duplicating that
> data. That would at the same time be a test case for how useful the QOM
> tree is
>
> I'm not sure if there was a misunderstanding or whether the PC QOM model
> still sucks^W is incomplete? Anthony and Ping Fang(?) had both posted
> patches to improve the composition tree once. If there's properties
> missing that you need to access for ACPI, we should simply add them.
> For i440fx we have /machine/i440fx.
> For q35 I encountered an mch child on q35-pcihost, but what's trivially
> missing apparently is to add q35-pcihost as a child to /machine, e.g.
> /machine/q35.
> Then you'll end up doing
> Object *obj = object_resolve_path_component(qdev_get_machine(), "q35/mch");
> object_property_get_int(obj, "foo", &err);
> object_property_get_string(obj, "bar", &err);
> and so on. No need to do the TYPE_... based search for everything.
>
> User-added -devices will show up in /machine/peripheral or
> /machine/peripheral-anon depending on whether id= is used, so there a
> type-based search probably makes sense. And there is nothing wrong with
> moving the TYPE_* constants to a device header where not yet the case,
> to allow that from generic code.
>
> Similarly, please don't open-code OBJECT_CHECK()s, do a trivial patch
> with a macro that we can then reuse elsewhere. I'd be happy to review
> such QOM patches and help fast-track them into master.
>
> Will take a closer look at the implementation later.
>
> Regards,
> Andreas
>
This is not my understanding of previous comments on list
or on KVM call.
Basically it sounds like you want to make my work depend on completion
of QOM conversion.
I think we explicitly agreed full QOM convertion is not a blocker.
Meanwhile, I'm adding APIs in particular so you can work on converting
things to QOM without bothering with ACPI. If you want to know what is
missing, you only need to look at the patches themselves, once they are
merged you can rework them internally without need to touch acpi code.
As for your suggestion to poke at internal structures in a central place -
generally, I don't see why poking at internal field or properties of all
kind of device structures or hard-coding paths in acpi-build is a good
idea, surely accessing structures through APIs is the basic idea of data
hiding.
Using QOM to find devices rather than passing pointers around makes
sense to me since this removes the need to depend on initialization
order.
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest
2013-07-25 15:50 ` [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Andreas Färber
2013-07-25 16:19 ` Michael S. Tsirkin
@ 2013-07-25 17:18 ` Michael S. Tsirkin
2013-07-26 12:25 ` Andreas Färber
1 sibling, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 17:18 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Anthony Liguori
On Thu, Jul 25, 2013 at 05:50:55PM +0200, Andreas Färber wrote:
> Am 24.07.2013 18:01, schrieb Michael S. Tsirkin:
> > This code can also be found here:
> > git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi
> >
> > Please review, and consider for 1.6.
>
> Quite frankly, this is still not looking the way I imagined it based on
> the KVM call discussion and Anthony's comments that I remember:
By the way, for examples which are exactly
like this code here, look no further than:
FWCfgState *fw_cfg_find(void);
and the use in hw/misc/pvpanic.c of said API.
Here we have device implementing an API to find it, and through this
pointer, it is accessed by more APIs access its state.
This is exactly what my patches do for piix etc.
So if you don't like this approach, please change
existing code using it.
--
MST
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs
2013-07-25 12:43 ` Gerd Hoffmann
2013-07-25 13:03 ` Michael S. Tsirkin
@ 2013-07-25 19:57 ` Michael S. Tsirkin
1 sibling, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-25 19:57 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Michael Walle, qemu-devel
On Thu, Jul 25, 2013 at 02:43:53PM +0200, Gerd Hoffmann wrote:
> On 07/25/13 14:28, Michael S. Tsirkin wrote:
> > On Thu, Jul 25, 2013 at 02:14:40PM +0200, Gerd Hoffmann wrote:
> >> On 07/24/13 18:01, Michael S. Tsirkin wrote:
> >>> QTAILQ_FOREACH(rom, &roms, next) {
> >>> + if (rom->mr) {
> >>> + continue;
> >>> + }
> >>> if (rom->fw_file) {
> >>> continue;
> >>> }
> >>> if (rom->data == NULL) {
> >>> continue;
> >>> }
> >>> - cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
> >>> + if (rom->mr) {
> >>> + void *host = memory_region_get_ram_ptr(rom->mr);
> >>> + memcpy(host, rom->data, rom->datasize);
> >>
> >> I think this code never ever runs ...
> >>
> >> cheers,
> >> Gerd
> >>
> >
> >
> > Could you be clearer please? This chunk is in rom_reset,
> > I think it runs on reset.
>
> You have the "if (rom->mr)" twice in the loop. The first does continue
> so the second will never ever evaluate to true, thereby making the
> memcpy dead code.
>
> cheers,
> Gerd
>
Ow, good catch. I'll fix that up, thanks!
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios
2013-07-25 15:14 ` Michael S. Tsirkin
@ 2013-07-26 9:06 ` Gerd Hoffmann
2013-07-26 15:30 ` Gerd Hoffmann
0 siblings, 1 reply; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-26 9:06 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Anthony Liguori, qemu-devel
Hi,
>> You can look at the tables without doing a full linker pass first, so
>> the firmware can easily initialize the hardware according to what it
>> finds in specific acpi tables. Check FADT for pm_base. Check MCFG for
>> mmconf xbar location.
>>
>> cheers,
>> Gerd
>
> That's something I think that it's best for firmware to avoid.
> Much better to load tables in memory and use standard ACPI
> methods to find specific tables.
Problem is this happens relatively late in the firmware boot process.
> It's a general thing: paravirtualization is often easier
> but let's use standard interfaces where possible.
Sure. Thats why I want read the info from the acpi tables. Being able
to do that without a full acpi table linker pass makes this easier for
the firmware, especially for informations needed very early in the
initialization process.
What is wrong with etc/acpi/fadt ?
> Sticking everything in one file will serve to keep firmware
> honest and not let it cut corners.
Parse error.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 06/14] i386: add bios linker/loader
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 06/14] i386: add bios linker/loader Michael S. Tsirkin
2013-07-25 12:11 ` Gerd Hoffmann
@ 2013-07-26 9:42 ` Gerd Hoffmann
2013-07-28 8:08 ` Michael S. Tsirkin
1 sibling, 1 reply; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-26 9:42 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
Hi,
Hacked up coreboot support to verify the interface.
> + /*
> + * COMMAND_ALLOCATE - allocate a table from @alloc_file
> + * subject to @alloc_align alignment (must be power of 2)
> + * and @alloc_zone (can be HIGH or FSEG) requirements.
> + *
> + * Must appear exactly once for each file, and before
> + * this file is referenced by any other command.
> + */
Do we need alloc_zone?
Rules are simple: rsdp goes to fseg, everything else to high, correct?
Both seabios and coreboot handle that by first placing *all* acpi tables
in high memory, then go place a rsdp copy in fseg.
> + /*
> + * COMMAND_ADD_POINTER - patch the table (originating from
> + * @dest_file) at @pointer_offset, by adding a pointer to the table
> + * originating from @src_file. 1,2,4 or 8 byte unsigned
> + * addition is used depending on @pointer_size.
> + */
Do we need pointer_size?
Current tables use 4 bytes only.
1+2 bytes is pointless, the src_file address will be big enougth that it
doesn't fit into one or two bytes, so I doubt they will ever be used.
8 bytes would only be used when placing acpi tables above 4g. Is that
something expected to happen? If not 4 bytes is enough, even for 8 byte
pointers as the 4 high bytes would be zero no matter what.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest
2013-07-25 16:19 ` Michael S. Tsirkin
@ 2013-07-26 12:19 ` Andreas Färber
2013-07-27 23:22 ` Andreas Färber
0 siblings, 1 reply; 69+ messages in thread
From: Andreas Färber @ 2013-07-26 12:19 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Anthony Liguori
Am 25.07.2013 18:19, schrieb Michael S. Tsirkin:
> On Thu, Jul 25, 2013 at 05:50:55PM +0200, Andreas Färber wrote:
>> Am 24.07.2013 18:01, schrieb Michael S. Tsirkin:
>>> This code can also be found here:
>>> git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi
>>>
>>> Please review, and consider for 1.6.
>>
>> Quite frankly, this is still not looking the way I imagined it based on
>> the KVM call discussion and Anthony's comments that I remember:
>>
>> I believe Anthony asked to extract the information from the QOM tree,
>> originally from the SeaBIOS side, then later agreeing to do it on the
>> QEMU side.
>>
>> However here I am still seeing *functions* added in device code to check
>> device existence and to extract individual fields. I was assuming (and
>> clearly prefer) such code to live in a central place, be it acpi-build.c
>> or something else, and to use QOM *API*s to obtain information when
>> needed rather than building up lots of new structs duplicating that
>> data. That would at the same time be a test case for how useful the QOM
>> tree is
>>
>> I'm not sure if there was a misunderstanding or whether the PC QOM model
>> still sucks^W is incomplete? Anthony and Ping Fang(?) had both posted
>> patches to improve the composition tree once. If there's properties
>> missing that you need to access for ACPI, we should simply add them.
>> For i440fx we have /machine/i440fx.
>> For q35 I encountered an mch child on q35-pcihost, but what's trivially
>> missing apparently is to add q35-pcihost as a child to /machine, e.g.
>> /machine/q35.
>> Then you'll end up doing
>> Object *obj = object_resolve_path_component(qdev_get_machine(), "q35/mch");
>> object_property_get_int(obj, "foo", &err);
>> object_property_get_string(obj, "bar", &err);
>> and so on. No need to do the TYPE_... based search for everything.
>>
>> User-added -devices will show up in /machine/peripheral or
>> /machine/peripheral-anon depending on whether id= is used, so there a
>> type-based search probably makes sense. And there is nothing wrong with
>> moving the TYPE_* constants to a device header where not yet the case,
>> to allow that from generic code.
>>
>> Similarly, please don't open-code OBJECT_CHECK()s, do a trivial patch
>> with a macro that we can then reuse elsewhere. I'd be happy to review
>> such QOM patches and help fast-track them into master.
>>
>> Will take a closer look at the implementation later.
>
> This is not my understanding of previous comments on list
> or on KVM call.
>
> Basically it sounds like you want to make my work depend on completion
> of QOM conversion.
> I think we explicitly agreed full QOM convertion is not a blocker.
Not sure what you mean with "completion of QOM conversion" or "full QOM
conversion". What I am saying is that instead of spending time adding
functions to devices that fulfill your own ACPI needs only, that time
were better spent adding QOM properties where not yet existent.
Because then what you can access for ACPI can also be accessed by
libvirt and other management tools as well as qtest - I consider it a
test case. QMP does not offer an instance/path search by type.
> Meanwhile, I'm adding APIs in particular so you can work on converting
> things to QOM without bothering with ACPI. If you want to know what is
> missing, you only need to look at the patches themselves, once they are
> merged you can rework them internally without need to touch acpi code.
I do intend to look at them but did not have time yesterday.
I brought up my comments early because Hard Freeze is approaching fast
and I fear that if your v3 series is applied to 1.6 and is working, you
will not bother to send follow-up fixes after 1.6 anymore because you do
not care about whether that code is considered bad design by others, and
thus things will likely stay in a bad shape. You cannot expect me to do
everything (not to mention that it was Anthony's idea in the first place).
> As for your suggestion to poke at internal structures in a central place -
I never suggested that, on the contrary. See my example above using
Object: There is no need to even expose structs to ACPI to access things
via QOM properties.
Regards,
Andreas
> generally, I don't see why poking at internal field or properties of all
> kind of device structures or hard-coding paths in acpi-build is a good
> idea, surely accessing structures through APIs is the basic idea of data
> hiding.
>
> Using QOM to find devices rather than passing pointers around makes
> sense to me since this removes the need to depend on initialization
> order.
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest
2013-07-25 17:18 ` Michael S. Tsirkin
@ 2013-07-26 12:25 ` Andreas Färber
0 siblings, 0 replies; 69+ messages in thread
From: Andreas Färber @ 2013-07-26 12:25 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Anthony Liguori
Am 25.07.2013 19:18, schrieb Michael S. Tsirkin:
> On Thu, Jul 25, 2013 at 05:50:55PM +0200, Andreas Färber wrote:
>> Am 24.07.2013 18:01, schrieb Michael S. Tsirkin:
>>> This code can also be found here:
>>> git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi
>>>
>>> Please review, and consider for 1.6.
>>
>> Quite frankly, this is still not looking the way I imagined it based on
>> the KVM call discussion and Anthony's comments that I remember:
>
> By the way, for examples which are exactly
> like this code here, look no further than:
>
> FWCfgState *fw_cfg_find(void);
>
> and the use in hw/misc/pvpanic.c of said API.
>
> Here we have device implementing an API to find it, and through this
> pointer, it is accessed by more APIs access its state.
>
> This is exactly what my patches do for piix etc.
>
> So if you don't like this approach, please change
> existing code using it.
According to git-blame that code was recently added by you:
http://repo.or.cz/w/qemu.git/commit/600c60b76d0682f6c39d19bfff79da9321e8cf86?f=hw/nvram/fw_cfg.c
So the existing-code argument is kind of moot. ;)
Further, that returns the device's state struct and does not copy fields
from that state struct into another state struct.
BTW if you want to avoid repeatedly hardcoding things, fw_cfg should be
using object_resolve_path_component(), I'll prepare a patch.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios
2013-07-26 9:06 ` Gerd Hoffmann
@ 2013-07-26 15:30 ` Gerd Hoffmann
2013-07-28 7:00 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Gerd Hoffmann @ 2013-07-26 15:30 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Anthony Liguori, qemu-devel
Hi,
>> That's something I think that it's best for firmware to avoid.
>> Much better to load tables in memory and use standard ACPI
>> methods to find specific tables.
>
> Problem is this happens relatively late in the firmware boot process.
Completely different idea to tackle the issue: use COMMAND_ADD_POINTER
not only for table pointers, but also register offsets. So the firmware
doesn't need to parse fadt to figure how it should program pm_base, but
instead can fixup the fadt according to the pm_base it has used.
That is more in line with how firmware works (pm_base and simliar things
tends to be #defines and are not runtime-configurable). And I think
it's also more robust when extending/changing tables for newer acpi spec
revisions.
cheers,
Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest
2013-07-26 12:19 ` Andreas Färber
@ 2013-07-27 23:22 ` Andreas Färber
2013-09-11 9:57 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Andreas Färber @ 2013-07-27 23:22 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Anthony Liguori
[-- Attachment #1: Type: text/plain, Size: 4185 bytes --]
Am 26.07.2013 14:19, schrieb Andreas Färber:
> Am 25.07.2013 18:19, schrieb Michael S. Tsirkin:
>> On Thu, Jul 25, 2013 at 05:50:55PM +0200, Andreas Färber wrote:
>>> Am 24.07.2013 18:01, schrieb Michael S. Tsirkin:
>>>> This code can also be found here:
>>>> git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi
>>>>
>>>> Please review, and consider for 1.6.
>>>
>>> Quite frankly, this is still not looking the way I imagined it based on
>>> the KVM call discussion and Anthony's comments that I remember:
>>>
>>> I believe Anthony asked to extract the information from the QOM tree,
>>> originally from the SeaBIOS side, then later agreeing to do it on the
>>> QEMU side.
>>>
>>> However here I am still seeing *functions* added in device code to check
>>> device existence and to extract individual fields. I was assuming (and
>>> clearly prefer) such code to live in a central place, be it acpi-build.c
>>> or something else, and to use QOM *API*s to obtain information when
>>> needed rather than building up lots of new structs duplicating that
>>> data. That would at the same time be a test case for how useful the QOM
>>> tree is
>>>
>>> I'm not sure if there was a misunderstanding or whether the PC QOM model
>>> still sucks^W is incomplete? Anthony and Ping Fang(?) had both posted
>>> patches to improve the composition tree once. If there's properties
>>> missing that you need to access for ACPI, we should simply add them.
>>> For i440fx we have /machine/i440fx.
>>> For q35 I encountered an mch child on q35-pcihost, but what's trivially
>>> missing apparently is to add q35-pcihost as a child to /machine, e.g.
>>> /machine/q35.
>>> Then you'll end up doing
>>> Object *obj = object_resolve_path_component(qdev_get_machine(), "q35/mch");
>>> object_property_get_int(obj, "foo", &err);
>>> object_property_get_string(obj, "bar", &err);
>>> and so on. No need to do the TYPE_... based search for everything.
>>>
>>> User-added -devices will show up in /machine/peripheral or
>>> /machine/peripheral-anon depending on whether id= is used, so there a
>>> type-based search probably makes sense. And there is nothing wrong with
>>> moving the TYPE_* constants to a device header where not yet the case,
>>> to allow that from generic code.
>>>
>>> Similarly, please don't open-code OBJECT_CHECK()s, do a trivial patch
>>> with a macro that we can then reuse elsewhere. I'd be happy to review
>>> such QOM patches and help fast-track them into master.
>>>
>>> Will take a closer look at the implementation later.
>>
>> This is not my understanding of previous comments on list
>> or on KVM call.
>>
>> Basically it sounds like you want to make my work depend on completion
>> of QOM conversion.
>> I think we explicitly agreed full QOM convertion is not a blocker.
>
> Not sure what you mean with "completion of QOM conversion" or "full QOM
> conversion". What I am saying is that instead of spending time adding
> functions to devices that fulfill your own ACPI needs only, that time
> were better spent adding QOM properties where not yet existent.
>
> Because then what you can access for ACPI can also be accessed by
> libvirt and other management tools as well as qtest - I consider it a
> test case. QMP does not offer an instance/path search by type.
To clarify for everyone what we're talking about here, I'm attaching
/machine composition tree dumps for pc,accel=kvm and q35,accel=kvm plus
the rudimentary script I used to generate it.
It shows for instance the mentioned /machine/i440fx and lack of
/machine/q35. It also shows that there would be a /machine/fw_cfg.
Paths starting with /machine/unassigned shouldn't be hardcoded anywhere
(that's the nobody-added-it-as-a-child<> bucket), except maybe for
/machine/unassigned/sysbus. But whenever there's a link from a named
device to a /machine/unassigned/device[n] that may of course be used
dynamically, e.g. /machine/icc-bridge/icc to discover CPUs and APICs.
HTH,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[-- Attachment #2: pc_i440fx_kvm.txt --]
[-- Type: text/plain, Size: 10959 bytes --]
/machine
type: container
/machine/i440fx
parent_bus: /machine/unattached/sysbus
realized: True
type: i440FX-pcihost
/machine/i440fx/ioapic
parent_bus: /machine/unattached/sysbus
gsi_base: 0
realized: True
type: kvm-ioapic
/machine/i440fx/pci.0
child[5]: /machine/unattached/device[23]
child[4]: /machine/unattached/device[21]
child[3]: /machine/unattached/device[20]
child[2]: /machine/unattached/device[8]
child[1]: /machine/unattached/device[5]
child[0]: /machine/unattached/device[4]
type: PCI
/machine/fw_cfg
parent_bus: /machine/unattached/sysbus
data_iobase: 1297
legacy-data_iobase: 0x511
ctl_iobase: 1296
legacy-ctl_iobase: 0x510
realized: True
type: fw_cfg
/machine/icc-bridge
parent_bus: /machine/unattached/sysbus
realized: True
type: icc-bridge
/machine/icc-bridge/icc
child[1]: /machine/unattached/device[0]/apic
child[0]: /machine/unattached/device[0]
type: icc-bus
/machine/unattached
type: container
/machine/unattached/device[32]
parent_bus: /machine/unattached/device[5]/isa.0
ioport: 1285
realized: True
type: pvpanic
/machine/unattached/device[31]
parent_bus: /machine/unattached/device[23]/i2c
address: 87
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[30]
parent_bus: /machine/unattached/device[23]/i2c
address: 86
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[29]
parent_bus: /machine/unattached/device[23]/i2c
address: 85
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[28]
parent_bus: /machine/unattached/device[23]/i2c
address: 84
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[27]
parent_bus: /machine/unattached/device[23]/i2c
address: 83
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[26]
parent_bus: /machine/unattached/device[23]/i2c
address: 82
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[25]
parent_bus: /machine/unattached/device[23]/i2c
address: 81
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[24]
parent_bus: /machine/unattached/device[23]/i2c
address: 80
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[23]
parent_bus: /machine/i440fx/pci.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: False
legacy-multifunction: off
rombar: 1
romfile:
legacy-romfile: <null>
addr: 11
legacy-addr: 01.3
s4_val: 2
disable_s4: 0
disable_s3: 0
smb_io_base: 45312
realized: True
type: PIIX4_PM
/machine/unattached/device[23]/i2c
child[7]: /machine/unattached/device[31]
child[6]: /machine/unattached/device[30]
child[5]: /machine/unattached/device[29]
child[4]: /machine/unattached/device[28]
child[3]: /machine/unattached/device[27]
child[2]: /machine/unattached/device[26]
child[1]: /machine/unattached/device[25]
child[0]: /machine/unattached/device[24]
type: i2c-bus
/machine/unattached/device[22]
parent_bus: /machine/unattached/device[21]/ide.1
unit: 0
model:
legacy-model: <null>
serial: QM00003
legacy-serial: "QM00003"
wwn: 0
legacy-wwn: 0x0
ver: 1.5.50
legacy-ver: "1.5.50"
discard_granularity: 512
bootindex: -1
opt_io_size: 0
min_io_size: 0
physical_block_size: 512
logical_block_size: 512
drive: ide1-cd0
realized: True
type: ide-cd
/machine/unattached/device[21]
parent_bus: /machine/i440fx/pci.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: False
legacy-multifunction: off
rombar: 1
romfile:
legacy-romfile: <null>
addr: 9
legacy-addr: 01.1
realized: True
type: piix3-ide
/machine/unattached/device[21]/ide.1
child[0]: /machine/unattached/device[22]
type: IDE
/machine/unattached/device[21]/ide.0
type: IDE
/machine/unattached/device[20]
parent_bus: /machine/i440fx/pci.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: False
legacy-multifunction: off
rombar: 1
romfile: efi-e1000.rom
legacy-romfile: "efi-e1000.rom"
addr: 24
legacy-addr: 03.0
autonegotiation: True
legacy-autonegotiation: on
bootindex: -1
netdev: hub0port0
vlan: 0
legacy-vlan: 0
mac: 52:54:00:12:34:56
realized: True
type: e1000
/machine/unattached/device[19]
parent_bus: /machine/unattached/device[5]/isa.0
check_media_rate: True
legacy-check_media_rate: on
bootindexB: -1
bootindexA: -1
driveB:
driveA: floppy0
dma: 2
irq: 6
iobase: 1008
legacy-iobase: 0x3f0
realized: True
type: isa-fdc
/machine/unattached/device[18]
parent_bus: /machine/unattached/device[5]/isa.0
realized: True
type: port92
/machine/unattached/device[17]
parent_bus: /machine/unattached/device[5]/isa.0
legacy-ps2_mouse: <EXCEPTION>
realized: True
type: vmmouse
/machine/unattached/device[16]
parent_bus: /machine/unattached/device[5]/isa.0
realized: True
type: vmport
/machine/unattached/device[15]
parent_bus: /machine/unattached/device[5]/isa.0
realized: True
type: i8042
/machine/unattached/device[14]
parent_bus: /machine/unattached/device[5]/isa.0
chardev: parallel0
irq: 7
iobase: 888
legacy-iobase: 0x378
index: 0
realized: True
type: isa-parallel
/machine/unattached/device[13]
parent_bus: /machine/unattached/device[5]/isa.0
wakeup: 0
chardev: serial0
irq: 4
iobase: 1016
legacy-iobase: 0x3f8
index: 0
realized: True
type: isa-serial
/machine/unattached/device[12]
parent_bus: /machine/unattached/device[5]/isa.0
legacy-pit: <EXCEPTION>
iobase: 97
legacy-iobase: 0x61
realized: True
type: isa-pcspk
/machine/unattached/device[11]
parent_bus: /machine/unattached/device[5]/isa.0
lost_tick_policy: delay
iobase: 64
legacy-iobase: 0x40
realized: True
type: kvm-pit
/machine/unattached/device[10]
date: {u'tm_sec': 31, u'tm_hour': 23, u'tm_mday': 27, u'tm_year': 113, u'tm_mon': 6, u'tm_min': 5}
parent_bus: /machine/unattached/device[5]/isa.0
lost_tick_policy: discard
base_year: 0
realized: True
type: mc146818rtc
/machine/unattached/device[9]
parent_bus: /machine/unattached/sysbus
msi: False
legacy-msi: off
timers: 3
realized: True
type: hpet
/machine/unattached/device[8]
parent_bus: /machine/i440fx/pci.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: False
legacy-multifunction: off
rombar: 1
romfile: vgabios-cirrus.bin
legacy-romfile: "vgabios-cirrus.bin"
addr: 16
legacy-addr: 02.0
vgamem_mb: 8
realized: True
type: cirrus-vga
/machine/unattached/device[7]
parent_bus: /machine/unattached/device[5]/isa.0
master: False
legacy-master: off
elcr_mask: 222
legacy-elcr_mask: 0xde
elcr_addr: 1233
legacy-elcr_addr: 0x4d1
iobase: 160
legacy-iobase: 0xa0
realized: True
type: kvm-i8259
/machine/unattached/device[6]
parent_bus: /machine/unattached/device[5]/isa.0
master: True
legacy-master: on
elcr_mask: 248
legacy-elcr_mask: 0xf8
elcr_addr: 1232
legacy-elcr_addr: 0x4d0
iobase: 32
legacy-iobase: 0x20
realized: True
type: kvm-i8259
/machine/unattached/device[5]
parent_bus: /machine/i440fx/pci.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: True
legacy-multifunction: on
rombar: 1
romfile:
legacy-romfile: <null>
addr: 8
legacy-addr: 01.0
realized: True
type: PIIX3
/machine/unattached/device[5]/isa.0
child[12]: /machine/unattached/device[32]
child[11]: /machine/unattached/device[19]
child[10]: /machine/unattached/device[18]
child[9]: /machine/unattached/device[17]
child[8]: /machine/unattached/device[16]
child[7]: /machine/unattached/device[15]
child[6]: /machine/unattached/device[14]
child[5]: /machine/unattached/device[13]
child[4]: /machine/unattached/device[12]
child[3]: /machine/unattached/device[11]
child[2]: /machine/unattached/device[10]
child[1]: /machine/unattached/device[7]
child[0]: /machine/unattached/device[6]
type: ISA
/machine/unattached/device[4]
parent_bus: /machine/i440fx/pci.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: False
legacy-multifunction: off
rombar: 1
romfile:
legacy-romfile: <null>
addr: 0
legacy-addr: 00.0
realized: True
type: i440FX
/machine/unattached/device[3]
parent_bus: /machine/unattached/sysbus
rom_only: 1
isapc_ram_fw: 0
realized: True
type: pc-sysfw
/machine/unattached/device[2]
parent_bus: /machine/unattached/sysbus
realized: True
type: kvmclock
/machine/unattached/device[1]
parent_bus: /machine/unattached/sysbus
realized: True
type: kvmvapic
/machine/unattached/device[0]
filtered-features: [{u'cpuid-register': u'EDX', u'cpuid-input-eax': 2147483658, u'features': 0}, {u'cpuid-register': u'EAX', u'cpuid-input-eax': 1073741825, u'features': 0}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 3221225473, u'features': 0}, {u'cpuid-register': u'ECX', u'cpuid-input-eax': 2147483649, u'features': 100}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 2147483649, u'features': 0}, {u'cpuid-register': u'EBX', u'cpuid-input-eax': 7, u'features': 0, u'cpuid-input-ecx': 0}, {u'cpuid-register': u'ECX', u'cpuid-input-eax': 1, u'features': 0}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 1, u'features': 0}]
feature-words: [{u'cpuid-register': u'EDX', u'cpuid-input-eax': 2147483658, u'features': 0}, {u'cpuid-register': u'EAX', u'cpuid-input-eax': 1073741825, u'features': 16777339}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 3221225473, u'features': 0}, {u'cpuid-register': u'ECX', u'cpuid-input-eax': 2147483649, u'features': 1}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 2147483649, u'features': 563194877}, {u'cpuid-register': u'EBX', u'cpuid-input-eax': 7, u'features': 0, u'cpuid-input-ecx': 0}, {u'cpuid-register': u'ECX', u'cpuid-input-eax': 1, u'features': 2155880449}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 1, u'features': 126614525}]
apic-id: 0
tsc-frequency: 0
model-id: QEMU Virtual CPU version 1.5.50
vendor: GenuineIntel
xlevel: 2147483658
level: 4
stepping: 3
model: 2
family: 6
parent_bus: /machine/icc-bridge/icc
realized: True
type: x86_64-cpu
/machine/unattached/device[0]/apic
parent_bus: /machine/icc-bridge/icc
vapic: True
legacy-vapic: on
id: 0
realized: True
type: kvm-apic
/machine/unattached/sysbus
child[7]: /machine/unattached/device[9]
child[6]: /machine/i440fx/ioapic
child[5]: /machine/i440fx
child[4]: /machine/fw_cfg
child[3]: /machine/unattached/device[3]
child[2]: /machine/unattached/device[2]
child[1]: /machine/unattached/device[1]
child[0]: /machine/icc-bridge
type: System
/machine/peripheral
type: container
/machine/peripheral-anon
type: container
[-- Attachment #3: pc_q35_kvm.txt --]
[-- Type: text/plain, Size: 10802 bytes --]
/machine
type: container
/machine/fw_cfg
parent_bus: /machine/unattached/sysbus
data_iobase: 1297
legacy-data_iobase: 0x511
ctl_iobase: 1296
legacy-ctl_iobase: 0x510
realized: True
type: fw_cfg
/machine/icc-bridge
parent_bus: /machine/unattached/sysbus
realized: True
type: icc-bridge
/machine/icc-bridge/icc
child[1]: /machine/unattached/device[0]/apic
child[0]: /machine/unattached/device[0]
type: icc-bus
/machine/unattached
type: container
/machine/unattached/device[32]
parent_bus: /machine/unattached/device[5]/isa.0
ioport: 1285
realized: True
type: pvpanic
/machine/unattached/device[31]
parent_bus: /machine/unattached/device[4]/pcie.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: False
legacy-multifunction: off
rombar: 1
romfile: efi-e1000.rom
legacy-romfile: "efi-e1000.rom"
addr: 16
legacy-addr: 02.0
autonegotiation: True
legacy-autonegotiation: on
bootindex: -1
netdev: hub0port0
vlan: 0
legacy-vlan: 0
mac: 52:54:00:12:34:56
realized: True
type: e1000
/machine/unattached/device[30]
parent_bus: /machine/unattached/device[4]/pcie.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: False
legacy-multifunction: off
rombar: 1
romfile: vgabios-cirrus.bin
legacy-romfile: "vgabios-cirrus.bin"
addr: 8
legacy-addr: 01.0
vgamem_mb: 8
realized: True
type: cirrus-vga
/machine/unattached/device[29]
parent_bus: /machine/unattached/device[21]/i2c
address: 87
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[28]
parent_bus: /machine/unattached/device[21]/i2c
address: 86
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[27]
parent_bus: /machine/unattached/device[21]/i2c
address: 85
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[26]
parent_bus: /machine/unattached/device[21]/i2c
address: 84
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[25]
parent_bus: /machine/unattached/device[21]/i2c
address: 83
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[24]
parent_bus: /machine/unattached/device[21]/i2c
address: 82
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[23]
parent_bus: /machine/unattached/device[21]/i2c
address: 81
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[22]
parent_bus: /machine/unattached/device[21]/i2c
address: 80
legacy-data: <EXCEPTION>
realized: True
type: smbus-eeprom
/machine/unattached/device[21]
parent_bus: /machine/unattached/device[4]/pcie.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: True
legacy-multifunction: on
rombar: 1
romfile:
legacy-romfile: <null>
addr: 251
legacy-addr: 1f.3
realized: True
type: ICH9 SMB
/machine/unattached/device[21]/i2c
child[7]: /machine/unattached/device[29]
child[6]: /machine/unattached/device[28]
child[5]: /machine/unattached/device[27]
child[4]: /machine/unattached/device[26]
child[3]: /machine/unattached/device[25]
child[2]: /machine/unattached/device[24]
child[1]: /machine/unattached/device[23]
child[0]: /machine/unattached/device[22]
type: i2c-bus
/machine/unattached/device[20]
parent_bus: /machine/unattached/device[4]/pcie.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: True
legacy-multifunction: on
rombar: 1
romfile:
legacy-romfile: <null>
addr: 250
legacy-addr: 1f.2
realized: True
type: ich9-ahci
/machine/unattached/device[20]/ide.5
type: IDE
/machine/unattached/device[20]/ide.4
type: IDE
/machine/unattached/device[20]/ide.3
type: IDE
/machine/unattached/device[20]/ide.2
type: IDE
/machine/unattached/device[20]/ide.1
type: IDE
/machine/unattached/device[20]/ide.0
type: IDE
/machine/unattached/device[19]
parent_bus: /machine/unattached/device[5]/isa.0
check_media_rate: True
legacy-check_media_rate: on
bootindexB: -1
bootindexA: -1
driveB:
driveA: floppy0
dma: 2
irq: 6
iobase: 1008
legacy-iobase: 0x3f0
realized: True
type: isa-fdc
/machine/unattached/device[18]
parent_bus: /machine/unattached/device[5]/isa.0
realized: True
type: port92
/machine/unattached/device[17]
parent_bus: /machine/unattached/device[5]/isa.0
legacy-ps2_mouse: <EXCEPTION>
realized: True
type: vmmouse
/machine/unattached/device[16]
parent_bus: /machine/unattached/device[5]/isa.0
realized: True
type: vmport
/machine/unattached/device[15]
parent_bus: /machine/unattached/device[5]/isa.0
realized: True
type: i8042
/machine/unattached/device[14]
parent_bus: /machine/unattached/device[5]/isa.0
chardev: parallel0
irq: 7
iobase: 888
legacy-iobase: 0x378
index: 0
realized: True
type: isa-parallel
/machine/unattached/device[13]
parent_bus: /machine/unattached/device[5]/isa.0
wakeup: 0
chardev: serial0
irq: 4
iobase: 1016
legacy-iobase: 0x3f8
index: 0
realized: True
type: isa-serial
/machine/unattached/device[12]
parent_bus: /machine/unattached/device[5]/isa.0
legacy-pit: <EXCEPTION>
iobase: 97
legacy-iobase: 0x61
realized: True
type: isa-pcspk
/machine/unattached/device[11]
parent_bus: /machine/unattached/device[5]/isa.0
lost_tick_policy: delay
iobase: 64
legacy-iobase: 0x40
realized: True
type: kvm-pit
/machine/unattached/device[10]
date: {u'tm_sec': 42, u'tm_hour': 23, u'tm_mday': 27, u'tm_year': 113, u'tm_mon': 6, u'tm_min': 4}
parent_bus: /machine/unattached/device[5]/isa.0
lost_tick_policy: discard
base_year: 0
realized: True
type: mc146818rtc
/machine/unattached/device[9]
parent_bus: /machine/unattached/sysbus
msi: False
legacy-msi: off
timers: 3
realized: True
type: hpet
/machine/unattached/device[8]
parent_bus: /machine/unattached/sysbus
gsi_base: 0
realized: True
type: kvm-ioapic
/machine/unattached/device[7]
parent_bus: /machine/unattached/device[5]/isa.0
master: False
legacy-master: off
elcr_mask: 222
legacy-elcr_mask: 0xde
elcr_addr: 1233
legacy-elcr_addr: 0x4d1
iobase: 160
legacy-iobase: 0xa0
realized: True
type: kvm-i8259
/machine/unattached/device[6]
parent_bus: /machine/unattached/device[5]/isa.0
master: True
legacy-master: on
elcr_mask: 248
legacy-elcr_mask: 0xf8
elcr_addr: 1232
legacy-elcr_addr: 0x4d0
iobase: 32
legacy-iobase: 0x20
realized: True
type: kvm-i8259
/machine/unattached/device[5]
parent_bus: /machine/unattached/device[4]/pcie.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: True
legacy-multifunction: on
rombar: 1
romfile:
legacy-romfile: <null>
addr: 248
legacy-addr: 1f.0
realized: True
type: ICH9 LPC
/machine/unattached/device[5]/isa.0
child[12]: /machine/unattached/device[32]
child[11]: /machine/unattached/device[19]
child[10]: /machine/unattached/device[18]
child[9]: /machine/unattached/device[17]
child[8]: /machine/unattached/device[16]
child[7]: /machine/unattached/device[15]
child[6]: /machine/unattached/device[14]
child[5]: /machine/unattached/device[13]
child[4]: /machine/unattached/device[12]
child[3]: /machine/unattached/device[11]
child[2]: /machine/unattached/device[10]
child[1]: /machine/unattached/device[7]
child[0]: /machine/unattached/device[6]
type: ISA
/machine/unattached/device[4]
parent_bus: /machine/unattached/sysbus
MCFG: -1
realized: True
type: q35-pcihost
/machine/unattached/device[4]/pcie.0
child[5]: /machine/unattached/device[31]
child[4]: /machine/unattached/device[30]
child[3]: /machine/unattached/device[21]
child[2]: /machine/unattached/device[20]
child[1]: /machine/unattached/device[5]
child[0]: /machine/unattached/device[4]/mch
type: PCIE
/machine/unattached/device[4]/mch
parent_bus: /machine/unattached/device[4]/pcie.0
command_serr_enable: True
legacy-command_serr_enable: on
multifunction: False
legacy-multifunction: off
rombar: 1
romfile:
legacy-romfile: <null>
addr: 0
legacy-addr: 00.0
realized: True
type: mch
/machine/unattached/device[3]
parent_bus: /machine/unattached/sysbus
rom_only: 1
isapc_ram_fw: 0
realized: True
type: pc-sysfw
/machine/unattached/device[2]
parent_bus: /machine/unattached/sysbus
realized: True
type: kvmclock
/machine/unattached/device[1]
parent_bus: /machine/unattached/sysbus
realized: True
type: kvmvapic
/machine/unattached/device[0]
filtered-features: [{u'cpuid-register': u'EDX', u'cpuid-input-eax': 2147483658, u'features': 0}, {u'cpuid-register': u'EAX', u'cpuid-input-eax': 1073741825, u'features': 0}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 3221225473, u'features': 0}, {u'cpuid-register': u'ECX', u'cpuid-input-eax': 2147483649, u'features': 100}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 2147483649, u'features': 0}, {u'cpuid-register': u'EBX', u'cpuid-input-eax': 7, u'features': 0, u'cpuid-input-ecx': 0}, {u'cpuid-register': u'ECX', u'cpuid-input-eax': 1, u'features': 0}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 1, u'features': 0}]
feature-words: [{u'cpuid-register': u'EDX', u'cpuid-input-eax': 2147483658, u'features': 0}, {u'cpuid-register': u'EAX', u'cpuid-input-eax': 1073741825, u'features': 16777339}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 3221225473, u'features': 0}, {u'cpuid-register': u'ECX', u'cpuid-input-eax': 2147483649, u'features': 1}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 2147483649, u'features': 563194877}, {u'cpuid-register': u'EBX', u'cpuid-input-eax': 7, u'features': 0, u'cpuid-input-ecx': 0}, {u'cpuid-register': u'ECX', u'cpuid-input-eax': 1, u'features': 2155880449}, {u'cpuid-register': u'EDX', u'cpuid-input-eax': 1, u'features': 126614525}]
apic-id: 0
tsc-frequency: 0
model-id: QEMU Virtual CPU version 1.5.50
vendor: GenuineIntel
xlevel: 2147483658
level: 4
stepping: 3
model: 2
family: 6
parent_bus: /machine/icc-bridge/icc
realized: True
type: x86_64-cpu
/machine/unattached/device[0]/apic
parent_bus: /machine/icc-bridge/icc
vapic: True
legacy-vapic: on
id: 0
realized: True
type: kvm-apic
/machine/unattached/sysbus
child[7]: /machine/unattached/device[9]
child[6]: /machine/unattached/device[8]
child[5]: /machine/unattached/device[4]
child[4]: /machine/fw_cfg
child[3]: /machine/unattached/device[3]
child[2]: /machine/unattached/device[2]
child[1]: /machine/unattached/device[1]
child[0]: /machine/icc-bridge
type: System
/machine/peripheral
type: container
/machine/peripheral-anon
type: container
[-- Attachment #4: qom-tree --]
[-- Type: text/plain, Size: 1799 bytes --]
#!/usr/bin/python
##
# QEMU Object Model test tools
#
# Copyright IBM, Corp. 2011
#
# Authors:
# Anthony Liguori <aliguori@us.ibm.com>
# Andreas Faerber <afaerber@suse.de>
#
# This work is licensed under the terms of the GNU GPL, version 2 or later. See
# the COPYING file in the top-level directory.
##
import sys
import os
from qmp import QEMUMonitorProtocol
cmd, args = sys.argv[0], sys.argv[1:]
socket_path = None
path = None
prop = None
def usage():
return '''environment variables:
QMP_SOCKET=<path | addr:port>
usage:
%s [-h] [-s <QMP socket path | addr:port>] [<path>]
''' % cmd
def usage_error(error_msg = "unspecified error"):
sys.stderr.write('%s\nERROR: %s\n' % (usage(), error_msg))
exit(1)
if len(args) > 0:
if args[0] == "-h":
print usage()
exit(0);
elif args[0] == "-s":
try:
socket_path = args[1]
except:
usage_error("missing argument: QMP socket path or address");
args = args[2:]
if not socket_path:
if os.environ.has_key('QMP_SOCKET'):
socket_path = os.environ['QMP_SOCKET']
else:
usage_error("no QMP socket path or address given");
srv = QEMUMonitorProtocol(socket_path)
srv.connect()
def list_node(path):
print '%s' % path
items = srv.command('qom-list', path=path)
for item in items:
if not item['type'].startswith('child<'): #and not item['type'].startswith('link<'):
try:
print ' %s: %s' % (item['name'], srv.command('qom-get', path=path, property=item['name']))
except:
print ' %s: <EXCEPTION>' % item['name']
print ''
for item in items:
if item['type'].startswith('child<'):
list_node(path + '/' + item['name'])
list_node('/machine')
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 13/14] hpet: add API to find it
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 13/14] hpet: add API to find it Michael S. Tsirkin
2013-07-25 12:36 ` Gerd Hoffmann
@ 2013-07-27 23:38 ` Andreas Färber
1 sibling, 0 replies; 69+ messages in thread
From: Andreas Färber @ 2013-07-27 23:38 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Gerd Hoffmann
Am 24.07.2013 18:02, schrieb Michael S. Tsirkin:
> Add API to find HPET using QOM.
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/timer/hpet.c | 5 +++++
> include/hw/timer/hpet.h | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
> index 648b383..11bf401 100644
> --- a/hw/timer/hpet.c
> +++ b/hw/timer/hpet.c
> @@ -757,6 +757,11 @@ static void hpet_device_class_init(ObjectClass *klass, void *data)
> dc->props = hpet_device_properties;
> }
>
> +bool hpet_find(void)
> +{
> + return object_resolve_path_type("", "hpet", NULL);
> +}
> +
> static const TypeInfo hpet_device_info = {
> .name = TYPE_HPET,
> .parent = TYPE_SYS_BUS_DEVICE,
"hpet" is being open-coded just above the new TYPE_HPET.
http://git.qemu.org/?p=qemu.git;a=commit;h=02f9a6f5da74251e1e5685ae57643d45c3fb6c30
But since you're doing it and the code is really trivial, you could also
inline it into ACPI code to spare us this single-use function.
> diff --git a/include/hw/timer/hpet.h b/include/hw/timer/hpet.h
> index 757f79f..ab44bd3 100644
> --- a/include/hw/timer/hpet.h
> +++ b/include/hw/timer/hpet.h
> @@ -71,4 +71,6 @@ struct hpet_fw_config
> } QEMU_PACKED;
>
> extern struct hpet_fw_config hpet_cfg;
> +
> +bool hpet_find(void);
> #endif
We could just as well move TYPE_HPET here to allow reuse from ACPI code.
Not having done above conversion patch myself, I did not notice there
was a header candidate.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port
2013-07-25 12:23 ` Michael S. Tsirkin
@ 2013-07-27 23:58 ` Andreas Färber
0 siblings, 0 replies; 69+ messages in thread
From: Andreas Färber @ 2013-07-27 23:58 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Gerd Hoffmann, Anthony Liguori, qemu-devel
Am 25.07.2013 14:23, schrieb Michael S. Tsirkin:
> On Thu, Jul 25, 2013 at 02:03:33PM +0200, Gerd Hoffmann wrote:
>> On 07/25/13 13:22, Michael S. Tsirkin wrote:
>>> On Thu, Jul 25, 2013 at 01:05:12PM +0200, Gerd Hoffmann wrote:
>>>>> I can change the implementation but I don't think it's
>>>>> a good idea to copy property names around:
>>>>> it's too fragile, compiler won't warn us if we
>>>>> change the name or value semantics,
>>>>
>>>> I'm not worried. Changing the strings will break the command line
>>>> interface too (qemu -device pvpanic,ioport=...), so that isn't going to
>>>> happen.
>>>
>>> What will catch this breakage?
>>> There are 0 users actually tweaking the port
>>> number so I'm sure no one will notice this.
>>>
>>> In any case, catching errors at compile time
>>> is much better than at runtime.
>>>
>>> What exactly are advantages of duplicating
>>> property names in this way? I don't see any.
>>
>> You don't need access to pvpanic internals then and thus the code can be
>> moved over to the acpi generator. At least in this case where all info
>> needed is already available via properties.
>
> We'll have to disagree here.
> There's no access to internals with an API.
> I prefer using APIs, since they are compiler-checked.
Sorry, I don't understand, is there a typo? A qdev "ioport" property is
hardly internal, and QOM has an API to access it.
For QOM properties we have ABI stability rules in place, not only for
the textual command line: No one is allowed to change the type of a
property in an incompatible way. And dropping it would be a
command-line-incompatible change in this case. Properties don't
magically disappear at runtime, and since you're writing this code you
can rely on the property being present and the person attempting to
remove it noticing it while testing.
You're writing redundant code here, and it's not your device IIRC.
I vaguely remember seeing you or Xen guys adding some check that the
pvpanic device can only be instantiated once, right? In that case I
would consider it best to add an
object_property_add_child(qdev_get_machine(), "pvpanic", foo, NULL);
call into pvpanic device creation, then you can access it from ACPI code
without needing to know the type via
obj = object_path_resolve_component(qdev_get_machine(), "pvpanic");
if (obj != NULL) {
val = object_property_get_int(obj, "ioport", &err);
assert_no_error(&err);
}
and pvpanic code remains untouched.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-25 9:32 ` Michael S. Tsirkin
@ 2013-07-28 0:12 ` Andreas Färber
2013-07-28 7:30 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Andreas Färber @ 2013-07-28 0:12 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Anthony Liguori, qemu-devel, Aurelien Jarno, Gerd Hoffmann
Am 25.07.2013 11:32, schrieb Michael S. Tsirkin:
> This adds APIs that will be used to fill in guest info table,
> implemented using QOM, to various piix components.
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
>
> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index c885690..2128f13 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -29,6 +29,7 @@
> #include "exec/ioport.h"
> #include "hw/nvram/fw_cfg.h"
> #include "exec/address-spaces.h"
> +#include "hw/acpi/piix4.h"
>
> //#define DEBUG
>
> @@ -63,7 +64,7 @@ typedef struct CPUStatus {
> uint8_t sts[PIIX4_PROC_LEN];
> } CPUStatus;
>
> -typedef struct PIIX4PMState {
> +struct PIIX4PMState {
> /*< private >*/
> PCIDevice parent_obj;
> /*< public >*/
> @@ -96,7 +97,7 @@ typedef struct PIIX4PMState {
>
> CPUStatus gpe_cpu;
> Notifier cpu_added_notifier;
> -} PIIX4PMState;
> +};
>
> #define TYPE_PIIX4_PM "PIIX4_PM"
>
Here add
#define PIIX4_PM(obj) OBJECT_CHECK(PIIX4PMState, obj, TYPE_PIIX4_PM)
for the general public ...
> @@ -458,6 +459,30 @@ static int piix4_pm_initfn(PCIDevice *dev)
> return 0;
> }
>
> +PIIX4PMState *piix4_pm_find(void)
> +{
> + bool ambig;
> + Object *o = object_resolve_path_type("", "PIIX4_PM", &ambig);
> +
> + if (ambig || !o) {
> + return NULL;
> + }
> + return OBJECT_CHECK(PIIX4PMState, o, "PIIX4_PM");
... instead of open-coding it where only you use it, please.
> +}
> +
> +void piix4_pm_get_acpi_pm_info(PIIX4PMState *s, AcpiPmInfo *info)
> +{
> + info->s3_disabled = s->disable_s3;
> + info->s4_disabled = s->disable_s4;
> + info->s4_val = s->s4_val;
These three are accessible as qdev/QOM properties.
> +
> + info->acpi_enable_cmd = ACPI_ENABLE;
> + info->acpi_disable_cmd = ACPI_DISABLE;
> + info->gpe0_blk = GPE_BASE;
> + info->gpe0_blk_len = GPE_LEN;
So here the issue is that values are constant?
> + info->sci_int = 9;
Magic number - use a define to share it with wherever it is used?
> +}
> +
> i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> qemu_irq sci_irq, qemu_irq smi_irq,
> int kvm_enabled, FWCfgState *fw_cfg)
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index de87241..14573ab 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -965,7 +965,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> - isa_get_irq(NULL, 9), NULL, 0, NULL);
> + isa_get_irq(NULL, 9), NULL, 0, NULL, NULL);
This looks fishy. Might belong into a different patch? Implementation
didn't change above.
> /* TODO: Populate SPD eeprom data. */
> smbus_eeprom_init(smbus, 8, NULL, 0);
> pit = pit_init(isa_bus, 0x40, 0, NULL);
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 3908860..daefdfb 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -349,6 +349,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
> return b;
> }
>
> +PCIBus *find_i440fx(void)
> +{
> + PCIHostState *s = OBJECT_CHECK(PCIHostState,
> + object_resolve_path("/machine/i440fx", NULL),
> + TYPE_PCI_HOST_BRIDGE);
Open-coded OBJECT_CHECK() - should use existing PCI_HOST_BRIDGE(...).
> + return s ? s->bus : NULL;
> +}
Is this function really necessary? /machine/i440fx/pci.0 is a trivial
addition to the path that's already being used here. You can do:
PCIBus *bus = PCI_BUS(object_resolve_path("/machine/i440fx/pci.0"));
where you actually need to access it.
Andreas
> +
> /* PIIX3 PCI to ISA bridge */
> static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
> {
> diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
> new file mode 100644
> index 0000000..2876428
> --- /dev/null
> +++ b/include/hw/acpi/piix4.h
> @@ -0,0 +1,10 @@
> +#ifndef HW_ACPI_PIIX4_H
> +#define HW_ACPI_PIIX4_H
> +
> +#include "qemu/typedefs.h"
> +
> +PIIX4PMState *piix4_pm_find(void);
> +
> +void piix4_pm_get_acpi_pm_info(PIIX4PMState *, AcpiPmInfo *);
> +
> +#endif
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 7c0bd50..76af5cd 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -186,6 +186,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
> MemoryRegion *pci_memory,
> MemoryRegion *ram_memory);
>
> +PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
> diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
> index cb66e19..7d42693 100644
> --- a/include/qemu/typedefs.h
> +++ b/include/qemu/typedefs.h
> @@ -65,6 +65,7 @@ typedef struct QEMUSGList QEMUSGList;
> typedef struct SHPCDevice SHPCDevice;
> typedef struct FWCfgState FWCfgState;
> typedef struct PcGuestInfo PcGuestInfo;
> +typedef struct PIIX4PMState PIIX4PMState;
> typedef struct AcpiPmInfo AcpiPmInfo;
>
> #endif /* QEMU_TYPEDEFS_H */
>
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 10/14] ich9: APIs for pc guest info
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 10/14] ich9: APIs for " Michael S. Tsirkin
2013-07-25 12:33 ` Gerd Hoffmann
@ 2013-07-28 0:37 ` Andreas Färber
2013-07-28 7:35 ` Michael S. Tsirkin
1 sibling, 1 reply; 69+ messages in thread
From: Andreas Färber @ 2013-07-28 0:37 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Anthony Liguori, Gerd Hoffmann
Am 24.07.2013 18:02, schrieb Michael S. Tsirkin:
> This adds APIs that will be used to fill in
> guest info table, implemented using QOM,
> to various ich9 components.
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/ich9.c | 6 ++++++
> hw/isa/lpc_ich9.c | 19 +++++++++++++++++++
> hw/pci-host/q35.c | 10 ++++++++++
> include/hw/acpi/ich9.h | 2 ++
> include/hw/i386/ich9.h | 3 +++
> include/hw/pci-host/q35.h | 2 ++
> 6 files changed, 42 insertions(+)
>
> diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
> index 3fb443d..7ea55e1 100644
> --- a/hw/acpi/ich9.c
> +++ b/hw/acpi/ich9.c
> @@ -228,3 +228,9 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
> pm->powerdown_notifier.notify = pm_powerdown_req;
> qemu_register_powerdown_notifier(&pm->powerdown_notifier);
> }
> +
> +void ich9_pm_get_acpi_pm_info(ICH9LPCPMRegs *pm, AcpiPmInfo *info)
> +{
> + info->gpe0_blk = PC_GUEST_PORT_ACPI_PM_BASE + ICH9_PMIO_GPE0_STS;
> + info->gpe0_blk_len = ICH9_PMIO_GPE0_LEN;
> +}
> diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
> index d1921aa..12d4a23 100644
> --- a/hw/isa/lpc_ich9.c
> +++ b/hw/isa/lpc_ich9.c
> @@ -562,6 +562,25 @@ static bool ich9_rst_cnt_needed(void *opaque)
> return (lpc->rst_cnt != 0);
> }
>
> +ICH9LPCState *ich9_lpc_find(void)
> +{
> + bool ambig;
> + Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig);
> +
> + if (ambig) {
> + return NULL;
> + }
> + return ICH9_LPC_DEVICE(o);
> +}
> +
> +void ich9_lpc_get_acpi_pm_info(ICH9LPCState *lpc, AcpiPmInfo *info)
> +{
> + info->sci_int = 9;
Magic value.
> + info->acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
> + info->acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
> + ich9_pm_get_acpi_pm_info(&lpc->pm, info);
> +}
> +
> static const VMStateDescription vmstate_ich9_rst_cnt = {
> .name = "ICH9LPC/rst_cnt",
> .version_id = 1,
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index 6b1b3b7..ca6f495 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -298,6 +298,16 @@ static int mch_init(PCIDevice *d)
> return 0;
> }
>
> +uint64_t mch_mcfg_base(void)
> +{
> + bool ambiguous;
> + Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
If you take the minute to add in q35 machine init
object_property_add_child(qdev_get_machine(), "q35", foo, NULL);
then not only can you use object_resolve_path("/machine/q35/mch") to
access it but everyone including qtest can.
> + if (!o) {
> + return 0;
> + }
> + return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
Another value constant for the device. Taking a wild guess: Is this an
offset of a memory subregion where long-term Anthony's proposed
MemoryRegion QOM'ification would allow us to get rid of this helper?
Anyway, I would like it much better as:
uint64_t mch_mcfg_base()
{
return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
}
with the path resolution stuff, i.e. check for necessity, happening in
ACPI code, if we don't get around these helpers for now.
Andreas
> +}
> +
> static void mch_class_init(ObjectClass *klass, void *data)
> {
> PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
> index b1fe71f..f5e8a88 100644
> --- a/include/hw/acpi/ich9.h
> +++ b/include/hw/acpi/ich9.h
> @@ -49,4 +49,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
> void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
> extern const VMStateDescription vmstate_ich9_pm;
>
> +void ich9_pm_get_acpi_pm_info(ICH9LPCPMRegs *, AcpiPmInfo *);
> +
> #endif /* HW_ACPI_ICH9_H */
> diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
> index c5f637b..6528dc0 100644
> --- a/include/hw/i386/ich9.h
> +++ b/include/hw/i386/ich9.h
> @@ -66,6 +66,9 @@ typedef struct ICH9LPCState {
> qemu_irq *ioapic;
> } ICH9LPCState;
>
> +ICH9LPCState *ich9_lpc_find(void);
> +void ich9_lpc_get_acpi_pm_info(ICH9LPCState *, AcpiPmInfo *);
> +
> #define Q35_MASK(bit, ms_bit, ls_bit) \
> ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
>
> diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
> index 3cb631e..6337dcf 100644
> --- a/include/hw/pci-host/q35.h
> +++ b/include/hw/pci-host/q35.h
> @@ -154,4 +154,6 @@ typedef struct Q35PCIHost {
> #define MCH_PCIE_DEV 1
> #define MCH_PCIE_FUNC 0
>
> +uint64_t mch_mcfg_base(void);
> +
> #endif /* HW_Q35_H */
>
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 09/14] i386: define pc guest info
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 09/14] i386: define pc guest info Michael S. Tsirkin
2013-07-25 12:31 ` Gerd Hoffmann
@ 2013-07-28 0:41 ` Andreas Färber
2013-07-28 7:36 ` Michael S. Tsirkin
1 sibling, 1 reply; 69+ messages in thread
From: Andreas Färber @ 2013-07-28 0:41 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Anthony Liguori, qemu-devel, Gerd Hoffmann
Am 24.07.2013 18:02, schrieb Michael S. Tsirkin:
> This defines a structure that will be used to fill in guest info table.
> This structure will be filled in in follow-up patches, using QOM. Fill
> in NUMA node info is not available in QOM so it is filled in directly.
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
> ---
> hw/i386/pc.c | 33 +++++++++++++++++++++++++++++++++
> include/hw/i386/pc.h | 31 +++++++++++++++++++++++++++++++
> include/qemu/typedefs.h | 1 +
> 3 files changed, 65 insertions(+)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index b0b98a8..b9b8f92 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1017,6 +1017,27 @@ static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
> fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
> }
>
> +static void pc_set_cpu_guest_info(CPUState *cpu, void *arg)
> +{
> + PcGuestInfo *guest_info = arg;
> + CPUClass *klass = CPU_GET_CLASS(cpu);
> + uint64_t apic_id = klass->get_arch_id(cpu);
Please use "cc" to avoid the dreaded "klass".
> + int j;
> +
> + assert(apic_id <= MAX_CPUMASK_BITS);
> + assert(apic_id < guest_info->apic_id_limit);
> +
> + set_bit(apic_id, guest_info->found_cpus);
> +
> + for (j = 0; j < guest_info->numa_nodes; j++) {
> + assert(cpu->cpu_index < max_cpus);
> + if (test_bit(cpu->cpu_index, node_cpumask[j])) {
> + guest_info->node_cpu[apic_id] = cpu_to_le64(j);
> + break;
> + }
> + }
> +}
> +
> typedef struct PcGuestInfoState {
> PcGuestInfo info;
> Notifier machine_done;
> @@ -1037,6 +1058,18 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
> PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
> PcGuestInfo *guest_info = &guest_info_state->info;
>
> + guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
> + guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
> + guest_info->apic_xrupt_override = kvm_allows_irq0_override();
> + guest_info->numa_nodes = nb_numa_nodes;
> + guest_info->node_mem = g_memdup(node_mem, guest_info->numa_nodes *
> + sizeof *guest_info->node_mem);
> + guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
> + sizeof *guest_info->node_cpu);
> +
> + memset(&guest_info->found_cpus, 0, sizeof guest_info->found_cpus);
> + qemu_for_each_cpu(pc_set_cpu_guest_info, guest_info);
> +
> guest_info->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
> if (sizeof(hwaddr) == 4) {
> guest_info->pci_info.w64.begin = 0;
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 7fb97b0..7c0bd50 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -9,6 +9,9 @@
> #include "hw/i386/ioapic.h"
>
> #include "qemu/range.h"
> +#include "qemu/bitmap.h"
> +#include "sysemu/sysemu.h"
> +#include "hw/pci/pci.h"
>
> /* PC-style peripherals (also used by other machines). */
>
> @@ -17,9 +20,37 @@ typedef struct PcPciInfo {
> Range w64;
> } PcPciInfo;
>
> +/* Matches the value hard-coded in BIOS */
> +#define PC_GUEST_PORT_ACPI_PM_BASE 0xb000
> +
> +struct AcpiPmInfo {
> + bool s3_disabled;
> + bool s4_disabled;
> + uint8_t s4_val;
> + uint16_t sci_int;
> + uint8_t acpi_enable_cmd;
> + uint8_t acpi_disable_cmd;
> + uint32_t gpe0_blk;
> + uint32_t gpe0_blk_len;
> +};
> +
> struct PcGuestInfo {
> PcPciInfo pci_info;
These capitalizations look weird. Can't we use at least PM rather than Pm?
Andreas
> bool has_pci_info;
> + hwaddr ram_size;
> + unsigned apic_id_limit;
> + bool apic_xrupt_override;
> + bool has_hpet;
> + uint64_t numa_nodes;
> + uint64_t *node_mem;
> + uint64_t *node_cpu;
> + DECLARE_BITMAP(found_cpus, MAX_CPUMASK_BITS + 1);
> + DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
> + AcpiPmInfo pm;
> + uint64_t mcfg_base;
> + const unsigned char *dsdt_code;
> + unsigned dsdt_size;
> + uint16_t pvpanic_port;
> FWCfgState *fw_cfg;
> };
>
> diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
> index ac9f8d4..cb66e19 100644
> --- a/include/qemu/typedefs.h
> +++ b/include/qemu/typedefs.h
> @@ -65,5 +65,6 @@ typedef struct QEMUSGList QEMUSGList;
> typedef struct SHPCDevice SHPCDevice;
> typedef struct FWCfgState FWCfgState;
> typedef struct PcGuestInfo PcGuestInfo;
> +typedef struct AcpiPmInfo AcpiPmInfo;
>
> #endif /* QEMU_TYPEDEFS_H */
>
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 01/14] hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 01/14] hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h Michael S. Tsirkin
2013-07-25 12:05 ` Gerd Hoffmann
@ 2013-07-28 0:44 ` Andreas Färber
1 sibling, 0 replies; 69+ messages in thread
From: Andreas Färber @ 2013-07-28 0:44 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Anthony Liguori, Laszlo Ersek, qemu-devel
Am 24.07.2013 18:01, schrieb Michael S. Tsirkin:
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> Signed-off-by: Laszlo Ersek <lersek@redhat.com>
> ---
> hw/i386/pc.c | 2 --
> include/hw/i386/apic.h | 2 ++
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Andreas Färber <afaerber@suse.de>
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios
2013-07-26 15:30 ` Gerd Hoffmann
@ 2013-07-28 7:00 ` Michael S. Tsirkin
0 siblings, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-28 7:00 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: Anthony Liguori, qemu-devel
On Fri, Jul 26, 2013 at 05:30:29PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> >> That's something I think that it's best for firmware to avoid.
> >> Much better to load tables in memory and use standard ACPI
> >> methods to find specific tables.
> >
> > Problem is this happens relatively late in the firmware boot process.
>
> Completely different idea to tackle the issue: use COMMAND_ADD_POINTER
> not only for table pointers, but also register offsets. So the firmware
> doesn't need to parse fadt to figure how it should program pm_base, but
> instead can fixup the fadt according to the pm_base it has used.
>
> That is more in line with how firmware works (pm_base and simliar things
> tends to be #defines and are not runtime-configurable). And I think
> it's also more robust when extending/changing tables for newer acpi spec
> revisions.
>
> cheers,
> Gerd
>
And for newer chipsets. I agree. I plan to add a file to configure how
firmware programs PCI devices at init.
--
MST
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-28 0:12 ` Andreas Färber
@ 2013-07-28 7:30 ` Michael S. Tsirkin
2013-07-28 9:38 ` Andreas Färber
0 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-28 7:30 UTC (permalink / raw)
To: Andreas Färber
Cc: Anthony Liguori, qemu-devel, Aurelien Jarno, Gerd Hoffmann
On Sun, Jul 28, 2013 at 02:12:49AM +0200, Andreas Färber wrote:
> Am 25.07.2013 11:32, schrieb Michael S. Tsirkin:
> > This adds APIs that will be used to fill in guest info table,
> > implemented using QOM, to various piix components.
> >
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > ---
> >
> > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> > index c885690..2128f13 100644
> > --- a/hw/acpi/piix4.c
> > +++ b/hw/acpi/piix4.c
> > @@ -29,6 +29,7 @@
> > #include "exec/ioport.h"
> > #include "hw/nvram/fw_cfg.h"
> > #include "exec/address-spaces.h"
> > +#include "hw/acpi/piix4.h"
> >
> > //#define DEBUG
> >
> > @@ -63,7 +64,7 @@ typedef struct CPUStatus {
> > uint8_t sts[PIIX4_PROC_LEN];
> > } CPUStatus;
> >
> > -typedef struct PIIX4PMState {
> > +struct PIIX4PMState {
> > /*< private >*/
> > PCIDevice parent_obj;
> > /*< public >*/
> > @@ -96,7 +97,7 @@ typedef struct PIIX4PMState {
> >
> > CPUStatus gpe_cpu;
> > Notifier cpu_added_notifier;
> > -} PIIX4PMState;
> > +};
> >
> > #define TYPE_PIIX4_PM "PIIX4_PM"
> >
>
> Here add
>
> #define PIIX4_PM(obj) OBJECT_CHECK(PIIX4PMState, obj, TYPE_PIIX4_PM)
>
> for the general public ...
>
> > @@ -458,6 +459,30 @@ static int piix4_pm_initfn(PCIDevice *dev)
> > return 0;
> > }
> >
> > +PIIX4PMState *piix4_pm_find(void)
> > +{
> > + bool ambig;
> > + Object *o = object_resolve_path_type("", "PIIX4_PM", &ambig);
> > +
> > + if (ambig || !o) {
> > + return NULL;
> > + }
> > + return OBJECT_CHECK(PIIX4PMState, o, "PIIX4_PM");
>
> ... instead of open-coding it where only you use it, please.
I don't really understand in which direction you want to take this.
On the one hand, you are saying "there's one caller of
this function so please open-code it".
On the other hand, you are saying "it does not matter that
there's one user of this macro put it in the header".
Is the point that macros are somehow better than functions so they
should be used where possible?
> > +}
> > +
> > +void piix4_pm_get_acpi_pm_info(PIIX4PMState *s, AcpiPmInfo *info)
> > +{
> > + info->s3_disabled = s->disable_s3;
> > + info->s4_disabled = s->disable_s4;
> > + info->s4_val = s->s4_val;
>
> These three are accessible as qdev/QOM properties.
>
> > +
> > + info->acpi_enable_cmd = ACPI_ENABLE;
> > + info->acpi_disable_cmd = ACPI_DISABLE;
> > + info->gpe0_blk = GPE_BASE;
> > + info->gpe0_blk_len = GPE_LEN;
>
> So here the issue is that values are constant?
Yes.
> > + info->sci_int = 9;
>
> Magic number - use a define to share it with wherever it is used?
>
> > +}
> > +
> > i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> > qemu_irq sci_irq, qemu_irq smi_irq,
> > int kvm_enabled, FWCfgState *fw_cfg)
> > diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> > index de87241..14573ab 100644
> > --- a/hw/mips/mips_malta.c
> > +++ b/hw/mips/mips_malta.c
> > @@ -965,7 +965,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
> > pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> > pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> > smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> > - isa_get_irq(NULL, 9), NULL, 0, NULL);
> > + isa_get_irq(NULL, 9), NULL, 0, NULL, NULL);
>
> This looks fishy. Might belong into a different patch? Implementation
> didn't change above.
>
> > /* TODO: Populate SPD eeprom data. */
> > smbus_eeprom_init(smbus, 8, NULL, 0);
> > pit = pit_init(isa_bus, 0x40, 0, NULL);
> > diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> > index 3908860..daefdfb 100644
> > --- a/hw/pci-host/piix.c
> > +++ b/hw/pci-host/piix.c
> > @@ -349,6 +349,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
> > return b;
> > }
> >
> > +PCIBus *find_i440fx(void)
> > +{
> > + PCIHostState *s = OBJECT_CHECK(PCIHostState,
> > + object_resolve_path("/machine/i440fx", NULL),
> > + TYPE_PCI_HOST_BRIDGE);
>
> Open-coded OBJECT_CHECK() - should use existing PCI_HOST_BRIDGE(...).
>
> > + return s ? s->bus : NULL;
> > +}
>
> Is this function really necessary? /machine/i440fx/pci.0 is a trivial
> addition to the path that's already being used here. You can do:
> PCIBus *bus = PCI_BUS(object_resolve_path("/machine/i440fx/pci.0"));
> where you actually need to access it.
>
> Andreas
I don't mind but I would like to avoid callers hard-coding
paths, in this case "i440fx".
Why the aversion to functions?
> > +
> > /* PIIX3 PCI to ISA bridge */
> > static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
> > {
> > diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
> > new file mode 100644
> > index 0000000..2876428
> > --- /dev/null
> > +++ b/include/hw/acpi/piix4.h
> > @@ -0,0 +1,10 @@
> > +#ifndef HW_ACPI_PIIX4_H
> > +#define HW_ACPI_PIIX4_H
> > +
> > +#include "qemu/typedefs.h"
> > +
> > +PIIX4PMState *piix4_pm_find(void);
> > +
> > +void piix4_pm_get_acpi_pm_info(PIIX4PMState *, AcpiPmInfo *);
> > +
> > +#endif
> > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> > index 7c0bd50..76af5cd 100644
> > --- a/include/hw/i386/pc.h
> > +++ b/include/hw/i386/pc.h
> > @@ -186,6 +186,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
> > MemoryRegion *pci_memory,
> > MemoryRegion *ram_memory);
> >
> > +PCIBus *find_i440fx(void);
> > /* piix4.c */
> > extern PCIDevice *piix4_dev;
> > int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
> > diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
> > index cb66e19..7d42693 100644
> > --- a/include/qemu/typedefs.h
> > +++ b/include/qemu/typedefs.h
> > @@ -65,6 +65,7 @@ typedef struct QEMUSGList QEMUSGList;
> > typedef struct SHPCDevice SHPCDevice;
> > typedef struct FWCfgState FWCfgState;
> > typedef struct PcGuestInfo PcGuestInfo;
> > +typedef struct PIIX4PMState PIIX4PMState;
> > typedef struct AcpiPmInfo AcpiPmInfo;
> >
> > #endif /* QEMU_TYPEDEFS_H */
> >
>
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 10/14] ich9: APIs for pc guest info
2013-07-28 0:37 ` Andreas Färber
@ 2013-07-28 7:35 ` Michael S. Tsirkin
0 siblings, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-28 7:35 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Anthony Liguori, Gerd Hoffmann
On Sun, Jul 28, 2013 at 02:37:59AM +0200, Andreas Färber wrote:
> Am 24.07.2013 18:02, schrieb Michael S. Tsirkin:
> > This adds APIs that will be used to fill in
> > guest info table, implemented using QOM,
> > to various ich9 components.
> >
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > ---
> > hw/acpi/ich9.c | 6 ++++++
> > hw/isa/lpc_ich9.c | 19 +++++++++++++++++++
> > hw/pci-host/q35.c | 10 ++++++++++
> > include/hw/acpi/ich9.h | 2 ++
> > include/hw/i386/ich9.h | 3 +++
> > include/hw/pci-host/q35.h | 2 ++
> > 6 files changed, 42 insertions(+)
> >
> > diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
> > index 3fb443d..7ea55e1 100644
> > --- a/hw/acpi/ich9.c
> > +++ b/hw/acpi/ich9.c
> > @@ -228,3 +228,9 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
> > pm->powerdown_notifier.notify = pm_powerdown_req;
> > qemu_register_powerdown_notifier(&pm->powerdown_notifier);
> > }
> > +
> > +void ich9_pm_get_acpi_pm_info(ICH9LPCPMRegs *pm, AcpiPmInfo *info)
> > +{
> > + info->gpe0_blk = PC_GUEST_PORT_ACPI_PM_BASE + ICH9_PMIO_GPE0_STS;
> > + info->gpe0_blk_len = ICH9_PMIO_GPE0_LEN;
> > +}
> > diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
> > index d1921aa..12d4a23 100644
> > --- a/hw/isa/lpc_ich9.c
> > +++ b/hw/isa/lpc_ich9.c
> > @@ -562,6 +562,25 @@ static bool ich9_rst_cnt_needed(void *opaque)
> > return (lpc->rst_cnt != 0);
> > }
> >
> > +ICH9LPCState *ich9_lpc_find(void)
> > +{
> > + bool ambig;
> > + Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig);
> > +
> > + if (ambig) {
> > + return NULL;
> > + }
> > + return ICH9_LPC_DEVICE(o);
> > +}
> > +
> > +void ich9_lpc_get_acpi_pm_info(ICH9LPCState *lpc, AcpiPmInfo *info)
> > +{
> > + info->sci_int = 9;
>
> Magic value.
>
> > + info->acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
> > + info->acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
> > + ich9_pm_get_acpi_pm_info(&lpc->pm, info);
> > +}
> > +
> > static const VMStateDescription vmstate_ich9_rst_cnt = {
> > .name = "ICH9LPC/rst_cnt",
> > .version_id = 1,
> > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> > index 6b1b3b7..ca6f495 100644
> > --- a/hw/pci-host/q35.c
> > +++ b/hw/pci-host/q35.c
> > @@ -298,6 +298,16 @@ static int mch_init(PCIDevice *d)
> > return 0;
> > }
> >
> > +uint64_t mch_mcfg_base(void)
> > +{
> > + bool ambiguous;
> > + Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
>
> If you take the minute to add in q35 machine init
> object_property_add_child(qdev_get_machine(), "q35", foo, NULL);
> then not only can you use object_resolve_path("/machine/q35/mch") to
> access it but everyone including qtest can.
That's fine but I'd like to avoid copying string literals around.
> > + if (!o) {
> > + return 0;
> > + }
> > + return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
>
> Another value constant for the device. Taking a wild guess: Is this an
> offset of a memory subregion where long-term Anthony's proposed
> MemoryRegion QOM'ification would allow us to get rid of this helper?
I'm not sure that will be possible because the offset it
programmable by guest. At the moment all guests are required to
program a hard-coded offset, but I think what we'll have long term,
is a guest interface that let us control what guest programs.
> Anyway, I would like it much better as:
>
> uint64_t mch_mcfg_base()
> {
> return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
> }
>
> with the path resolution stuff, i.e. check for necessity, happening in
> ACPI code, if we don't get around these helpers for now.
>
> Andreas
>
> > +}
> > +
> > static void mch_class_init(ObjectClass *klass, void *data)
> > {
> > PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> > diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
> > index b1fe71f..f5e8a88 100644
> > --- a/include/hw/acpi/ich9.h
> > +++ b/include/hw/acpi/ich9.h
> > @@ -49,4 +49,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
> > void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
> > extern const VMStateDescription vmstate_ich9_pm;
> >
> > +void ich9_pm_get_acpi_pm_info(ICH9LPCPMRegs *, AcpiPmInfo *);
> > +
> > #endif /* HW_ACPI_ICH9_H */
> > diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
> > index c5f637b..6528dc0 100644
> > --- a/include/hw/i386/ich9.h
> > +++ b/include/hw/i386/ich9.h
> > @@ -66,6 +66,9 @@ typedef struct ICH9LPCState {
> > qemu_irq *ioapic;
> > } ICH9LPCState;
> >
> > +ICH9LPCState *ich9_lpc_find(void);
> > +void ich9_lpc_get_acpi_pm_info(ICH9LPCState *, AcpiPmInfo *);
> > +
> > #define Q35_MASK(bit, ms_bit, ls_bit) \
> > ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
> >
> > diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
> > index 3cb631e..6337dcf 100644
> > --- a/include/hw/pci-host/q35.h
> > +++ b/include/hw/pci-host/q35.h
> > @@ -154,4 +154,6 @@ typedef struct Q35PCIHost {
> > #define MCH_PCIE_DEV 1
> > #define MCH_PCIE_FUNC 0
> >
> > +uint64_t mch_mcfg_base(void);
> > +
> > #endif /* HW_Q35_H */
> >
>
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 09/14] i386: define pc guest info
2013-07-28 0:41 ` Andreas Färber
@ 2013-07-28 7:36 ` Michael S. Tsirkin
0 siblings, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-28 7:36 UTC (permalink / raw)
To: Andreas Färber; +Cc: Anthony Liguori, qemu-devel, Gerd Hoffmann
On Sun, Jul 28, 2013 at 02:41:51AM +0200, Andreas Färber wrote:
> Am 24.07.2013 18:02, schrieb Michael S. Tsirkin:
> > This defines a structure that will be used to fill in guest info table.
> > This structure will be filled in in follow-up patches, using QOM. Fill
> > in NUMA node info is not available in QOM so it is filled in directly.
> >
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > Reviewed-by: Laszlo Ersek <lersek@redhat.com>
> > ---
> > hw/i386/pc.c | 33 +++++++++++++++++++++++++++++++++
> > include/hw/i386/pc.h | 31 +++++++++++++++++++++++++++++++
> > include/qemu/typedefs.h | 1 +
> > 3 files changed, 65 insertions(+)
> >
> > diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> > index b0b98a8..b9b8f92 100644
> > --- a/hw/i386/pc.c
> > +++ b/hw/i386/pc.c
> > @@ -1017,6 +1017,27 @@ static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
> > fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
> > }
> >
> > +static void pc_set_cpu_guest_info(CPUState *cpu, void *arg)
> > +{
> > + PcGuestInfo *guest_info = arg;
> > + CPUClass *klass = CPU_GET_CLASS(cpu);
> > + uint64_t apic_id = klass->get_arch_id(cpu);
>
> Please use "cc" to avoid the dreaded "klass".
>
> > + int j;
> > +
> > + assert(apic_id <= MAX_CPUMASK_BITS);
> > + assert(apic_id < guest_info->apic_id_limit);
> > +
> > + set_bit(apic_id, guest_info->found_cpus);
> > +
> > + for (j = 0; j < guest_info->numa_nodes; j++) {
> > + assert(cpu->cpu_index < max_cpus);
> > + if (test_bit(cpu->cpu_index, node_cpumask[j])) {
> > + guest_info->node_cpu[apic_id] = cpu_to_le64(j);
> > + break;
> > + }
> > + }
> > +}
> > +
> > typedef struct PcGuestInfoState {
> > PcGuestInfo info;
> > Notifier machine_done;
> > @@ -1037,6 +1058,18 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
> > PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
> > PcGuestInfo *guest_info = &guest_info_state->info;
> >
> > + guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
> > + guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
> > + guest_info->apic_xrupt_override = kvm_allows_irq0_override();
> > + guest_info->numa_nodes = nb_numa_nodes;
> > + guest_info->node_mem = g_memdup(node_mem, guest_info->numa_nodes *
> > + sizeof *guest_info->node_mem);
> > + guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
> > + sizeof *guest_info->node_cpu);
> > +
> > + memset(&guest_info->found_cpus, 0, sizeof guest_info->found_cpus);
> > + qemu_for_each_cpu(pc_set_cpu_guest_info, guest_info);
> > +
> > guest_info->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
> > if (sizeof(hwaddr) == 4) {
> > guest_info->pci_info.w64.begin = 0;
> > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> > index 7fb97b0..7c0bd50 100644
> > --- a/include/hw/i386/pc.h
> > +++ b/include/hw/i386/pc.h
> > @@ -9,6 +9,9 @@
> > #include "hw/i386/ioapic.h"
> >
> > #include "qemu/range.h"
> > +#include "qemu/bitmap.h"
> > +#include "sysemu/sysemu.h"
> > +#include "hw/pci/pci.h"
> >
> > /* PC-style peripherals (also used by other machines). */
> >
> > @@ -17,9 +20,37 @@ typedef struct PcPciInfo {
> > Range w64;
> > } PcPciInfo;
> >
> > +/* Matches the value hard-coded in BIOS */
> > +#define PC_GUEST_PORT_ACPI_PM_BASE 0xb000
> > +
> > +struct AcpiPmInfo {
> > + bool s3_disabled;
> > + bool s4_disabled;
> > + uint8_t s4_val;
> > + uint16_t sci_int;
> > + uint8_t acpi_enable_cmd;
> > + uint8_t acpi_disable_cmd;
> > + uint32_t gpe0_blk;
> > + uint32_t gpe0_blk_len;
> > +};
> > +
> > struct PcGuestInfo {
> > PcPciInfo pci_info;
>
> These capitalizations look weird. Can't we use at least PM rather than Pm?
>
> Andreas
I prefer making a first letter in each work upper case consistently but
I don't mind so much.
> > bool has_pci_info;
> > + hwaddr ram_size;
> > + unsigned apic_id_limit;
> > + bool apic_xrupt_override;
> > + bool has_hpet;
> > + uint64_t numa_nodes;
> > + uint64_t *node_mem;
> > + uint64_t *node_cpu;
> > + DECLARE_BITMAP(found_cpus, MAX_CPUMASK_BITS + 1);
> > + DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
> > + AcpiPmInfo pm;
> > + uint64_t mcfg_base;
> > + const unsigned char *dsdt_code;
> > + unsigned dsdt_size;
> > + uint16_t pvpanic_port;
> > FWCfgState *fw_cfg;
> > };
> >
> > diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
> > index ac9f8d4..cb66e19 100644
> > --- a/include/qemu/typedefs.h
> > +++ b/include/qemu/typedefs.h
> > @@ -65,5 +65,6 @@ typedef struct QEMUSGList QEMUSGList;
> > typedef struct SHPCDevice SHPCDevice;
> > typedef struct FWCfgState FWCfgState;
> > typedef struct PcGuestInfo PcGuestInfo;
> > +typedef struct AcpiPmInfo AcpiPmInfo;
> >
> > #endif /* QEMU_TYPEDEFS_H */
> >
>
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 06/14] i386: add bios linker/loader
2013-07-26 9:42 ` Gerd Hoffmann
@ 2013-07-28 8:08 ` Michael S. Tsirkin
0 siblings, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-28 8:08 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel
On Fri, Jul 26, 2013 at 11:42:45AM +0200, Gerd Hoffmann wrote:
> Hi,
>
> Hacked up coreboot support to verify the interface.
>
> > + /*
> > + * COMMAND_ALLOCATE - allocate a table from @alloc_file
> > + * subject to @alloc_align alignment (must be power of 2)
> > + * and @alloc_zone (can be HIGH or FSEG) requirements.
> > + *
> > + * Must appear exactly once for each file, and before
> > + * this file is referenced by any other command.
> > + */
>
> Do we need alloc_zone?
>
> Rules are simple: rsdp goes to fseg, everything else to high, correct?
Yes but I prefer marking it explicitly at link time and avoid hard-coding
things in the bios, so that whoever allocates memory can go just by
linker rules and not poke at tables themselves.
> Both seabios and coreboot handle that by first placing *all* acpi tables
> in high memory, then go place a rsdp copy in fseg.
No, what happens is we put everything in tmp memory, then
copy where appropriately.
> > + /*
> > + * COMMAND_ADD_POINTER - patch the table (originating from
> > + * @dest_file) at @pointer_offset, by adding a pointer to the table
> > + * originating from @src_file. 1,2,4 or 8 byte unsigned
> > + * addition is used depending on @pointer_size.
> > + */
>
> Do we need pointer_size?
>
> Current tables use 4 bytes only.
>
> 1+2 bytes is pointless, the src_file address will be big enougth that it
> doesn't fit into one or two bytes, so I doubt they will ever be used.
>
> 8 bytes would only be used when placing acpi tables above 4g. Is that
> something expected to happen?
Yes, the spec allows 64 bit pointers.
> If not 4 bytes is enough, even for 8 byte
> pointers as the 4 high bytes would be zero no matter what.
>
> cheers,
> Gerd
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-28 7:30 ` Michael S. Tsirkin
@ 2013-07-28 9:38 ` Andreas Färber
2013-07-28 10:14 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Andreas Färber @ 2013-07-28 9:38 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Anthony Liguori, qemu-devel, Aurelien Jarno, Gerd Hoffmann
Am 28.07.2013 09:30, schrieb Michael S. Tsirkin:
> On Sun, Jul 28, 2013 at 02:12:49AM +0200, Andreas Färber wrote:
>> Am 25.07.2013 11:32, schrieb Michael S. Tsirkin:
>>> This adds APIs that will be used to fill in guest info table,
>>> implemented using QOM, to various piix components.
>>>
>>> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>>> ---
>>>
>>> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
>>> index c885690..2128f13 100644
>>> --- a/hw/acpi/piix4.c
>>> +++ b/hw/acpi/piix4.c
>>> @@ -29,6 +29,7 @@
>>> #include "exec/ioport.h"
>>> #include "hw/nvram/fw_cfg.h"
>>> #include "exec/address-spaces.h"
>>> +#include "hw/acpi/piix4.h"
>>>
>>> //#define DEBUG
>>>
>>> @@ -63,7 +64,7 @@ typedef struct CPUStatus {
>>> uint8_t sts[PIIX4_PROC_LEN];
>>> } CPUStatus;
>>>
>>> -typedef struct PIIX4PMState {
>>> +struct PIIX4PMState {
>>> /*< private >*/
>>> PCIDevice parent_obj;
>>> /*< public >*/
>>> @@ -96,7 +97,7 @@ typedef struct PIIX4PMState {
>>>
>>> CPUStatus gpe_cpu;
>>> Notifier cpu_added_notifier;
>>> -} PIIX4PMState;
>>> +};
>>>
>>> #define TYPE_PIIX4_PM "PIIX4_PM"
>>>
>>
>> Here add
>>
>> #define PIIX4_PM(obj) OBJECT_CHECK(PIIX4PMState, obj, TYPE_PIIX4_PM)
>>
>> for the general public ...
>>
>>> @@ -458,6 +459,30 @@ static int piix4_pm_initfn(PCIDevice *dev)
>>> return 0;
>>> }
>>>
>>> +PIIX4PMState *piix4_pm_find(void)
>>> +{
>>> + bool ambig;
>>> + Object *o = object_resolve_path_type("", "PIIX4_PM", &ambig);
>>> +
>>> + if (ambig || !o) {
>>> + return NULL;
>>> + }
>>> + return OBJECT_CHECK(PIIX4PMState, o, "PIIX4_PM");
>>
>> ... instead of open-coding it where only you use it, please.
>
> I don't really understand in which direction you want to take this.
> On the one hand, you are saying "there's one caller of
> this function so please open-code it".
> On the other hand, you are saying "it does not matter that
> there's one user of this macro put it in the header".
>
> Is the point that macros are somehow better than functions so they
> should be used where possible?
No, the point is reuse: For QOM realize we will very likely need the
same thing. It was not my decision to make these macros, I'm just making
Anthony's QOM pattern consistent.
>>> +}
>>> +
>>> +void piix4_pm_get_acpi_pm_info(PIIX4PMState *s, AcpiPmInfo *info)
>>> +{
>>> + info->s3_disabled = s->disable_s3;
>>> + info->s4_disabled = s->disable_s4;
>>> + info->s4_val = s->s4_val;
>>
>> These three are accessible as qdev/QOM properties.
>>
>>> +
>>> + info->acpi_enable_cmd = ACPI_ENABLE;
>>> + info->acpi_disable_cmd = ACPI_DISABLE;
>>> + info->gpe0_blk = GPE_BASE;
>>> + info->gpe0_blk_len = GPE_LEN;
>>
>> So here the issue is that values are constant?
>
> Yes.
>
>>> + info->sci_int = 9;
>>
>> Magic number - use a define to share it with wherever it is used?
>>
>>> +}
>>> +
>>> i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>>> qemu_irq sci_irq, qemu_irq smi_irq,
>>> int kvm_enabled, FWCfgState *fw_cfg)
>>> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
>>> index de87241..14573ab 100644
>>> --- a/hw/mips/mips_malta.c
>>> +++ b/hw/mips/mips_malta.c
>>> @@ -965,7 +965,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
>>> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
>>> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>>> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>>> - isa_get_irq(NULL, 9), NULL, 0, NULL);
>>> + isa_get_irq(NULL, 9), NULL, 0, NULL, NULL);
>>
>> This looks fishy. Might belong into a different patch? Implementation
>> didn't change above.
>>
>>> /* TODO: Populate SPD eeprom data. */
>>> smbus_eeprom_init(smbus, 8, NULL, 0);
>>> pit = pit_init(isa_bus, 0x40, 0, NULL);
>>> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>>> index 3908860..daefdfb 100644
>>> --- a/hw/pci-host/piix.c
>>> +++ b/hw/pci-host/piix.c
>>> @@ -349,6 +349,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
>>> return b;
>>> }
>>>
>>> +PCIBus *find_i440fx(void)
>>> +{
>>> + PCIHostState *s = OBJECT_CHECK(PCIHostState,
>>> + object_resolve_path("/machine/i440fx", NULL),
>>> + TYPE_PCI_HOST_BRIDGE);
>>
>> Open-coded OBJECT_CHECK() - should use existing PCI_HOST_BRIDGE(...).
>>
>>> + return s ? s->bus : NULL;
>>> +}
>>
>> Is this function really necessary? /machine/i440fx/pci.0 is a trivial
>> addition to the path that's already being used here. You can do:
>> PCIBus *bus = PCI_BUS(object_resolve_path("/machine/i440fx/pci.0"));
>> where you actually need to access it.
>
>
> I don't mind but I would like to avoid callers hard-coding
> paths, in this case "i440fx".
> Why the aversion to functions?
Simply because QMP cannot call functions. It has to work with qom-list
and qom-get, so this is a test case showing what is missing and can IMO
easily be addressed for both parties.
The suggested cast to PCI_BUS() lets you use regular qdev functions btw
as a shortcut, QMP users would need to iterate children of that node.
The suggested "pci.0" is considered stable for -device ...,bus=pci.0
according to review feedback the Xen people have received for libxl.
Andreas
>
>>> +
>>> /* PIIX3 PCI to ISA bridge */
>>> static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
>>> {
>>> diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
>>> new file mode 100644
>>> index 0000000..2876428
>>> --- /dev/null
>>> +++ b/include/hw/acpi/piix4.h
>>> @@ -0,0 +1,10 @@
>>> +#ifndef HW_ACPI_PIIX4_H
>>> +#define HW_ACPI_PIIX4_H
>>> +
>>> +#include "qemu/typedefs.h"
>>> +
>>> +PIIX4PMState *piix4_pm_find(void);
>>> +
>>> +void piix4_pm_get_acpi_pm_info(PIIX4PMState *, AcpiPmInfo *);
>>> +
>>> +#endif
>>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>>> index 7c0bd50..76af5cd 100644
>>> --- a/include/hw/i386/pc.h
>>> +++ b/include/hw/i386/pc.h
>>> @@ -186,6 +186,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
>>> MemoryRegion *pci_memory,
>>> MemoryRegion *ram_memory);
>>>
>>> +PCIBus *find_i440fx(void);
>>> /* piix4.c */
>>> extern PCIDevice *piix4_dev;
>>> int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>>> diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
>>> index cb66e19..7d42693 100644
>>> --- a/include/qemu/typedefs.h
>>> +++ b/include/qemu/typedefs.h
>>> @@ -65,6 +65,7 @@ typedef struct QEMUSGList QEMUSGList;
>>> typedef struct SHPCDevice SHPCDevice;
>>> typedef struct FWCfgState FWCfgState;
>>> typedef struct PcGuestInfo PcGuestInfo;
>>> +typedef struct PIIX4PMState PIIX4PMState;
>>> typedef struct AcpiPmInfo AcpiPmInfo;
>>>
>>> #endif /* QEMU_TYPEDEFS_H */
>>>
>>
>>
>> --
>> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
>> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-28 9:38 ` Andreas Färber
@ 2013-07-28 10:14 ` Michael S. Tsirkin
2013-07-28 10:31 ` Andreas Färber
0 siblings, 1 reply; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-28 10:14 UTC (permalink / raw)
To: Andreas Färber
Cc: Anthony Liguori, qemu-devel, Aurelien Jarno, Gerd Hoffmann
On Sun, Jul 28, 2013 at 11:38:17AM +0200, Andreas Färber wrote:
> Am 28.07.2013 09:30, schrieb Michael S. Tsirkin:
> > On Sun, Jul 28, 2013 at 02:12:49AM +0200, Andreas Färber wrote:
> >> Am 25.07.2013 11:32, schrieb Michael S. Tsirkin:
> >>> This adds APIs that will be used to fill in guest info table,
> >>> implemented using QOM, to various piix components.
> >>>
> >>> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> >>> ---
> >>>
> >>> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> >>> index c885690..2128f13 100644
> >>> --- a/hw/acpi/piix4.c
> >>> +++ b/hw/acpi/piix4.c
> >>> @@ -29,6 +29,7 @@
> >>> #include "exec/ioport.h"
> >>> #include "hw/nvram/fw_cfg.h"
> >>> #include "exec/address-spaces.h"
> >>> +#include "hw/acpi/piix4.h"
> >>>
> >>> //#define DEBUG
> >>>
> >>> @@ -63,7 +64,7 @@ typedef struct CPUStatus {
> >>> uint8_t sts[PIIX4_PROC_LEN];
> >>> } CPUStatus;
> >>>
> >>> -typedef struct PIIX4PMState {
> >>> +struct PIIX4PMState {
> >>> /*< private >*/
> >>> PCIDevice parent_obj;
> >>> /*< public >*/
> >>> @@ -96,7 +97,7 @@ typedef struct PIIX4PMState {
> >>>
> >>> CPUStatus gpe_cpu;
> >>> Notifier cpu_added_notifier;
> >>> -} PIIX4PMState;
> >>> +};
> >>>
> >>> #define TYPE_PIIX4_PM "PIIX4_PM"
> >>>
> >>
> >> Here add
> >>
> >> #define PIIX4_PM(obj) OBJECT_CHECK(PIIX4PMState, obj, TYPE_PIIX4_PM)
> >>
> >> for the general public ...
> >>
> >>> @@ -458,6 +459,30 @@ static int piix4_pm_initfn(PCIDevice *dev)
> >>> return 0;
> >>> }
> >>>
> >>> +PIIX4PMState *piix4_pm_find(void)
> >>> +{
> >>> + bool ambig;
> >>> + Object *o = object_resolve_path_type("", "PIIX4_PM", &ambig);
> >>> +
> >>> + if (ambig || !o) {
> >>> + return NULL;
> >>> + }
> >>> + return OBJECT_CHECK(PIIX4PMState, o, "PIIX4_PM");
> >>
> >> ... instead of open-coding it where only you use it, please.
> >
> > I don't really understand in which direction you want to take this.
> > On the one hand, you are saying "there's one caller of
> > this function so please open-code it".
> > On the other hand, you are saying "it does not matter that
> > there's one user of this macro put it in the header".
> >
> > Is the point that macros are somehow better than functions so they
> > should be used where possible?
>
> No, the point is reuse: For QOM realize we will very likely need the
> same thing. It was not my decision to make these macros, I'm just making
> Anthony's QOM pattern consistent.
>
> >>> +}
> >>> +
> >>> +void piix4_pm_get_acpi_pm_info(PIIX4PMState *s, AcpiPmInfo *info)
> >>> +{
> >>> + info->s3_disabled = s->disable_s3;
> >>> + info->s4_disabled = s->disable_s4;
> >>> + info->s4_val = s->s4_val;
> >>
> >> These three are accessible as qdev/QOM properties.
> >>
> >>> +
> >>> + info->acpi_enable_cmd = ACPI_ENABLE;
> >>> + info->acpi_disable_cmd = ACPI_DISABLE;
> >>> + info->gpe0_blk = GPE_BASE;
> >>> + info->gpe0_blk_len = GPE_LEN;
> >>
> >> So here the issue is that values are constant?
> >
> > Yes.
> >
> >>> + info->sci_int = 9;
> >>
> >> Magic number - use a define to share it with wherever it is used?
> >>
> >>> +}
> >>> +
> >>> i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> >>> qemu_irq sci_irq, qemu_irq smi_irq,
> >>> int kvm_enabled, FWCfgState *fw_cfg)
> >>> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> >>> index de87241..14573ab 100644
> >>> --- a/hw/mips/mips_malta.c
> >>> +++ b/hw/mips/mips_malta.c
> >>> @@ -965,7 +965,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
> >>> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> >>> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> >>> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> >>> - isa_get_irq(NULL, 9), NULL, 0, NULL);
> >>> + isa_get_irq(NULL, 9), NULL, 0, NULL, NULL);
> >>
> >> This looks fishy. Might belong into a different patch? Implementation
> >> didn't change above.
> >>
> >>> /* TODO: Populate SPD eeprom data. */
> >>> smbus_eeprom_init(smbus, 8, NULL, 0);
> >>> pit = pit_init(isa_bus, 0x40, 0, NULL);
> >>> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> >>> index 3908860..daefdfb 100644
> >>> --- a/hw/pci-host/piix.c
> >>> +++ b/hw/pci-host/piix.c
> >>> @@ -349,6 +349,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
> >>> return b;
> >>> }
> >>>
> >>> +PCIBus *find_i440fx(void)
> >>> +{
> >>> + PCIHostState *s = OBJECT_CHECK(PCIHostState,
> >>> + object_resolve_path("/machine/i440fx", NULL),
> >>> + TYPE_PCI_HOST_BRIDGE);
> >>
> >> Open-coded OBJECT_CHECK() - should use existing PCI_HOST_BRIDGE(...).
> >>
> >>> + return s ? s->bus : NULL;
> >>> +}
> >>
> >> Is this function really necessary? /machine/i440fx/pci.0 is a trivial
> >> addition to the path that's already being used here. You can do:
> >> PCIBus *bus = PCI_BUS(object_resolve_path("/machine/i440fx/pci.0"));
> >> where you actually need to access it.
> >
> >
> > I don't mind but I would like to avoid callers hard-coding
> > paths, in this case "i440fx".
> > Why the aversion to functions?
>
> Simply because QMP cannot call functions. It has to work with qom-list
> and qom-get, so this is a test case showing what is missing and can IMO
> easily be addressed for both parties.
Fine but if the function calls QOM things internally
then where's the problem?
> The suggested cast to PCI_BUS() lets you use regular qdev functions btw
> as a shortcut, QMP users would need to iterate children of that node.
>
> The suggested "pci.0" is considered stable for -device ...,bus=pci.0
> according to review feedback the Xen people have received for libxl.
>
> Andreas
>
> >
> >>> +
> >>> /* PIIX3 PCI to ISA bridge */
> >>> static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
> >>> {
> >>> diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
> >>> new file mode 100644
> >>> index 0000000..2876428
> >>> --- /dev/null
> >>> +++ b/include/hw/acpi/piix4.h
> >>> @@ -0,0 +1,10 @@
> >>> +#ifndef HW_ACPI_PIIX4_H
> >>> +#define HW_ACPI_PIIX4_H
> >>> +
> >>> +#include "qemu/typedefs.h"
> >>> +
> >>> +PIIX4PMState *piix4_pm_find(void);
> >>> +
> >>> +void piix4_pm_get_acpi_pm_info(PIIX4PMState *, AcpiPmInfo *);
> >>> +
> >>> +#endif
> >>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> >>> index 7c0bd50..76af5cd 100644
> >>> --- a/include/hw/i386/pc.h
> >>> +++ b/include/hw/i386/pc.h
> >>> @@ -186,6 +186,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
> >>> MemoryRegion *pci_memory,
> >>> MemoryRegion *ram_memory);
> >>>
> >>> +PCIBus *find_i440fx(void);
> >>> /* piix4.c */
> >>> extern PCIDevice *piix4_dev;
> >>> int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
> >>> diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
> >>> index cb66e19..7d42693 100644
> >>> --- a/include/qemu/typedefs.h
> >>> +++ b/include/qemu/typedefs.h
> >>> @@ -65,6 +65,7 @@ typedef struct QEMUSGList QEMUSGList;
> >>> typedef struct SHPCDevice SHPCDevice;
> >>> typedef struct FWCfgState FWCfgState;
> >>> typedef struct PcGuestInfo PcGuestInfo;
> >>> +typedef struct PIIX4PMState PIIX4PMState;
> >>> typedef struct AcpiPmInfo AcpiPmInfo;
> >>>
> >>> #endif /* QEMU_TYPEDEFS_H */
> >>>
> >>
> >>
> >> --
> >> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> >> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
>
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-28 10:14 ` Michael S. Tsirkin
@ 2013-07-28 10:31 ` Andreas Färber
2013-07-28 11:08 ` Andreas Färber
0 siblings, 1 reply; 69+ messages in thread
From: Andreas Färber @ 2013-07-28 10:31 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Anthony Liguori, qemu-devel, Aurelien Jarno, Gerd Hoffmann
Am 28.07.2013 12:14, schrieb Michael S. Tsirkin:
> On Sun, Jul 28, 2013 at 11:38:17AM +0200, Andreas Färber wrote:
>> Am 28.07.2013 09:30, schrieb Michael S. Tsirkin:
>>> On Sun, Jul 28, 2013 at 02:12:49AM +0200, Andreas Färber wrote:
>>>> Am 25.07.2013 11:32, schrieb Michael S. Tsirkin:
>>>>> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>>>>> index 3908860..daefdfb 100644
>>>>> --- a/hw/pci-host/piix.c
>>>>> +++ b/hw/pci-host/piix.c
>>>>> @@ -349,6 +349,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
>>>>> return b;
>>>>> }
>>>>>
>>>>> +PCIBus *find_i440fx(void)
>>>>> +{
>>>>> + PCIHostState *s = OBJECT_CHECK(PCIHostState,
>>>>> + object_resolve_path("/machine/i440fx", NULL),
>>>>> + TYPE_PCI_HOST_BRIDGE);
>>>>
>>>> Open-coded OBJECT_CHECK() - should use existing PCI_HOST_BRIDGE(...).
>>>>
>>>>> + return s ? s->bus : NULL;
>>>>> +}
>>>>
>>>> Is this function really necessary? /machine/i440fx/pci.0 is a trivial
>>>> addition to the path that's already being used here. You can do:
>>>> PCIBus *bus = PCI_BUS(object_resolve_path("/machine/i440fx/pci.0"));
>>>> where you actually need to access it.
>>>
>>>
>>> I don't mind but I would like to avoid callers hard-coding
>>> paths, in this case "i440fx".
>>> Why the aversion to functions?
>>
>> Simply because QMP cannot call functions. It has to work with qom-list
>> and qom-get, so this is a test case showing what is missing and can IMO
>> easily be addressed for both parties.
>
> Fine but if the function calls QOM things internally
> then where's the problem?
The grief with object_path_resolve_type() is that it's a "hack" Paolo
has added for his convenience (in audio code?) that QMP cannot use, so
we need name-based paths to be available.
And to clarify, I have been talking about two different time frames:
Small adjustments that you can make for 1.6 (e.g., casts, q35 property,
different QOM function/callsite used; if Anthony is okay with taking
ACPI at this late point) and post-1.6 cleanups to replace interim
constructs that involve refactorings outside your control (e.g.,
MemoryRegion QOM'ification, adding properties to random devices).
Andreas
>> The suggested cast to PCI_BUS() lets you use regular qdev functions btw
>> as a shortcut, QMP users would need to iterate children of that node.
>>
>> The suggested "pci.0" is considered stable for -device ...,bus=pci.0
>> according to review feedback the Xen people have received for libxl.
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-28 10:31 ` Andreas Färber
@ 2013-07-28 11:08 ` Andreas Färber
2013-07-28 12:19 ` Michael S. Tsirkin
0 siblings, 1 reply; 69+ messages in thread
From: Andreas Färber @ 2013-07-28 11:08 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Aurelien Jarno, qemu-devel, Anthony Liguori, Gerd Hoffmann
Am 28.07.2013 12:31, schrieb Andreas Färber:
> Am 28.07.2013 12:14, schrieb Michael S. Tsirkin:
>> On Sun, Jul 28, 2013 at 11:38:17AM +0200, Andreas Färber wrote:
>>> Am 28.07.2013 09:30, schrieb Michael S. Tsirkin:
>>>> On Sun, Jul 28, 2013 at 02:12:49AM +0200, Andreas Färber wrote:
>>>>> Am 25.07.2013 11:32, schrieb Michael S. Tsirkin:
>>>>>> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>>>>>> index 3908860..daefdfb 100644
>>>>>> --- a/hw/pci-host/piix.c
>>>>>> +++ b/hw/pci-host/piix.c
>>>>>> @@ -349,6 +349,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
>>>>>> return b;
>>>>>> }
>>>>>>
>>>>>> +PCIBus *find_i440fx(void)
>>>>>> +{
>>>>>> + PCIHostState *s = OBJECT_CHECK(PCIHostState,
>>>>>> + object_resolve_path("/machine/i440fx", NULL),
>>>>>> + TYPE_PCI_HOST_BRIDGE);
>>>>>
>>>>> Open-coded OBJECT_CHECK() - should use existing PCI_HOST_BRIDGE(...).
>>>>>
>>>>>> + return s ? s->bus : NULL;
>>>>>> +}
>>>>>
>>>>> Is this function really necessary? /machine/i440fx/pci.0 is a trivial
>>>>> addition to the path that's already being used here. You can do:
>>>>> PCIBus *bus = PCI_BUS(object_resolve_path("/machine/i440fx/pci.0"));
>>>>> where you actually need to access it.
>>>>
>>>>
>>>> I don't mind but I would like to avoid callers hard-coding
>>>> paths, in this case "i440fx".
>>>> Why the aversion to functions?
>>>
>>> Simply because QMP cannot call functions. It has to work with qom-list
>>> and qom-get, so this is a test case showing what is missing and can IMO
>>> easily be addressed for both parties.
>>
>> Fine but if the function calls QOM things internally
>> then where's the problem?
>
> The grief with object_path_resolve_type() is that it's a "hack" Paolo
> has added for his convenience (in audio code?) that QMP cannot use, so
> we need name-based paths to be available.
Add to that, the way I see QOM devices (as opposed to qdev or pre-qdev
devices) is that they are instantiated from the outside - a different
source file or command line or config file - via QOM APIs, and they
allow other source files to interact with them via mydev_foo(MyDev *d,
...) APIs that operate on an instance.
Having functions to create devices often hints at legacy code from
pre-qdev times (we had such a discussion with Alex when I tried to
qdev'ify the prep_pci device), indicating that either something is not
yet accessible via qdev/QOM APIs (e.g., IRQs) or that the device is not
yet implementing composition properly (e.g., creating a bus after the
bridge device rather than in the bridge, or a PCIDevice after the PHB
rather than by the PHB).
Having functions in the device's file to obtain a random instance of
that device in the form MyDev *mydev_get(void) is what I dislike here.
My personal preference (which you may ignore if others disagree) would
be to have accessors, where unavoidable, in the form:
foo mydev_get_bar(MyDev *s)
{
return s->baz;
}
which we can then later easily convert into dynamic property getters,
and it would hopefully spare us new per-device ...Info structs by
obtaining the info where and when you need it.
I admit it's a bit of boilerplate to code, but I've seen at most 4 cases
per device where this would apply and I'm saying this with our
longer-term QOM goals in mind.
I'm skeptical towards Igor's suggestion of adding Last Minute 1.6 qdev
properties (as opposed to a composition property, you force me to become
very explicit in my explanations...) as that would bring ABI stability
rules onto us.
Andreas
> And to clarify, I have been talking about two different time frames:
> Small adjustments that you can make for 1.6 (e.g., casts, q35 property,
> different QOM function/callsite used; if Anthony is okay with taking
> ACPI at this late point) and post-1.6 cleanups to replace interim
> constructs that involve refactorings outside your control (e.g.,
> MemoryRegion QOM'ification, adding properties to random devices).
>
> Andreas
>
>>> The suggested cast to PCI_BUS() lets you use regular qdev functions btw
>>> as a shortcut, QMP users would need to iterate children of that node.
>>>
>>> The suggested "pci.0" is considered stable for -device ...,bus=pci.0
>>> according to review feedback the Xen people have received for libxl.
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/14] piix: APIs for pc guest info
2013-07-28 11:08 ` Andreas Färber
@ 2013-07-28 12:19 ` Michael S. Tsirkin
0 siblings, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-07-28 12:19 UTC (permalink / raw)
To: Andreas Färber
Cc: Aurelien Jarno, qemu-devel, Anthony Liguori, Gerd Hoffmann
On Sun, Jul 28, 2013 at 01:08:13PM +0200, Andreas Färber wrote:
> Am 28.07.2013 12:31, schrieb Andreas Färber:
> > Am 28.07.2013 12:14, schrieb Michael S. Tsirkin:
> >> On Sun, Jul 28, 2013 at 11:38:17AM +0200, Andreas Färber wrote:
> >>> Am 28.07.2013 09:30, schrieb Michael S. Tsirkin:
> >>>> On Sun, Jul 28, 2013 at 02:12:49AM +0200, Andreas Färber wrote:
> >>>>> Am 25.07.2013 11:32, schrieb Michael S. Tsirkin:
> >>>>>> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> >>>>>> index 3908860..daefdfb 100644
> >>>>>> --- a/hw/pci-host/piix.c
> >>>>>> +++ b/hw/pci-host/piix.c
> >>>>>> @@ -349,6 +349,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
> >>>>>> return b;
> >>>>>> }
> >>>>>>
> >>>>>> +PCIBus *find_i440fx(void)
> >>>>>> +{
> >>>>>> + PCIHostState *s = OBJECT_CHECK(PCIHostState,
> >>>>>> + object_resolve_path("/machine/i440fx", NULL),
> >>>>>> + TYPE_PCI_HOST_BRIDGE);
> >>>>>
> >>>>> Open-coded OBJECT_CHECK() - should use existing PCI_HOST_BRIDGE(...).
> >>>>>
> >>>>>> + return s ? s->bus : NULL;
> >>>>>> +}
> >>>>>
> >>>>> Is this function really necessary? /machine/i440fx/pci.0 is a trivial
> >>>>> addition to the path that's already being used here. You can do:
> >>>>> PCIBus *bus = PCI_BUS(object_resolve_path("/machine/i440fx/pci.0"));
> >>>>> where you actually need to access it.
> >>>>
> >>>>
> >>>> I don't mind but I would like to avoid callers hard-coding
> >>>> paths, in this case "i440fx".
> >>>> Why the aversion to functions?
> >>>
> >>> Simply because QMP cannot call functions. It has to work with qom-list
> >>> and qom-get, so this is a test case showing what is missing and can IMO
> >>> easily be addressed for both parties.
> >>
> >> Fine but if the function calls QOM things internally
> >> then where's the problem?
> >
> > The grief with object_path_resolve_type() is that it's a "hack" Paolo
> > has added for his convenience (in audio code?) that QMP cannot use, so
> > we need name-based paths to be available.
>
> Add to that, the way I see QOM devices (as opposed to qdev or pre-qdev
> devices) is that they are instantiated from the outside - a different
> source file or command line or config file - via QOM APIs, and they
> allow other source files to interact with them via mydev_foo(MyDev *d,
> ...) APIs that operate on an instance.
>
> Having functions to create devices often hints at legacy code from
> pre-qdev times (we had such a discussion with Alex when I tried to
> qdev'ify the prep_pci device), indicating that either something is not
> yet accessible via qdev/QOM APIs (e.g., IRQs) or that the device is not
> yet implementing composition properly (e.g., creating a bus after the
> bridge device rather than in the bridge, or a PCIDevice after the PHB
> rather than by the PHB).
>
> Having functions in the device's file to obtain a random instance of
> that device in the form MyDev *mydev_get(void) is what I dislike here.
Absolutely but what would you do?
E.g. we can't handle more than one instance of PIIX ATM.
> My personal preference (which you may ignore if others disagree) would
> be to have accessors, where unavoidable, in the form:
>
> foo mydev_get_bar(MyDev *s)
> {
> return s->baz;
> }
So how about
implementing mydev_get_bar(void) and make that do the lookup
internally using a path?
Also mydev_present to test that.
>
> which we can then later easily convert into dynamic property getters,
> and it would hopefully spare us new per-device ...Info structs by
> obtaining the info where and when you need it.
> I admit it's a bit of boilerplate to code, but I've seen at most 4 cases
> per device where this would apply and I'm saying this with our
> longer-term QOM goals in mind.
>
> I'm skeptical towards Igor's suggestion of adding Last Minute 1.6 qdev
> properties (as opposed to a composition property, you force me to become
> very explicit in my explanations...) as that would bring ABI stability
> rules onto us.
>
> Andreas
>
> > And to clarify, I have been talking about two different time frames:
> > Small adjustments that you can make for 1.6 (e.g., casts, q35 property,
> > different QOM function/callsite used; if Anthony is okay with taking
> > ACPI at this late point) and post-1.6 cleanups to replace interim
> > constructs that involve refactorings outside your control (e.g.,
> > MemoryRegion QOM'ification, adding properties to random devices).
> >
> > Andreas
> >
> >>> The suggested cast to PCI_BUS() lets you use regular qdev functions btw
> >>> as a shortcut, QMP users would need to iterate children of that node.
> >>>
> >>> The suggested "pci.0" is considered stable for -device ...,bus=pci.0
> >>> according to review feedback the Xen people have received for libxl.
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
` (14 preceding siblings ...)
2013-07-25 15:50 ` [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Andreas Färber
@ 2013-07-29 15:27 ` Anthony Liguori
15 siblings, 0 replies; 69+ messages in thread
From: Anthony Liguori @ 2013-07-29 15:27 UTC (permalink / raw)
To: Michael S. Tsirkin, qemu-devel
"Michael S. Tsirkin" <mst@redhat.com> writes:
> This code can also be found here:
> git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi
>
> Please review, and consider for 1.6.
This isn't ready for 1.6 so it's going to have to wait for 1.7.
Regards,
Anthony Liguori
>
> Changes from v2 repost:
> - address comment by Anthony - convert to use APIs implemented
> using QOM
> - address comment by Anthony - avoid tricky pointer path,
> use GArray from glib instead
> - Address lots of comments by Hu Tao and Laszlo Ersek
> - rebase to latest bits
>
> Changes from v2:
> - added missing patches to make it actually build
> Changes from v1 RFC:
> - added code to address cross version compatibility
> - rebased to latest bits
> - updated seabios code to latest bits (added pvpanic device)
>
> This patchset moves all generation of ACPI tables
> from guest BIOS to the hypervisor.
>
> Although ACPI tables come from a system BIOS on real hw,
> it makes sense that the ACPI tables are coupled with the
> virtual machine, since they have to abstract the x86 machine to
> the OS's.
>
> This is widely desired as a way to avoid the churn
> and proliferation of QEMU-specific interfaces
> associated with ACPI tables in bios code.
>
> There's a bit of code duplication where we
> already declare similar acpi structures in qemu.
>
> I think it's best to do it in this order: port
> code directly, and apply cleanups and reduce duplication
> that results, on top.
> This way it's much easier to see that we don't introduce
> regressions.
>
> In particular, I booted a guest on qemu with and without the
> change, and verified that ACPI tables are
> unchanged except for trivial pointer address changes.
>
> Such binary compatibility makes it easier to be
> confident that this change won't break things.
>
> Michael S. Tsirkin (14):
> hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h
> i386: add ACPI table files from seabios
> acpi: add rules to compile ASL source
> acpi: pre-compiled ASL files
> loader: use file path size from fw_cfg.h
> i386: add bios linker/loader
> loader: support for unmapped ROM blobs
> loader: allow adding ROMs in done callbacks
> i386: define pc guest info
> ich9: APIs for pc guest info
> piix: APIs for pc guest info
> pvpanic: add API to access io port
> hpet: add API to find it
> i386: ACPI table generation code from seabios
>
> configure | 9 +-
> hw/acpi/ich9.c | 6 +
> hw/acpi/piix4.c | 29 +-
> hw/core/loader.c | 40 +-
> hw/i386/Makefile.objs | 27 +
> hw/i386/acpi-build.c | 907 +++++
> hw/i386/acpi-defs.h | 327 ++
> hw/i386/acpi-dsdt-cpu-hotplug.dsl | 93 +
> hw/i386/acpi-dsdt-dbug.dsl | 41 +
> hw/i386/acpi-dsdt-hpet.dsl | 51 +
> hw/i386/acpi-dsdt-isa.dsl | 117 +
> hw/i386/acpi-dsdt-pci-crs.dsl | 105 +
> hw/i386/acpi-dsdt.dsl | 343 ++
> hw/i386/acpi-dsdt.hex.generated | 4409 ++++++++++++++++++++
> hw/i386/bios-linker-loader.c | 156 +
> hw/i386/pc.c | 37 +-
> hw/i386/pc_piix.c | 5 +
> hw/i386/pc_q35.c | 3 +
> hw/i386/q35-acpi-dsdt.dsl | 452 +++
> hw/i386/q35-acpi-dsdt.hex.generated | 7346 ++++++++++++++++++++++++++++++++++
> hw/i386/ssdt-misc.dsl | 119 +
> hw/i386/ssdt-misc.hex.generated | 190 +
> hw/i386/ssdt-pcihp.dsl | 51 +
> hw/i386/ssdt-pcihp.hex.generated | 108 +
> hw/i386/ssdt-proc.dsl | 63 +
> hw/i386/ssdt-proc.hex.generated | 134 +
> hw/isa/lpc_ich9.c | 19 +
> hw/lm32/lm32_hwsetup.h | 2 +-
> hw/mips/mips_malta.c | 2 +-
> hw/misc/pvpanic.c | 11 +
> hw/pci-host/piix.c | 8 +
> hw/pci-host/q35.c | 10 +
> hw/timer/hpet.c | 5 +
> include/hw/acpi/ich9.h | 2 +
> include/hw/i386/acpi-build.h | 9 +
> include/hw/i386/apic.h | 2 +
> include/hw/i386/bios-linker-loader.h | 26 +
> include/hw/i386/ich9.h | 3 +
> include/hw/i386/pc.h | 34 +
> include/hw/loader.h | 5 +-
> include/hw/nvram/fw_cfg.h | 4 +-
> include/hw/pci-host/q35.h | 2 +
> include/hw/timer/hpet.h | 2 +
> include/qemu/typedefs.h | 2 +
> scripts/acpi_extract.py | 362 ++
> scripts/acpi_extract_preprocess.py | 51 +
> scripts/update-acpi.sh | 4 +
> vl.c | 3 +
> 48 files changed, 15721 insertions(+), 15 deletions(-)
> create mode 100644 hw/i386/acpi-build.c
> create mode 100644 hw/i386/acpi-defs.h
> create mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl
> create mode 100644 hw/i386/acpi-dsdt-dbug.dsl
> create mode 100644 hw/i386/acpi-dsdt-hpet.dsl
> create mode 100644 hw/i386/acpi-dsdt-isa.dsl
> create mode 100644 hw/i386/acpi-dsdt-pci-crs.dsl
> create mode 100644 hw/i386/acpi-dsdt.dsl
> create mode 100644 hw/i386/acpi-dsdt.hex.generated
> create mode 100644 hw/i386/bios-linker-loader.c
> create mode 100644 hw/i386/q35-acpi-dsdt.dsl
> create mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
> create mode 100644 hw/i386/ssdt-misc.dsl
> create mode 100644 hw/i386/ssdt-misc.hex.generated
> create mode 100644 hw/i386/ssdt-pcihp.dsl
> create mode 100644 hw/i386/ssdt-pcihp.hex.generated
> create mode 100644 hw/i386/ssdt-proc.dsl
> create mode 100644 hw/i386/ssdt-proc.hex.generated
> create mode 100644 include/hw/i386/acpi-build.h
> create mode 100644 include/hw/i386/bios-linker-loader.h
> create mode 100755 scripts/acpi_extract.py
> create mode 100755 scripts/acpi_extract_preprocess.py
> create mode 100644 scripts/update-acpi.sh
>
> --
> MST
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest
2013-07-27 23:22 ` Andreas Färber
@ 2013-09-11 9:57 ` Michael S. Tsirkin
0 siblings, 0 replies; 69+ messages in thread
From: Michael S. Tsirkin @ 2013-09-11 9:57 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Anthony Liguori
On Sun, Jul 28, 2013 at 01:22:57AM +0200, Andreas Färber wrote:
> Am 26.07.2013 14:19, schrieb Andreas Färber:
> > Am 25.07.2013 18:19, schrieb Michael S. Tsirkin:
> >> On Thu, Jul 25, 2013 at 05:50:55PM +0200, Andreas Färber wrote:
> >>> Am 24.07.2013 18:01, schrieb Michael S. Tsirkin:
> >>>> This code can also be found here:
> >>>> git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi
> >>>>
> >>>> Please review, and consider for 1.6.
> >>>
> >>> Quite frankly, this is still not looking the way I imagined it based on
> >>> the KVM call discussion and Anthony's comments that I remember:
> >>>
> >>> I believe Anthony asked to extract the information from the QOM tree,
> >>> originally from the SeaBIOS side, then later agreeing to do it on the
> >>> QEMU side.
> >>>
> >>> However here I am still seeing *functions* added in device code to check
> >>> device existence and to extract individual fields. I was assuming (and
> >>> clearly prefer) such code to live in a central place, be it acpi-build.c
> >>> or something else, and to use QOM *API*s to obtain information when
> >>> needed rather than building up lots of new structs duplicating that
> >>> data. That would at the same time be a test case for how useful the QOM
> >>> tree is
> >>>
> >>> I'm not sure if there was a misunderstanding or whether the PC QOM model
> >>> still sucks^W is incomplete? Anthony and Ping Fang(?) had both posted
> >>> patches to improve the composition tree once. If there's properties
> >>> missing that you need to access for ACPI, we should simply add them.
> >>> For i440fx we have /machine/i440fx.
> >>> For q35 I encountered an mch child on q35-pcihost, but what's trivially
> >>> missing apparently is to add q35-pcihost as a child to /machine, e.g.
> >>> /machine/q35.
> >>> Then you'll end up doing
> >>> Object *obj = object_resolve_path_component(qdev_get_machine(), "q35/mch");
> >>> object_property_get_int(obj, "foo", &err);
> >>> object_property_get_string(obj, "bar", &err);
> >>> and so on. No need to do the TYPE_... based search for everything.
> >>>
> >>> User-added -devices will show up in /machine/peripheral or
> >>> /machine/peripheral-anon depending on whether id= is used, so there a
> >>> type-based search probably makes sense. And there is nothing wrong with
> >>> moving the TYPE_* constants to a device header where not yet the case,
> >>> to allow that from generic code.
> >>>
> >>> Similarly, please don't open-code OBJECT_CHECK()s, do a trivial patch
> >>> with a macro that we can then reuse elsewhere. I'd be happy to review
> >>> such QOM patches and help fast-track them into master.
> >>>
> >>> Will take a closer look at the implementation later.
> >>
> >> This is not my understanding of previous comments on list
> >> or on KVM call.
> >>
> >> Basically it sounds like you want to make my work depend on completion
> >> of QOM conversion.
> >> I think we explicitly agreed full QOM convertion is not a blocker.
> >
> > Not sure what you mean with "completion of QOM conversion" or "full QOM
> > conversion". What I am saying is that instead of spending time adding
> > functions to devices that fulfill your own ACPI needs only, that time
> > were better spent adding QOM properties where not yet existent.
> >
> > Because then what you can access for ACPI can also be accessed by
> > libvirt and other management tools as well as qtest - I consider it a
> > test case. QMP does not offer an instance/path search by type.
>
> To clarify for everyone what we're talking about here, I'm attaching
> /machine composition tree dumps for pc,accel=kvm and q35,accel=kvm plus
> the rudimentary script I used to generate it.
>
> It shows for instance the mentioned /machine/i440fx and lack of
> /machine/q35. It also shows that there would be a /machine/fw_cfg.
>
> Paths starting with /machine/unassigned shouldn't be hardcoded anywhere
> (that's the nobody-added-it-as-a-child<> bucket), except maybe for
> /machine/unassigned/sysbus. But whenever there's a link from a named
> device to a /machine/unassigned/device[n] that may of course be used
> dynamically, e.g. /machine/icc-bridge/icc to discover CPUs and APICs.
>
> HTH,
> Andreas
So q35 is all "unassigned".
I assume it's fine to use APIs for that, then?
--
MST
^ permalink raw reply [flat|nested] 69+ messages in thread
end of thread, other threads:[~2013-09-11 9:55 UTC | newest]
Thread overview: 69+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-07-24 16:01 [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 01/14] hw/i386/pc.c: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/apic.h Michael S. Tsirkin
2013-07-25 12:05 ` Gerd Hoffmann
2013-07-28 0:44 ` Andreas Färber
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 02/14] i386: add ACPI table files from seabios Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 03/14] acpi: add rules to compile ASL source Michael S. Tsirkin
2013-07-25 12:09 ` Gerd Hoffmann
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 04/14] acpi: pre-compiled ASL files Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 05/14] loader: use file path size from fw_cfg.h Michael S. Tsirkin
2013-07-24 23:42 ` Andreas Färber
2013-07-25 12:10 ` Gerd Hoffmann
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 06/14] i386: add bios linker/loader Michael S. Tsirkin
2013-07-25 12:11 ` Gerd Hoffmann
2013-07-26 9:42 ` Gerd Hoffmann
2013-07-28 8:08 ` Michael S. Tsirkin
2013-07-24 16:01 ` [Qemu-devel] [PATCH v3 07/14] loader: support for unmapped ROM blobs Michael S. Tsirkin
2013-07-25 12:14 ` Gerd Hoffmann
2013-07-25 12:28 ` Michael S. Tsirkin
2013-07-25 12:43 ` Gerd Hoffmann
2013-07-25 13:03 ` Michael S. Tsirkin
2013-07-25 19:57 ` Michael S. Tsirkin
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 08/14] loader: allow adding ROMs in done callbacks Michael S. Tsirkin
2013-07-25 12:15 ` Gerd Hoffmann
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 09/14] i386: define pc guest info Michael S. Tsirkin
2013-07-25 12:31 ` Gerd Hoffmann
2013-07-28 0:41 ` Andreas Färber
2013-07-28 7:36 ` Michael S. Tsirkin
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 10/14] ich9: APIs for " Michael S. Tsirkin
2013-07-25 12:33 ` Gerd Hoffmann
2013-07-28 0:37 ` Andreas Färber
2013-07-28 7:35 ` Michael S. Tsirkin
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 11/14] piix: " Michael S. Tsirkin
2013-07-25 9:32 ` Michael S. Tsirkin
2013-07-28 0:12 ` Andreas Färber
2013-07-28 7:30 ` Michael S. Tsirkin
2013-07-28 9:38 ` Andreas Färber
2013-07-28 10:14 ` Michael S. Tsirkin
2013-07-28 10:31 ` Andreas Färber
2013-07-28 11:08 ` Andreas Färber
2013-07-28 12:19 ` Michael S. Tsirkin
2013-07-25 12:34 ` Gerd Hoffmann
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 12/14] pvpanic: add API to access io port Michael S. Tsirkin
2013-07-25 10:29 ` Gerd Hoffmann
2013-07-25 10:55 ` Michael S. Tsirkin
2013-07-25 10:58 ` Michael S. Tsirkin
2013-07-25 11:05 ` Gerd Hoffmann
2013-07-25 11:22 ` Michael S. Tsirkin
2013-07-25 12:03 ` Gerd Hoffmann
2013-07-25 12:23 ` Michael S. Tsirkin
2013-07-27 23:58 ` Andreas Färber
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 13/14] hpet: add API to find it Michael S. Tsirkin
2013-07-25 12:36 ` Gerd Hoffmann
2013-07-27 23:38 ` Andreas Färber
2013-07-24 16:02 ` [Qemu-devel] [PATCH v3 14/14] i386: ACPI table generation code from seabios Michael S. Tsirkin
2013-07-25 13:06 ` Gerd Hoffmann
2013-07-25 13:23 ` Michael S. Tsirkin
2013-07-25 14:58 ` Gerd Hoffmann
2013-07-25 15:14 ` Michael S. Tsirkin
2013-07-26 9:06 ` Gerd Hoffmann
2013-07-26 15:30 ` Gerd Hoffmann
2013-07-28 7:00 ` Michael S. Tsirkin
2013-07-25 15:50 ` [Qemu-devel] [PATCH v3 00/14] qemu: generate acpi tables for the guest Andreas Färber
2013-07-25 16:19 ` Michael S. Tsirkin
2013-07-26 12:19 ` Andreas Färber
2013-07-27 23:22 ` Andreas Färber
2013-09-11 9:57 ` Michael S. Tsirkin
2013-07-25 17:18 ` Michael S. Tsirkin
2013-07-26 12:25 ` Andreas Färber
2013-07-29 15:27 ` Anthony Liguori
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