[RFC 0/2] DWC3 USB support for Qualcomm platform

[RFC 0/2] DWC3 USB support for Qualcomm platform

[Ivan T. Ivanov]

From: "Ivan T. Ivanov" <iivanov@mm-sol.com>

Hi, 

These patches add basic support for USB3.0 controllers found on
MSM platforms. First patch add 2 USB PHY drivers and second one
add support for Qualcomm wrapper IP over DWC3 controller. Patches 
are just skeletons, no power management. 

DWC3 IP in MSM also support OTG but right now I am not sure how to
add support for it. Probably OTG have to be instantiated from core 
dwc3 driver, but usually PHY drivers are those which create OTG
instance.

Generated on top of Felipe 'testing' branch.

Regards,
Ivan

Ivan T. Ivanov (2):
  usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
  usb: dwc3: Add Qualcomm DWC3 glue layer driver

 .../devicetree/bindings/usb/msm-ssusb.txt          |   88 +++++
 drivers/usb/dwc3/Kconfig                           |    8 +
 drivers/usb/dwc3/Makefile                          |    1 +
 drivers/usb/dwc3/dwc3-msm.c                        |  175 +++++++++
 drivers/usb/phy/Kconfig                            |   11 +
 drivers/usb/phy/Makefile                           |    2 +
 drivers/usb/phy/phy-msm-dwc3-usb2.c                |  342 +++++++++++++++++
 drivers/usb/phy/phy-msm-dwc3-usb3.c                |  389 ++++++++++++++++++++
 8 files changed, 1016 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
 create mode 100644 drivers/usb/dwc3/dwc3-msm.c
 create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
 create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c

-- 
1.7.9.5

[RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core

[Ivan T. Ivanov]

From: "Ivan T. Ivanov" <iivanov@mm-sol.com>

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
---
 .../devicetree/bindings/usb/msm-ssusb.txt          |   49 +++
 drivers/usb/phy/Kconfig                            |   11 +
 drivers/usb/phy/Makefile                           |    2 +
 drivers/usb/phy/phy-msm-dwc3-usb2.c                |  342 +++++++++++++++++
 drivers/usb/phy/phy-msm-dwc3-usb3.c                |  389 ++++++++++++++++++++
 5 files changed, 793 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
 create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
 create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c

diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
new file mode 100644
index 0000000..550b496
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -0,0 +1,49 @@
+MSM SuperSpeed USB3.0 SoC controllers
+
+Required properities :
+- compatible sould be "qcom,dwc3-usb2";
+- reg : offset and length of the register set in the memory map
+- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
+- clock-names: "xo", "sleep_a_clk";
+<supply-name>-supply: phandle to the regulator device tree node
+Required "supply-name" examples are:
+	"v1p8" : 1.8v supply for HSPHY
+	"v3p3" : 3.3v supply for HSPHY
+	"vbus" : vbus supply for host mode
+	"vddcx" : vdd supply for HS-PHY digital circuit operation
+
+Required properities :
+- compatible sould be "qcom,dwc3-usb3";
+- reg : offset and length of the register set in the memory map
+- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
+- clock-names: "xo", "ref_clk";
+<supply-name>-supply: phandle to the regulator device tree node
+Required "supply-name" examples are:
+	"v1p8" : 1.8v supply for SS-PHY
+	"vddcx" : vdd supply for SS-PHY digital circuit operation
+
+Example device nodes:
+
+	dwc3_usb2: phy@f92f8800 {
+		compatible = "qcom,dwc3-usb2";
+		reg = <0xf92f8800 0x30>;
+
+		clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
+		clock-names = "xo", "sleep_a_clk";
+
+		vbus-supply = <&supply>;
+		vddcx-supply = <&supply>;
+		v1p8-supply = <&supply>;
+		v3p3-supply = <&supply>;
+	};
+
+	dwc3_usb3: phy@f92f8830 {
+		compatible = "qcom,dwc3-usb3";
+		reg = <0xf92f8830 0x30>;
+
+		clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
+		clock-names = "xo", "ref_clk";
+
+		vddcx-supply = <&supply>;
+		v1p8-supply = <&supply>;
+	};
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 5443958..40e83b5 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -202,6 +202,17 @@ config USB_RCAR_PHY
 	  To compile this driver as a module, choose M here: the
 	  module will be called phy-rcar-usb.
 
+config USB_MSM_DWC3_PHYS
+	tristate "Qualcomm DWC3 USB controller PHY's support"
+	depends on (USB || USB_GADGET) && ARCH_MSM
+	select USB_PHY
+	help
+	  Enable this to support the USB PHY transceivers on MSM chips with
+	  DWC3 USB core. It handles PHY initialization, clock management
+	  required after resetting the hardware and power management.
+	  This driver is required even for peripheral only or host only
+	  mode configurations.
+
 config USB_ULPI
 	bool "Generic ULPI Transceiver Driver"
 	depends on ARM
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 98730ca..53355ec 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -24,6 +24,8 @@ obj-$(CONFIG_USB_EHCI_TEGRA)		+= phy-tegra-usb.o
 obj-$(CONFIG_USB_GPIO_VBUS)		+= phy-gpio-vbus-usb.o
 obj-$(CONFIG_USB_ISP1301)		+= phy-isp1301.o
 obj-$(CONFIG_USB_MSM_OTG)		+= phy-msm-usb.o
+obj-$(CONFIG_USB_MSM_DWC3_PHYS)		+= phy-msm-dwc3-usb2.o
+obj-$(CONFIG_USB_MSM_DWC3_PHYS)		+= phy-msm-dwc3-usb3.o
 obj-$(CONFIG_USB_MV_OTG)		+= phy-mv-usb.o
 obj-$(CONFIG_USB_MXS_PHY)		+= phy-mxs-usb.o
 obj-$(CONFIG_USB_RCAR_PHY)		+= phy-rcar-usb.o
diff --git a/drivers/usb/phy/phy-msm-dwc3-usb2.c b/drivers/usb/phy/phy-msm-dwc3-usb2.c
new file mode 100644
index 0000000..174c72c
--- /dev/null
+++ b/drivers/usb/phy/phy-msm-dwc3-usb2.c
@@ -0,0 +1,342 @@
+/* Copyright (c) 2013, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#undef CONFIG_REGULATOR
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/phy.h>
+
+/**
+ *  USB QSCRATCH Hardware registers
+ */
+#define QSCRATCH_CTRL_REG		(0x04)
+#define QSCRATCH_GENERAL_CFG		(0x08)
+#define PHY_CTRL_REG			(0x10)
+#define PARAMETER_OVERRIDE_X_REG	(0x14)
+#define CHARGING_DET_CTRL_REG		(0x18)
+#define CHARGING_DET_OUTPUT_REG		(0x1c)
+#define ALT_INTERRUPT_EN_REG		(0x20)
+#define PHY_IRQ_STAT_REG		(0x24)
+#define CGCTL_REG			(0x28)
+
+#define PHY_3P3_VOL_MIN			3050000 /* uV */
+#define PHY_3P3_VOL_MAX			3300000 /* uV */
+#define PHY_3P3_HPM_LOAD		16000	/* uA */
+
+#define PHY_1P8_VOL_MIN			1800000 /* uV */
+#define PHY_1P8_VOL_MAX			1800000 /* uV */
+#define PHY_1P8_HPM_LOAD		19000	/* uA */
+
+/* TODO: these are suspicious */
+#define USB_VDDCX_NO			1	/* uV */
+#define USB_VDDCX_MIN			5	/* uV */
+#define USB_VDDCX_MAX			7	/* uV */
+
+struct msm_dwc3_usb2_phy {
+	struct usb_phy		phy;
+	void __iomem		*base;
+	struct device		*dev;
+
+	struct clk		*xo_clk;
+	struct clk		*sleep_a_clk;
+
+	struct regulator	*v3p3;
+	struct regulator	*v1p8;
+	struct regulator	*vddcx;
+	struct regulator	*vbus;
+};
+
+#define	phy_to_dwc3_phy(x)	container_of((x), struct msm_dwc3_usb2_phy, phy)
+
+
+/**
+ *
+ * Write register with debug info.
+ *
+ * @base - DWC3 base virtual address.
+ * @offset - register offset.
+ * @val - value to write.
+ *
+ */
+static inline void msm_dwc3_usb2_write(void *base, u32 offset, u32 val)
+{
+	iowrite32(val, base + offset);
+}
+
+/**
+ * Write register and read back masked value to confirm it is written
+ *
+ * @base - DWC3 base virtual address.
+ * @offset - register offset.
+ * @mask - register bitmask specifying what should be updated
+ * @val - value to write.
+ *
+ */
+static inline void msm_dwc3_usb2_write_readback(void *base, u32 offset,
+					    const u32 mask, u32 val)
+{
+	u32 write_val, tmp = ioread32(base + offset);
+
+	tmp &= ~mask;		/* retain other bits */
+	write_val = tmp | val;
+
+	iowrite32(write_val, base + offset);
+
+	/* Read back to see if val was written */
+	tmp = ioread32(base + offset);
+	tmp &= mask;		/* clear other bits */
+
+	if (tmp != val)
+		pr_err("write: %x to QSCRATCH: %x FAILED\n", val, offset);
+}
+
+static void msm_dwc3_usb2_phy_shutdown(struct usb_phy *x)
+{
+	struct msm_dwc3_usb2_phy *phy = phy_to_dwc3_phy(x);
+	int ret;
+
+	ret = regulator_set_voltage(phy->v3p3, 0, PHY_3P3_VOL_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set voltage for v3p3\n");
+
+	ret = regulator_set_voltage(phy->v1p8, 0, PHY_1P8_VOL_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set voltage for v1p8\n");
+
+	ret = regulator_disable(phy->v1p8);
+	if (ret)
+		dev_err(phy->dev, "cannot disable v1p8\n");
+
+	ret = regulator_disable(phy->v3p3);
+	if (ret)
+		dev_err(phy->dev, "cannot disable v3p3\n");
+
+	ret = regulator_set_voltage(phy->vddcx, USB_VDDCX_NO, USB_VDDCX_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set voltage for vddcx\n");
+
+	ret = regulator_disable(phy->vddcx);
+	if (ret)
+		dev_err(phy->dev, "unable to enable the vddcx\n");
+
+	clk_disable_unprepare(phy->sleep_a_clk);
+}
+
+static int msm_dwc3_usb2_phy_init(struct usb_phy *x)
+{
+	struct msm_dwc3_usb2_phy	*phy = phy_to_dwc3_phy(x);
+	int ret;
+
+	clk_prepare_enable(phy->sleep_a_clk);
+
+	ret = regulator_set_voltage(phy->vddcx, USB_VDDCX_MIN, USB_VDDCX_MAX);
+	if (ret) {
+		dev_err(phy->dev, "unable to set voltage for vddcx\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->vddcx);
+	if (ret) {
+		dev_err(phy->dev, "unable to enable the vddcx\n");
+		return ret;
+	}
+
+	ret = regulator_set_voltage(phy->v3p3, PHY_3P3_VOL_MIN,
+				    PHY_3P3_VOL_MAX);
+	if (ret) {
+		dev_err(phy->dev, "unable to set voltage for v3p3\n");
+		return ret;
+	}
+
+	ret = regulator_set_voltage(phy->v1p8, PHY_1P8_VOL_MIN,
+				    PHY_1P8_VOL_MAX);
+	if (ret) {
+		dev_err(phy->dev, "unable to set voltage for v1p8\n");
+		return ret;
+	}
+
+	ret = regulator_set_optimum_mode(phy->v1p8, PHY_1P8_HPM_LOAD);
+	if (ret < 0) {
+		dev_err(phy->dev, "unable to set HPM of regulator v1p8\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->v1p8);
+	if (ret) {
+		dev_err(phy->dev, "unable to enable v1p8\n");
+		return ret;
+	}
+
+	ret = regulator_set_optimum_mode(phy->v3p3, PHY_3P3_HPM_LOAD);
+	if (ret < 0) {
+		dev_err(phy->dev, "unable to set HPM of regulator v3p3\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->v3p3);
+	if (ret) {
+		dev_err(phy->dev, "unable to enable v3p3\n");
+		return ret;
+	}
+
+	/*
+	 * HSPHY Initialization: Enable UTMI clock and clamp enable HVINTs,
+	 * and disable RETENTION (power-on default is ENABLED)
+	 */
+	msm_dwc3_usb2_write(phy->base, PHY_CTRL_REG, 0x5220bb2);
+	usleep_range(2000, 2200);
+
+	/*
+	 * write HSPHY init value to QSCRATCH reg to set HSPHY parameters like
+	 * VBUS valid threshold, disconnect valid threshold, DC voltage level,
+	 * preempasis and rise/fall time.
+	 */
+	msm_dwc3_usb2_write_readback(phy->base, PARAMETER_OVERRIDE_X_REG,
+				0x03ffffff, 0x00d191a4);
+
+	/* Disable (bypass) VBUS and ID filters */
+	msm_dwc3_usb2_write(phy->base, QSCRATCH_GENERAL_CFG, 0x78);
+
+	return 0;
+}
+
+static int msm_dwc3_usb2_phy_set_vbus(struct usb_phy *x, int on)
+{
+	struct msm_dwc3_usb2_phy	*phy = phy_to_dwc3_phy(x);
+	int ret;
+
+	if (on)
+		ret = regulator_enable(phy->vbus);
+	else
+		ret = regulator_disable(phy->vbus);
+
+	if (ret)
+		dev_err(x->dev, "Cannot %s Vbus\n", on ? "set" : "off");
+	return ret;
+}
+
+static int msm_dwc3_usb2_probe(struct platform_device *pdev)
+{
+	struct msm_dwc3_usb2_phy	*phy;
+	struct resource			*res;
+	void __iomem			*base;
+
+	dev_info(&pdev->dev, "MSM DWC3 HS-PHY\n");
+
+	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy) {
+		dev_err(&pdev->dev, "no alloc mem for MSM DWC3 HS-PHY\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, phy);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	phy->vddcx = devm_regulator_get(&pdev->dev, "vddcx");
+	if (IS_ERR(phy->vddcx)) {
+		dev_err(&pdev->dev, "unable to get vddcx\n");
+		return  PTR_ERR(phy->vddcx);
+	}
+
+	phy->v3p3 = devm_regulator_get(phy->dev, "v3p3");
+	if (IS_ERR(phy->v3p3)) {
+		dev_err(phy->dev, "unable to get v3p3\n");
+		return PTR_ERR(phy->v3p3);
+	}
+
+	phy->v1p8 = devm_regulator_get(phy->dev, "v1p8");
+	if (IS_ERR(phy->v1p8)) {
+		dev_err(phy->dev, "unable to get v1p8\n");
+		return PTR_ERR(phy->v1p8);
+	}
+
+	phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
+	if (IS_ERR(phy->vbus)) {
+		dev_err(phy->dev, "Failed to get vbus\n");
+		return PTR_ERR(phy->vbus);
+	}
+
+	phy->xo_clk = devm_clk_get(&pdev->dev, "xo");
+	if (IS_ERR(phy->xo_clk)) {
+		dev_err(&pdev->dev, "unable to get TCXO buffer handle\n");
+		return PTR_ERR(phy->xo_clk);
+	}
+
+	phy->sleep_a_clk = devm_clk_get(&pdev->dev, "sleep_a_clk");
+	if (IS_ERR(phy->sleep_a_clk)) {
+		dev_err(&pdev->dev, "failed to get sleep_a_clk\n");
+		return PTR_ERR(phy->sleep_a_clk);
+	}
+
+	clk_prepare_enable(phy->xo_clk);
+
+	phy->dev		= &pdev->dev;
+	phy->base		= base;
+	phy->phy.dev		= phy->dev;
+	phy->phy.label		= "msm-dwc3-usb2";
+	phy->phy.init		= msm_dwc3_usb2_phy_init;
+	phy->phy.shutdown	= msm_dwc3_usb2_phy_shutdown;
+	phy->phy.set_vbus	= msm_dwc3_usb2_phy_set_vbus;
+	phy->phy.type		= USB_PHY_TYPE_USB2;
+	phy->phy.state          = OTG_STATE_UNDEFINED;
+
+	usb_add_phy_dev(&phy->phy);
+
+	return 0;
+}
+
+static int msm_dwc3_usb2_remove(struct platform_device *pdev)
+{
+	struct msm_dwc3_usb2_phy *phy = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(phy->xo_clk);
+	usb_remove_phy(&phy->phy);
+	return 0;
+}
+
+static const struct of_device_id msm_dwc3_usb2_id_table[] = {
+	{ .compatible = "qcom,dwc3-usb2" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, msm_dwc3_usb2_id_table);
+
+static struct platform_driver msm_dwc3_usb2_driver = {
+	.probe		= msm_dwc3_usb2_probe,
+	.remove		= msm_dwc3_usb2_remove,
+	.driver		= {
+		.name	= "msm-dwc3-usb2",
+		.owner	= THIS_MODULE,
+		.of_match_table = msm_dwc3_usb2_id_table,
+	},
+};
+
+module_platform_driver(msm_dwc3_usb2_driver);
+
+MODULE_ALIAS("platform:msm_dwc3_usb2");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 MSM HS-PHY driver");
diff --git a/drivers/usb/phy/phy-msm-dwc3-usb3.c b/drivers/usb/phy/phy-msm-dwc3-usb3.c
new file mode 100644
index 0000000..f7bafff
--- /dev/null
+++ b/drivers/usb/phy/phy-msm-dwc3-usb3.c
@@ -0,0 +1,389 @@
+/* Copyright (c) 2013, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#undef CONFIG_REGULATOR
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/phy.h>
+
+/**
+ *  USB QSCRATCH Hardware registers
+ */
+#define PHY_CTRL_REG			(0x00)
+#define PHY_PARAM_CTRL_1		(0x04)
+#define PHY_PARAM_CTRL_2		(0x08)
+#define CR_PROTOCOL_DATA_IN_REG		(0x0c)
+#define CR_PROTOCOL_DATA_OUT_REG	(0x10)
+#define CR_PROTOCOL_CAP_ADDR_REG	(0x14)
+#define CR_PROTOCOL_CAP_DATA_REG	(0x18)
+#define CR_PROTOCOL_READ_REG		(0x1c)
+#define CR_PROTOCOL_WRITE_REG		(0x20)
+
+#define PHY_1P8_VOL_MIN			1800000 /* uV */
+#define PHY_1P8_VOL_MAX			1800000 /* uV */
+#define PHY_1P8_HPM_LOAD		23000	/* uA */
+
+/* TODO: these are suspicious */
+#define USB_VDDCX_NO			1	/* uV */
+#define USB_VDDCX_MIN			5	/* uV */
+#define USB_VDDCX_MAX			7	/* uV */
+
+struct msm_dwc3_usb3_phy {
+	struct usb_phy		phy;
+	void __iomem		*base;
+	struct device		*dev;
+
+	struct regulator	*v1p8;
+	struct regulator	*vddcx;
+
+	struct clk		*xo_clk;
+	struct clk		*ref_clk;
+};
+
+#define	phy_to_dwc3_phy(x)	container_of((x), struct msm_dwc3_usb3_phy, phy)
+
+
+/**
+ *
+ * Write register with debug info.
+ *
+ * @base - DWC3 base virtual address.
+ * @offset - register offset.
+ * @val - value to write.
+ *
+ */
+static inline void msm_dwc3_usb3_write(void *base, u32 offset, u32 val)
+{
+	iowrite32(val, base + offset);
+}
+
+/**
+ * Write register and read back masked value to confirm it is written
+ *
+ * @base - DWC3 base virtual address.
+ * @offset - register offset.
+ * @mask - register bitmask specifying what should be updated
+ * @val - value to write.
+ *
+ */
+static inline void msm_dwc3_usb3_write_readback(void *base, u32 offset,
+					    const u32 mask, u32 val)
+{
+	u32 write_val, tmp = ioread32(base + offset);
+
+	tmp &= ~mask;		/* retain other bits */
+	write_val = tmp | val;
+
+	iowrite32(write_val, base + offset);
+
+	/* Read back to see if val was written */
+	tmp = ioread32(base + offset);
+	tmp &= mask;		/* clear other bits */
+
+	if (tmp != val)
+		pr_err("write: %x to QSCRATCH: %x FAILED\n", val, offset);
+}
+
+/**
+ *
+ * Write SSPHY register with debug info.
+ *
+ * @base - DWC3 base virtual address.
+ * @addr - SSPHY address to write.
+ * @val - value to write.
+ *
+ */
+static void msm_dwc3_usb3_write_phycreg(void *base, u32 addr, u32 val)
+{
+	iowrite32(addr, base + CR_PROTOCOL_DATA_IN_REG);
+	iowrite32(0x1, base + CR_PROTOCOL_CAP_ADDR_REG);
+	while (ioread32(base + CR_PROTOCOL_CAP_ADDR_REG))
+		cpu_relax();
+
+	iowrite32(val, base + CR_PROTOCOL_DATA_IN_REG);
+	iowrite32(0x1, base + CR_PROTOCOL_CAP_DATA_REG);
+	while (ioread32(base + CR_PROTOCOL_CAP_DATA_REG))
+		cpu_relax();
+
+	iowrite32(0x1, base + CR_PROTOCOL_WRITE_REG);
+	while (ioread32(base + CR_PROTOCOL_WRITE_REG))
+		cpu_relax();
+}
+
+/**
+ *
+ * Read SSPHY register with debug info.
+ *
+ * @base - DWC3 base virtual address.
+ * @addr - SSPHY address to read.
+ *
+ */
+static u32 msm_dwc3_usb3_read_phycreg(void *base, u32 addr)
+{
+	bool first_read = true;
+
+	iowrite32(addr, base + CR_PROTOCOL_DATA_IN_REG);
+	iowrite32(0x1, base + CR_PROTOCOL_CAP_ADDR_REG);
+	while (ioread32(base + CR_PROTOCOL_CAP_ADDR_REG))
+		cpu_relax();
+
+	/*
+	 * Due to hardware bug, first read of SSPHY register might be
+	 * incorrect. Hence as workaround, SW should perform SSPHY register
+	 * read twice, but use only second read and ignore first read.
+	 */
+retry:
+	iowrite32(0x1, base + CR_PROTOCOL_READ_REG);
+	while (ioread32(base + CR_PROTOCOL_READ_REG))
+		cpu_relax();
+
+	if (first_read) {
+		ioread32(base + CR_PROTOCOL_DATA_OUT_REG);
+		first_read = false;
+		goto retry;
+	}
+
+	return ioread32(base + CR_PROTOCOL_DATA_OUT_REG);
+}
+
+static void msm_dwc3_usb3_phy_shutdown(struct usb_phy *x)
+{
+	struct msm_dwc3_usb3_phy *phy = phy_to_dwc3_phy(x);
+	int ret;
+
+	/* Sequence to put SSPHY in low power state:
+	 * 1. Clear REF_PHY_EN in PHY_CTRL_REG
+	 * 2. Clear REF_USE_PAD in PHY_CTRL_REG
+	 * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
+	 * 4. Disable SSPHY ref clk
+	 */
+	msm_dwc3_usb3_write_readback(phy->base, PHY_CTRL_REG, (1 << 8), 0x0);
+	msm_dwc3_usb3_write_readback(phy->base, PHY_CTRL_REG, (1 << 28), 0x0);
+	msm_dwc3_usb3_write_readback(phy->base, PHY_CTRL_REG,
+				    (1 << 26), (1 << 26));
+
+	usleep_range(1000, 1200);
+	clk_disable_unprepare(phy->ref_clk);
+
+	ret = regulator_set_voltage(phy->vddcx, USB_VDDCX_NO, USB_VDDCX_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set voltage for vddcx\n");
+
+	regulator_disable(phy->vddcx);
+
+	ret = regulator_set_voltage(phy->v1p8, 0, PHY_1P8_VOL_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set v1p8\n");
+
+	regulator_disable(phy->v1p8);
+}
+
+static int msm_dwc3_usb3_phy_init(struct usb_phy *x)
+{
+	struct msm_dwc3_usb3_phy *phy = phy_to_dwc3_phy(x);
+	u32 data = 0;
+	int ret;
+
+	ret = regulator_set_voltage(phy->vddcx, USB_VDDCX_MIN, USB_VDDCX_MAX);
+	if (ret) {
+		dev_err(phy->dev, "unable to set voltage for vddcx\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->vddcx);
+	if (ret) {
+		dev_err(phy->dev, "cannot enable the vddcx\n");
+		return ret;
+	}
+
+	ret = regulator_set_voltage(phy->v1p8, PHY_1P8_VOL_MIN,
+				    PHY_1P8_VOL_MAX);
+	if (ret) {
+		regulator_disable(phy->vddcx);
+		dev_err(phy->dev, "unable to set v1p8\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->v1p8);
+	if (ret) {
+		regulator_disable(phy->vddcx);
+		dev_err(phy->dev, "cannot enable the v1p8\n");
+		return ret;
+	}
+
+	clk_prepare_enable(phy->ref_clk);
+	usleep_range(1000, 1200);
+
+	/* SSPHY Initialization: Use ref_clk from pads and set its parameters */
+	msm_dwc3_usb3_write(phy->base, PHY_CTRL_REG, 0x10210002);
+	msleep(30);
+	/* Assert SSPHY reset */
+	msm_dwc3_usb3_write(phy->base, PHY_CTRL_REG, 0x10210082);
+	usleep_range(2000, 2200);
+	/* De-assert SSPHY reset - power and ref_clock must be ON */
+	msm_dwc3_usb3_write(phy->base, PHY_CTRL_REG, 0x10210002);
+	usleep_range(2000, 2200);
+	/* Ref clock must be stable now, enable ref clock for HS mode */
+	msm_dwc3_usb3_write(phy->base, PHY_CTRL_REG, 0x10210102);
+	usleep_range(2000, 2200);
+
+	/*
+	 * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
+	 * in HS mode instead of SS mode. Workaround it by asserting
+	 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
+	 */
+	data = msm_dwc3_usb3_read_phycreg(phy->base, 0x102d);
+	data |= (1 << 7);
+	msm_dwc3_usb3_write_phycreg(phy->base, 0x102D, data);
+
+	data = msm_dwc3_usb3_read_phycreg(phy->base, 0x1010);
+	data &= ~0xff0;
+	data |= 0x20;
+	msm_dwc3_usb3_write_phycreg(phy->base, 0x1010, data);
+
+	/*
+	 * Fix RX Equalization setting as follows
+	 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
+	 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
+	 * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
+	 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
+	 */
+	data = msm_dwc3_usb3_read_phycreg(phy->base, 0x1006);
+	data &= ~(1 << 6);
+	data |= (1 << 7);
+	data &= ~(0x7 << 8);
+	data |= (0x3 << 8);
+	data |= (0x1 << 11);
+	msm_dwc3_usb3_write_phycreg(phy->base, 0x1006, data);
+
+	/*
+	 * Set EQ and TX launch amplitudes as follows
+	 * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
+	 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
+	 * LANE0.TX_OVRD_DRV_LO.EN set to 1.
+	 */
+	data = msm_dwc3_usb3_read_phycreg(phy->base, 0x1002);
+	data &= ~0x3f80;
+	data |= (0x16 << 7);
+	data &= ~0x7f;
+	data |= (0x7f | (1 << 14));
+	msm_dwc3_usb3_write_phycreg(phy->base, 0x1002, data);
+
+	/*
+	 * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
+	 * TX_FULL_SWING [26:20] amplitude to 127
+	 * TX_DEEMPH_3_5DB [13:8] to 22
+	 * LOS_BIAS [2:0] to 0x5
+	 */
+	msm_dwc3_usb3_write_readback(phy->base, PHY_PARAM_CTRL_1,
+				0x07f03f07, 0x07f01605);
+	return 0;
+}
+
+static int msm_dwc3_usb3_probe(struct platform_device *pdev)
+{
+	struct msm_dwc3_usb3_phy	*phy;
+	struct resource			*res;
+	void __iomem			*base;
+
+	dev_info(&pdev->dev, "MSM DWC3 SS-PHY\n");
+
+	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy) {
+		dev_err(&pdev->dev, "no mem for MSM DWC3 SS-PHY\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, phy);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	phy->vddcx = devm_regulator_get(phy->dev, "vddcx");
+	if (IS_ERR(phy->vddcx))
+		return -EPROBE_DEFER;
+
+	phy->v1p8 = devm_regulator_get(phy->dev, "v1p8");
+	if (IS_ERR(phy->v1p8))
+		return -EPROBE_DEFER;
+
+	phy->xo_clk = devm_clk_get(&pdev->dev, "xo");
+	if (IS_ERR(phy->xo_clk)) {
+		dev_err(&pdev->dev, "unable to get TCXO buffer handle\n");
+		return PTR_ERR(phy->xo_clk);
+	}
+
+	phy->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
+	if (IS_ERR(phy->ref_clk)) {
+		dev_err(&pdev->dev, "unable to get ref_clk handle\n");
+		return PTR_ERR(phy->ref_clk);
+	}
+
+	clk_prepare_enable(phy->xo_clk);
+
+	phy->dev		= &pdev->dev;
+	phy->base		= base;
+	phy->phy.dev		= phy->dev;
+	phy->phy.label		= "msm-dwc3-usb3";
+	phy->phy.init		= msm_dwc3_usb3_phy_init;
+	phy->phy.shutdown       = msm_dwc3_usb3_phy_shutdown;
+	phy->phy.type		= USB_PHY_TYPE_USB3;
+
+	usb_add_phy_dev(&phy->phy);
+
+	return 0;
+}
+
+static int msm_dwc3_usb3_remove(struct platform_device *pdev)
+{
+	struct msm_dwc3_usb3_phy *phy = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(phy->xo_clk);
+	usb_remove_phy(&phy->phy);
+	return 0;
+}
+
+static const struct of_device_id msm_dwc3_usb3_id_table[] = {
+	{ .compatible = "qcom,dwc3-usb3" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, msm_dwc3_usb3_id_table);
+
+static struct platform_driver msm_dwc3_usb3_driver = {
+	.probe		= msm_dwc3_usb3_probe,
+	.remove		= msm_dwc3_usb3_remove,
+	.driver		= {
+		.name	= "msm-dwc3-usb3",
+		.owner	= THIS_MODULE,
+		.of_match_table = msm_dwc3_usb3_id_table,
+	},
+};
+
+module_platform_driver(msm_dwc3_usb3_driver);
+
+MODULE_ALIAS("platform:msm_dwc3_usb3");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 MSM SS-PHY driver");
-- 
1.7.9.5

[RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core

[Ivan T. Ivanov]

From: "Ivan T. Ivanov" <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>

Signed-off-by: Ivan T. Ivanov <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/usb/msm-ssusb.txt          |   49 +++
 drivers/usb/phy/Kconfig                            |   11 +
 drivers/usb/phy/Makefile                           |    2 +
 drivers/usb/phy/phy-msm-dwc3-usb2.c                |  342 +++++++++++++++++
 drivers/usb/phy/phy-msm-dwc3-usb3.c                |  389 ++++++++++++++++++++
 5 files changed, 793 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
 create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
 create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c

diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
new file mode 100644
index 0000000..550b496
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -0,0 +1,49 @@
+MSM SuperSpeed USB3.0 SoC controllers
+
+Required properities :
+- compatible sould be "qcom,dwc3-usb2";
+- reg : offset and length of the register set in the memory map
+- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
+- clock-names: "xo", "sleep_a_clk";
+<supply-name>-supply: phandle to the regulator device tree node
+Required "supply-name" examples are:
+	"v1p8" : 1.8v supply for HSPHY
+	"v3p3" : 3.3v supply for HSPHY
+	"vbus" : vbus supply for host mode
+	"vddcx" : vdd supply for HS-PHY digital circuit operation
+
+Required properities :
+- compatible sould be "qcom,dwc3-usb3";
+- reg : offset and length of the register set in the memory map
+- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
+- clock-names: "xo", "ref_clk";
+<supply-name>-supply: phandle to the regulator device tree node
+Required "supply-name" examples are:
+	"v1p8" : 1.8v supply for SS-PHY
+	"vddcx" : vdd supply for SS-PHY digital circuit operation
+
+Example device nodes:
+
+	dwc3_usb2: phy@f92f8800 {
+		compatible = "qcom,dwc3-usb2";
+		reg = <0xf92f8800 0x30>;
+
+		clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
+		clock-names = "xo", "sleep_a_clk";
+
+		vbus-supply = <&supply>;
+		vddcx-supply = <&supply>;
+		v1p8-supply = <&supply>;
+		v3p3-supply = <&supply>;
+	};
+
+	dwc3_usb3: phy@f92f8830 {
+		compatible = "qcom,dwc3-usb3";
+		reg = <0xf92f8830 0x30>;
+
+		clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
+		clock-names = "xo", "ref_clk";
+
+		vddcx-supply = <&supply>;
+		v1p8-supply = <&supply>;
+	};
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 5443958..40e83b5 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -202,6 +202,17 @@ config USB_RCAR_PHY
 	  To compile this driver as a module, choose M here: the
 	  module will be called phy-rcar-usb.
 
+config USB_MSM_DWC3_PHYS
+	tristate "Qualcomm DWC3 USB controller PHY's support"
+	depends on (USB || USB_GADGET) && ARCH_MSM
+	select USB_PHY
+	help
+	  Enable this to support the USB PHY transceivers on MSM chips with
+	  DWC3 USB core. It handles PHY initialization, clock management
+	  required after resetting the hardware and power management.
+	  This driver is required even for peripheral only or host only
+	  mode configurations.
+
 config USB_ULPI
 	bool "Generic ULPI Transceiver Driver"
 	depends on ARM
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 98730ca..53355ec 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -24,6 +24,8 @@ obj-$(CONFIG_USB_EHCI_TEGRA)		+= phy-tegra-usb.o
 obj-$(CONFIG_USB_GPIO_VBUS)		+= phy-gpio-vbus-usb.o
 obj-$(CONFIG_USB_ISP1301)		+= phy-isp1301.o
 obj-$(CONFIG_USB_MSM_OTG)		+= phy-msm-usb.o
+obj-$(CONFIG_USB_MSM_DWC3_PHYS)		+= phy-msm-dwc3-usb2.o
+obj-$(CONFIG_USB_MSM_DWC3_PHYS)		+= phy-msm-dwc3-usb3.o
 obj-$(CONFIG_USB_MV_OTG)		+= phy-mv-usb.o
 obj-$(CONFIG_USB_MXS_PHY)		+= phy-mxs-usb.o
 obj-$(CONFIG_USB_RCAR_PHY)		+= phy-rcar-usb.o
diff --git a/drivers/usb/phy/phy-msm-dwc3-usb2.c b/drivers/usb/phy/phy-msm-dwc3-usb2.c
new file mode 100644
index 0000000..174c72c
--- /dev/null
+++ b/drivers/usb/phy/phy-msm-dwc3-usb2.c
@@ -0,0 +1,342 @@
+/* Copyright (c) 2013, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#undef CONFIG_REGULATOR
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/phy.h>
+
+/**
+ *  USB QSCRATCH Hardware registers
+ */
+#define QSCRATCH_CTRL_REG		(0x04)
+#define QSCRATCH_GENERAL_CFG		(0x08)
+#define PHY_CTRL_REG			(0x10)
+#define PARAMETER_OVERRIDE_X_REG	(0x14)
+#define CHARGING_DET_CTRL_REG		(0x18)
+#define CHARGING_DET_OUTPUT_REG		(0x1c)
+#define ALT_INTERRUPT_EN_REG		(0x20)
+#define PHY_IRQ_STAT_REG		(0x24)
+#define CGCTL_REG			(0x28)
+
+#define PHY_3P3_VOL_MIN			3050000 /* uV */
+#define PHY_3P3_VOL_MAX			3300000 /* uV */
+#define PHY_3P3_HPM_LOAD		16000	/* uA */
+
+#define PHY_1P8_VOL_MIN			1800000 /* uV */
+#define PHY_1P8_VOL_MAX			1800000 /* uV */
+#define PHY_1P8_HPM_LOAD		19000	/* uA */
+
+/* TODO: these are suspicious */
+#define USB_VDDCX_NO			1	/* uV */
+#define USB_VDDCX_MIN			5	/* uV */
+#define USB_VDDCX_MAX			7	/* uV */
+
+struct msm_dwc3_usb2_phy {
+	struct usb_phy		phy;
+	void __iomem		*base;
+	struct device		*dev;
+
+	struct clk		*xo_clk;
+	struct clk		*sleep_a_clk;
+
+	struct regulator	*v3p3;
+	struct regulator	*v1p8;
+	struct regulator	*vddcx;
+	struct regulator	*vbus;
+};
+
+#define	phy_to_dwc3_phy(x)	container_of((x), struct msm_dwc3_usb2_phy, phy)
+
+
+/**
+ *
+ * Write register with debug info.
+ *
+ * @base - DWC3 base virtual address.
+ * @offset - register offset.
+ * @val - value to write.
+ *
+ */
+static inline void msm_dwc3_usb2_write(void *base, u32 offset, u32 val)
+{
+	iowrite32(val, base + offset);
+}
+
+/**
+ * Write register and read back masked value to confirm it is written
+ *
+ * @base - DWC3 base virtual address.
+ * @offset - register offset.
+ * @mask - register bitmask specifying what should be updated
+ * @val - value to write.
+ *
+ */
+static inline void msm_dwc3_usb2_write_readback(void *base, u32 offset,
+					    const u32 mask, u32 val)
+{
+	u32 write_val, tmp = ioread32(base + offset);
+
+	tmp &= ~mask;		/* retain other bits */
+	write_val = tmp | val;
+
+	iowrite32(write_val, base + offset);
+
+	/* Read back to see if val was written */
+	tmp = ioread32(base + offset);
+	tmp &= mask;		/* clear other bits */
+
+	if (tmp != val)
+		pr_err("write: %x to QSCRATCH: %x FAILED\n", val, offset);
+}
+
+static void msm_dwc3_usb2_phy_shutdown(struct usb_phy *x)
+{
+	struct msm_dwc3_usb2_phy *phy = phy_to_dwc3_phy(x);
+	int ret;
+
+	ret = regulator_set_voltage(phy->v3p3, 0, PHY_3P3_VOL_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set voltage for v3p3\n");
+
+	ret = regulator_set_voltage(phy->v1p8, 0, PHY_1P8_VOL_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set voltage for v1p8\n");
+
+	ret = regulator_disable(phy->v1p8);
+	if (ret)
+		dev_err(phy->dev, "cannot disable v1p8\n");
+
+	ret = regulator_disable(phy->v3p3);
+	if (ret)
+		dev_err(phy->dev, "cannot disable v3p3\n");
+
+	ret = regulator_set_voltage(phy->vddcx, USB_VDDCX_NO, USB_VDDCX_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set voltage for vddcx\n");
+
+	ret = regulator_disable(phy->vddcx);
+	if (ret)
+		dev_err(phy->dev, "unable to enable the vddcx\n");
+
+	clk_disable_unprepare(phy->sleep_a_clk);
+}
+
+static int msm_dwc3_usb2_phy_init(struct usb_phy *x)
+{
+	struct msm_dwc3_usb2_phy	*phy = phy_to_dwc3_phy(x);
+	int ret;
+
+	clk_prepare_enable(phy->sleep_a_clk);
+
+	ret = regulator_set_voltage(phy->vddcx, USB_VDDCX_MIN, USB_VDDCX_MAX);
+	if (ret) {
+		dev_err(phy->dev, "unable to set voltage for vddcx\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->vddcx);
+	if (ret) {
+		dev_err(phy->dev, "unable to enable the vddcx\n");
+		return ret;
+	}
+
+	ret = regulator_set_voltage(phy->v3p3, PHY_3P3_VOL_MIN,
+				    PHY_3P3_VOL_MAX);
+	if (ret) {
+		dev_err(phy->dev, "unable to set voltage for v3p3\n");
+		return ret;
+	}
+
+	ret = regulator_set_voltage(phy->v1p8, PHY_1P8_VOL_MIN,
+				    PHY_1P8_VOL_MAX);
+	if (ret) {
+		dev_err(phy->dev, "unable to set voltage for v1p8\n");
+		return ret;
+	}
+
+	ret = regulator_set_optimum_mode(phy->v1p8, PHY_1P8_HPM_LOAD);
+	if (ret < 0) {
+		dev_err(phy->dev, "unable to set HPM of regulator v1p8\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->v1p8);
+	if (ret) {
+		dev_err(phy->dev, "unable to enable v1p8\n");
+		return ret;
+	}
+
+	ret = regulator_set_optimum_mode(phy->v3p3, PHY_3P3_HPM_LOAD);
+	if (ret < 0) {
+		dev_err(phy->dev, "unable to set HPM of regulator v3p3\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->v3p3);
+	if (ret) {
+		dev_err(phy->dev, "unable to enable v3p3\n");
+		return ret;
+	}
+
+	/*
+	 * HSPHY Initialization: Enable UTMI clock and clamp enable HVINTs,
+	 * and disable RETENTION (power-on default is ENABLED)
+	 */
+	msm_dwc3_usb2_write(phy->base, PHY_CTRL_REG, 0x5220bb2);
+	usleep_range(2000, 2200);
+
+	/*
+	 * write HSPHY init value to QSCRATCH reg to set HSPHY parameters like
+	 * VBUS valid threshold, disconnect valid threshold, DC voltage level,
+	 * preempasis and rise/fall time.
+	 */
+	msm_dwc3_usb2_write_readback(phy->base, PARAMETER_OVERRIDE_X_REG,
+				0x03ffffff, 0x00d191a4);
+
+	/* Disable (bypass) VBUS and ID filters */
+	msm_dwc3_usb2_write(phy->base, QSCRATCH_GENERAL_CFG, 0x78);
+
+	return 0;
+}
+
+static int msm_dwc3_usb2_phy_set_vbus(struct usb_phy *x, int on)
+{
+	struct msm_dwc3_usb2_phy	*phy = phy_to_dwc3_phy(x);
+	int ret;
+
+	if (on)
+		ret = regulator_enable(phy->vbus);
+	else
+		ret = regulator_disable(phy->vbus);
+
+	if (ret)
+		dev_err(x->dev, "Cannot %s Vbus\n", on ? "set" : "off");
+	return ret;
+}
+
+static int msm_dwc3_usb2_probe(struct platform_device *pdev)
+{
+	struct msm_dwc3_usb2_phy	*phy;
+	struct resource			*res;
+	void __iomem			*base;
+
+	dev_info(&pdev->dev, "MSM DWC3 HS-PHY\n");
+
+	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy) {
+		dev_err(&pdev->dev, "no alloc mem for MSM DWC3 HS-PHY\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, phy);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	phy->vddcx = devm_regulator_get(&pdev->dev, "vddcx");
+	if (IS_ERR(phy->vddcx)) {
+		dev_err(&pdev->dev, "unable to get vddcx\n");
+		return  PTR_ERR(phy->vddcx);
+	}
+
+	phy->v3p3 = devm_regulator_get(phy->dev, "v3p3");
+	if (IS_ERR(phy->v3p3)) {
+		dev_err(phy->dev, "unable to get v3p3\n");
+		return PTR_ERR(phy->v3p3);
+	}
+
+	phy->v1p8 = devm_regulator_get(phy->dev, "v1p8");
+	if (IS_ERR(phy->v1p8)) {
+		dev_err(phy->dev, "unable to get v1p8\n");
+		return PTR_ERR(phy->v1p8);
+	}
+
+	phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
+	if (IS_ERR(phy->vbus)) {
+		dev_err(phy->dev, "Failed to get vbus\n");
+		return PTR_ERR(phy->vbus);
+	}
+
+	phy->xo_clk = devm_clk_get(&pdev->dev, "xo");
+	if (IS_ERR(phy->xo_clk)) {
+		dev_err(&pdev->dev, "unable to get TCXO buffer handle\n");
+		return PTR_ERR(phy->xo_clk);
+	}
+
+	phy->sleep_a_clk = devm_clk_get(&pdev->dev, "sleep_a_clk");
+	if (IS_ERR(phy->sleep_a_clk)) {
+		dev_err(&pdev->dev, "failed to get sleep_a_clk\n");
+		return PTR_ERR(phy->sleep_a_clk);
+	}
+
+	clk_prepare_enable(phy->xo_clk);
+
+	phy->dev		= &pdev->dev;
+	phy->base		= base;
+	phy->phy.dev		= phy->dev;
+	phy->phy.label		= "msm-dwc3-usb2";
+	phy->phy.init		= msm_dwc3_usb2_phy_init;
+	phy->phy.shutdown	= msm_dwc3_usb2_phy_shutdown;
+	phy->phy.set_vbus	= msm_dwc3_usb2_phy_set_vbus;
+	phy->phy.type		= USB_PHY_TYPE_USB2;
+	phy->phy.state          = OTG_STATE_UNDEFINED;
+
+	usb_add_phy_dev(&phy->phy);
+
+	return 0;
+}
+
+static int msm_dwc3_usb2_remove(struct platform_device *pdev)
+{
+	struct msm_dwc3_usb2_phy *phy = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(phy->xo_clk);
+	usb_remove_phy(&phy->phy);
+	return 0;
+}
+
+static const struct of_device_id msm_dwc3_usb2_id_table[] = {
+	{ .compatible = "qcom,dwc3-usb2" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, msm_dwc3_usb2_id_table);
+
+static struct platform_driver msm_dwc3_usb2_driver = {
+	.probe		= msm_dwc3_usb2_probe,
+	.remove		= msm_dwc3_usb2_remove,
+	.driver		= {
+		.name	= "msm-dwc3-usb2",
+		.owner	= THIS_MODULE,
+		.of_match_table = msm_dwc3_usb2_id_table,
+	},
+};
+
+module_platform_driver(msm_dwc3_usb2_driver);
+
+MODULE_ALIAS("platform:msm_dwc3_usb2");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 MSM HS-PHY driver");
diff --git a/drivers/usb/phy/phy-msm-dwc3-usb3.c b/drivers/usb/phy/phy-msm-dwc3-usb3.c
new file mode 100644
index 0000000..f7bafff
--- /dev/null
+++ b/drivers/usb/phy/phy-msm-dwc3-usb3.c
@@ -0,0 +1,389 @@
+/* Copyright (c) 2013, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#undef CONFIG_REGULATOR
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/phy.h>
+
+/**
+ *  USB QSCRATCH Hardware registers
+ */
+#define PHY_CTRL_REG			(0x00)
+#define PHY_PARAM_CTRL_1		(0x04)
+#define PHY_PARAM_CTRL_2		(0x08)
+#define CR_PROTOCOL_DATA_IN_REG		(0x0c)
+#define CR_PROTOCOL_DATA_OUT_REG	(0x10)
+#define CR_PROTOCOL_CAP_ADDR_REG	(0x14)
+#define CR_PROTOCOL_CAP_DATA_REG	(0x18)
+#define CR_PROTOCOL_READ_REG		(0x1c)
+#define CR_PROTOCOL_WRITE_REG		(0x20)
+
+#define PHY_1P8_VOL_MIN			1800000 /* uV */
+#define PHY_1P8_VOL_MAX			1800000 /* uV */
+#define PHY_1P8_HPM_LOAD		23000	/* uA */
+
+/* TODO: these are suspicious */
+#define USB_VDDCX_NO			1	/* uV */
+#define USB_VDDCX_MIN			5	/* uV */
+#define USB_VDDCX_MAX			7	/* uV */
+
+struct msm_dwc3_usb3_phy {
+	struct usb_phy		phy;
+	void __iomem		*base;
+	struct device		*dev;
+
+	struct regulator	*v1p8;
+	struct regulator	*vddcx;
+
+	struct clk		*xo_clk;
+	struct clk		*ref_clk;
+};
+
+#define	phy_to_dwc3_phy(x)	container_of((x), struct msm_dwc3_usb3_phy, phy)
+
+
+/**
+ *
+ * Write register with debug info.
+ *
+ * @base - DWC3 base virtual address.
+ * @offset - register offset.
+ * @val - value to write.
+ *
+ */
+static inline void msm_dwc3_usb3_write(void *base, u32 offset, u32 val)
+{
+	iowrite32(val, base + offset);
+}
+
+/**
+ * Write register and read back masked value to confirm it is written
+ *
+ * @base - DWC3 base virtual address.
+ * @offset - register offset.
+ * @mask - register bitmask specifying what should be updated
+ * @val - value to write.
+ *
+ */
+static inline void msm_dwc3_usb3_write_readback(void *base, u32 offset,
+					    const u32 mask, u32 val)
+{
+	u32 write_val, tmp = ioread32(base + offset);
+
+	tmp &= ~mask;		/* retain other bits */
+	write_val = tmp | val;
+
+	iowrite32(write_val, base + offset);
+
+	/* Read back to see if val was written */
+	tmp = ioread32(base + offset);
+	tmp &= mask;		/* clear other bits */
+
+	if (tmp != val)
+		pr_err("write: %x to QSCRATCH: %x FAILED\n", val, offset);
+}
+
+/**
+ *
+ * Write SSPHY register with debug info.
+ *
+ * @base - DWC3 base virtual address.
+ * @addr - SSPHY address to write.
+ * @val - value to write.
+ *
+ */
+static void msm_dwc3_usb3_write_phycreg(void *base, u32 addr, u32 val)
+{
+	iowrite32(addr, base + CR_PROTOCOL_DATA_IN_REG);
+	iowrite32(0x1, base + CR_PROTOCOL_CAP_ADDR_REG);
+	while (ioread32(base + CR_PROTOCOL_CAP_ADDR_REG))
+		cpu_relax();
+
+	iowrite32(val, base + CR_PROTOCOL_DATA_IN_REG);
+	iowrite32(0x1, base + CR_PROTOCOL_CAP_DATA_REG);
+	while (ioread32(base + CR_PROTOCOL_CAP_DATA_REG))
+		cpu_relax();
+
+	iowrite32(0x1, base + CR_PROTOCOL_WRITE_REG);
+	while (ioread32(base + CR_PROTOCOL_WRITE_REG))
+		cpu_relax();
+}
+
+/**
+ *
+ * Read SSPHY register with debug info.
+ *
+ * @base - DWC3 base virtual address.
+ * @addr - SSPHY address to read.
+ *
+ */
+static u32 msm_dwc3_usb3_read_phycreg(void *base, u32 addr)
+{
+	bool first_read = true;
+
+	iowrite32(addr, base + CR_PROTOCOL_DATA_IN_REG);
+	iowrite32(0x1, base + CR_PROTOCOL_CAP_ADDR_REG);
+	while (ioread32(base + CR_PROTOCOL_CAP_ADDR_REG))
+		cpu_relax();
+
+	/*
+	 * Due to hardware bug, first read of SSPHY register might be
+	 * incorrect. Hence as workaround, SW should perform SSPHY register
+	 * read twice, but use only second read and ignore first read.
+	 */
+retry:
+	iowrite32(0x1, base + CR_PROTOCOL_READ_REG);
+	while (ioread32(base + CR_PROTOCOL_READ_REG))
+		cpu_relax();
+
+	if (first_read) {
+		ioread32(base + CR_PROTOCOL_DATA_OUT_REG);
+		first_read = false;
+		goto retry;
+	}
+
+	return ioread32(base + CR_PROTOCOL_DATA_OUT_REG);
+}
+
+static void msm_dwc3_usb3_phy_shutdown(struct usb_phy *x)
+{
+	struct msm_dwc3_usb3_phy *phy = phy_to_dwc3_phy(x);
+	int ret;
+
+	/* Sequence to put SSPHY in low power state:
+	 * 1. Clear REF_PHY_EN in PHY_CTRL_REG
+	 * 2. Clear REF_USE_PAD in PHY_CTRL_REG
+	 * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
+	 * 4. Disable SSPHY ref clk
+	 */
+	msm_dwc3_usb3_write_readback(phy->base, PHY_CTRL_REG, (1 << 8), 0x0);
+	msm_dwc3_usb3_write_readback(phy->base, PHY_CTRL_REG, (1 << 28), 0x0);
+	msm_dwc3_usb3_write_readback(phy->base, PHY_CTRL_REG,
+				    (1 << 26), (1 << 26));
+
+	usleep_range(1000, 1200);
+	clk_disable_unprepare(phy->ref_clk);
+
+	ret = regulator_set_voltage(phy->vddcx, USB_VDDCX_NO, USB_VDDCX_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set voltage for vddcx\n");
+
+	regulator_disable(phy->vddcx);
+
+	ret = regulator_set_voltage(phy->v1p8, 0, PHY_1P8_VOL_MAX);
+	if (ret)
+		dev_err(phy->dev, "unable to set v1p8\n");
+
+	regulator_disable(phy->v1p8);
+}
+
+static int msm_dwc3_usb3_phy_init(struct usb_phy *x)
+{
+	struct msm_dwc3_usb3_phy *phy = phy_to_dwc3_phy(x);
+	u32 data = 0;
+	int ret;
+
+	ret = regulator_set_voltage(phy->vddcx, USB_VDDCX_MIN, USB_VDDCX_MAX);
+	if (ret) {
+		dev_err(phy->dev, "unable to set voltage for vddcx\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->vddcx);
+	if (ret) {
+		dev_err(phy->dev, "cannot enable the vddcx\n");
+		return ret;
+	}
+
+	ret = regulator_set_voltage(phy->v1p8, PHY_1P8_VOL_MIN,
+				    PHY_1P8_VOL_MAX);
+	if (ret) {
+		regulator_disable(phy->vddcx);
+		dev_err(phy->dev, "unable to set v1p8\n");
+		return ret;
+	}
+
+	ret = regulator_enable(phy->v1p8);
+	if (ret) {
+		regulator_disable(phy->vddcx);
+		dev_err(phy->dev, "cannot enable the v1p8\n");
+		return ret;
+	}
+
+	clk_prepare_enable(phy->ref_clk);
+	usleep_range(1000, 1200);
+
+	/* SSPHY Initialization: Use ref_clk from pads and set its parameters */
+	msm_dwc3_usb3_write(phy->base, PHY_CTRL_REG, 0x10210002);
+	msleep(30);
+	/* Assert SSPHY reset */
+	msm_dwc3_usb3_write(phy->base, PHY_CTRL_REG, 0x10210082);
+	usleep_range(2000, 2200);
+	/* De-assert SSPHY reset - power and ref_clock must be ON */
+	msm_dwc3_usb3_write(phy->base, PHY_CTRL_REG, 0x10210002);
+	usleep_range(2000, 2200);
+	/* Ref clock must be stable now, enable ref clock for HS mode */
+	msm_dwc3_usb3_write(phy->base, PHY_CTRL_REG, 0x10210102);
+	usleep_range(2000, 2200);
+
+	/*
+	 * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
+	 * in HS mode instead of SS mode. Workaround it by asserting
+	 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
+	 */
+	data = msm_dwc3_usb3_read_phycreg(phy->base, 0x102d);
+	data |= (1 << 7);
+	msm_dwc3_usb3_write_phycreg(phy->base, 0x102D, data);
+
+	data = msm_dwc3_usb3_read_phycreg(phy->base, 0x1010);
+	data &= ~0xff0;
+	data |= 0x20;
+	msm_dwc3_usb3_write_phycreg(phy->base, 0x1010, data);
+
+	/*
+	 * Fix RX Equalization setting as follows
+	 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
+	 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
+	 * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
+	 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
+	 */
+	data = msm_dwc3_usb3_read_phycreg(phy->base, 0x1006);
+	data &= ~(1 << 6);
+	data |= (1 << 7);
+	data &= ~(0x7 << 8);
+	data |= (0x3 << 8);
+	data |= (0x1 << 11);
+	msm_dwc3_usb3_write_phycreg(phy->base, 0x1006, data);
+
+	/*
+	 * Set EQ and TX launch amplitudes as follows
+	 * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
+	 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
+	 * LANE0.TX_OVRD_DRV_LO.EN set to 1.
+	 */
+	data = msm_dwc3_usb3_read_phycreg(phy->base, 0x1002);
+	data &= ~0x3f80;
+	data |= (0x16 << 7);
+	data &= ~0x7f;
+	data |= (0x7f | (1 << 14));
+	msm_dwc3_usb3_write_phycreg(phy->base, 0x1002, data);
+
+	/*
+	 * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
+	 * TX_FULL_SWING [26:20] amplitude to 127
+	 * TX_DEEMPH_3_5DB [13:8] to 22
+	 * LOS_BIAS [2:0] to 0x5
+	 */
+	msm_dwc3_usb3_write_readback(phy->base, PHY_PARAM_CTRL_1,
+				0x07f03f07, 0x07f01605);
+	return 0;
+}
+
+static int msm_dwc3_usb3_probe(struct platform_device *pdev)
+{
+	struct msm_dwc3_usb3_phy	*phy;
+	struct resource			*res;
+	void __iomem			*base;
+
+	dev_info(&pdev->dev, "MSM DWC3 SS-PHY\n");
+
+	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy) {
+		dev_err(&pdev->dev, "no mem for MSM DWC3 SS-PHY\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, phy);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	phy->vddcx = devm_regulator_get(phy->dev, "vddcx");
+	if (IS_ERR(phy->vddcx))
+		return -EPROBE_DEFER;
+
+	phy->v1p8 = devm_regulator_get(phy->dev, "v1p8");
+	if (IS_ERR(phy->v1p8))
+		return -EPROBE_DEFER;
+
+	phy->xo_clk = devm_clk_get(&pdev->dev, "xo");
+	if (IS_ERR(phy->xo_clk)) {
+		dev_err(&pdev->dev, "unable to get TCXO buffer handle\n");
+		return PTR_ERR(phy->xo_clk);
+	}
+
+	phy->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
+	if (IS_ERR(phy->ref_clk)) {
+		dev_err(&pdev->dev, "unable to get ref_clk handle\n");
+		return PTR_ERR(phy->ref_clk);
+	}
+
+	clk_prepare_enable(phy->xo_clk);
+
+	phy->dev		= &pdev->dev;
+	phy->base		= base;
+	phy->phy.dev		= phy->dev;
+	phy->phy.label		= "msm-dwc3-usb3";
+	phy->phy.init		= msm_dwc3_usb3_phy_init;
+	phy->phy.shutdown       = msm_dwc3_usb3_phy_shutdown;
+	phy->phy.type		= USB_PHY_TYPE_USB3;
+
+	usb_add_phy_dev(&phy->phy);
+
+	return 0;
+}
+
+static int msm_dwc3_usb3_remove(struct platform_device *pdev)
+{
+	struct msm_dwc3_usb3_phy *phy = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(phy->xo_clk);
+	usb_remove_phy(&phy->phy);
+	return 0;
+}
+
+static const struct of_device_id msm_dwc3_usb3_id_table[] = {
+	{ .compatible = "qcom,dwc3-usb3" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, msm_dwc3_usb3_id_table);
+
+static struct platform_driver msm_dwc3_usb3_driver = {
+	.probe		= msm_dwc3_usb3_probe,
+	.remove		= msm_dwc3_usb3_remove,
+	.driver		= {
+		.name	= "msm-dwc3-usb3",
+		.owner	= THIS_MODULE,
+		.of_match_table = msm_dwc3_usb3_id_table,
+	},
+};
+
+module_platform_driver(msm_dwc3_usb3_driver);
+
+MODULE_ALIAS("platform:msm_dwc3_usb3");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 MSM SS-PHY driver");
-- 
1.7.9.5

--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core

[Pawel Moll]

On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> 
> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>

I am sure that the information in the subject is more than enough for
you, but would you care to give some more background for the commit log?
Where can we find such controllers? What is DWC3 core? Is it
Qualcomm-specific block, or does it come from one of the IP providers
like Synopsys or Cadence?

>  .../devicetree/bindings/usb/msm-ssusb.txt          |   49 +++
>  drivers/usb/phy/Kconfig                            |   11 +
>  drivers/usb/phy/Makefile                           |    2 +
>  drivers/usb/phy/phy-msm-dwc3-usb2.c                |  342 +++++++++++++++++
>  drivers/usb/phy/phy-msm-dwc3-usb3.c                |  389 ++++++++++++++++++++
>  5 files changed, 793 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
>  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
>  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
> 
> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> new file mode 100644
> index 0000000..550b496
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> @@ -0,0 +1,49 @@
> +MSM SuperSpeed USB3.0 SoC controllers

I understand that the device always come in doublets? As in: are nodes
for both USB2 and 3 always required?

> +Required properities :
> +- compatible sould be "qcom,dwc3-usb2";
> +- reg : offset and length of the register set in the memory map
> +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
> +- clock-names: "xo", "sleep_a_clk";
> +<supply-name>-supply: phandle to the regulator device tree node
> +Required "supply-name" examples are:

So required or examples? ;-)

> +       "v1p8" : 1.8v supply for HSPHY
> +       "v3p3" : 3.3v supply for HSPHY
> +       "vbus" : vbus supply for host mode
> +       "vddcx" : vdd supply for HS-PHY digital circuit operation
>
> +Required properities :
> +- compatible sould be "qcom,dwc3-usb3";
> +- reg : offset and length of the register set in the memory map
> +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
> +- clock-names: "xo", "ref_clk";
> +<supply-name>-supply: phandle to the regulator device tree node
> +Required "supply-name" examples are:
> +       "v1p8" : 1.8v supply for SS-PHY
> +       "vddcx" : vdd supply for SS-PHY digital circuit operation
> +
> +Example device nodes:
> +
> +       dwc3_usb2: phy@f92f8800 {
> +               compatible = "qcom,dwc3-usb2";
> +               reg = <0xf92f8800 0x30>;
> +
> +               clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> +               clock-names = "xo", "sleep_a_clk";
> +
> +               vbus-supply = <&supply>;
> +               vddcx-supply = <&supply>;
> +               v1p8-supply = <&supply>;
> +               v3p3-supply = <&supply>;
> +       };
> +
> +       dwc3_usb3: phy@f92f8830 {
> +               compatible = "qcom,dwc3-usb3";
> +               reg = <0xf92f8830 0x30>;
> +
> +               clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> +               clock-names = "xo", "ref_clk";
> +
> +               vddcx-supply = <&supply>;
> +               v1p8-supply = <&supply>;
> +       };

Note that I had a look at the bindings only - I don't feel competent to
review the drivers/usb part of the patch...

Thanks!

Pawel

Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core

[Ivan T. Ivanov]

Hi, 

On Tue, 2013-08-06 at 13:12 +0100, Pawel Moll wrote:
> On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> > 
> > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> 
> I am sure that the information in the subject is more than enough for
> you, but would you care to give some more background for the commit log?
> Where can we find such controllers? What is DWC3 core? Is it
> Qualcomm-specific block, or does it come from one of the IP providers
> like Synopsys or Cadence?
> 

You are right, I have to add more info here. DesignWare USB Core could 
also be found in TI OMAP's and Samasung SoC's, at least. And it is
IP from Synopsys. Usually SoC vendors wrap it with additional logic, 
which provides required clocks and power supplies. 



> >  .../devicetree/bindings/usb/msm-ssusb.txt          |   49 +++
> >  drivers/usb/phy/Kconfig                            |   11 +
> >  drivers/usb/phy/Makefile                           |    2 +
> >  drivers/usb/phy/phy-msm-dwc3-usb2.c                |  342 +++++++++++++++++
> >  drivers/usb/phy/phy-msm-dwc3-usb3.c                |  389 ++++++++++++++++++++
> >  5 files changed, 793 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> >  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
> >  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > new file mode 100644
> > index 0000000..550b496
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > @@ -0,0 +1,49 @@
> > +MSM SuperSpeed USB3.0 SoC controllers
> 
> I understand that the device always come in doublets? As in: are nodes
> for both USB2 and 3 always required?

The core dwc3 driver expects 2 USB PHY interfaces, so both nodes
are mandatory.

> 
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb2";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
> > +- clock-names: "xo", "sleep_a_clk";
> > +<supply-name>-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
> 
> So required or examples? ;-)


It should be Required, will fix this.

> 
> > +       "v1p8" : 1.8v supply for HSPHY
> > +       "v3p3" : 3.3v supply for HSPHY
> > +       "vbus" : vbus supply for host mode
> > +       "vddcx" : vdd supply for HS-PHY digital circuit operation
> >
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb3";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
> > +- clock-names: "xo", "ref_clk";
> > +<supply-name>-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
> > +       "v1p8" : 1.8v supply for SS-PHY
> > +       "vddcx" : vdd supply for SS-PHY digital circuit operation
> > +
> > +Example device nodes:
> > +
> > +       dwc3_usb2: phy@f92f8800 {
> > +               compatible = "qcom,dwc3-usb2";
> > +               reg = <0xf92f8800 0x30>;
> > +
> > +               clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> > +               clock-names = "xo", "sleep_a_clk";
> > +
> > +               vbus-supply = <&supply>;
> > +               vddcx-supply = <&supply>;
> > +               v1p8-supply = <&supply>;
> > +               v3p3-supply = <&supply>;
> > +       };
> > +
> > +       dwc3_usb3: phy@f92f8830 {
> > +               compatible = "qcom,dwc3-usb3";
> > +               reg = <0xf92f8830 0x30>;
> > +
> > +               clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> > +               clock-names = "xo", "ref_clk";
> > +
> > +               vddcx-supply = <&supply>;
> > +               v1p8-supply = <&supply>;
> > +       };
> 
> Note that I had a look at the bindings only - I don't feel competent to
> review the drivers/usb part of the patch...

Sure, thank you.
Ivan

> 
> Thanks!
> 
> Pawel

Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core

[Ivan T. Ivanov]

Hi, 

On Tue, 2013-08-06 at 13:12 +0100, Pawel Moll wrote:
> On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov" <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>
> > 
> > Signed-off-by: Ivan T. Ivanov <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>
> 
> I am sure that the information in the subject is more than enough for
> you, but would you care to give some more background for the commit log?
> Where can we find such controllers? What is DWC3 core? Is it
> Qualcomm-specific block, or does it come from one of the IP providers
> like Synopsys or Cadence?
> 

You are right, I have to add more info here. DesignWare USB Core could 
also be found in TI OMAP's and Samasung SoC's, at least. And it is
IP from Synopsys. Usually SoC vendors wrap it with additional logic, 
which provides required clocks and power supplies. 



> >  .../devicetree/bindings/usb/msm-ssusb.txt          |   49 +++
> >  drivers/usb/phy/Kconfig                            |   11 +
> >  drivers/usb/phy/Makefile                           |    2 +
> >  drivers/usb/phy/phy-msm-dwc3-usb2.c                |  342 +++++++++++++++++
> >  drivers/usb/phy/phy-msm-dwc3-usb3.c                |  389 ++++++++++++++++++++
> >  5 files changed, 793 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> >  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
> >  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > new file mode 100644
> > index 0000000..550b496
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > @@ -0,0 +1,49 @@
> > +MSM SuperSpeed USB3.0 SoC controllers
> 
> I understand that the device always come in doublets? As in: are nodes
> for both USB2 and 3 always required?

The core dwc3 driver expects 2 USB PHY interfaces, so both nodes
are mandatory.

> 
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb2";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
> > +- clock-names: "xo", "sleep_a_clk";
> > +<supply-name>-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
> 
> So required or examples? ;-)


It should be Required, will fix this.

> 
> > +       "v1p8" : 1.8v supply for HSPHY
> > +       "v3p3" : 3.3v supply for HSPHY
> > +       "vbus" : vbus supply for host mode
> > +       "vddcx" : vdd supply for HS-PHY digital circuit operation
> >
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb3";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
> > +- clock-names: "xo", "ref_clk";
> > +<supply-name>-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
> > +       "v1p8" : 1.8v supply for SS-PHY
> > +       "vddcx" : vdd supply for SS-PHY digital circuit operation
> > +
> > +Example device nodes:
> > +
> > +       dwc3_usb2: phy@f92f8800 {
> > +               compatible = "qcom,dwc3-usb2";
> > +               reg = <0xf92f8800 0x30>;
> > +
> > +               clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> > +               clock-names = "xo", "sleep_a_clk";
> > +
> > +               vbus-supply = <&supply>;
> > +               vddcx-supply = <&supply>;
> > +               v1p8-supply = <&supply>;
> > +               v3p3-supply = <&supply>;
> > +       };
> > +
> > +       dwc3_usb3: phy@f92f8830 {
> > +               compatible = "qcom,dwc3-usb3";
> > +               reg = <0xf92f8830 0x30>;
> > +
> > +               clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> > +               clock-names = "xo", "ref_clk";
> > +
> > +               vddcx-supply = <&supply>;
> > +               v1p8-supply = <&supply>;
> > +       };
> 
> Note that I had a look at the bindings only - I don't feel competent to
> review the drivers/usb part of the patch...

Sure, thank you.
Ivan

> 
> Thanks!
> 
> Pawel


--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core

[Mark Rutland]

On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
>
> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> ---
>  .../devicetree/bindings/usb/msm-ssusb.txt          |   49 +++
>  drivers/usb/phy/Kconfig                            |   11 +
>  drivers/usb/phy/Makefile                           |    2 +
>  drivers/usb/phy/phy-msm-dwc3-usb2.c                |  342 +++++++++++++++++
>  drivers/usb/phy/phy-msm-dwc3-usb3.c                |  389 ++++++++++++++++++++
>  5 files changed, 793 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
>  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
>  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
>
> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> new file mode 100644
> index 0000000..550b496
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> @@ -0,0 +1,49 @@
> +MSM SuperSpeed USB3.0 SoC controllers
> +
> +Required properities :
> +- compatible sould be "qcom,dwc3-usb2";
> +- reg : offset and length of the register set in the memory map
> +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;

Huh? That doesn't describe what these are. These would be better
explained with a reference to clock-names and a basic description as to
what the input's called, what it drives, etc, as you've done done for
the *-supply properties.

> +- clock-names: "xo", "sleep_a_clk";
> +<supply-name>-supply: phandle to the regulator device tree node
> +Required "supply-name" examples are:
> +       "v1p8" : 1.8v supply for HSPHY
> +       "v3p3" : 3.3v supply for HSPHY
> +       "vbus" : vbus supply for host mode
> +       "vddcx" : vdd supply for HS-PHY digital circuit operation
> +
> +Required properities :
> +- compatible sould be "qcom,dwc3-usb3";
> +- reg : offset and length of the register set in the memory map
> +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;

Similarly, this doesn't describe what the clocks are.

> +- clock-names: "xo", "ref_clk";
> +<supply-name>-supply: phandle to the regulator device tree node
> +Required "supply-name" examples are:
> +       "v1p8" : 1.8v supply for SS-PHY
> +       "vddcx" : vdd supply for SS-PHY digital circuit operation
> +
> +Example device nodes:
> +
> +       dwc3_usb2: phy@f92f8800 {
> +               compatible = "qcom,dwc3-usb2";
> +               reg = <0xf92f8800 0x30>;
> +
> +               clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> +               clock-names = "xo", "sleep_a_clk";
> +
> +               vbus-supply = <&supply>;
> +               vddcx-supply = <&supply>;
> +               v1p8-supply = <&supply>;
> +               v3p3-supply = <&supply>;
> +       };
> +
> +       dwc3_usb3: phy@f92f8830 {
> +               compatible = "qcom,dwc3-usb3";
> +               reg = <0xf92f8830 0x30>;
> +
> +               clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> +               clock-names = "xo", "ref_clk";
> +
> +               vddcx-supply = <&supply>;
> +               v1p8-supply = <&supply>;
> +       };


Those regster banks look suspiciously close. Are these the same IP
block? Can they ever appear separately?

Do the drivers not trample each other when messing with shared clocks
and regulators?

Thanks,
Mark.

Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core

[Ivan T. Ivanov]

Hi,

On Tue, 2013-08-06 at 15:03 +0100, Mark Rutland wrote:
> On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> >
> > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> > ---
> >  .../devicetree/bindings/usb/msm-ssusb.txt          |   49 +++
> >  drivers/usb/phy/Kconfig                            |   11 +
> >  drivers/usb/phy/Makefile                           |    2 +
> >  drivers/usb/phy/phy-msm-dwc3-usb2.c                |  342 +++++++++++++++++
> >  drivers/usb/phy/phy-msm-dwc3-usb3.c                |  389 ++++++++++++++++++++
> >  5 files changed, 793 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> >  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
> >  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
> >
> > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > new file mode 100644
> > index 0000000..550b496
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > @@ -0,0 +1,49 @@
> > +MSM SuperSpeed USB3.0 SoC controllers
> > +
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb2";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
> 
> Huh? That doesn't describe what these are. These would be better
> explained with a reference to clock-names and a basic description as to
> what the input's called, what it drives, etc, as you've done done for
> the *-supply properties.

Ok, I will fix this.

> 
> > +- clock-names: "xo", "sleep_a_clk";
> > +<supply-name>-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
> > +       "v1p8" : 1.8v supply for HSPHY
> > +       "v3p3" : 3.3v supply for HSPHY
> > +       "vbus" : vbus supply for host mode
> > +       "vddcx" : vdd supply for HS-PHY digital circuit operation
> > +
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb3";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
> 
> Similarly, this doesn't describe what the clocks are.

Understood.

> 
> > +- clock-names: "xo", "ref_clk";
> > +<supply-name>-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
> > +       "v1p8" : 1.8v supply for SS-PHY
> > +       "vddcx" : vdd supply for SS-PHY digital circuit operation
> > +
> > +Example device nodes:
> > +
> > +       dwc3_usb2: phy@f92f8800 {
> > +               compatible = "qcom,dwc3-usb2";
> > +               reg = <0xf92f8800 0x30>;
> > +
> > +               clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> > +               clock-names = "xo", "sleep_a_clk";
> > +
> > +               vbus-supply = <&supply>;
> > +               vddcx-supply = <&supply>;
> > +               v1p8-supply = <&supply>;
> > +               v3p3-supply = <&supply>;
> > +       };
> > +
> > +       dwc3_usb3: phy@f92f8830 {
> > +               compatible = "qcom,dwc3-usb3";
> > +               reg = <0xf92f8830 0x30>;
> > +
> > +               clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> > +               clock-names = "xo", "ref_clk";
> > +
> > +               vddcx-supply = <&supply>;
> > +               v1p8-supply = <&supply>;
> > +       };
> 
> 
> Those regster banks look suspiciously close. Are these the same IP
> block? Can they ever appear separately?
> 

They are part of the wrapper Qualcomm logic around Synopsys USB3 core.
In this sense they are part of the one IP, I believe. Manage them from
separate drivers simplify code.

> Do the drivers not trample each other when messing with shared clocks
> and regulators?
> 

Regulators and clocks have reference counting, right?, so this should
be safe. Even if they are part of the one driver, clocks and regulators
could be switched off only if both PHY's do not use them.

Thanks, 
Ivan


> Thanks,
> Mark.

Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core

[Mark Rutland]

On Tue, Aug 06, 2013 at 03:36:33PM +0100, Ivan T. Ivanov wrote:
> Hi,
> 
> On Tue, 2013-08-06 at 15:03 +0100, Mark Rutland wrote:
> > On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
> > > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> > >
> > > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> > > ---
> > >  .../devicetree/bindings/usb/msm-ssusb.txt          |   49 +++
> > >  drivers/usb/phy/Kconfig                            |   11 +
> > >  drivers/usb/phy/Makefile                           |    2 +
> > >  drivers/usb/phy/phy-msm-dwc3-usb2.c                |  342 +++++++++++++++++
> > >  drivers/usb/phy/phy-msm-dwc3-usb3.c                |  389 ++++++++++++++++++++
> > >  5 files changed, 793 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > >  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
> > >  create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
> > >
> > > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > > new file mode 100644
> > > index 0000000..550b496
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > > @@ -0,0 +1,49 @@
> > > +MSM SuperSpeed USB3.0 SoC controllers
> > > +
> > > +Required properities :
> > > +- compatible sould be "qcom,dwc3-usb2";
> > > +- reg : offset and length of the register set in the memory map
> > > +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
> > 
> > Huh? That doesn't describe what these are. These would be better
> > explained with a reference to clock-names and a basic description as to
> > what the input's called, what it drives, etc, as you've done done for
> > the *-supply properties.
> 
> Ok, I will fix this.
> 
> > 
> > > +- clock-names: "xo", "sleep_a_clk";
> > > +<supply-name>-supply: phandle to the regulator device tree node
> > > +Required "supply-name" examples are:
> > > +       "v1p8" : 1.8v supply for HSPHY
> > > +       "v3p3" : 3.3v supply for HSPHY
> > > +       "vbus" : vbus supply for host mode
> > > +       "vddcx" : vdd supply for HS-PHY digital circuit operation
> > > +
> > > +Required properities :
> > > +- compatible sould be "qcom,dwc3-usb3";
> > > +- reg : offset and length of the register set in the memory map
> > > +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
> > 
> > Similarly, this doesn't describe what the clocks are.
> 
> Understood.
> 
> > 
> > > +- clock-names: "xo", "ref_clk";
> > > +<supply-name>-supply: phandle to the regulator device tree node
> > > +Required "supply-name" examples are:
> > > +       "v1p8" : 1.8v supply for SS-PHY
> > > +       "vddcx" : vdd supply for SS-PHY digital circuit operation
> > > +
> > > +Example device nodes:
> > > +
> > > +       dwc3_usb2: phy@f92f8800 {
> > > +               compatible = "qcom,dwc3-usb2";
> > > +               reg = <0xf92f8800 0x30>;
> > > +
> > > +               clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> > > +               clock-names = "xo", "sleep_a_clk";
> > > +
> > > +               vbus-supply = <&supply>;
> > > +               vddcx-supply = <&supply>;
> > > +               v1p8-supply = <&supply>;
> > > +               v3p3-supply = <&supply>;
> > > +       };
> > > +
> > > +       dwc3_usb3: phy@f92f8830 {
> > > +               compatible = "qcom,dwc3-usb3";
> > > +               reg = <0xf92f8830 0x30>;
> > > +
> > > +               clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> > > +               clock-names = "xo", "ref_clk";
> > > +
> > > +               vddcx-supply = <&supply>;
> > > +               v1p8-supply = <&supply>;
> > > +       };
> > 
> > 
> > Those regster banks look suspiciously close. Are these the same IP
> > block? Can they ever appear separately?
> > 
> 
> They are part of the wrapper Qualcomm logic around Synopsys USB3 core.
> In this sense they are part of the one IP, I believe. Manage them from
> separate drivers simplify code.

Hmmm. I'm not entirely certain on this. On the one hand, they're
separate IP blocks, and have lgoically separate drivers, so describing
them as two devices makes sense. On the other hand, they've been fused
into one IP block with shared resources. Describing them as two devices
probably makes sense given you have the wrapper driver.

> 
> > Do the drivers not trample each other when messing with shared clocks
> > and regulators?
> > 
> 
> Regulators and clocks have reference counting, right?, so this should
> be safe. Even if they are part of the one driver, clocks and regulators
> could be switched off only if both PHY's do not use them.

Ok, I just wanted to be sure this had been considered :)

Thanks,
Mark.

[RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Ivan T. Ivanov]

From: "Ivan T. Ivanov" <iivanov@mm-sol.com>

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
---
 .../devicetree/bindings/usb/msm-ssusb.txt          |   39 +++++
 drivers/usb/dwc3/Kconfig                           |    8 +
 drivers/usb/dwc3/Makefile                          |    1 +
 drivers/usb/dwc3/dwc3-msm.c                        |  175 ++++++++++++++++++++
 4 files changed, 223 insertions(+)
 create mode 100644 drivers/usb/dwc3/dwc3-msm.c

diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
index 550b496..313ae0d 100644
--- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -22,6 +22,23 @@ Required "supply-name" examples are:
 	"v1p8" : 1.8v supply for SS-PHY
 	"vddcx" : vdd supply for SS-PHY digital circuit operation
 
+Required properties :
+- compatible : should be "qcom,dwc-usb3-msm"
+- reg : offset and length of the register set in the memory map
+	offset and length of the TCSR register for routing USB
+	signals to either picoPHY0 or picoPHY1.
+- clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
+- clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
+
+Optional properties :
+- gdsc-supply : phandle to the globally distributed switch controller
+  regulator node to the USB controller.
+
+Sub nodes:
+- Sub node for "DWC3- USB3 controller".
+  This sub node is required property for device node. The properties of this subnode
+  are specified in dwc3.txt.
+
 Example device nodes:
 
 	dwc3_usb2: phy@f92f8800 {
@@ -47,3 +64,25 @@ Example device nodes:
 		vddcx-supply = <&supply>;
 		v1p8-supply = <&supply>;
 	};
+
+	usb@fd4ab000 {
+		compatible = "qcom,dwc-usb3-msm";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xfd4ab000 0x4>;
+
+		clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
+		clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
+
+		gdsc-supply = <&supply>;
+		ranges;
+
+		dwc3@f9200000 {
+			compatible = "snps,dwc3";
+			reg = <0xf9200000 0xcd00>;
+			interrupts = <0 131 0>;
+			interrupt-names = "irq";
+			usb-phy = <&dwc3_usb2>, <&dwc3_usb3>;
+			tx-fifo-resize;
+		};
+	};
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 3e225d5..e2032c4 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -70,6 +70,14 @@ config USB_DWC3_PCI
 	  One such PCIe-based platform is Synopsys' PCIe HAPS model of
 	  this IP.
 
+config USB_DWC3_MSM
+	tristate "Qualcomm MSM/APQ Platforms"
+	default USB_DWC3
+	select USB_MSM_DWC3_PHYS
+	help
+	  Recent Qualcomm SoCs ship with one DesignWare Core USB3 IP inside,
+	  say 'Y' or 'M' if you have one such device.
+
 comment "Debugging features"
 
 config USB_DWC3_DEBUG
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index dd17601..5226681 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -32,3 +32,4 @@ endif
 obj-$(CONFIG_USB_DWC3_OMAP)		+= dwc3-omap.o
 obj-$(CONFIG_USB_DWC3_EXYNOS)		+= dwc3-exynos.o
 obj-$(CONFIG_USB_DWC3_PCI)		+= dwc3-pci.o
+obj-$(CONFIG_USB_DWC3_MSM)		+= dwc3-msm.o
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
new file mode 100644
index 0000000..e509abc
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -0,0 +1,175 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#undef CONFIG_REGULATOR
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/phy.h>
+
+struct dwc3_msm {
+	struct device		*dev;
+	void __iomem		*base;
+
+	struct clk		*core_clk;
+	struct clk		*iface_clk;
+	struct clk		*sleep_clk;
+	struct clk		*utmi_clk;
+
+	struct regulator	*gdsc;
+};
+
+static int dwc3_msm_probe(struct platform_device *pdev)
+{
+	struct device_node *node = pdev->dev.of_node;
+	struct dwc3_msm *mdwc;
+	struct resource *res;
+	void __iomem *tcsr;
+	int ret = 0;
+
+	dev_info(&pdev->dev, "MSM DWC3\n");
+
+	mdwc = devm_kzalloc(&pdev->dev, sizeof(*mdwc), GFP_KERNEL);
+	if (!mdwc) {
+		dev_err(&pdev->dev, "not enough memory\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, mdwc);
+	mdwc->dev = &pdev->dev;
+
+	mdwc->gdsc = devm_regulator_get(mdwc->dev, "gbsc");
+
+	mdwc->core_clk = devm_clk_get(&pdev->dev, "core_clk");
+	if (IS_ERR(mdwc->core_clk)) {
+		dev_err(&pdev->dev, "failed to get core_clk\n");
+		return PTR_ERR(mdwc->core_clk);
+	}
+
+	mdwc->iface_clk = devm_clk_get(&pdev->dev, "iface_clk");
+	if (IS_ERR(mdwc->iface_clk)) {
+		dev_err(&pdev->dev, "failed to get iface_clk\n");
+		return PTR_ERR(mdwc->iface_clk);
+	}
+
+	mdwc->sleep_clk = devm_clk_get(&pdev->dev, "sleep_clk");
+	if (IS_ERR(mdwc->sleep_clk)) {
+		dev_err(&pdev->dev, "failed to get sleep_clk\n");
+		return  PTR_ERR(mdwc->sleep_clk);
+	}
+
+	mdwc->utmi_clk = devm_clk_get(&pdev->dev, "utmi_clk");
+	if (IS_ERR(mdwc->utmi_clk)) {
+		dev_err(&pdev->dev, "failed to get utmi_clk\n");
+		return  PTR_ERR(mdwc->utmi_clk);
+	}
+
+	if (!IS_ERR(mdwc->gdsc)) {
+		ret = regulator_enable(mdwc->gdsc);
+		if (ret)
+			dev_err(mdwc->dev, "unable to enable usb3 gdsc\n");
+	}
+
+	/*
+	 * DWC3 Core requires its CORE CLK (aka master / bus clk) to
+	 * run at 125Mhz in SSUSB mode and >60MHZ for HSUSB mode.
+	 */
+	clk_set_rate(mdwc->core_clk, 125000000);
+	clk_prepare_enable(mdwc->core_clk);
+	clk_prepare_enable(mdwc->iface_clk);
+	clk_prepare_enable(mdwc->sleep_clk);
+	clk_prepare_enable(mdwc->utmi_clk);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	tcsr = devm_ioremap_resource(&pdev->dev, res);
+	if (!tcsr) {
+		dev_dbg(&pdev->dev, "tcsr ioremap failed\n");
+	} else {
+		/* TODO: This has to be revised */
+
+		/* Enable USB3 on the primary USB port. */
+		writel_relaxed(0x1, tcsr);
+		/*
+		 * Ensure that TCSR write is completed before
+		 * USB registers initialization.
+		 */
+		mb();
+	}
+
+	ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to add create dwc3 core\n");
+		goto dis_clks;
+	}
+
+	return 0;
+
+dis_clks:
+	clk_disable_unprepare(mdwc->utmi_clk);
+	clk_disable_unprepare(mdwc->sleep_clk);
+	clk_disable_unprepare(mdwc->iface_clk);
+	clk_disable_unprepare(mdwc->core_clk);
+	if (!IS_ERR(mdwc->gdsc)) {
+		ret = regulator_disable(mdwc->gdsc);
+		if (ret)
+			dev_err(mdwc->dev, "cannot disable usb3 gdsc\n");
+	}
+
+	return ret;
+}
+
+static int dwc3_msm_remove(struct platform_device *pdev)
+{
+	struct dwc3_msm	*mdwc = platform_get_drvdata(pdev);
+	int ret;
+
+	clk_disable_unprepare(mdwc->utmi_clk);
+	clk_disable_unprepare(mdwc->sleep_clk);
+	clk_disable_unprepare(mdwc->iface_clk);
+	clk_disable_unprepare(mdwc->core_clk);
+
+	if (!IS_ERR(mdwc->gdsc)) {
+		ret = regulator_disable(mdwc->gdsc);
+		if (ret)
+			dev_err(mdwc->dev, "cannot disable usb3 gdsc\n");
+	}
+
+	return 0;
+}
+
+static const struct of_device_id of_dwc3_matach[] = {
+	{
+		.compatible = "qcom,dwc-usb3-msm",
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, of_dwc3_matach);
+
+static struct platform_driver dwc3_msm_driver = {
+	.probe		= dwc3_msm_probe,
+	.remove		= dwc3_msm_remove,
+	.driver		= {
+		.name	= "msm-dwc3",
+		.owner	= THIS_MODULE,
+		.of_match_table	= of_dwc3_matach,
+	},
+};
+
+module_platform_driver(dwc3_msm_driver);
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 MSM Glue Layer");
-- 
1.7.9.5

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Pawel Moll]

On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> 
> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>

The same comment as for the RFC 1/2 here...

>  .../devicetree/bindings/usb/msm-ssusb.txt          |   39 +++++
>  drivers/usb/dwc3/Kconfig                           |    8 +
>  drivers/usb/dwc3/Makefile                          |    1 +
>  drivers/usb/dwc3/dwc3-msm.c                        |  175 ++++++++++++++++++++
>  4 files changed, 223 insertions(+)
>  create mode 100644 drivers/usb/dwc3/dwc3-msm.c
> 
> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> index 550b496..313ae0d 100644
> --- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> @@ -22,6 +22,23 @@ Required "supply-name" examples are:
>  	"v1p8" : 1.8v supply for SS-PHY
>  	"vddcx" : vdd supply for SS-PHY digital circuit operation
>  
> +Required properties :
> +- compatible : should be "qcom,dwc-usb3-msm"
> +- reg : offset and length of the register set in the memory map
> +	offset and length of the TCSR register for routing USB
> +	signals to either picoPHY0 or picoPHY1.
> +- clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
> +- clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
> +
> +Optional properties :
> +- gdsc-supply : phandle to the globally distributed switch controller
> +  regulator node to the USB controller.
> +
> +Sub nodes:
> +- Sub node for "DWC3- USB3 controller".
> +  This sub node is required property for device node. The properties of this subnode
> +  are specified in dwc3.txt.

Ah, this answers one of my questions - DWC3 comes from Synopsys.

>  Example device nodes:
>  
>  	dwc3_usb2: phy@f92f8800 {
> @@ -47,3 +64,25 @@ Example device nodes:
>  		vddcx-supply = <&supply>;
>  		v1p8-supply = <&supply>;
>  	};
> +
> +	usb@fd4ab000 {
> +		compatible = "qcom,dwc-usb3-msm";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xfd4ab000 0x4>;
> +
> +		clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
> +		clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
> +
> +		gdsc-supply = <&supply>;
> +		ranges;
> +
> +		dwc3@f9200000 {
> +			compatible = "snps,dwc3";

Note that the Documentation/devicetree/bindings/usb/dwc3.txt is
mentioning "synopsys,dwc3" (which is clearly in opposition to the
vendor-prefixes.txt file) and this compatible value is used in the
drivers/usb/dwc3/core.c and omap5.dtsi. Unless it has been already fixed
recently, could you take care of that?

> +			reg = <0xf9200000 0xcd00>;
> +			interrupts = <0 131 0>;
> +			interrupt-names = "irq";
> +			usb-phy = <&dwc3_usb2>, <&dwc3_usb3>;
> +			tx-fifo-resize;
> +		};
> +	};

And now I'm really confused... Maybe it's just lack of documentation...

How does the "qcom,dwc-usb3-msm" relate to "qcom,dwc-usb3"?

Paweł

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Pawel Moll]

On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov" <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>
> 
> Signed-off-by: Ivan T. Ivanov <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>

The same comment as for the RFC 1/2 here...

>  .../devicetree/bindings/usb/msm-ssusb.txt          |   39 +++++
>  drivers/usb/dwc3/Kconfig                           |    8 +
>  drivers/usb/dwc3/Makefile                          |    1 +
>  drivers/usb/dwc3/dwc3-msm.c                        |  175 ++++++++++++++++++++
>  4 files changed, 223 insertions(+)
>  create mode 100644 drivers/usb/dwc3/dwc3-msm.c
> 
> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> index 550b496..313ae0d 100644
> --- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> @@ -22,6 +22,23 @@ Required "supply-name" examples are:
>  	"v1p8" : 1.8v supply for SS-PHY
>  	"vddcx" : vdd supply for SS-PHY digital circuit operation
>  
> +Required properties :
> +- compatible : should be "qcom,dwc-usb3-msm"
> +- reg : offset and length of the register set in the memory map
> +	offset and length of the TCSR register for routing USB
> +	signals to either picoPHY0 or picoPHY1.
> +- clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
> +- clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
> +
> +Optional properties :
> +- gdsc-supply : phandle to the globally distributed switch controller
> +  regulator node to the USB controller.
> +
> +Sub nodes:
> +- Sub node for "DWC3- USB3 controller".
> +  This sub node is required property for device node. The properties of this subnode
> +  are specified in dwc3.txt.

Ah, this answers one of my questions - DWC3 comes from Synopsys.

>  Example device nodes:
>  
>  	dwc3_usb2: phy@f92f8800 {
> @@ -47,3 +64,25 @@ Example device nodes:
>  		vddcx-supply = <&supply>;
>  		v1p8-supply = <&supply>;
>  	};
> +
> +	usb@fd4ab000 {
> +		compatible = "qcom,dwc-usb3-msm";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xfd4ab000 0x4>;
> +
> +		clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
> +		clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
> +
> +		gdsc-supply = <&supply>;
> +		ranges;
> +
> +		dwc3@f9200000 {
> +			compatible = "snps,dwc3";

Note that the Documentation/devicetree/bindings/usb/dwc3.txt is
mentioning "synopsys,dwc3" (which is clearly in opposition to the
vendor-prefixes.txt file) and this compatible value is used in the
drivers/usb/dwc3/core.c and omap5.dtsi. Unless it has been already fixed
recently, could you take care of that?

> +			reg = <0xf9200000 0xcd00>;
> +			interrupts = <0 131 0>;
> +			interrupt-names = "irq";
> +			usb-phy = <&dwc3_usb2>, <&dwc3_usb3>;
> +			tx-fifo-resize;
> +		};
> +	};

And now I'm really confused... Maybe it's just lack of documentation...

How does the "qcom,dwc-usb3-msm" relate to "qcom,dwc-usb3"?

Paweł


--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Ivan T. Ivanov]

On Tue, 2013-08-06 at 13:21 +0100, Pawel Moll wrote:
> On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> > 
> > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> 
> The same comment as for the RFC 1/2 here...

Will fix this.

> 
> >  .../devicetree/bindings/usb/msm-ssusb.txt          |   39 +++++
> >  drivers/usb/dwc3/Kconfig                           |    8 +
> >  drivers/usb/dwc3/Makefile                          |    1 +
> >  drivers/usb/dwc3/dwc3-msm.c                        |  175 ++++++++++++++++++++
> >  4 files changed, 223 insertions(+)
> >  create mode 100644 drivers/usb/dwc3/dwc3-msm.c
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > index 550b496..313ae0d 100644
> > --- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > @@ -22,6 +22,23 @@ Required "supply-name" examples are:
> >  	"v1p8" : 1.8v supply for SS-PHY
> >  	"vddcx" : vdd supply for SS-PHY digital circuit operation
> >  
> > +Required properties :
> > +- compatible : should be "qcom,dwc-usb3-msm"
> > +- reg : offset and length of the register set in the memory map
> > +	offset and length of the TCSR register for routing USB
> > +	signals to either picoPHY0 or picoPHY1.
> > +- clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
> > +- clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
> > +
> > +Optional properties :
> > +- gdsc-supply : phandle to the globally distributed switch controller
> > +  regulator node to the USB controller.
> > +
> > +Sub nodes:
> > +- Sub node for "DWC3- USB3 controller".
> > +  This sub node is required property for device node. The properties of this subnode
> > +  are specified in dwc3.txt.
> 
> Ah, this answers one of my questions - DWC3 comes from Synopsys.

Yes, sorry.

> 
> >  Example device nodes:
> >  
> >  	dwc3_usb2: phy@f92f8800 {
> > @@ -47,3 +64,25 @@ Example device nodes:
> >  		vddcx-supply = <&supply>;
> >  		v1p8-supply = <&supply>;
> >  	};
> > +
> > +	usb@fd4ab000 {
> > +		compatible = "qcom,dwc-usb3-msm";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0xfd4ab000 0x4>;
> > +
> > +		clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
> > +		clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
> > +
> > +		gdsc-supply = <&supply>;
> > +		ranges;
> > +
> > +		dwc3@f9200000 {
> > +			compatible = "snps,dwc3";
> 
> Note that the Documentation/devicetree/bindings/usb/dwc3.txt is
> mentioning "synopsys,dwc3" (which is clearly in opposition to the
> vendor-prefixes.txt file) and this compatible value is used in the
> drivers/usb/dwc3/core.c and omap5.dtsi. Unless it has been already fixed
> recently, could you take care of that?

Yes, it is fixed already. Patch is in linux-next 
"usb: dwc3: core: switch to snps,dwc3"

> 
> > +			reg = <0xf9200000 0xcd00>;
> > +			interrupts = <0 131 0>;
> > +			interrupt-names = "irq";
> > +			usb-phy = <&dwc3_usb2>, <&dwc3_usb3>;
> > +			tx-fifo-resize;
> > +		};
> > +	};
> 
> And now I'm really confused... Maybe it's just lack of documentation...
> 
> How does the "qcom,dwc-usb3-msm" relate to "qcom,dwc-usb3"?

Not sure from where you get this "qcom,dwc-usb3", but now I think
that "qcom,dwc-usb3" should be enough for compatible.  

Thanks, 
Ivan

> 
> Paweł

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Pawel Moll]

On Tue, 2013-08-06 at 14:46 +0100, Ivan T. Ivanov wrote:
> > > +			reg = <0xf9200000 0xcd00>;
> > > +			interrupts = <0 131 0>;
> > > +			interrupt-names = "irq";
> > > +			usb-phy = <&dwc3_usb2>, <&dwc3_usb3>;
> > > +			tx-fifo-resize;
> > > +		};
> > > +	};
> > 
> > And now I'm really confused... Maybe it's just lack of documentation...
> > 
> > How does the "qcom,dwc-usb3-msm" relate to "qcom,dwc-usb3"?
> 
> Not sure from where you get this "qcom,dwc-usb3", but now I think
> that "qcom,dwc-usb3" should be enough for compatible.  

The other patch introduces "qcom,dwc3-usb3" compatible value...

Paweł

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Ivan T. Ivanov]

On Tue, 2013-08-06 at 16:15 +0100, Pawel Moll wrote:
> On Tue, 2013-08-06 at 14:46 +0100, Ivan T. Ivanov wrote:
> > > > +			reg = <0xf9200000 0xcd00>;
> > > > +			interrupts = <0 131 0>;
> > > > +			interrupt-names = "irq";
> > > > +			usb-phy = <&dwc3_usb2>, <&dwc3_usb3>;
> > > > +			tx-fifo-resize;
> > > > +		};
> > > > +	};
> > > 
> > > And now I'm really confused... Maybe it's just lack of documentation...
> > > 
> > > How does the "qcom,dwc-usb3-msm" relate to "qcom,dwc-usb3"?
> > 
> > Not sure from where you get this "qcom,dwc-usb3", but now I think
> > that "qcom,dwc-usb3" should be enough for compatible.  
> 
> The other patch introduces "qcom,dwc3-usb3" compatible value...

Oh, of course. Intention was that "qcom,dwc-usb3" will handle SS-PHY, 
while "qcom,dwc-usb2" will handle HS-PHY. Probably it will better if
I rename them to "qcom,dwc-ssphy" and "qcom,dwc-hsphy".

Regards,
Ivan

> 
> Paweł

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 856 bytes --]

Hi,

On Tue, Aug 06, 2013 at 01:21:38PM +0100, Pawel Moll wrote:
> > @@ -47,3 +64,25 @@ Example device nodes:
> >  		vddcx-supply = <&supply>;
> >  		v1p8-supply = <&supply>;
> >  	};
> > +
> > +	usb@fd4ab000 {
> > +		compatible = "qcom,dwc-usb3-msm";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0xfd4ab000 0x4>;
> > +
> > +		clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
> > +		clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
> > +
> > +		gdsc-supply = <&supply>;
> > +		ranges;
> > +
> > +		dwc3@f9200000 {
> > +			compatible = "snps,dwc3";
> 
> Note that the Documentation/devicetree/bindings/usb/dwc3.txt is
> mentioning "synopsys,dwc3" (which is clearly in opposition to the

I have a patch converting to snps,dwc3.

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Mark Rutland]

On Tue, Aug 06, 2013 at 12:53:11PM +0100, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov" <iivanov@mm-sol.com>

What does the "glue layer" do? Is it an actual piece of hardware, or
just some platform-specific code?

> 
> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> ---
>  .../devicetree/bindings/usb/msm-ssusb.txt          |   39 +++++
>  drivers/usb/dwc3/Kconfig                           |    8 +
>  drivers/usb/dwc3/Makefile                          |    1 +
>  drivers/usb/dwc3/dwc3-msm.c                        |  175 ++++++++++++++++++++
>  4 files changed, 223 insertions(+)
>  create mode 100644 drivers/usb/dwc3/dwc3-msm.c
> 
> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> index 550b496..313ae0d 100644
> --- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> @@ -22,6 +22,23 @@ Required "supply-name" examples are:
>  	"v1p8" : 1.8v supply for SS-PHY
>  	"vddcx" : vdd supply for SS-PHY digital circuit operation
>  
> +Required properties :
> +- compatible : should be "qcom,dwc-usb3-msm"
> +- reg : offset and length of the register set in the memory map
> +	offset and length of the TCSR register for routing USB
> +	signals to either picoPHY0 or picoPHY1.
> +- clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;

Similarly to my comment on patch 1, these need to be described better.

Thanks,
Mark.

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Ivan T. Ivanov]

Hi, 

On Tue, 2013-08-06 at 15:07 +0100, Mark Rutland wrote:
> On Tue, Aug 06, 2013 at 12:53:11PM +0100, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> 
> What does the "glue layer" do? Is it an actual piece of hardware, or
> just some platform-specific code?
> 

It is hardware layer around Synopsys DesignWare USB3 core. The 
term 'glue layer' is what is used in TI OMAP's and Samsung Exynos
drivers implementations.

> > 
> > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> > ---
> >  .../devicetree/bindings/usb/msm-ssusb.txt          |   39 +++++
> >  drivers/usb/dwc3/Kconfig                           |    8 +
> >  drivers/usb/dwc3/Makefile                          |    1 +
> >  drivers/usb/dwc3/dwc3-msm.c                        |  175 ++++++++++++++++++++
> >  4 files changed, 223 insertions(+)
> >  create mode 100644 drivers/usb/dwc3/dwc3-msm.c
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > index 550b496..313ae0d 100644
> > --- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > @@ -22,6 +22,23 @@ Required "supply-name" examples are:
> >  	"v1p8" : 1.8v supply for SS-PHY
> >  	"vddcx" : vdd supply for SS-PHY digital circuit operation
> >  
> > +Required properties :
> > +- compatible : should be "qcom,dwc-usb3-msm"
> > +- reg : offset and length of the register set in the memory map
> > +	offset and length of the TCSR register for routing USB
> > +	signals to either picoPHY0 or picoPHY1.
> > +- clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
> 
> Similarly to my comment on patch 1, these need to be described better.

Sure, will fix this.

Thanks, 
Ivan

> 
> Thanks,
> Mark.

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 2229 bytes --]

Hi,

On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
> diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
> new file mode 100644
> index 0000000..e509abc
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-msm.c
> @@ -0,0 +1,175 @@
> +#undef CONFIG_REGULATOR

why ??????

> +static int dwc3_msm_probe(struct platform_device *pdev)
> +{
> +	struct device_node *node = pdev->dev.of_node;
> +	struct dwc3_msm *mdwc;
> +	struct resource *res;
> +	void __iomem *tcsr;
> +	int ret = 0;
> +
> +	dev_info(&pdev->dev, "MSM DWC3\n");

please don't. This is hardly necessary.

> +	mdwc = devm_kzalloc(&pdev->dev, sizeof(*mdwc), GFP_KERNEL);
> +	if (!mdwc) {
> +		dev_err(&pdev->dev, "not enough memory\n");

this message isn't needed either

> +	/*
> +	 * DWC3 Core requires its CORE CLK (aka master / bus clk) to
> +	 * run at 125Mhz in SSUSB mode and >60MHZ for HSUSB mode.
> +	 */
> +	clk_set_rate(mdwc->core_clk, 125000000);

if this is dwc3's core clock, why don't we teach dwc3.ko about this
requirement ? Just make sure to have it optional, since x86 and OMAP
wouldn't need direct fiddling with the clocks.

> +	clk_prepare_enable(mdwc->core_clk);
> +	clk_prepare_enable(mdwc->iface_clk);
> +	clk_prepare_enable(mdwc->sleep_clk);
> +	clk_prepare_enable(mdwc->utmi_clk);

do you really need to enable your clocks here ? Why don't you enable
them on runtime_resume and disable on runtime_suspend ?

> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	tcsr = devm_ioremap_resource(&pdev->dev, res);
> +	if (!tcsr) {
> +		dev_dbg(&pdev->dev, "tcsr ioremap failed\n");

no need to ioremap, also you're likely leaking clocks and regulators
enabled here.

Make sure to have something like:

	if (!tcsr)
		goto err_disable_clocks;

	/* TODO This has to be revised */\

	[...]

> +	} else {
> +		/* TODO: This has to be revised */
> +
> +		/* Enable USB3 on the primary USB port. */
> +		writel_relaxed(0x1, tcsr);
> +		/*
> +		 * Ensure that TCSR write is completed before
> +		 * USB registers initialization.
> +		 */
> +		mb();

why don't you use writel() instead. It will add the memory barrier for
you.

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 2229 bytes --]

Hi,

On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
> diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
> new file mode 100644
> index 0000000..e509abc
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-msm.c
> @@ -0,0 +1,175 @@
> +#undef CONFIG_REGULATOR

why ??????

> +static int dwc3_msm_probe(struct platform_device *pdev)
> +{
> +	struct device_node *node = pdev->dev.of_node;
> +	struct dwc3_msm *mdwc;
> +	struct resource *res;
> +	void __iomem *tcsr;
> +	int ret = 0;
> +
> +	dev_info(&pdev->dev, "MSM DWC3\n");

please don't. This is hardly necessary.

> +	mdwc = devm_kzalloc(&pdev->dev, sizeof(*mdwc), GFP_KERNEL);
> +	if (!mdwc) {
> +		dev_err(&pdev->dev, "not enough memory\n");

this message isn't needed either

> +	/*
> +	 * DWC3 Core requires its CORE CLK (aka master / bus clk) to
> +	 * run at 125Mhz in SSUSB mode and >60MHZ for HSUSB mode.
> +	 */
> +	clk_set_rate(mdwc->core_clk, 125000000);

if this is dwc3's core clock, why don't we teach dwc3.ko about this
requirement ? Just make sure to have it optional, since x86 and OMAP
wouldn't need direct fiddling with the clocks.

> +	clk_prepare_enable(mdwc->core_clk);
> +	clk_prepare_enable(mdwc->iface_clk);
> +	clk_prepare_enable(mdwc->sleep_clk);
> +	clk_prepare_enable(mdwc->utmi_clk);

do you really need to enable your clocks here ? Why don't you enable
them on runtime_resume and disable on runtime_suspend ?

> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	tcsr = devm_ioremap_resource(&pdev->dev, res);
> +	if (!tcsr) {
> +		dev_dbg(&pdev->dev, "tcsr ioremap failed\n");

no need to ioremap, also you're likely leaking clocks and regulators
enabled here.

Make sure to have something like:

	if (!tcsr)
		goto err_disable_clocks;

	/* TODO This has to be revised */\

	[...]

> +	} else {
> +		/* TODO: This has to be revised */
> +
> +		/* Enable USB3 on the primary USB port. */
> +		writel_relaxed(0x1, tcsr);
> +		/*
> +		 * Ensure that TCSR write is completed before
> +		 * USB registers initialization.
> +		 */
> +		mb();

why don't you use writel() instead. It will add the memory barrier for
you.

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Ivan T. Ivanov]

Hi, 

On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:
> Hi,
> 
> On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
> > diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
> > new file mode 100644
> > index 0000000..e509abc
> > --- /dev/null
> > +++ b/drivers/usb/dwc3/dwc3-msm.c
> > @@ -0,0 +1,175 @@
> > +#undef CONFIG_REGULATOR
> 
> why ??????
> 

1. This shows that driver is still not fully tested 
   Regulators support is still missing in the MSM
2. Helps me to load driver successfully. 

> > +static int dwc3_msm_probe(struct platform_device *pdev)
> > +{
> > +	struct device_node *node = pdev->dev.of_node;
> > +	struct dwc3_msm *mdwc;
> > +	struct resource *res;
> > +	void __iomem *tcsr;
> > +	int ret = 0;
> > +
> > +	dev_info(&pdev->dev, "MSM DWC3\n");
> 
> please don't. This is hardly necessary.

Sure, this will be removed.

> 
> > +	mdwc = devm_kzalloc(&pdev->dev, sizeof(*mdwc), GFP_KERNEL);
> > +	if (!mdwc) {
> > +		dev_err(&pdev->dev, "not enough memory\n");
> 
> this message isn't needed either

ok.

> 
> > +	/*
> > +	 * DWC3 Core requires its CORE CLK (aka master / bus clk) to
> > +	 * run at 125Mhz in SSUSB mode and >60MHZ for HSUSB mode.
> > +	 */
> > +	clk_set_rate(mdwc->core_clk, 125000000);
> 
> if this is dwc3's core clock, why don't we teach dwc3.ko about this
> requirement ? Just make sure to have it optional, since x86 and OMAP
> wouldn't need direct fiddling with the clocks.

I have to check whether DWC3 core or Qcom wrapper requires this clock.

> 
> > +	clk_prepare_enable(mdwc->core_clk);
> > +	clk_prepare_enable(mdwc->iface_clk);
> > +	clk_prepare_enable(mdwc->sleep_clk);
> > +	clk_prepare_enable(mdwc->utmi_clk);
> 
> do you really need to enable your clocks here ? Why don't you enable
> them on runtime_resume and disable on runtime_suspend ?

I will like to make it working first and then will improve
power management.

> 
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	tcsr = devm_ioremap_resource(&pdev->dev, res);
> > +	if (!tcsr) {
> > +		dev_dbg(&pdev->dev, "tcsr ioremap failed\n");
> 
> no need to ioremap, also you're likely leaking clocks and regulators
> enabled here.
> 
> Make sure to have something like:
> 
> 	if (!tcsr)
> 		goto err_disable_clocks;
> 
> 	/* TODO This has to be revised */\
> 
> 	[...]
> 

Sure.

> > +	} else {
> > +		/* TODO: This has to be revised */
> > +
> > +		/* Enable USB3 on the primary USB port. */
> > +		writel_relaxed(0x1, tcsr);
> > +		/*
> > +		 * Ensure that TCSR write is completed before
> > +		 * USB registers initialization.
> > +		 */
> > +		mb();
> 
> why don't you use writel() instead. It will add the memory barrier for
> you.

Ok.

Thanks
Ivan

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1743 bytes --]

On Fri, Aug 09, 2013 at 07:09:18PM +0300, Ivan T. Ivanov wrote:
> Hi, 
> 
> On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:
> > Hi,
> > 
> > On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
> > > diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
> > > new file mode 100644
> > > index 0000000..e509abc
> > > --- /dev/null
> > > +++ b/drivers/usb/dwc3/dwc3-msm.c
> > > @@ -0,0 +1,175 @@
> > > +#undef CONFIG_REGULATOR
> > 
> > why ??????
> > 
> 
> 1. This shows that driver is still not fully tested 
>    Regulators support is still missing in the MSM
> 2. Helps me to load driver successfully. 

Then remove all the regulator-related code from this.

> > > +	clk_prepare_enable(mdwc->core_clk);
> > > +	clk_prepare_enable(mdwc->iface_clk);
> > > +	clk_prepare_enable(mdwc->sleep_clk);
> > > +	clk_prepare_enable(mdwc->utmi_clk);
> > 
> > do you really need to enable your clocks here ? Why don't you enable
> > them on runtime_resume and disable on runtime_suspend ?
> 
> I will like to make it working first and then will improve
> power management.

alright, makes sense.

> > > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > +	tcsr = devm_ioremap_resource(&pdev->dev, res);
> > > +	if (!tcsr) {
> > > +		dev_dbg(&pdev->dev, "tcsr ioremap failed\n");
> > 
> > no need to ioremap, also you're likely leaking clocks and regulators
> > enabled here.
> > 
> > Make sure to have something like:
> > 
> > 	if (!tcsr)
> > 		goto err_disable_clocks;
> > 
> > 	/* TODO This has to be revised */\
> > 
> > 	[...]
> > 
> 
> Sure.

just to make it clear, I meant to say that you don't need to print the
error message :-)

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1743 bytes --]

On Fri, Aug 09, 2013 at 07:09:18PM +0300, Ivan T. Ivanov wrote:
> Hi, 
> 
> On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:
> > Hi,
> > 
> > On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
> > > diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
> > > new file mode 100644
> > > index 0000000..e509abc
> > > --- /dev/null
> > > +++ b/drivers/usb/dwc3/dwc3-msm.c
> > > @@ -0,0 +1,175 @@
> > > +#undef CONFIG_REGULATOR
> > 
> > why ??????
> > 
> 
> 1. This shows that driver is still not fully tested 
>    Regulators support is still missing in the MSM
> 2. Helps me to load driver successfully. 

Then remove all the regulator-related code from this.

> > > +	clk_prepare_enable(mdwc->core_clk);
> > > +	clk_prepare_enable(mdwc->iface_clk);
> > > +	clk_prepare_enable(mdwc->sleep_clk);
> > > +	clk_prepare_enable(mdwc->utmi_clk);
> > 
> > do you really need to enable your clocks here ? Why don't you enable
> > them on runtime_resume and disable on runtime_suspend ?
> 
> I will like to make it working first and then will improve
> power management.

alright, makes sense.

> > > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > +	tcsr = devm_ioremap_resource(&pdev->dev, res);
> > > +	if (!tcsr) {
> > > +		dev_dbg(&pdev->dev, "tcsr ioremap failed\n");
> > 
> > no need to ioremap, also you're likely leaking clocks and regulators
> > enabled here.
> > 
> > Make sure to have something like:
> > 
> > 	if (!tcsr)
> > 		goto err_disable_clocks;
> > 
> > 	/* TODO This has to be revised */\
> > 
> > 	[...]
> > 
> 
> Sure.

just to make it clear, I meant to say that you don't need to print the
error message :-)

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Ivan T. Ivanov]

Hi, 

On Mon, 2013-08-12 at 13:24 -0500, Felipe Balbi wrote: 
> On Fri, Aug 09, 2013 at 07:09:18PM +0300, Ivan T. Ivanov wrote:
> > Hi, 
> > 
> > On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:
> > > Hi,
> > > 
> > > On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
> > > > diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
> > > > new file mode 100644
> > > > index 0000000..e509abc
> > > > --- /dev/null
> > > > +++ b/drivers/usb/dwc3/dwc3-msm.c
> > > > @@ -0,0 +1,175 @@
> > > > +#undef CONFIG_REGULATOR
> > > 
> > > why ??????
> > > 
> > 
> > 1. This shows that driver is still not fully tested 
> >    Regulators support is still missing in the MSM
> > 2. Helps me to load driver successfully. 
> 
> Then remove all the regulator-related code from this.

I would like to keep them. I will just remove #undef line. 
Code will continue to build fine. And once regulators drivers 
are upstreamed this driver 'will not' require further
modifications.

> 
> > > > +	clk_prepare_enable(mdwc->core_clk);
> > > > +	clk_prepare_enable(mdwc->iface_clk);
> > > > +	clk_prepare_enable(mdwc->sleep_clk);
> > > > +	clk_prepare_enable(mdwc->utmi_clk);
> > > 
> > > do you really need to enable your clocks here ? Why don't you enable
> > > them on runtime_resume and disable on runtime_suspend ?
> > 
> > I will like to make it working first and then will improve
> > power management.
> 
> alright, makes sense.
> 
> > > > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > > +	tcsr = devm_ioremap_resource(&pdev->dev, res);
> > > > +	if (!tcsr) {
> > > > +		dev_dbg(&pdev->dev, "tcsr ioremap failed\n");
> > > 
> > > no need to ioremap, also you're likely leaking clocks and regulators
> > > enabled here.
> > > 
> > > Make sure to have something like:
> > > 
> > > 	if (!tcsr)
> > > 		goto err_disable_clocks;
> > > 
> > > 	/* TODO This has to be revised */\
> > > 
> > > 	[...]
> > > 
> > 
> > Sure.
> 
> just to make it clear, I meant to say that you don't need to print the
> error message :-)

Yes. I got it.

Regards,
Ivan

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1187 bytes --]

On Wed, Aug 14, 2013 at 12:28:17PM +0300, Ivan T. Ivanov wrote:
> 
> Hi, 
> 
> On Mon, 2013-08-12 at 13:24 -0500, Felipe Balbi wrote: 
> > On Fri, Aug 09, 2013 at 07:09:18PM +0300, Ivan T. Ivanov wrote:
> > > Hi, 
> > > 
> > > On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:
> > > > Hi,
> > > > 
> > > > On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
> > > > > diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
> > > > > new file mode 100644
> > > > > index 0000000..e509abc
> > > > > --- /dev/null
> > > > > +++ b/drivers/usb/dwc3/dwc3-msm.c
> > > > > @@ -0,0 +1,175 @@
> > > > > +#undef CONFIG_REGULATOR
> > > > 
> > > > why ??????
> > > > 
> > > 
> > > 1. This shows that driver is still not fully tested 
> > >    Regulators support is still missing in the MSM
> > > 2. Helps me to load driver successfully. 
> > 
> > Then remove all the regulator-related code from this.
> 
> I would like to keep them. I will just remove #undef line. 
> Code will continue to build fine. And once regulators drivers 
> are upstreamed this driver 'will not' require further
> modifications.

fair enough.

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1187 bytes --]

On Wed, Aug 14, 2013 at 12:28:17PM +0300, Ivan T. Ivanov wrote:
> 
> Hi, 
> 
> On Mon, 2013-08-12 at 13:24 -0500, Felipe Balbi wrote: 
> > On Fri, Aug 09, 2013 at 07:09:18PM +0300, Ivan T. Ivanov wrote:
> > > Hi, 
> > > 
> > > On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:
> > > > Hi,
> > > > 
> > > > On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
> > > > > diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
> > > > > new file mode 100644
> > > > > index 0000000..e509abc
> > > > > --- /dev/null
> > > > > +++ b/drivers/usb/dwc3/dwc3-msm.c
> > > > > @@ -0,0 +1,175 @@
> > > > > +#undef CONFIG_REGULATOR
> > > > 
> > > > why ??????
> > > > 
> > > 
> > > 1. This shows that driver is still not fully tested 
> > >    Regulators support is still missing in the MSM
> > > 2. Helps me to load driver successfully. 
> > 
> > Then remove all the regulator-related code from this.
> 
> I would like to keep them. I will just remove #undef line. 
> Code will continue to build fine. And once regulators drivers 
> are upstreamed this driver 'will not' require further
> modifications.

fair enough.

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [RFC 2/2] usb: dwc3: Add Qualcomm DWC3 glue layer driver

[Ivan T. Ivanov]

Hi, 

On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:

<snip>

> 
> > +	/*
> > +	 * DWC3 Core requires its CORE CLK (aka master / bus clk) to
> > +	 * run at 125Mhz in SSUSB mode and >60MHZ for HSUSB mode.
> > +	 */
> > +	clk_set_rate(mdwc->core_clk, 125000000);
> 
> if this is dwc3's core clock, why don't we teach dwc3.ko about this
> requirement ? Just make sure to have it optional, since x86 and OMAP
> wouldn't need direct fiddling with the clocks.

I believe this is Qualcomm specific requirement. Something is modified
inside DWC in respect of the clocks. I will like to keep this here, in
the glue layer driver.

Regards,
Ivan