[U-Boot] [PATCH V2 0/4]ARM: AM33xx: Cleanup clocks and hwinit

[U-Boot] [PATCH V2 0/4]ARM: AM33xx: Cleanup clocks and hwinit

[Lokesh Vutla]

This series tries to cleanup code for AM33xx,
inorder to ensure code reusabilty by moving the
duplicated code to common place.
This also helps in addition of new Soc with minimal
changes.

Testing:
Boot tested on BeagleBone White/Black, AM35xx EVM/EVMSK.
Verified ./MAKEALL -s am33xx.

Changes Since V1:
- Rebased on top of u-boot-ti
- Created a function get_dpll_ddr_params() for getting
  ddr dpll params from board files.
- Updated License header for newly created files.

Heiko Schocher (1):
  ARM: AM33xx: Move s_init to a common place

Lokesh Vutla (3):
  ARM: AM33xx: Cleanup dplls data
  ARM: AM33xx: Cleanup clocks layer
  musb: Disable extra prints

 arch/arm/cpu/armv7/am33xx/Makefile               |    1 +
 arch/arm/cpu/armv7/am33xx/board.c                |   68 ++-
 arch/arm/cpu/armv7/am33xx/clock.c                |  171 ++++++++
 arch/arm/cpu/armv7/am33xx/clock_am33xx.c         |  495 +++++-----------------
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c         |   25 +-
 arch/arm/cpu/armv7/am33xx/emif4.c                |    5 +-
 arch/arm/include/asm/arch-am33xx/clock.h         |   94 ++++
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |    6 +-
 arch/arm/include/asm/arch-am33xx/sys_proto.h     |    9 +-
 board/isee/igep0033/board.c                      |   55 +--
 board/phytec/pcm051/board.c                      |   57 +--
 board/ti/am335x/board.c                          |  102 ++---
 board/ti/am335x/mux.c                            |   19 +
 board/ti/ti814x/evm.c                            |   65 +--
 drivers/usb/musb-new/musb_core.c                 |   20 +-
 15 files changed, 573 insertions(+), 619 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c

-- 
1.7.9.5

[U-Boot] [PATCH V2 1/4] ARM: AM33xx: Cleanup dplls data

[Lokesh Vutla]

Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.

This is derived from OMAP4 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/am33xx/Makefile           |    1 +
 arch/arm/cpu/armv7/am33xx/clock.c            |  111 +++++++++++++
 arch/arm/cpu/armv7/am33xx/clock_am33xx.c     |  220 +++++---------------------
 arch/arm/cpu/armv7/am33xx/emif4.c            |    4 +
 arch/arm/include/asm/arch-am33xx/clock.h     |   70 ++++++++
 arch/arm/include/asm/arch-am33xx/ddr_defs.h  |    2 +
 arch/arm/include/asm/arch-am33xx/sys_proto.h |    1 +
 board/isee/igep0033/board.c                  |   10 ++
 board/phytec/pcm051/board.c                  |    9 ++
 board/ti/am335x/board.c                      |   27 ++++
 10 files changed, 273 insertions(+), 182 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c

diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index dbd1ec3..7fd21af 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -10,6 +10,7 @@ LIB	= $(obj)lib$(SOC).o
 
 COBJS-$(CONFIG_AM33XX)	+= clock_am33xx.o
 COBJS-$(CONFIG_TI814X)	+= clock_ti814x.o
+COBJS-$(CONFIG_AM33XX)	+= clock.o
 COBJS	+= sys_info.o
 COBJS	+= mem.o
 COBJS	+= ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 0000000..15f4a2c
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,111 @@
+/*
+ * clock.c
+ *
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+			 const struct dpll_params *params)
+{
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, dpll_regs->cm_div_m6_dpll);
+}
+
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+		hang();
+	}
+}
+
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("Bypassing DPLL failed 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+	}
+}
+
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	do_bypass_dpll(dpll_regs);
+	wait_for_bypass(dpll_regs);
+}
+
+void do_setup_dpll(const struct dpll_regs *dpll_regs,
+		   const struct dpll_params *params)
+{
+	u32 temp;
+
+	if (!params)
+		return;
+
+	temp = readl(dpll_regs->cm_clksel_dpll);
+
+	bypass_dpll(dpll_regs);
+
+	/* Set M & N */
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, dpll_regs->cm_clksel_dpll);
+
+	setup_post_dividers(dpll_regs, params);
+
+	/* Wait till the DPLL locks */
+	do_lock_dpll(dpll_regs);
+	wait_for_lock(dpll_regs);
+}
+
+void setup_dplls(void)
+{
+	const struct dpll_params *params;
+	do_setup_dpll(&dpll_core_regs, &dpll_core);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
+	do_setup_dpll(&dpll_per_regs, &dpll_per);
+	writel(0x300, &cmwkup->clkdcoldodpllper);
+
+	params = get_dpll_ddr_params();
+	do_setup_dpll(&dpll_ddr_regs, params);
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index fb3fb43..d5d47ad 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -18,56 +18,51 @@
 #define PRCM_FORCE_WAKEUP	0x2
 #define PRCM_FUNCTL		0x0
 
-#define PRCM_EMIF_CLK_ACTIVITY	BIT(2)
-#define PRCM_L3_GCLK_ACTIVITY	BIT(4)
-
-#define PLL_BYPASS_MODE		0x4
-#define ST_MN_BYPASS		0x00000100
-#define ST_DPLL_CLK		0x00000001
-#define CLK_SEL_MASK		0x7ffff
-#define CLK_DIV_MASK		0x1f
-#define CLK_DIV2_MASK		0x7f
-#define CLK_SEL_SHIFT		0x8
-#define CLK_MODE_SEL		0x7
-#define CLK_MODE_MASK		0xfffffff8
-#define CLK_DIV_SEL		0xFFFFFFE0
 #define CPGMAC0_IDLE		0x30000
-#define DPLL_CLKDCOLDO_GATE_CTRL        0x300
-
 #define OSC	(V_OSCK/1000000)
 
-#define MPUPLL_M	CONFIG_SYS_MPUCLK
-#define MPUPLL_N	(OSC-1)
-#define MPUPLL_M2	1
-
-/* Core PLL Fdll = 1 GHZ, */
-#define COREPLL_M	1000
-#define COREPLL_N	(OSC-1)
-
-#define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
-#define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
-#define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
-
-/*
- * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
- * frequency needs to be set to 960 MHZ. Hence,
- * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
- */
-#define PERPLL_M	960
-#define PERPLL_N	(OSC-1)
-#define PERPLL_M2	5
-
-/* DDR Freq is 266 MHZ for now */
-/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
-#define DDRPLL_M	266
-#define DDRPLL_N	(OSC-1)
-#define DDRPLL_M2	1
-
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
 const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
 
+const struct dpll_regs dpll_mpu_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x88,
+	.cm_idlest_dpll		= CM_WKUP + 0x20,
+	.cm_clksel_dpll		= CM_WKUP + 0x2C,
+	.cm_div_m2_dpll		= CM_WKUP + 0xA8,
+};
+
+const struct dpll_regs dpll_core_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x90,
+	.cm_idlest_dpll		= CM_WKUP + 0x5C,
+	.cm_clksel_dpll		= CM_WKUP + 0x68,
+	.cm_div_m4_dpll		= CM_WKUP + 0x80,
+	.cm_div_m5_dpll		= CM_WKUP + 0x84,
+	.cm_div_m6_dpll		= CM_WKUP + 0xD8,
+};
+
+const struct dpll_regs dpll_per_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x8C,
+	.cm_idlest_dpll		= CM_WKUP + 0x70,
+	.cm_clksel_dpll		= CM_WKUP + 0x9C,
+	.cm_div_m2_dpll		= CM_WKUP + 0xAC,
+};
+
+const struct dpll_regs dpll_ddr_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x94,
+	.cm_idlest_dpll		= CM_WKUP + 0x34,
+	.cm_clksel_dpll		= CM_WKUP + 0x40,
+	.cm_div_m2_dpll		= CM_WKUP + 0xA0,
+};
+
+const struct dpll_params dpll_mpu = {
+		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+		1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_per = {
+		960, OSC-1, 5, -1, -1, -1, -1};
+
 static void enable_interface_clocks(void)
 {
 	/* Enable all the Interconnect Modules */
@@ -238,142 +233,6 @@ static void enable_per_clocks(void)
 		;
 }
 
-void mpu_pll_config_val(int mpull_m)
-{
-	u32 clkmode, clksel, div_m2;
-
-	clkmode = readl(&cmwkup->clkmoddpllmpu);
-	clksel = readl(&cmwkup->clkseldpllmpu);
-	div_m2 = readl(&cmwkup->divm2dpllmpu);
-
-	/* Set the PLL to bypass Mode */
-	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
-	while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
-	writel(clksel, &cmwkup->clkseldpllmpu);
-
-	div_m2 = div_m2 & ~CLK_DIV_MASK;
-	div_m2 = div_m2 | MPUPLL_M2;
-	writel(div_m2, &cmwkup->divm2dpllmpu);
-
-	clkmode = clkmode | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllmpu);
-
-	while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
-		;
-}
-
-static void mpu_pll_config(void)
-{
-	mpu_pll_config_val(CONFIG_SYS_MPUCLK);
-}
-
-static void core_pll_config(void)
-{
-	u32 clkmode, clksel, div_m4, div_m5, div_m6;
-
-	clkmode = readl(&cmwkup->clkmoddpllcore);
-	clksel = readl(&cmwkup->clkseldpllcore);
-	div_m4 = readl(&cmwkup->divm4dpllcore);
-	div_m5 = readl(&cmwkup->divm5dpllcore);
-	div_m6 = readl(&cmwkup->divm6dpllcore);
-
-	/* Set the PLL to bypass Mode */
-	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
-
-	while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
-	writel(clksel, &cmwkup->clkseldpllcore);
-
-	div_m4 = div_m4 & ~CLK_DIV_MASK;
-	div_m4 = div_m4 | COREPLL_M4;
-	writel(div_m4, &cmwkup->divm4dpllcore);
-
-	div_m5 = div_m5 & ~CLK_DIV_MASK;
-	div_m5 = div_m5 | COREPLL_M5;
-	writel(div_m5, &cmwkup->divm5dpllcore);
-
-	div_m6 = div_m6 & ~CLK_DIV_MASK;
-	div_m6 = div_m6 | COREPLL_M6;
-	writel(div_m6, &cmwkup->divm6dpllcore);
-
-	clkmode = clkmode | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllcore);
-
-	while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
-		;
-}
-
-static void per_pll_config(void)
-{
-	u32 clkmode, clksel, div_m2;
-
-	clkmode = readl(&cmwkup->clkmoddpllper);
-	clksel = readl(&cmwkup->clkseldpllper);
-	div_m2 = readl(&cmwkup->divm2dpllper);
-
-	/* Set the PLL to bypass Mode */
-	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
-
-	while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
-	writel(clksel, &cmwkup->clkseldpllper);
-
-	div_m2 = div_m2 & ~CLK_DIV2_MASK;
-	div_m2 = div_m2 | PERPLL_M2;
-	writel(div_m2, &cmwkup->divm2dpllper);
-
-	clkmode = clkmode | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllper);
-
-	while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
-		;
-
-	writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
-}
-
-void ddr_pll_config(unsigned int ddrpll_m)
-{
-	u32 clkmode, clksel, div_m2;
-
-	clkmode = readl(&cmwkup->clkmoddpllddr);
-	clksel = readl(&cmwkup->clkseldpllddr);
-	div_m2 = readl(&cmwkup->divm2dpllddr);
-
-	/* Set the PLL to bypass Mode */
-	clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
-	writel(clkmode, &cmwkup->clkmoddpllddr);
-
-	/* Wait till bypass mode is enabled */
-	while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
-				!= ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
-	writel(clksel, &cmwkup->clkseldpllddr);
-
-	div_m2 = div_m2 & CLK_DIV_SEL;
-	div_m2 = div_m2 | DDRPLL_M2;
-	writel(div_m2, &cmwkup->divm2dpllddr);
-
-	clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllddr);
-
-	/* Wait till dpll is locked */
-	while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
-		;
-}
-
 void enable_emif_clocks(void)
 {
 	/* Enable the  EMIF_FW Functional clock */
@@ -390,10 +249,7 @@ void enable_emif_clocks(void)
  */
 void pll_init()
 {
-	mpu_pll_config();
-	core_pll_config();
-	per_pll_config();
-
+	setup_dplls();
 	/* Enable the required interconnect clocks */
 	enable_interface_clocks();
 
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 55dc321..15c4734 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -79,6 +79,10 @@ static void config_vtp(int nr)
 		;
 }
 
+void __weak ddr_pll_config(unsigned int ddrpll_m)
+{
+}
+
 void config_ddr(unsigned int pll, unsigned int ioctrl,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr)
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 44c1e5d..703b80e 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -13,4 +13,74 @@
 
 #include <asm/arch/clocks_am33xx.h>
 
+#define LDELAY 1000000
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+
+struct dpll_params {
+	u32 m;
+	u32 n;
+	s8 m2;
+	s8 m3;
+	s8 m4;
+	s8 m5;
+	s8 m6;
+};
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+};
+
+extern const struct dpll_regs dpll_mpu_regs;
+extern const struct dpll_regs dpll_core_regs;
+extern const struct dpll_regs dpll_per_regs;
+extern const struct dpll_regs dpll_ddr_regs;
+extern const struct dpll_params dpll_mpu;
+extern const struct dpll_params dpll_core;
+extern const struct dpll_params dpll_per;
+extern const struct dpll_params dpll_ddr;
+
+extern const struct cm_wkuppll *cmwkup;
+
+void setup_dplls(void);
+const struct dpll_params *get_dpll_ddr_params(void);
+void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
+
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 18d7d99..683ba8e 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -146,6 +146,8 @@ void set_sdram_timings(const struct emif_regs *regs, int nr);
  */
 void config_ddr_phy(const struct emif_regs *regs, int nr);
 
+void ddr_pll_config(unsigned int ddrpll_m);
+
 struct ddr_cmd_regs {
 	unsigned int resv0[7];
 	unsigned int cm0csratio;	/* offset 0x01C */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 1424f90..dbcede0 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -37,4 +37,5 @@ void omap_nand_switch_ecc(uint32_t, uint32_t);
 
 void rtc32k_enable(void);
 void uart_soft_reset(void);
+u32 wait_on_value(u32, u32, void *, u32);
 #endif
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index c0f0c0d..034a8aa 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -66,6 +66,16 @@ static struct emif_regs ddr3_emif_reg_data = {
 	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
 };
+
+#define OSC    (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+		303, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
 #endif
 
 /*
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 6291d03..17a98ff 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -44,6 +44,15 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 /* DDR RAM defines */
 #define DDR_CLK_MHZ		303 /* DDR_DPLL_MULT value */
 
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+		DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
 	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 728afc2..2be2297 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -242,6 +242,33 @@ int spl_start_uboot(void)
 }
 #endif
 
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+		266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+		303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_bone_black = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	struct am335x_baseboard_id header;
+
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	if (read_eeprom(&header) < 0)
+		puts("Could not get board ID.\n");
+
+	if (board_is_evm_sk(&header))
+		return &dpll_ddr_evm_sk;
+	else if (board_is_bone_lt(&header))
+		return &dpll_ddr_bone_black;
+	else if (board_is_evm_15_or_later(&header))
+		return &dpll_ddr_evm_sk;
+	else
+		return &dpll_ddr;
+}
+
 #endif
 
 /*
-- 
1.7.9.5

[U-Boot] [PATCH V2 2/4] ARM: AM33xx: Cleanup clocks layer

[Lokesh Vutla]

Cleaning up the clocks layer.
This helps in addition of new Soc with minimal
changes.
This is derived from OMAP4 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/am33xx/board.c           |    6 -
 arch/arm/cpu/armv7/am33xx/clock.c           |   62 +++++-
 arch/arm/cpu/armv7/am33xx/clock_am33xx.c    |  275 ++++++++-------------------
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c    |   19 +-
 arch/arm/cpu/armv7/am33xx/emif4.c           |    1 -
 arch/arm/include/asm/arch-am33xx/clock.h    |   28 ++-
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    2 -
 board/isee/igep0033/board.c                 |   11 +-
 board/ti/am335x/board.c                     |   13 +-
 board/ti/ti814x/evm.c                       |   12 +-
 10 files changed, 193 insertions(+), 236 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index f1623db..64a3af7 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -56,12 +56,6 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-void setup_clocks_for_console(void)
-{
-	/* Not yet implemented */
-	return;
-}
-
 /* AM33XX has two MUSB controllers which can be host or gadget */
 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
 	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 15f4a2c..8e5f3c6 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -98,7 +98,7 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
 	wait_for_lock(dpll_regs);
 }
 
-void setup_dplls(void)
+static void setup_dplls(void)
 {
 	const struct dpll_params *params;
 	do_setup_dpll(&dpll_core_regs, &dpll_core);
@@ -109,3 +109,63 @@ void setup_dplls(void)
 	params = get_dpll_ddr_params();
 	do_setup_dpll(&dpll_ddr_regs, params);
 }
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+				       u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - %p\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - %p\n", clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+		      u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+	u32 i, max = 100;
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++) {
+		enable_clock_domain(clk_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+}
+
+void prcm_init()
+{
+	enable_basic_clocks();
+	setup_dplls();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index d5d47ad..e5f287b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -14,17 +14,12 @@
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 
-#define PRCM_MOD_EN		0x2
-#define PRCM_FORCE_WAKEUP	0x2
-#define PRCM_FUNCTL		0x0
-
-#define CPGMAC0_IDLE		0x30000
 #define OSC	(V_OSCK/1000000)
 
-const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
 
 const struct dpll_regs dpll_mpu_regs = {
 	.cm_clkmode_dpll	= CM_WKUP + 0x88,
@@ -63,199 +58,85 @@ const struct dpll_params dpll_core = {
 const struct dpll_params dpll_per = {
 		960, OSC-1, 5, -1, -1, -1, -1};
 
-static void enable_interface_clocks(void)
-{
-	/* Enable all the Interconnect Modules */
-	writel(PRCM_MOD_EN, &cmper->l3clkctrl);
-	while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
-	while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
-	while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
-	while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
-	while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
-	while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
-	while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
-		;
-}
-
-/*
- * Force power domain wake up transition
- * Ensure that the corresponding interface clock is active before
- * using the peripheral
- */
-static void power_domain_wkup_transition(void)
+void setup_clocks_for_console(void)
 {
-	writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
+	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart1clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart2clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart3clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart4clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart5clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 }
 
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
+void enable_basic_clocks(void)
 {
-	/* Enable the control module though RBL would have done it*/
-	writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
-	while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Enable the module clock */
-	writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
-	while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
-		;
+	u32 *const clk_domains[] = {
+		&cmper->l3clkstctrl,
+		&cmper->l4fwclkstctrl,
+		&cmper->l3sclkstctrl,
+		&cmper->l4lsclkstctrl,
+		&cmwkup->wkclkstctrl,
+		&cmper->emiffwclkctrl,
+		&cmrtc->clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en[] = {
+		&cmper->l3clkctrl,
+		&cmper->l4lsclkctrl,
+		&cmper->l4fwclkctrl,
+		&cmwkup->wkl4wkclkctrl,
+		&cmper->l3instrclkctrl,
+		&cmper->l4hsclkctrl,
+		&cmwkup->wkgpio0clkctrl,
+		&cmwkup->wkctrlclkctrl,
+		&cmper->timer2clkctrl,
+		&cmper->gpmcclkctrl,
+		&cmper->elmclkctrl,
+		&cmper->mmc0clkctrl,
+		&cmper->mmc1clkctrl,
+		&cmwkup->wkup_i2c0ctrl,
+		&cmper->gpio1clkctrl,
+		&cmper->gpio2clkctrl,
+		&cmper->gpio3clkctrl,
+		&cmper->i2c1clkctrl,
+		&cmper->cpgmac0clkctrl,
+		&cmper->spi0clkctrl,
+		&cmrtc->rtcclkctrl,
+		&cmper->usb0clkctrl,
+		&cmper->emiffwclkctrl,
+		&cmper->emifclkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 
 	/* Select the Master osc 24 MHZ as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
-
-	/* UART0 */
-	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
-	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
-		;
-
-	/* UART1 */
-#ifdef CONFIG_SERIAL2
-	writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
-	while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL2 */
-
-	/* UART2 */
-#ifdef CONFIG_SERIAL3
-	writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
-	while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL3 */
-
-	/* UART3 */
-#ifdef CONFIG_SERIAL4
-	writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
-	while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL4 */
-
-	/* UART4 */
-#ifdef CONFIG_SERIAL5
-	writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
-	while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL5 */
-
-	/* UART5 */
-#ifdef CONFIG_SERIAL6
-	writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
-	while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL6 */
-
-	/* GPMC */
-	writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
-	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* ELM */
-	writel(PRCM_MOD_EN, &cmper->elmclkctrl);
-	while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* MMC0*/
-	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
-	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* MMC1 */
-	writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
-	while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* i2c0 */
-	writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
-	while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
-		;
-
-	/* gpio1 module */
-	writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
-	while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* gpio2 module */
-	writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
-	while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* gpio3 module */
-	writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
-	while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* i2c1 */
-	writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
-	while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Ethernet */
-	writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
-	while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
-		;
-
-	/* spi0 */
-	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
-	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* RTC */
-	writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
-	while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* MUSB */
-	writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
-	while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
-		;
-}
-
-void enable_emif_clocks(void)
-{
-	/* Enable the  EMIF_FW Functional clock */
-	writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
-	/* Enable EMIF0 Clock */
-	writel(PRCM_MOD_EN, &cmper->emifclkctrl);
-	/* Poll if module is functional */
-	while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
-		;
-}
-
-/*
- * Configure the PLL/PRCM for necessary peripherals
- */
-void pll_init()
-{
-	setup_dplls();
-	/* Enable the required interconnect clocks */
-	enable_interface_clocks();
-
-	/* Power domain wake up transition */
-	power_domain_wkup_transition();
-
-	/* Enable the required peripherals */
-	enable_per_clocks();
 }
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 658772b..965e875 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -264,11 +264,6 @@ const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
  */
 static void enable_per_clocks(void)
 {
-	/* UART0 */
-	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
-	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
-		;
-
 	/* HSMMC1 */
 	writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
 	while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
@@ -455,8 +450,6 @@ void sata_pll_config(void)
 		;
 }
 
-void enable_emif_clocks(void) {};
-
 void enable_dmm_clocks(void)
 {
 	writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
@@ -477,13 +470,19 @@ void enable_dmm_clocks(void)
 		;
 }
 
+void setup_clocks_for_console(void)
+{
+	unlock_pll_control_mmr();
+	/* UART0 */
+	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+		;
+}
 /*
  * Configure the PLL/PRCM for necessary peripherals
  */
-void pll_init()
+void prcm_init(void)
 {
-	unlock_pll_control_mmr();
-
 	/* Enable the control module */
 	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
 
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 15c4734..21cefd4 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -87,7 +87,6 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr)
 {
-	enable_emif_clocks();
 	ddr_pll_config(pll);
 	config_vtp(nr);
 	config_cmd_ctrl(ctrl, nr);
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 703b80e..0d4b9ae 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -15,6 +15,28 @@
 
 #define LDELAY 1000000
 
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
 /* CM_CLKMODE_DPLL */
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
@@ -77,10 +99,12 @@ extern const struct dpll_params dpll_core;
 extern const struct dpll_params dpll_per;
 extern const struct dpll_params dpll_ddr;
 
-extern const struct cm_wkuppll *cmwkup;
+extern struct cm_wkuppll *const cmwkup;
 
-void setup_dplls(void);
 const struct dpll_params *get_dpll_ddr_params(void);
 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
+void prcm_init(void);
+void enable_basic_clocks(void);
+void do_enable_clocks(u32 *const *, u32 *const *, u8);
 
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 683ba8e..18d7d99 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -146,8 +146,6 @@ void set_sdram_timings(const struct emif_regs *regs, int nr);
  */
 void config_ddr_phy(const struct emif_regs *regs, int nr);
 
-void ddr_pll_config(unsigned int ddrpll_m);
-
 struct ddr_cmd_regs {
 	unsigned int resv0[7];
 	unsigned int cm0csratio;	/* offset 0x01C */
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 034a8aa..a065a74 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -103,11 +103,7 @@ void s_init(void)
 		;
 
 #ifdef CONFIG_SPL_BUILD
-	/* Setup the PLLs and the clocks for the peripherals */
-	pll_init();
-
-	/* Enable RTC32K clock */
-	rtc32k_enable();
+	setup_clocks_for_console();
 
 	enable_uart0_pin_mux();
 
@@ -116,6 +112,11 @@ void s_init(void)
 
 	preloader_console_init();
 
+	prcm_init();
+
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
 	/* Configure board pin mux */
 	enable_board_pin_mux();
 
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 2be2297..a6edc2d 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -317,10 +317,7 @@ void s_init(void)
 
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 	/* Setup the PLLs and the clocks for the peripherals */
-	pll_init();
-
-	/* Enable RTC32K clock */
-	rtc32k_enable();
+	setup_clocks_for_console();
 
 #ifdef CONFIG_SERIAL1
 	enable_uart0_pin_mux();
@@ -354,12 +351,14 @@ void s_init(void)
 	preloader_console_init();
 #endif
 
-	/* Initalize the board header */
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	prcm_init();
+
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
 	enable_board_pin_mux(&header);
 	if (board_is_evm_sk(&header)) {
 		/*
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index c469645..bd708bb 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -125,11 +125,7 @@ void s_init(void)
 	/* Enable timer */
 	timer_init();
 
-	/* Setup the PLLs and the clocks for the peripherals */
-	pll_init();
-
-	/* Enable RTC32K clock */
-	rtc32k_enable();
+	setup_clocks_for_console();
 
 	/* Set UART pins */
 	enable_uart0_pin_mux();
@@ -147,6 +143,12 @@ void s_init(void)
 
 	preloader_console_init();
 
+	/* Setup the PLLs and the clocks for the peripherals */
+	prcm_init();
+
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
 	config_dmm(&evm_lisa_map_regs);
 
 	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
-- 
1.7.9.5

[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place

[Lokesh Vutla]

From: Heiko Schocher <hs@denx.de>

s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/board.c                |   62 +++++++++++++++--
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c         |    6 ++
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |    6 +-
 arch/arm/include/asm/arch-am33xx/sys_proto.h     |    8 ++-
 board/isee/igep0033/board.c                      |   50 +++-----------
 board/phytec/pcm051/board.c                      |   48 +++----------
 board/ti/am335x/board.c                          |   80 ++++------------------
 board/ti/am335x/mux.c                            |   19 +++++
 board/ti/ti814x/evm.c                            |   67 +++---------------
 9 files changed, 128 insertions(+), 218 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 64a3af7..2ea3d69 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -137,7 +137,7 @@ int arch_misc_init(void)
 }
 
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
-void rtc32k_enable(void)
+static void rtc32k_enable(void)
 {
 	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
@@ -153,11 +153,7 @@ void rtc32k_enable(void)
 	writel((1 << 3) | (1 << 6), &rtc->osc);
 }
 
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-
-void uart_soft_reset(void)
+static void uart_soft_reset(void)
 {
 	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 	u32 regval;
@@ -174,4 +170,58 @@ void uart_soft_reset(void)
 	regval |= UART_SMART_IDLE_EN;
 	writel(regval, &uart_base->uartsyscfg);
 }
+
+static void watchdog_disable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
 #endif
+
+void s_init(void)
+{
+	/*
+	 * The ROM will only have set up sufficient pinmux to allow for the
+	 * first 4KiB NOR to be read, we must finish doing what we know of
+	 * the NOR mux in this space in order to continue.
+	 */
+#ifdef CONFIG_NOR_BOOT
+	enable_norboot_pin_mux();
+#endif
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+	watchdog_disable();
+	timer_init();
+	set_uart_mux_conf();
+	setup_clocks_for_console();
+	uart_soft_reset();
+#endif
+#ifdef CONFIG_NOR_BOOT
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();
+	gd->have_console = 1;
+#else
+	gd = &gdata;
+	preloader_console_init();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+	prcm_init();
+	set_mux_conf_regs();
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+	sdram_init();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 965e875..93c7f7b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -277,6 +277,12 @@ static void enable_per_clocks(void)
 	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
 	while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
 		;
+
+	/* RTC clocks */
+	writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
+	writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
+	while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
+		;
 }
 
 /*
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 80e1899..140379f 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -16,8 +16,10 @@
 #define CONFIG_SYS_MPUCLK	550
 #endif
 
-extern void pll_init(void);
-extern void enable_emif_clocks(void);
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
 extern void enable_dmm_clocks(void);
 
 #endif	/* endif _CLOCKS_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index dbcede0..c6070a3 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -35,7 +35,11 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
 void omap_nand_switch_ecc(uint32_t, uint32_t);
 
-void rtc32k_enable(void);
-void uart_soft_reset(void);
+void set_uart_mux_conf(void);
+void set_mux_conf_regs(void);
+void sdram_init(void);
 u32 wait_on_value(u32, u32, void *, u32);
+#ifdef CONFIG_NOR_BOOT
+void enable_norboot_pin_mux(void);
+#endif
 #endif
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index a065a74..f71aaa0 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -27,8 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
 /* MII mode defines */
 #define RMII_MODE_ENABLE	0x4D
 
@@ -76,54 +74,22 @@ const struct dpll_params *get_dpll_ddr_params(void)
 	return &dpll_ddr;
 }
 
-#endif
-
-/*
- * Early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
 {
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-#ifdef CONFIG_SPL_BUILD
-	save_omap_boot_params();
-#endif
-
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-
-#ifdef CONFIG_SPL_BUILD
-	setup_clocks_for_console();
-
 	enable_uart0_pin_mux();
+}
 
-	uart_soft_reset();
-	gd = &gdata;
-
-	preloader_console_init();
-
-	prcm_init();
-
-	/* Enable RTC32K clock */
-	rtc32k_enable();
-
-	/* Configure board pin mux */
+void set_mux_conf_regs(void)
+{
 	enable_board_pin_mux();
+}
 
+void sdram_init(void)
+{
 	config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
 		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-#endif
 }
+#endif
 
 /*
  * Basic board specific setup.  Pinmux has been handled already.
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 17a98ff..f3bad76 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -30,8 +30,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
 /* MII mode defines */
 #define MII_MODE_ENABLE		0x0
 #define RGMII_MODE_ENABLE	0xA
@@ -85,57 +83,27 @@ static struct emif_regs ddr3_emif_reg_data = {
 	.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
 				PHY_EN_DYN_PWRDN,
 };
-#endif
 
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
 {
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-#ifdef CONFIG_SPL_BUILD
-	save_omap_boot_params();
-#endif
-
-	/*
-	 * WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-
-#ifdef CONFIG_SPL_BUILD
-	/* Setup the PLLs and the clocks for the peripherals */
-	pll_init();
-
-	/* Enable RTC32K clock */
-	rtc32k_enable();
-
 	enable_uart0_pin_mux();
-	uart_soft_reset();
-
-	gd = &gdata;
-
-	preloader_console_init();
+}
 
+void set_mux_conf_regs(void)
+{
 	/* Initalize the board header */
 	enable_i2c0_pin_mux();
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	enable_board_pin_mux();
+}
 
+void sdram_init(void)
+{
 	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
 			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-#endif
 }
+#endif
 
 /*
  * Basic board specific setup.  Pinmux has been handled already.
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index a6edc2d..eac9cc9 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -30,8 +30,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
 /* MII mode defines */
 #define MII_MODE_ENABLE		0x0
 #define RGMII_MODE_ENABLE	0x3A
@@ -269,56 +267,8 @@ const struct dpll_params *get_dpll_ddr_params(void)
 		return &dpll_ddr;
 }
 
-#endif
-
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
 {
-	__maybe_unused struct am335x_baseboard_id header;
-
-	/*
-	 * The ROM will only have set up sufficient pinmux to allow for the
-	 * first 4KiB NOR to be read, we must finish doing what we know of
-	 * the NOR mux in this space in order to continue.
-	 */
-#ifdef CONFIG_NOR_BOOT
-	asm("stmfd      sp!, {r2 - r4}");
-	asm("movw       r4, #0x8A4");
-	asm("movw       r3, #0x44E1");
-	asm("orr        r4, r4, r3, lsl #16");
-	asm("mov        r2, #9");
-	asm("mov        r3, #8");
-	asm("gpmc_mux:  str     r2, [r4], #4");
-	asm("subs       r3, r3, #1");
-	asm("bne        gpmc_mux");
-	asm("ldmfd      sp!, {r2 - r4}");
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-	save_omap_boot_params();
-#endif
-
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
-	/* Setup the PLLs and the clocks for the peripherals */
-	setup_clocks_for_console();
-
 #ifdef CONFIG_SERIAL1
 	enable_uart0_pin_mux();
 #endif /* CONFIG_SERIAL1 */
@@ -337,29 +287,25 @@ void s_init(void)
 #ifdef CONFIG_SERIAL6
 	enable_uart5_pin_mux();
 #endif /* CONFIG_SERIAL6 */
+}
 
-	uart_soft_reset();
+void set_mux_conf_regs(void)
+{
+	__maybe_unused struct am335x_baseboard_id header;
 
-#if defined(CONFIG_NOR_BOOT)
-	/* We want our console now. */
-	gd->baudrate = CONFIG_BAUDRATE;
-	serial_init();
-	gd->have_console = 1;
-#else
-	gd = &gdata;
+	if (read_eeprom(&header) < 0)
+		puts("Could not get board ID.\n");
 
-	preloader_console_init();
-#endif
+	enable_board_pin_mux(&header);
+}
 
-	prcm_init();
+void sdram_init(void)
+{
+	__maybe_unused struct am335x_baseboard_id header;
 
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 
-	/* Enable RTC32K clock */
-	rtc32k_enable();
-
-	enable_board_pin_mux(&header);
 	if (board_is_evm_sk(&header)) {
 		/*
 		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
@@ -383,8 +329,8 @@ void s_init(void)
 	else
 		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
-#endif
 }
+#endif
 
 /*
  * Basic board specific setup.  Pinmux has been handled already.
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 5b7ed63..b2bfda5 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -239,6 +239,25 @@ static struct module_pin_mux bone_norcape_pin_mux[] = {
 };
 #endif
 
+#if defined(CONFIG_NOR_BOOT)
+static struct module_pin_mux norboot_pin_mux[] = {
+	{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
+	{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
+	{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
+	{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
+	{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
+	{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
+	{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
+	{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
+	{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
+	{-1},
+};
+
+void enable_norboot_pin_mux(void)
+{
+	configure_module_pin_mux(norboot_pin_mux);
+}
+#endif
 
 void enable_uart0_pin_mux(void)
 {
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index bd708bb..31ddc68 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -27,30 +27,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_SPL_BUILD
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#endif
-
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 /* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-static void uart_enable(void)
-{
-	/* UART softreset */
-	uart_soft_reset();
-}
-
-static void wdt_disable(void)
-{
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-}
-
 static const struct cmd_control evm_ddr2_cctrl_data = {
 	.cmd0csratio	= 0x80,
 	.cmd0dldiff	= 0x04,
@@ -100,63 +80,32 @@ static const struct ddr_data evm_ddr2_data = {
 	.datauserank0delay	= 1,
 	.datadldiff0		= 0x4,
 };
-#endif
 
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
 {
-#ifdef CONFIG_SPL_BUILD
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-#ifdef CONFIG_SPL_BUILD
-	save_omap_boot_params();
-#endif
-
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	wdt_disable();
-
-	/* Enable timer */
-	timer_init();
-
-	setup_clocks_for_console();
-
 	/* Set UART pins */
 	enable_uart0_pin_mux();
+}
 
+void set_mux_conf_regs(void)
+{
 	/* Set MMC pins */
 	enable_mmc1_pin_mux();
 
 	/* Set Ethernet pins */
 	enable_enet_pin_mux();
+}
 
-	/* Enable UART */
-	uart_enable();
-
-	gd = &gdata;
-
-	preloader_console_init();
-
-	/* Setup the PLLs and the clocks for the peripherals */
-	prcm_init();
-
-	/* Enable RTC32K clock */
-	rtc32k_enable();
-
+void sdram_init(void)
+{
 	config_dmm(&evm_lisa_map_regs);
 
 	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif0_regs, 0);
 	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif1_regs, 1);
-#endif
 }
+#endif
 
 /*
  * Basic board specific setup.  Pinmux has been handled already.
-- 
1.7.9.5

[U-Boot] [PATCH V2 4/4] musb: Disable extra prints

[Lokesh Vutla]

There are many musb prints in SPL and U-Boot log.
These prints are required only during musb debug.
So replacing printk with pr_debug in musb_core.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/usb/musb-new/musb_core.c |   20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index da93571..36681b6 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -1311,9 +1311,7 @@ static int __devinit ep_config_from_table(struct musb *musb)
 		break;
 	}
 
-	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
-			musb_driver_name, fifo_mode);
-
+	pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
 
 done:
 	offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
@@ -1341,10 +1339,9 @@ done:
 		musb->nr_endpoints = max(epn, musb->nr_endpoints);
 	}
 
-	printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
-			musb_driver_name,
-			n + 1, musb->config->num_eps * 2 - 1,
-			offset, (1 << (musb->config->ram_bits + 2)));
+	pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1,
+		 musb->config->num_eps * 2 - 1, offset,
+		 (1 << (musb->config->ram_bits + 2)));
 
 	if (!musb->bulk_ep) {
 		pr_debug("%s: missing bulk\n", musb_driver_name);
@@ -1447,8 +1444,7 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
 	if (reg & MUSB_CONFIGDATA_SOFTCONE)
 		strcat(aInfo, ", SoftConn");
 
-	printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
-			musb_driver_name, reg, aInfo);
+	pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
 
 	aDate[0] = 0;
 	if (MUSB_CONTROLLER_MHDRC == musb_type) {
@@ -1469,8 +1465,8 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
 	snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
 		MUSB_HWVERS_MINOR(musb->hwvers),
 		(musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
-	printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
-			musb_driver_name, type, aRevision, aDate);
+	pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type,
+		 aRevision, aDate);
 
 	/* configure ep0 */
 	musb_configure_ep0(musb);
@@ -2122,7 +2118,7 @@ musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev,
 
 	pm_runtime_put(musb->controller);
 
-	dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
+	pr_debug("USB %s mode controller at %p using %s, IRQ %d\n",
 			({char *s;
 			 switch (musb->board_mode) {
 			 case MUSB_HOST:		s = "Host"; break;
-- 
1.7.9.5

[U-Boot] [PATCH V2 1/4] ARM: AM33xx: Cleanup dplls data

[Heiko Schocher]

Hello LOkesh,

Am 30.07.2013 07:18, schrieb Lokesh Vutla:
> Locking sequence for all the dplls is same.
> In the current code same sequence is done repeatedly
> for each dpll. Instead have a generic function
> for locking dplls and pass dpll data to that function.
>
> This is derived from OMAP4 boards.
>
> Signed-off-by: Lokesh Vutla<lokeshvutla@ti.com>
> ---
>   arch/arm/cpu/armv7/am33xx/Makefile           |    1 +
>   arch/arm/cpu/armv7/am33xx/clock.c            |  111 +++++++++++++
>   arch/arm/cpu/armv7/am33xx/clock_am33xx.c     |  220 +++++---------------------
>   arch/arm/cpu/armv7/am33xx/emif4.c            |    4 +
>   arch/arm/include/asm/arch-am33xx/clock.h     |   70 ++++++++
>   arch/arm/include/asm/arch-am33xx/ddr_defs.h  |    2 +
>   arch/arm/include/asm/arch-am33xx/sys_proto.h |    1 +
>   board/isee/igep0033/board.c                  |   10 ++
>   board/phytec/pcm051/board.c                  |    9 ++
>   board/ti/am335x/board.c                      |   27 ++++
>   10 files changed, 273 insertions(+), 182 deletions(-)
>   create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c

Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>

Thanks!

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH V2 2/4] ARM: AM33xx: Cleanup clocks layer

[Heiko Schocher]

Hello Lokesh,

Am 30.07.2013 07:18, schrieb Lokesh Vutla:
> Cleaning up the clocks layer.
> This helps in addition of new Soc with minimal
> changes.
> This is derived from OMAP4 boards.
>
> Signed-off-by: Lokesh Vutla<lokeshvutla@ti.com>
> ---
>   arch/arm/cpu/armv7/am33xx/board.c           |    6 -
>   arch/arm/cpu/armv7/am33xx/clock.c           |   62 +++++-
>   arch/arm/cpu/armv7/am33xx/clock_am33xx.c    |  275 ++++++++-------------------
>   arch/arm/cpu/armv7/am33xx/clock_ti814x.c    |   19 +-
>   arch/arm/cpu/armv7/am33xx/emif4.c           |    1 -
>   arch/arm/include/asm/arch-am33xx/clock.h    |   28 ++-
>   arch/arm/include/asm/arch-am33xx/ddr_defs.h |    2 -
>   board/isee/igep0033/board.c                 |   11 +-
>   board/ti/am335x/board.c                     |   13 +-
>   board/ti/ti814x/evm.c                       |   12 +-
>   10 files changed, 193 insertions(+), 236 deletions(-)

Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>

Thanks!

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place

[Heiko Schocher]

Hello Lokesh,

Am 30.07.2013 07:18, schrieb Lokesh Vutla:
> From: Heiko Schocher<hs@denx.de>
>
> s_init has the same outline for all the AM33xx based
> board. So making it generic.
> This also helps in addition of new Soc with minimal changes.
>
> Signed-off-by: Lokesh Vutla<lokeshvutla@ti.com>
> Signed-off-by: Heiko Schocher<hs@denx.de>
> Signed-off-by: Tom Rini<trini@ti.com>
> ---
>   arch/arm/cpu/armv7/am33xx/board.c                |   62 +++++++++++++++--
>   arch/arm/cpu/armv7/am33xx/clock_ti814x.c         |    6 ++
>   arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |    6 +-
>   arch/arm/include/asm/arch-am33xx/sys_proto.h     |    8 ++-
>   board/isee/igep0033/board.c                      |   50 +++-----------
>   board/phytec/pcm051/board.c                      |   48 +++----------
>   board/ti/am335x/board.c                          |   80 ++++------------------
>   board/ti/am335x/mux.c                            |   19 +++++
>   board/ti/ti814x/evm.c                            |   67 +++---------------
>   9 files changed, 128 insertions(+), 218 deletions(-)
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>

Thanks!

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH V2 4/4] musb: Disable extra prints

[Heiko Schocher]

Hello Lokesh,

Am 30.07.2013 07:18, schrieb Lokesh Vutla:
> There are many musb prints in SPL and U-Boot log.
> These prints are required only during musb debug.
> So replacing printk with pr_debug in musb_core.
>
> Signed-off-by: Lokesh Vutla<lokeshvutla@ti.com>
> ---
>   drivers/usb/musb-new/musb_core.c |   20 ++++++++------------
>   1 file changed, 8 insertions(+), 12 deletions(-)

Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>

Thanks!

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH V2 0/4]ARM: AM33xx: Cleanup clocks and hwinit

[Tom Rini]

On Tue, Jul 30, 2013 at 10:48:51AM +0530, Lokesh Vutla wrote:

> This series tries to cleanup code for AM33xx,
> inorder to ensure code reusabilty by moving the
> duplicated code to common place.
> This also helps in addition of new Soc with minimal
> changes.
> 
> Testing:
> Boot tested on BeagleBone White/Black, AM35xx EVM/EVMSK.
> Verified ./MAKEALL -s am33xx.
> 
> Changes Since V1:
> - Rebased on top of u-boot-ti
> - Created a function get_dpll_ddr_params() for getting
>   ddr dpll params from board files.
> - Updated License header for newly created files.
> 
> Heiko Schocher (1):
>   ARM: AM33xx: Move s_init to a common place
> 
> Lokesh Vutla (3):
>   ARM: AM33xx: Cleanup dplls data
>   ARM: AM33xx: Cleanup clocks layer
>   musb: Disable extra prints
> 
>  arch/arm/cpu/armv7/am33xx/Makefile               |    1 +
>  arch/arm/cpu/armv7/am33xx/board.c                |   68 ++-
>  arch/arm/cpu/armv7/am33xx/clock.c                |  171 ++++++++
>  arch/arm/cpu/armv7/am33xx/clock_am33xx.c         |  495 +++++-----------------
>  arch/arm/cpu/armv7/am33xx/clock_ti814x.c         |   25 +-
>  arch/arm/cpu/armv7/am33xx/emif4.c                |    5 +-
>  arch/arm/include/asm/arch-am33xx/clock.h         |   94 ++++
>  arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |    6 +-
>  arch/arm/include/asm/arch-am33xx/sys_proto.h     |    9 +-
>  board/isee/igep0033/board.c                      |   55 +--
>  board/phytec/pcm051/board.c                      |   57 +--
>  board/ti/am335x/board.c                          |  102 ++---
>  board/ti/am335x/mux.c                            |   19 +
>  board/ti/ti814x/evm.c                            |   65 +--
>  drivers/usb/musb-new/musb_core.c                 |   20 +-
>  15 files changed, 573 insertions(+), 619 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c

Applied to u-boot-ti/master, thanks!

-- 
Tom
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[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place

[Mark Jackson]

On 30/07/13 08:34, Heiko Schocher wrote:
> Hello Lokesh,
> 
> Am 30.07.2013 07:18, schrieb Lokesh Vutla:
>> From: Heiko Schocher<hs@denx.de>
>>
>> s_init has the same outline for all the AM33xx based
>> board. So making it generic.
>> This also helps in addition of new Soc with minimal changes.

There's a new function now defined ...

void enable_norboot_pin_mux(void)

... but our board *always* boots via NOR.  All the required
pinmux config is handled by enable_board_pin_mux().

Should I just define this an empty function ?

Or should it be a "maybe unused" function ?

Mark J.

[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place

[Tom Rini]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 08/21/2013 11:51 AM, Mark Jackson wrote:
> On 30/07/13 08:34, Heiko Schocher wrote:
>> Hello Lokesh,
>> 
>> Am 30.07.2013 07:18, schrieb Lokesh Vutla:
>>> From: Heiko Schocher<hs@denx.de>
>>> 
>>> s_init has the same outline for all the AM33xx based board. So
>>>  making it generic. This also helps in addition of new Soc with
>>>  minimal changes.
> 
> There's a new function now defined ...
> 
> void enable_norboot_pin_mux(void)
> 
> ... but our board *always* boots via NOR.  All the required

OK, then you should rip out the SPL bits, yes? Or do you support SD
too? :)

> pinmux config is handled by enable_board_pin_mux().
> 
> Should I just define this an empty function ?
> 
> Or should it be a "maybe unused" function ?

Well, why can't it still be done in that function?

- -- 
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iQIcBAEBAgAGBQJSFOo4AAoJENk4IS6UOR1WZ+wQAJRjGVg/7dygiaJZmtuyHm7D
9uyQJU0o/xrQu3A3i+GBOuYP7D6awCLBCVyTDgTibWcXtvKtHsVwFSc4oDhgVRKl
YU5fuO8qVYyCBRiS9QsEOFIPAgubBWg6PWgdCG9pakveNRJ9hWQLsjusePrObGyn
pxhFSB4zx6KFuGBufzC+fLzPcM9hY9Xxuiqbj7qvK/oO/k8vdekOWrHE4+y2UBxS
LsFzGWlHpN3h5iZwVk+EgrClKK+f4V5MNxyzW8dMGKF42Vl9KVaG7krXl4pUs4ju
SoYIxfJ/r8DZjfFi1IuKMacKER1eROTdhGCZl0PtlL4VRxomSNix/gne3gG0ykB6
lGZuv9C046gpkQWQW90+t1IQIDWTOMkEadJ3cVUBZqraIk3bcybLk0pOoaah7ayC
bmknCM7hVB+V7HfPGG6U20nhy5R2SebBIt5VdH4xIP5SFMpgcWKCXf9fbjWVwH3v
ptnqYIlXgUBoDzA3u3UuaI91i4bsFmnjZfvbKeC4zHXK8uhwow06mU2hMaotGeEg
qpki2Ga1CevKddDPJSwzOUyFIo6Tp8HhD//u2EXMEf1jB880fKdSsHbt2URYmxYb
0HmvPFMCP04AOrgmADq3K1Yd4DbxejaWyORdF7rWvAl/lUSElnzo4Q/1DS2LjHOe
Ngcvd53zCmpV/51VpbQq
=gAOw
-----END PGP SIGNATURE-----

[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place

[Mark Jackson]

On 30/07/13 06:18, Lokesh Vutla wrote:
> From: Heiko Schocher <hs@denx.de>
> 
> s_init has the same outline for all the AM33xx based
> board. So making it generic.
> This also helps in addition of new Soc with minimal changes.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Signed-off-by: Heiko Schocher <hs@denx.de>
> Signed-off-by: Tom Rini <trini@ti.com>

<snip>

This patch introduces the following new function call ...

> +void s_init(void)
> +{
> +	/*
> +	 * The ROM will only have set up sufficient pinmux to allow for the
> +	 * first 4KiB NOR to be read, we must finish doing what we know of
> +	 * the NOR mux in this space in order to continue.
> +	 */
> +#ifdef CONFIG_NOR_BOOT
> +	enable_norboot_pin_mux();
> +#endif

... which replaces the old code ...

> -	/*
> -	 * The ROM will only have set up sufficient pinmux to allow for the
> -	 * first 4KiB NOR to be read, we must finish doing what we know of
> -	 * the NOR mux in this space in order to continue.
> -	 */
> -#ifdef CONFIG_NOR_BOOT
> -	asm("stmfd      sp!, {r2 - r4}");
> -	asm("movw       r4, #0x8A4");
> -	asm("movw       r3, #0x44E1");
> -	asm("orr        r4, r4, r3, lsl #16");
> -	asm("mov        r2, #9");
> -	asm("mov        r3, #8");
> -	asm("gpmc_mux:  str     r2, [r4], #4");
> -	asm("subs       r3, r3, #1");
> -	asm("bne        gpmc_mux");
> -	asm("ldmfd      sp!, {r2 - r4}");
> -#endif

Now (for the TI boards) enable_norboot_pin_mux() is defined as:-

> +#if defined(CONFIG_NOR_BOOT)
> +static struct module_pin_mux norboot_pin_mux[] = {
> +	{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
> +	{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
> +	{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
> +	{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
> +	{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
> +	{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
> +	{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
> +	{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
> +	{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
> +	{-1},
> +};
> +
> +void enable_norboot_pin_mux(void)
> +{
> +	configure_module_pin_mux(norboot_pin_mux);
> +}
> +#endif

Firstly, this pinmux code seems wrong, since lcd_data pin map:-

lcd_data1 (mode 1) => gpmc_a1_mux1
lcd_data2 (mode 1) => gpmc_a2_mux1
lcd_data3 (mode 1) => gpmc_a3_mux1
lcd_data4 (mode 1) => gpmc_a4_mux1
lcd_data5 (mode 1) => gpmc_a5_mux1
lcd_data6 (mode 1) => gpmc_a6_mux1
lcd_data7 (mode 1) => gpmc_a7_mux1
lcd_data8 (mode 1) => gpmc_a12_mux1
lcd_data9 (mode 1) => gpmc_a13_mux1

Doesn't this leave gpmc_a[8..11] unconfigured ?
Shouldn't we configure lcd_vsync, lcd_hsync and lcd_pclk ?

Secondly, I've modded our Nanobone code to match this new setup, as follows:-

static struct module_pin_mux norboot_pin_mux[] = {
	{OFFSET(lcd_data1), (MODE(1) | PULLUDDIS)},	/* GPMC A17 */
	{OFFSET(lcd_data2), (MODE(1) | PULLUDDIS)},	/* GPMC A18 */
	{OFFSET(lcd_data3), (MODE(1) | PULLUDDIS)},	/* GPMC A19 */
	{OFFSET(lcd_data4), (MODE(1) | PULLUDDIS)},	/* GPMC A20 */
	{OFFSET(lcd_data5), (MODE(1) | PULLUDDIS)},	/* GPMC A21 */
	{OFFSET(lcd_data6), (MODE(1) | PULLUDDIS)},	/* GPMC A22 */
	{OFFSET(lcd_data7), (MODE(1) | PULLUDDIS)},	/* GPMC A23 */
	{OFFSET(lcd_vsync), (MODE(1) | PULLUDDIS)},	/* GPMC A24 */
	{OFFSET(lcd_hsync), (MODE(1) | PULLUDDIS)},	/* GPMC A25 */
	{OFFSET(lcd_pclk), (MODE(1) | PULLUDDIS)},	/* GPMC A26 */
	{-1},
};

void enable_norboot_pin_mux(void)
{
	configure_module_pin_mux(norboot_pin_mux);
}

But this fails to boot. However, if I use the old ASM code:-

void enable_norboot_pin_mux(void)
{
	asm("stmfd      sp!, {r2 - r4}");
	asm("movw       r4, #0x8A4");
	asm("movw       r3, #0x44E1");
	asm("orr        r4, r4, r3, lsl #16");
	asm("mov        r2, #9");
	asm("mov        r3, #8");
	asm("gpmc_mux:  str     r2, [r4], #4");
	asm("subs       r3, r3, #1");
	asm("bne        gpmc_mux");
	asm("ldmfd      sp!, {r2 - r4}");
}

... this now boots correctly !!

Anyone care to comment ?

[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place

[Lokesh Vutla]

Hi Mark,

On Friday 23 August 2013 02:58 PM, Mark Jackson wrote:
> On 30/07/13 06:18, Lokesh Vutla wrote:
>> From: Heiko Schocher <hs@denx.de>
>>
>> s_init has the same outline for all the AM33xx based
>> board. So making it generic.
>> This also helps in addition of new Soc with minimal changes.
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> Signed-off-by: Heiko Schocher <hs@denx.de>
>> Signed-off-by: Tom Rini <trini@ti.com>
> 
> <snip>
> 
> This patch introduces the following new function call ...
> 
>> +void s_init(void)
>> +{
>> +	/*
>> +	 * The ROM will only have set up sufficient pinmux to allow for the
>> +	 * first 4KiB NOR to be read, we must finish doing what we know of
>> +	 * the NOR mux in this space in order to continue.
>> +	 */
>> +#ifdef CONFIG_NOR_BOOT
>> +	enable_norboot_pin_mux();
>> +#endif
> 
> ... which replaces the old code ...
> 
>> -	/*
>> -	 * The ROM will only have set up sufficient pinmux to allow for the
>> -	 * first 4KiB NOR to be read, we must finish doing what we know of
>> -	 * the NOR mux in this space in order to continue.
>> -	 */
>> -#ifdef CONFIG_NOR_BOOT
>> -	asm("stmfd      sp!, {r2 - r4}");
>> -	asm("movw       r4, #0x8A4");
>> -	asm("movw       r3, #0x44E1");
>> -	asm("orr        r4, r4, r3, lsl #16");
>> -	asm("mov        r2, #9");
>> -	asm("mov        r3, #8");
>> -	asm("gpmc_mux:  str     r2, [r4], #4");
>> -	asm("subs       r3, r3, #1");
>> -	asm("bne        gpmc_mux");
>> -	asm("ldmfd      sp!, {r2 - r4}");
>> -#endif
> 
> Now (for the TI boards) enable_norboot_pin_mux() is defined as:-
> 
>> +#if defined(CONFIG_NOR_BOOT)
>> +static struct module_pin_mux norboot_pin_mux[] = {
>> +	{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
>> +	{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
>> +	{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
>> +	{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
>> +	{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
>> +	{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
>> +	{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
>> +	{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
>> +	{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
>> +	{-1},
>> +};
 Is this configuration not working for you?
>> +
>> +void enable_norboot_pin_mux(void)
>> +{
>> +	configure_module_pin_mux(norboot_pin_mux);
>> +}
>> +#endif
> 
> Firstly, this pinmux code seems wrong, since lcd_data pin map:-
> 
> lcd_data1 (mode 1) => gpmc_a1_mux1
> lcd_data2 (mode 1) => gpmc_a2_mux1
> lcd_data3 (mode 1) => gpmc_a3_mux1
> lcd_data4 (mode 1) => gpmc_a4_mux1
> lcd_data5 (mode 1) => gpmc_a5_mux1
> lcd_data6 (mode 1) => gpmc_a6_mux1
> lcd_data7 (mode 1) => gpmc_a7_mux1
> lcd_data8 (mode 1) => gpmc_a12_mux1
> lcd_data9 (mode 1) => gpmc_a13_mux1
> 
> Doesn't this leave gpmc_a[8..11] unconfigured ?
> Shouldn't we configure lcd_vsync, lcd_hsync and lcd_pclk ?
> 
> Secondly, I've modded our Nanobone code to match this new setup, as follows:-
> 
> static struct module_pin_mux norboot_pin_mux[] = {
> 	{OFFSET(lcd_data1), (MODE(1) | PULLUDDIS)},	/* GPMC A17 */
> 	{OFFSET(lcd_data2), (MODE(1) | PULLUDDIS)},	/* GPMC A18 */
> 	{OFFSET(lcd_data3), (MODE(1) | PULLUDDIS)},	/* GPMC A19 */
> 	{OFFSET(lcd_data4), (MODE(1) | PULLUDDIS)},	/* GPMC A20 */
> 	{OFFSET(lcd_data5), (MODE(1) | PULLUDDIS)},	/* GPMC A21 */
> 	{OFFSET(lcd_data6), (MODE(1) | PULLUDDIS)},	/* GPMC A22 */
> 	{OFFSET(lcd_data7), (MODE(1) | PULLUDDIS)},	/* GPMC A23 */
> 	{OFFSET(lcd_vsync), (MODE(1) | PULLUDDIS)},	/* GPMC A24 */
> 	{OFFSET(lcd_hsync), (MODE(1) | PULLUDDIS)},	/* GPMC A25 */
> 	{OFFSET(lcd_pclk), (MODE(1) | PULLUDDIS)},	/* GPMC A26 */
> 	{-1},
> };
> 
> void enable_norboot_pin_mux(void)
> {
> 	configure_module_pin_mux(norboot_pin_mux);
> }
> 
> But this fails to boot. However, if I use the old ASM code:-
> 
> void enable_norboot_pin_mux(void)
> {
> 	asm("stmfd      sp!, {r2 - r4}");
> 	asm("movw       r4, #0x8A4");
> 	asm("movw       r3, #0x44E1");
> 	asm("orr        r4, r4, r3, lsl #16");
> 	asm("mov        r2, #9");
> 	asm("mov        r3, #8");
> 	asm("gpmc_mux:  str     r2, [r4], #4");
> 	asm("subs       r3, r3, #1");
> 	asm("bne        gpmc_mux");
> 	asm("ldmfd      sp!, {r2 - r4}");
> }
This code writes 0x9 into 8 continuous registers starting from
0x44e108a4, this is what done in module_pin_mux norboot_pin_mux
except that it has 9 registers(i guess 9th register was added by mistake..:( )
Correct me if I am wrong.

So you are telling this is wrong but boots properly ?
Steve in CC can comment more on this configuration.

Thanks and regards,
Lokesh

> 
> ... this now boots correctly !!
> 
> Anyone care to comment ?
> 

[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place

[Mark Jackson]

On 23/08/13 11:25, Lokesh Vutla wrote:
> Hi Mark,
> 
> On Friday 23 August 2013 02:58 PM, Mark Jackson wrote:
>> On 30/07/13 06:18, Lokesh Vutla wrote:
>>> From: Heiko Schocher <hs@denx.de>
>>>
>>> s_init has the same outline for all the AM33xx based
>>> board. So making it generic.
>>> This also helps in addition of new Soc with minimal changes.
>>>
>>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>>> Signed-off-by: Heiko Schocher <hs@denx.de>
>>> Signed-off-by: Tom Rini <trini@ti.com>
>>

<snip>

>> But this fails to boot. However, if I use the old ASM code:-
>>
>> void enable_norboot_pin_mux(void)
>> {
>> 	asm("stmfd      sp!, {r2 - r4}");
>> 	asm("movw       r4, #0x8A4");
>> 	asm("movw       r3, #0x44E1");
>> 	asm("orr        r4, r4, r3, lsl #16");
>> 	asm("mov        r2, #9");
>> 	asm("mov        r3, #8");
>> 	asm("gpmc_mux:  str     r2, [r4], #4");
>> 	asm("subs       r3, r3, #1");
>> 	asm("bne        gpmc_mux");
>> 	asm("ldmfd      sp!, {r2 - r4}");
>> }
> This code writes 0x9 into 8 continuous registers starting from
> 0x44e108a4, this is what done in module_pin_mux norboot_pin_mux
> except that it has 9 registers(i guess 9th register was added by mistake..:( )
> Correct me if I am wrong.

Not sure about the code, but it was introduced here:-

http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commit;h=c5c7a7c32d552592ac49749e5c184c89bd50c098

> So you are telling this is wrong but boots properly ?

Basically ... yes !!

[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place

[Mark Jackson]

On 23/08/13 11:55, Mark Jackson wrote:
> On 23/08/13 11:25, Lokesh Vutla wrote:
>> Hi Mark,
>>
>> On Friday 23 August 2013 02:58 PM, Mark Jackson wrote:
>>> On 30/07/13 06:18, Lokesh Vutla wrote:
>>>> From: Heiko Schocher <hs@denx.de>
>>>>
>>>> s_init has the same outline for all the AM33xx based
>>>> board. So making it generic.
>>>> This also helps in addition of new Soc with minimal changes.
>>>>
>>>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>>>> Signed-off-by: Heiko Schocher <hs@denx.de>
>>>> Signed-off-by: Tom Rini <trini@ti.com>
>>>
> 
> <snip>
> 
>>> But this fails to boot. However, if I use the old ASM code:-
>>>
>>> void enable_norboot_pin_mux(void)
>>> {
>>> 	asm("stmfd      sp!, {r2 - r4}");
>>> 	asm("movw       r4, #0x8A4");
>>> 	asm("movw       r3, #0x44E1");
>>> 	asm("orr        r4, r4, r3, lsl #16");
>>> 	asm("mov        r2, #9");
>>> 	asm("mov        r3, #8");
>>> 	asm("gpmc_mux:  str     r2, [r4], #4");
>>> 	asm("subs       r3, r3, #1");
>>> 	asm("bne        gpmc_mux");
>>> 	asm("ldmfd      sp!, {r2 - r4}");
>>> }
>> This code writes 0x9 into 8 continuous registers starting from
>> 0x44e108a4, this is what done in module_pin_mux norboot_pin_mux
>> except that it has 9 registers(i guess 9th register was added by mistake..:( )
>> Correct me if I am wrong.
> 
> Not sure about the code, but it was introduced here:-
> 
> http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commit;h=c5c7a7c32d552592ac49749e5c184c89bd50c098
> 
>> So you are telling this is wrong but boots properly ?
> 
> Basically ... yes !!

Is there any update on this issue ?

I'm keen to get our board support files pushed through.