[PATCH V3: Add Smp support for Allwinner A20. 0/3]

[PATCH V3: Add Smp support for Allwinner A20. 0/3]

[Fan Rong]

This is the version3 patch. It delete platform.h and delete some code in platsmp.c that's not necessary. The patchs add smp support for Allwinner A20. It add cpu register node and arch timer node in dts for smp booting. SMP need arch timer as clocksource, It does use virtual counter timer and does not use physical counter timer, so bootloader ***must*** set CNTVOFF register for a20 before kernel booting. I have add support set CNTVOFF register for uboot, if you want to test it in a20 board, you need update uboot. Thanks for advice of Mark Rutland, Marc Zyngier, Ian Campbell, Russell King and Maxime Ripard.

Fan Rong (3):
  Add smp support for Allwinner A20(sunxi 7i).
  Add cpuconfig nodes in dts for smp configure.
  add arch count timer node in dts for Allwinner A20(sunxi 7i).

 arch/arm/boot/dts/sun7i-a20.dtsi | 19 ++++++++-
 arch/arm/mach-sunxi/Makefile     |  2 +
 arch/arm/mach-sunxi/headsmp.S    | 17 ++++++++
 arch/arm/mach-sunxi/platsmp.c    | 86 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/sunxi.c      | 31 +++++++++++++++
 5 files changed, 153 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S
 create mode 100644 arch/arm/mach-sunxi/platsmp.c

-- 
1.8.1.2

[PATCH V3: Add Smp support for Allwinner A20. 0/3]

[Fan Rong]

This is the version3 patch. It delete platform.h and delete some code in platsmp.c that's not necessary. The patchs add smp support for Allwinner A20. It add cpu register node and arch timer node in dts for smp booting. SMP need arch timer as clocksource, It does use virtual counter timer and does not use physical counter timer, so bootloader ***must*** set CNTVOFF register for a20 before kernel booting. I have add support set CNTVOFF register for uboot, if you want to test it in a20 board, you need update uboot. Thanks for advice of Mark Rutland, Marc Zyngier, Ian Campbell, Russell King and Maxime Ripard.

Fan Rong (3):
  Add smp support for Allwinner A20(sunxi 7i).
  Add cpuconfig nodes in dts for smp configure.
  add arch count timer node in dts for Allwinner A20(sunxi 7i).

 arch/arm/boot/dts/sun7i-a20.dtsi | 19 ++++++++-
 arch/arm/mach-sunxi/Makefile     |  2 +
 arch/arm/mach-sunxi/headsmp.S    | 17 ++++++++
 arch/arm/mach-sunxi/platsmp.c    | 86 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/sunxi.c      | 31 +++++++++++++++
 5 files changed, 153 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S
 create mode 100644 arch/arm/mach-sunxi/platsmp.c

-- 
1.8.1.2

[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Fan Rong]

Signed-off-by: Fan Rong <cinifr@gmail.com>
---
 arch/arm/mach-sunxi/Makefile  |  2 +
 arch/arm/mach-sunxi/headsmp.S | 17 +++++++++
 arch/arm/mach-sunxi/platsmp.c | 86 +++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/sunxi.c   | 31 ++++++++++++++++
 4 files changed, 136 insertions(+)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S
 create mode 100644 arch/arm/mach-sunxi/platsmp.c

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 93bebfc..d7f1ef4 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1 +1,3 @@
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_ARCH_SUNXI) += platsmp.o
+obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 0000000..5899399
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,17 @@
+/*
+ * SMP support for A20
+ *
+ *  Copyright (C) 2013 Fan Rong <cinifr@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
+msr cpsr_fsxc,
+#0xd3
+b secondary_startup ENDPROC(sun7i_secondary_startup)
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
new file mode 100644
index 0000000..5e3e994
--- /dev/null
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -0,0 +1,86 @@
+/*
+ *  linux/arch/arm/mach-sun7i/platsmp.c
+ *
+ *  Copyright (C) 2013 Fan Rong <cinifr@gmail.com>
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+
+extern void __iomem *sunxi7i_cc_base;
+void sun7i_secondary_startup(void);
+
+/*
+ * CPUCFG
+ */
+#define SUN7I_CPUCFG_BOOTADDR	0x01a4
+
+#define SUN7I_CPUCFG_GENCTL	0x0184
+#define SUN7I_CPUCFG_DBGCTL0	0x01e0
+#define SUN7I_CPUCFG_DBGCTL1	0x01e4
+
+#define SUN7I_CPU1_PWR_CLAMP	0x01b0
+#define SUN7I_CPU1_PWROFF_REG	0x01b4
+#define SUN7I_CPUX_RESET_CTL(x)	(0x40 + (x)*0x40)
+
+static int sun7i_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	long paddr;
+	uint32_t pwr_reg;
+	uint32_t j = 0xff << 1;
+	if (!sunxi7i_cc_base) {
+		pr_debug("error map cpu configure\n");
+		return -ENOSYS;
+	}
+	/* Set boot addr */
+	paddr = virt_to_phys(sun7i_secondary_startup);
+	writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
+
+	/* Assert cpu core reset */
+	writel(0, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
+
+	/* Ensure CPU reset also invalidates L1 caches */
+	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
+	pwr_reg &= ~ BIT(cpu);
+	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
+
+	/* DBGPWRDUP hold low */
+	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+	pwr_reg &= ~ BIT(cpu);
+	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+
+	/* Ramp up power to CPU1 */
+	do {
+		writel(j, sunxi7i_cc_base + SUN7I_CPU1_PWR_CLAMP);
+		j = j >> 1;
+	} while (j != 0);
+
+	mdelay(10);
+
+	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
+	pwr_reg &= ~1;
+	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
+	mdelay(1);
+
+	/* Release CPU reset */
+	writel(3, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
+
+	/* Unlock CPU */
+	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+	pwr_reg |= BIT(cpu);
+	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+
+	return 0;
+}
+
+struct smp_operations sun7i_smp_ops __initdata = {
+	.smp_boot_secondary = sun7i_boot_secondary,
+};
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index e79fb34..a692350 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -26,6 +26,8 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 
+extern struct smp_operations sun7i_smp_ops;
+
 #define SUN4I_WATCHDOG_CTRL_REG		0x00
 #define SUN4I_WATCHDOG_CTRL_RESTART		BIT(0)
 #define SUN4I_WATCHDOG_MODE_REG		0x04
@@ -42,6 +44,14 @@
 #define SUN6I_WATCHDOG1_MODE_ENABLE		BIT(0)
 
 static void __iomem *wdt_base;
+/*
+ * CPU Configure module support
+ * 1: Software reset for smp cpus
+ * 2: Configure for smp cpus including boot.
+ * 3: Three 64-bit idle counters and two 64-bit common counters
+ * it is needed for smp cpus
+ */
+void __iomem *sunxi7i_cc_base; /*CPU Configure Base*/
 
 static void sun4i_restart(enum reboot_mode mode, const char *cmd)
 {
@@ -98,6 +108,11 @@ static struct of_device_id sunxi_restart_ids[] = {
 	{ /*sentinel*/ }
 };
 
+static struct of_device_id sunxi_cc_ids[] = {
+	{ .compatible = "allwinner,sun7i-a20-cpuconfig"},
+	{ /*sentinel*/ }
+};
+
 static void sunxi_setup_restart(void)
 {
 	const struct of_device_id *of_id;
@@ -138,7 +153,23 @@ static const char * const sunxi_board_dt_compat[] = {
 	NULL,
 };
 
+static int __init sunxi_init_cpuconfig_map(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, sunxi_cc_ids);
+	if (WARN(!np, "unable to setup cup configure"))
+		return -ENOSYS;
+	sunxi7i_cc_base = of_iomap(np, 0);
+	if (WARN(!sunxi7i_cc_base, "failed to map cup configure base address"))
+		return -ENOSYS;
+	return 0;
+}
+
+early_initcall(sunxi_init_cpuconfig_map);
+
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
+	.smp	= smp_ops(sun7i_smp_ops),
 	.init_machine	= sunxi_dt_init,
 	.init_time	= sunxi_timer_init,
 	.dt_compat	= sunxi_board_dt_compat,
-- 
1.8.1.2

[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Fan Rong]

Signed-off-by: Fan Rong <cinifr@gmail.com>
---
 arch/arm/mach-sunxi/Makefile  |  2 +
 arch/arm/mach-sunxi/headsmp.S | 17 +++++++++
 arch/arm/mach-sunxi/platsmp.c | 86 +++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/sunxi.c   | 31 ++++++++++++++++
 4 files changed, 136 insertions(+)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S
 create mode 100644 arch/arm/mach-sunxi/platsmp.c

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 93bebfc..d7f1ef4 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1 +1,3 @@
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_ARCH_SUNXI) += platsmp.o
+obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 0000000..5899399
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,17 @@
+/*
+ * SMP support for A20
+ *
+ *  Copyright (C) 2013 Fan Rong <cinifr@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
+msr cpsr_fsxc,
+#0xd3
+b secondary_startup ENDPROC(sun7i_secondary_startup)
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
new file mode 100644
index 0000000..5e3e994
--- /dev/null
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -0,0 +1,86 @@
+/*
+ *  linux/arch/arm/mach-sun7i/platsmp.c
+ *
+ *  Copyright (C) 2013 Fan Rong <cinifr@gmail.com>
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+
+extern void __iomem *sunxi7i_cc_base;
+void sun7i_secondary_startup(void);
+
+/*
+ * CPUCFG
+ */
+#define SUN7I_CPUCFG_BOOTADDR	0x01a4
+
+#define SUN7I_CPUCFG_GENCTL	0x0184
+#define SUN7I_CPUCFG_DBGCTL0	0x01e0
+#define SUN7I_CPUCFG_DBGCTL1	0x01e4
+
+#define SUN7I_CPU1_PWR_CLAMP	0x01b0
+#define SUN7I_CPU1_PWROFF_REG	0x01b4
+#define SUN7I_CPUX_RESET_CTL(x)	(0x40 + (x)*0x40)
+
+static int sun7i_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	long paddr;
+	uint32_t pwr_reg;
+	uint32_t j = 0xff << 1;
+	if (!sunxi7i_cc_base) {
+		pr_debug("error map cpu configure\n");
+		return -ENOSYS;
+	}
+	/* Set boot addr */
+	paddr = virt_to_phys(sun7i_secondary_startup);
+	writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
+
+	/* Assert cpu core reset */
+	writel(0, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
+
+	/* Ensure CPU reset also invalidates L1 caches */
+	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
+	pwr_reg &= ~ BIT(cpu);
+	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
+
+	/* DBGPWRDUP hold low */
+	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+	pwr_reg &= ~ BIT(cpu);
+	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+
+	/* Ramp up power to CPU1 */
+	do {
+		writel(j, sunxi7i_cc_base + SUN7I_CPU1_PWR_CLAMP);
+		j = j >> 1;
+	} while (j != 0);
+
+	mdelay(10);
+
+	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
+	pwr_reg &= ~1;
+	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
+	mdelay(1);
+
+	/* Release CPU reset */
+	writel(3, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
+
+	/* Unlock CPU */
+	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+	pwr_reg |= BIT(cpu);
+	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+
+	return 0;
+}
+
+struct smp_operations sun7i_smp_ops __initdata = {
+	.smp_boot_secondary = sun7i_boot_secondary,
+};
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index e79fb34..a692350 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -26,6 +26,8 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 
+extern struct smp_operations sun7i_smp_ops;
+
 #define SUN4I_WATCHDOG_CTRL_REG		0x00
 #define SUN4I_WATCHDOG_CTRL_RESTART		BIT(0)
 #define SUN4I_WATCHDOG_MODE_REG		0x04
@@ -42,6 +44,14 @@
 #define SUN6I_WATCHDOG1_MODE_ENABLE		BIT(0)
 
 static void __iomem *wdt_base;
+/*
+ * CPU Configure module support
+ * 1: Software reset for smp cpus
+ * 2: Configure for smp cpus including boot.
+ * 3: Three 64-bit idle counters and two 64-bit common counters
+ * it is needed for smp cpus
+ */
+void __iomem *sunxi7i_cc_base; /*CPU Configure Base*/
 
 static void sun4i_restart(enum reboot_mode mode, const char *cmd)
 {
@@ -98,6 +108,11 @@ static struct of_device_id sunxi_restart_ids[] = {
 	{ /*sentinel*/ }
 };
 
+static struct of_device_id sunxi_cc_ids[] = {
+	{ .compatible = "allwinner,sun7i-a20-cpuconfig"},
+	{ /*sentinel*/ }
+};
+
 static void sunxi_setup_restart(void)
 {
 	const struct of_device_id *of_id;
@@ -138,7 +153,23 @@ static const char * const sunxi_board_dt_compat[] = {
 	NULL,
 };
 
+static int __init sunxi_init_cpuconfig_map(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, sunxi_cc_ids);
+	if (WARN(!np, "unable to setup cup configure"))
+		return -ENOSYS;
+	sunxi7i_cc_base = of_iomap(np, 0);
+	if (WARN(!sunxi7i_cc_base, "failed to map cup configure base address"))
+		return -ENOSYS;
+	return 0;
+}
+
+early_initcall(sunxi_init_cpuconfig_map);
+
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
+	.smp	= smp_ops(sun7i_smp_ops),
 	.init_machine	= sunxi_dt_init,
 	.init_time	= sunxi_timer_init,
 	.dt_compat	= sunxi_board_dt_compat,
-- 
1.8.1.2

[PATCH V3: Add Smp support for Allwinner A20. 2/3] Add cpuconfig nodes in dts for smp configure.

[Fan Rong]

Signed-off-by: Fan Rong <cinifr@gmail.com>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 999ff45..f745e0b 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -20,13 +20,13 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0  {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <1>;
@@ -167,6 +167,11 @@
 		#size-cells = <1>;
 		ranges;
 
+		cpuconfig: cpuconfig@01c25c00 {
+			compatible = "allwinner,sun7i-a20-cpuconfig";
+			reg = <0x01c25c00 0x400>;
+		};
+
 		pio: pinctrl@01c20800 {
 			compatible = "allwinner,sun7i-a20-pinctrl";
 			reg = <0x01c20800 0x400>;
-- 
1.8.1.2

[PATCH V3: Add Smp support for Allwinner A20. 2/3] Add cpuconfig nodes in dts for smp configure.

[Fan Rong]

Signed-off-by: Fan Rong <cinifr@gmail.com>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 999ff45..f745e0b 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -20,13 +20,13 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu at 0 {
+		cpu0: cpu at 0  {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0>;
 		};
 
-		cpu at 1 {
+		cpu1: cpu at 1 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <1>;
@@ -167,6 +167,11 @@
 		#size-cells = <1>;
 		ranges;
 
+		cpuconfig: cpuconfig at 01c25c00 {
+			compatible = "allwinner,sun7i-a20-cpuconfig";
+			reg = <0x01c25c00 0x400>;
+		};
+
 		pio: pinctrl at 01c20800 {
 			compatible = "allwinner,sun7i-a20-pinctrl";
 			reg = <0x01c20800 0x400>;
-- 
1.8.1.2

[PATCH V3: Add Smp support for Allwinner A20. 3/3] add arch count timer node in dts for Allwinner A20(sunxi 7i).

[Fan Rong]

Signed-off-by: Fan Rong <cinifr@gmail.com>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f745e0b..76b8c3f 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -312,5 +312,15 @@
 			#interrupt-cells = <3>;
 			interrupts = <1 9 0xf04>;
 		};
+
+		timer {
+			compatible ="arm,armv7-timer";
+			interrupts = <1 13 0x308>,
+				     <1 14 0x308>,
+				     <1 11 0x308>,
+				     <1 10 0x308>;
+			clock-frequency = <24000000>;
+		};
+
 	};
 };
-- 
1.8.1.2

[PATCH V3: Add Smp support for Allwinner A20. 3/3] add arch count timer node in dts for Allwinner A20(sunxi 7i).

[Fan Rong]

Signed-off-by: Fan Rong <cinifr@gmail.com>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f745e0b..76b8c3f 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -312,5 +312,15 @@
 			#interrupt-cells = <3>;
 			interrupts = <1 9 0xf04>;
 		};
+
+		timer {
+			compatible ="arm,armv7-timer";
+			interrupts = <1 13 0x308>,
+				     <1 14 0x308>,
+				     <1 11 0x308>,
+				     <1 10 0x308>;
+			clock-frequency = <24000000>;
+		};
+
 	};
 };
-- 
1.8.1.2

Re: [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Russell King - ARM Linux]

On Sun, Sep 22, 2013 at 08:21:26PM +0800, Fan Rong wrote:
> +.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
> +msr cpsr_fsxc,
> +#0xd3
> +b secondary_startup ENDPROC(sun7i_secondary_startup)

This looks like it's been messed up somehow.

[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Russell King - ARM Linux]

On Sun, Sep 22, 2013 at 08:21:26PM +0800, Fan Rong wrote:
> +.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
> +msr cpsr_fsxc,
> +#0xd3
> +b secondary_startup ENDPROC(sun7i_secondary_startup)

This looks like it's been messed up somehow.

Re: [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[cinifr]

Yes, I get it, it is cause by using ./scripts/Lindent. I have to
remail patch aggin. :)

On 22 September 2013 21:00, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Sun, Sep 22, 2013 at 08:21:26PM +0800, Fan Rong wrote:
>> +.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
>> +msr cpsr_fsxc,
>> +#0xd3
>> +b secondary_startup ENDPROC(sun7i_secondary_startup)
>
> This looks like it's been messed up somehow.
>

[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[cinifr]

Yes, I get it, it is cause by using ./scripts/Lindent. I have to
remail patch aggin. :)

On 22 September 2013 21:00, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Sun, Sep 22, 2013 at 08:21:26PM +0800, Fan Rong wrote:
>> +.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
>> +msr cpsr_fsxc,
>> +#0xd3
>> +b secondary_startup ENDPROC(sun7i_secondary_startup)
>
> This looks like it's been messed up somehow.
>

Re: [linux-sunxi] [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Ian Campbell]

On Sun, 2013-09-22 at 20:21 +0800, Fan Rong wrote:

> +	/* Set boot addr */
> +	paddr = virt_to_phys(sun7i_secondary_startup);
> +	writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);

This means that the secondary cores will miss out on any setup which the
bootloader might have done for the primary CPU, e.g. switching to NS HYP
mode, setting the CNTFRQ etc.

Wouldn't it be better to do all this stuff in the bootloader and either
implement PSCI or have the bootloader do the traditional holding pen and
mbox address thing?

[linux-sunxi] [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Ian Campbell]

On Sun, 2013-09-22 at 20:21 +0800, Fan Rong wrote:

> +	/* Set boot addr */
> +	paddr = virt_to_phys(sun7i_secondary_startup);
> +	writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);

This means that the secondary cores will miss out on any setup which the
bootloader might have done for the primary CPU, e.g. switching to NS HYP
mode, setting the CNTFRQ etc.

Wouldn't it be better to do all this stuff in the bootloader and either
implement PSCI or have the bootloader do the traditional holding pen and
mbox address thing?

Re: [PATCH 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Ian Campbell]

On Sun, 2013-09-22 at 23:31 +0800, cinifr wrote:
> 
> 
> On Sunday, 22 September 2013, Ian Campbell <ijc@hellion.org.uk> wrote:
> > On Sun, 2013-09-22 at 20:21 +0800, Fan Rong wrote:
> >
> >> +     /* Set boot addr */
> >> +     paddr = virt_to_phys(sun7i_secondary_startup);
> >> +     writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
> >
> > This means that the secondary cores will miss out on any setup which
> the
> > bootloader might have done for the primary CPU, e.g. switching to NS
> HYP
> > mode, setting the CNTFRQ etc.
> Yes, I think that is what bootloader should do.

In which case this kernel patch needs instead to speak the bootloader
wakeup protocol instead of speaking to the h/w directly like you've done
here, right?

Or is it possible for the bootloader to set these things up and then put
the CPU back to sleep such that it both retains any settings and is
wakable by this patch? This code contains core resets and power control,
which makes me suspect not.

> > Wouldn't it be better to do all this stuff in the bootloader and
> either
> > implement PSCI or have the bootloader do the traditional holding pen
> and
> > mbox address thing?
> >
> I have modified uboot to set cntfrq and cntvoff in all smp cpus,and it
> works well. I guess kernel should believe all cpu should be all same
> when kernel boot. Bootloader should do it to ensure that.

Yes, I think all CPUs must be in the same state at boot.

But if you've done all that then what is this patch for?

Do you have links to your u-boot patches?

Ian.

[PATCH 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Ian Campbell]

On Sun, 2013-09-22 at 23:31 +0800, cinifr wrote:
> 
> 
> On Sunday, 22 September 2013, Ian Campbell <ijc@hellion.org.uk> wrote:
> > On Sun, 2013-09-22 at 20:21 +0800, Fan Rong wrote:
> >
> >> +     /* Set boot addr */
> >> +     paddr = virt_to_phys(sun7i_secondary_startup);
> >> +     writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
> >
> > This means that the secondary cores will miss out on any setup which
> the
> > bootloader might have done for the primary CPU, e.g. switching to NS
> HYP
> > mode, setting the CNTFRQ etc.
> Yes, I think that is what bootloader should do.

In which case this kernel patch needs instead to speak the bootloader
wakeup protocol instead of speaking to the h/w directly like you've done
here, right?

Or is it possible for the bootloader to set these things up and then put
the CPU back to sleep such that it both retains any settings and is
wakable by this patch? This code contains core resets and power control,
which makes me suspect not.

> > Wouldn't it be better to do all this stuff in the bootloader and
> either
> > implement PSCI or have the bootloader do the traditional holding pen
> and
> > mbox address thing?
> >
> I have modified uboot to set cntfrq and cntvoff in all smp cpus,and it
> works well. I guess kernel should believe all cpu should be all same
> when kernel boot. Bootloader should do it to ensure that.

Yes, I think all CPUs must be in the same state at boot.

But if you've done all that then what is this patch for?

Do you have links to your u-boot patches?

Ian.

Re: [PATCH 1/3] Add smp support for Allwinner A20(sunxi 7i).

[cinifr]

[-- Attachment #1: Type: text/plain, Size: 1321 bytes --]

> In which case this kernel patch needs instead to speak the bootloader
> wakeup protocol instead of speaking to the h/w directly like you've done
> here, right?
>
> Or is it possible for the bootloader to set these things up and then put
> the CPU back to sleep such that it both retains any settings and is
> wakable by this patch? This code contains core resets and power control,
> which makes me suspect not.

And I think secondary cpus  remains setting after h/w boot.
>> > Wouldn't it be better to do all this stuff in the bootloader and
>> either
>> > implement PSCI or have the bootloader do the traditional holding pen
>> and
>> > mbox address thing?
Uboot doesnot support PSCI, it use  traditional holding pen for sunxi
platform now.

>> >
>> I have modified uboot to set cntfrq and cntvoff in all smp cpus,and it
>> works well. I guess kernel should believe all cpu should be all same
>> when kernel boot. Bootloader should do it to ensure that.
>
> Yes, I think all CPUs must be in the same state at boot.
>
> But if you've done all that then what is this patch for?
>
> Do you have links to your u-boot patches?
>
> Ian.
Yes, This is my patch for uboot.
My working uboot code is in https://github.com/linux-sunxi/u-boot-sunxi.git
Note this is only test patch. I have not commit it  formally for uboot.

Fan

[-- Attachment #2: 0001-Add-setting-CNTVOFF-and-CNTFRQ-for-all-smp-cpus.patch --]
[-- Type: application/octet-stream, Size: 11285 bytes --]

From 773d25e3ef709fbb7ec5ac3299d7a9776185a865 Mon Sep 17 00:00:00 2001
From: Fan Rong <cinifr@gmail.com>
Date: Mon, 23 Sep 2013 22:29:56 +0800
Subject: [PATCH] Add setting CNTVOFF and CNTFRQ for all smp cpus

Signed-off-by: Fan Rong <cinifr@gmail.com>
---
 arch/arm/cpu/armv7/sunxi/Makefile         |   2 +
 arch/arm/cpu/armv7/sunxi/monitor.S        |  97 ++++++++
 arch/arm/cpu/armv7/sunxi/secondary_init.S |   2 +-
 arch/arm/cpu/armv7/sunxi/smp.c            |   9 +-
 arch/arm/cpu/armv7/sunxi/vir.c            | 398 ++++++++++++++++++++++++++++++
 board/sunxi/board.c                       |   3 +
 include/configs/sun7i.h                   |   3 +
 7 files changed, 510 insertions(+), 4 deletions(-)
 mode change 100644 => 100755 arch/arm/cpu/armv7/sunxi/Makefile
 create mode 100755 arch/arm/cpu/armv7/sunxi/monitor.S
 mode change 100644 => 100755 arch/arm/cpu/armv7/sunxi/secondary_init.S
 mode change 100644 => 100755 arch/arm/cpu/armv7/sunxi/smp.c
 create mode 100755 arch/arm/cpu/armv7/sunxi/vir.c
 mode change 100644 => 100755 include/configs/sun7i.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
old mode 100644
new mode 100755
index 115181f..1ff5c21
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -36,6 +36,8 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= pinmux.o
 COBJS	+= watchdog.o
+COBJS	+= vir.o
+COBJS	+= monitor.o
 ifdef DEBUG
 COBJS	+= early_print.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/monitor.S b/arch/arm/cpu/armv7/sunxi/monitor.S
new file mode 100755
index 0000000..8d52ad9
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/monitor.S
@@ -0,0 +1,97 @@
+/*
+ *
+ * Copyright (C) 2013 Fan Rong <cinifr@gmail.com>.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+
+
+	.text
+	.pushsection    .hyp.idmap.text,"ax"
+	.align 5
+	.arch_extension virt
+
+
+
+/******************************************************************************
+cini
+******************************************************************************/
+	.align 5
+__vir_init_start:
+	.globl __vir_init_start
+
+__vir_init_monitor_vector:
+	.globl __vir_init_monitor_vector
+	
+	@ Monitor-mode exception vector
+	.word 0	/* reset */
+	.word 0	/* undef */
+	b	mon_smc
+	.word 0 /* pabt */
+	.word 0 /* dabt */
+	b	hyp_hvc
+	.word 0 /* irq */
+	.word 0 /* fiq */
+	.align
+mon_smc:
+	mov	sp,r1	
+	push	{lr}
+	mov	lr,r0	
+	blx	lr
+	pop	{lr}	
+	movs	pc, lr
+	
+	@push	{lr}
+	@mov	lr, r0
+
+	@blx	lr
+	@pop	{lr}
+	movs	pc, lr
+	
+	.align 5
+__vir_init_hyp_vector:
+	.globl __vir_init_hyp_vector
+	
+	@ Monitor-mode exception vector
+	.word 0x1234	/* reset */
+	.word 0x5678	/* undef */
+	.word 0 /* pabt */
+	b	hyp_hyt
+	.word 0 /* dabt */
+	b	hyp_hyt
+	.word 0 /* irq */
+	.word 0 /* fiq */
+	.align
+
+
+hyp_hvc:
+	eret
+	b	hyp_hvc
+
+
+hyp_hyt:
+	mov	sp,r1
+	mov	lr,r0	
+	blx	lr
+	eret
+
+	
+	push	{lr}
+	mov	lr,r0	
+	blx	lr
+	pop	{lr}
+	@b	hyp_hyt
+
+
+
+	.ltorg
+
+	.globl __vir_hyp_init_end
+__vir_hyp_init_end:
+
+__vir_init_end:
+	.globl __vir_init_end
+
+	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/secondary_init.S b/arch/arm/cpu/armv7/sunxi/secondary_init.S
old mode 100644
new mode 100755
index 034acde..af66355
--- a/arch/arm/cpu/armv7/sunxi/secondary_init.S
+++ b/arch/arm/cpu/armv7/sunxi/secondary_init.S
@@ -37,7 +37,7 @@ ENTRY(secondary_init)
 	 * Setup a secondary stack, each core gets 128 bytes.
 	 */
 	ldr	sp, =secondary_stack
-	mov	r0, #0x80
+	mov	r0, #0x1000
 	add	sp, sp, r0, lsl r5
 
 	/*
diff --git a/arch/arm/cpu/armv7/sunxi/smp.c b/arch/arm/cpu/armv7/sunxi/smp.c
old mode 100644
new mode 100755
index 59717a2..fd200f5
--- a/arch/arm/cpu/armv7/sunxi/smp.c
+++ b/arch/arm/cpu/armv7/sunxi/smp.c
@@ -32,7 +32,6 @@
 #else
 #error unsupported SoC
 #endif
-
 static void secondary_pen(void)
 {
 	struct sunxi_cpucfg *cpucfg = (struct sunxi_cpucfg *)SUNXI_CPUCFG_BASE;
@@ -50,10 +49,14 @@ static void secondary_pen(void)
 	};
 }
 
-u32 secondary_stack[32*(NUM_CORES-1)];
+u32 secondary_stack[0x400*(NUM_CORES-1)];
 
 void secondary_start(void)
 {
+	/* CNTFRQ == 24 MHz */
+	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
+
+	vir_init();
 	secondary_pen();
 }
 
@@ -62,7 +65,7 @@ void startup_secondaries(void)
 {
 	int i;
 	struct sunxi_cpucfg *cpucfg = (struct sunxi_cpucfg *)SUNXI_CPUCFG_BASE;
-
+	printf("startup_secondaries\n");
 	writel((u32)secondary_init, &cpucfg->boot_addr);
 
 	for (i = 1; i < NUM_CORES; i++) {
diff --git a/arch/arm/cpu/armv7/sunxi/vir.c b/arch/arm/cpu/armv7/sunxi/vir.c
new file mode 100755
index 0000000..02309e0
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/vir.c
@@ -0,0 +1,398 @@
+/*
+ * (C) Copyright 2013 Fan Rong <cinifr@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+
+#include <common.h>
+
+
+volatile unsigned int dist_addr; 
+volatile unsigned int cpu_addr; 
+
+
+
+/* Hyp System Control Register (HSCTLR) bits */
+#define HSCTLR_TE	(1 << 30)
+#define HSCTLR_EE	(1 << 25)
+#define HSCTLR_FI	(1 << 21)
+#define HSCTLR_WXN	(1 << 19)
+#define HSCTLR_I	(1 << 12)
+#define HSCTLR_C	(1 << 2)
+#define HSCTLR_A	(1 << 1)
+#define HSCTLR_M	1
+#define HSCTLR_MASK	(HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \
+			 HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE)
+
+
+
+extern char __vir_init_monitor_vector[];
+
+
+static char smc_stack[2048];
+
+int i;
+
+#define VIR_INFO(fmt, ...)   \
+printf("[%s] " fmt,__FUNCTION__,## __VA_ARGS__)
+
+#define VIR_INFO(fmt, ...) 
+
+
+#define FUN_SPE(regname,...)	\
+void write_##regname(unsigned int tmp)	\
+{	\
+	asm	\
+	(	\
+		"mcr "# __VA_ARGS__	\
+		:	\
+		:"r"(tmp)	\
+		:"memory"	\
+	);	\
+	VIR_INFO("0x%x\r\n",tmp);	\	
+}	\
+unsigned int read_##regname(void)	\
+{	\
+	unsigned int tmp;	\
+	asm \
+	(	\
+		"mrc "# __VA_ARGS__ \
+		:"=r"(tmp)	\
+		:	\
+		:"memory"	\
+	);	\
+	VIR_INFO("0x%x\r\n",tmp);	\	
+	return tmp;	\
+}
+
+
+
+
+
+#define FUN_SPE__NO_PRINT(regname,...)	\
+void write_##regname(int tmp)	\
+{	\
+	asm	\
+	(	\
+		"mcr "# __VA_ARGS__	\
+		:	\
+		:"r"(tmp)	\
+		:"memory"	\
+	);	\
+}	\
+unsigned int read_##regname(void)	\
+{	\
+	unsigned int tmp;	\
+	asm \
+	(	\
+		"mrc "# __VA_ARGS__ \
+		:"=r"(tmp)	\
+		:	\
+		:"memory"	\
+	);	\
+	return tmp;	\
+}
+
+
+FUN_SPE(sctlr,p15,0,%0,c1,c0,0)
+FUN_SPE(vbar,p15,0,%0,c12,c0,0)
+FUN_SPE(mvbar,p15,0,%0,c12,c0,1)
+FUN_SPE(hvbar,p15,4,%0,c12,c0,0)
+FUN_SPE(scr,p15,0,%0,c1,c1,0)
+FUN_SPE(hcr,p15,4,%0,c1,c1,0)
+FUN_SPE(hdcr,p15,4,%0,c1,c1,1)
+
+FUN_SPE(hsctlr,p15,4,%0,c1,c0,0)
+FUN_SPE(hcptr,p15,4,%0,c1,c1,2)
+FUN_SPE(hstr,p15,4,%0,c1,c1,3)
+
+FUN_SPE(vpidr,p15,4,%0,c0,c0,0)
+FUN_SPE(vmpidr,p15,4,%0,c0,c0,5)
+
+FUN_SPE(mpidr,p15,0,%0,c0,c0,5)
+
+
+FUN_SPE(ttbr0,p15,0,%0,c2,c0,0)
+FUN_SPE(ttbr1,p15,0,%0,c2,c0,1)
+FUN_SPE(ttbcr,p15,0,%0,c2,c0,2)
+FUN_SPE(par,p15,0,%0,c7, c4, 0)
+
+FUN_SPE(prrr,p15,0,%0,c10,c2,0)
+FUN_SPE(nmrr,p15,0,%0,c10,c2,1)
+
+FUN_SPE(fcseidr,p15,0,%0,c13,c0,0)
+FUN_SPE(contextidr,p15,0,%0,c13,c0,1)
+FUN_SPE(tpidrurw,p15,0,%0,c13,c0,2)
+FUN_SPE(tpidruro,p15,0,%0,c13,c0,3)
+FUN_SPE(tpidrprw,p15,0,%0,c13,c0,4)
+
+
+FUN_SPE(csselr,p15,2,%0,c0,c0,0)
+FUN_SPE(dacr,p15,0,%0,c3,c0,0)
+
+FUN_SPE(dfsr,p15,0,%0,c5,c0,0)
+FUN_SPE(ifsr,p15,0,%0,c5,c0,1)
+
+
+FUN_SPE(dfar,p15,0,%0,c6,c0,0)
+FUN_SPE(ifar,p15,0,%0,c6,c0,2)
+
+FUN_SPE(nsacr,p15,0,%0,c1,c1,2)
+
+
+FUN_SPE__NO_PRINT(dccisw,p15,0,%0,c7,c14,2)
+
+FUN_SPE(tlbiall,p15,0,%0,c8,c7,0)
+
+FUN_SPE(cpacr,p15,0,%0,c1,c0,2)
+
+
+
+
+
+
+int write_cpsr(int tmp)
+{
+	asm
+	(
+		"msr	cpsr,%0"
+		:
+		:"r"(tmp)
+		:"memory"
+	);
+	VIR_INFO("VIR: write_cpsr 0x%x\r\n",tmp);		
+	return tmp;
+}
+
+int read_cpsr(void)
+{
+	int tmp;
+	asm
+	(
+		"mrs	%0,cpsr"
+		:"=r"(tmp)
+		:
+		:"memory"
+	);
+	VIR_INFO("VIR: read_cpsr 0x%x\r\n",tmp);		
+	return tmp;
+}
+
+
+int write_spsr(int tmp)
+{
+	asm
+	(
+		"msr	spsr,%0"
+		:
+		:"r"(tmp)
+		:"memory"
+	);
+	
+	VIR_INFO("VIR: write_spsr 0x%x\r\n",tmp);
+	return tmp;
+}
+
+int read_spsr(void)
+{
+	int tmp;
+	asm
+	(
+		"mrs	%0,spsr"
+		:"=r"(tmp)
+		:
+		:"memory"
+	);
+	
+	VIR_INFO("VIR: read_spsr 0x%x\r\n",tmp);
+	return tmp;
+}
+
+
+
+int write_cntvoff(int tmp1,int tmp2)
+{
+
+	asm
+	(
+		"mcrr	p15, 4, %0,%1,c14"
+		:
+		:"r"(tmp1),"r"(tmp2)		
+		:"memory"
+	);
+	
+	VIR_INFO("0x%x 0x%x\r\n",tmp1,tmp2);
+	return 0;
+}
+
+int read_cntvoff(int *tmp1,int *tmp2)
+{
+	int tmp;
+	asm
+	(
+		"mrrc	p15, 4, %0,%1,c14"
+		:"=r"(*tmp1),"=r"(*tmp2)		
+		:
+		:"memory"
+	);
+	
+	VIR_INFO("0x%x 0x%x\r\n",*tmp1,*tmp2);
+	return 0;
+}
+
+
+
+
+int write_httbr(int tmp1,int tmp2)
+{
+
+	asm
+	(
+		"mcrr	p15, 4, %0,%1,c2"
+		:
+		:"r"(tmp1),"r"(tmp2)		
+		:"memory"
+	);
+	
+	VIR_INFO("0x%x 0x%x\r\n",tmp1,tmp2);
+	return 0;
+}
+
+int read_httbr(int *tmp1,int *tmp2)
+{
+	int tmp;
+	asm
+	(
+		"mrrc	p15, 4, %0,%1,c2"
+		:"=r"(*tmp1),"=r"(*tmp2)		
+		:
+		:"memory"
+	);
+	
+	VIR_INFO("0x%x 0x%x\r\n",*tmp1,*tmp2);
+	return 0;
+}
+
+
+
+int read_sp(void)
+{
+	int tmp;
+	asm
+	(
+		"mov	%0,sp"
+		:"=r"(tmp)
+		:
+		:"memory"
+	);
+	VIR_INFO("0x%x\r\n",tmp);	
+	return tmp;
+}
+
+
+
+int call_smc(void *fn, ...)
+{
+	asm
+	(
+		"mov r0,%0"
+		:
+		:"r"(fn)
+		:"memory"
+
+	);
+	asm
+	(
+		".arch_extension sec\n\t"	
+		"mov r7,#0\n\t"
+		"mcr p15, 0, r7, c7, c5, 6\n\t"
+		"dsb\n\t"
+		"dmb\n\t"
+		"smc #0\n\t"	
+	);
+	read_cpsr();
+	return 0;
+}
+
+
+int call_hvc(void *fn, ...)
+{
+	asm
+	(	
+		".arch_extension virt \n\t"
+		"isb	\n\t"
+		"hvc #0"
+	);
+	VIR_INFO("VIR: call_hvc \r\n");
+	return 0;
+}
+
+#define VIR_INFO(fmt, ...) 
+
+void smc_handler(void)
+{
+
+	unsigned int tmp1,tmp2;
+	unsigned int tmp,ttbr0,ttbr1,ttbcr,par,vbar,prrr,nmrr;
+	unsigned int dfsr,ifsr,dfar,ifar,csselr,dacr,fcseidr,contextidr,tpidrurw,tpidruro,tpidrprw;
+	
+	unsigned int scr;
+	unsigned int pgd_low,pgd_high;
+
+
+	scr = read_scr();
+
+	write_scr(scr|1);	//set to non secure bit
+	/* now cpu in monitor with NS=1*/
+
+	read_cntvoff(&tmp1,&tmp2);
+
+	tmp1 = 0;
+	tmp2 = 0;
+	
+	write_cntvoff(tmp1,tmp2);
+	
+	read_cntvoff(&tmp1,&tmp2);
+
+	write_scr(scr);
+	
+	read_scr();
+	return 0;
+
+
+	
+}
+
+
+int vir_init()
+{
+	int result;
+	unsigned int cpsr,sctlr;	
+	unsigned int contextidr;
+	int i=0;
+	//printf("vir_init mpidr 0x%x\n",read_mpidr());
+	read_ttbr0();
+	read_ttbr1();
+	cpsr = read_cpsr();
+	sctlr = read_sctlr();	
+	write_cpsr(cpsr |(0x80)); //disable irq
+	write_sctlr(sctlr&(~0x1004));//disable cache
+	write_nsacr(0xffc00);
+
+
+	read_mvbar();
+	write_mvbar(__vir_init_monitor_vector);
+	read_mvbar();
+
+	call_smc(smc_handler,smc_stack+2048);	
+	
+	write_cpsr(cpsr);   //restore cpsr	
+	write_sctlr(sctlr);//restore sctlr	
+	return 0;
+}	
+
+
+
+
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 85f9708..fbda71c 100755
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -45,6 +45,9 @@ int board_init(void)
 {
 	int id_pfr1;
 
+	vir_init();
+	startup_secondaries();
+
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100);
 
 	asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
old mode 100644
new mode 100755
index a6ede2a..fcb36bf
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -34,6 +34,9 @@
 #define CONFIG_SYS_PROMPT		"sun7i# "
 #define CONFIG_MACH_TYPE		4283
 
+
+#define CONFIG_SYS_SECONDARY_ON   1
+
 #if defined(CONFIG_SYS_SECONDARY_ON)
 #define CONFIG_BOARD_POSTCLK_INIT 1
 #endif
-- 
1.8.1.2

[PATCH 1/3] Add smp support for Allwinner A20(sunxi 7i).

[cinifr]

> In which case this kernel patch needs instead to speak the bootloader
> wakeup protocol instead of speaking to the h/w directly like you've done
> here, right?
>
> Or is it possible for the bootloader to set these things up and then put
> the CPU back to sleep such that it both retains any settings and is
> wakable by this patch? This code contains core resets and power control,
> which makes me suspect not.

And I think secondary cpus  remains setting after h/w boot.
>> > Wouldn't it be better to do all this stuff in the bootloader and
>> either
>> > implement PSCI or have the bootloader do the traditional holding pen
>> and
>> > mbox address thing?
Uboot doesnot support PSCI, it use  traditional holding pen for sunxi
platform now.

>> >
>> I have modified uboot to set cntfrq and cntvoff in all smp cpus,and it
>> works well. I guess kernel should believe all cpu should be all same
>> when kernel boot. Bootloader should do it to ensure that.
>
> Yes, I think all CPUs must be in the same state at boot.
>
> But if you've done all that then what is this patch for?
>
> Do you have links to your u-boot patches?
>
> Ian.
Yes, This is my patch for uboot.
My working uboot code is in https://github.com/linux-sunxi/u-boot-sunxi.git
Note this is only test patch. I have not commit it  formally for uboot.

Fan
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Re: [PATCH V3: Add Smp support for Allwinner A20. 2/3] Add cpuconfig nodes in dts for smp configure.

[Maxime Ripard]

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Hi Fan,

On Sun, Sep 22, 2013 at 08:21:27PM +0800, Fan Rong wrote:
> Signed-off-by: Fan Rong <cinifr@gmail.com>
> ---
>  arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 999ff45..f745e0b 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -20,13 +20,13 @@
>  		#address-cells = <1>;
>  		#size-cells = <0>;
>  
> -		cpu@0 {
> +		cpu0: cpu@0  {
>  			compatible = "arm,cortex-a7";
>  			device_type = "cpu";
>  			reg = <0>;
>  		};
>  
> -		cpu@1 {
> +		cpu1: cpu@1 {

You still haven't replied on why you need these two changes.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH V3: Add Smp support for Allwinner A20. 2/3] Add cpuconfig nodes in dts for smp configure.

[Maxime Ripard]

Hi Fan,

On Sun, Sep 22, 2013 at 08:21:27PM +0800, Fan Rong wrote:
> Signed-off-by: Fan Rong <cinifr@gmail.com>
> ---
>  arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 999ff45..f745e0b 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -20,13 +20,13 @@
>  		#address-cells = <1>;
>  		#size-cells = <0>;
>  
> -		cpu at 0 {
> +		cpu0: cpu at 0  {
>  			compatible = "arm,cortex-a7";
>  			device_type = "cpu";
>  			reg = <0>;
>  		};
>  
> -		cpu at 1 {
> +		cpu1: cpu at 1 {

You still haven't replied on why you need these two changes.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH V3: Add Smp support for Allwinner A20. 3/3] add arch count timer node in dts for Allwinner A20(sunxi 7i).

[Maxime Ripard]

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Hi Fang,

On Sun, Sep 22, 2013 at 08:21:28PM +0800, Fan Rong wrote:
> Signed-off-by: Fan Rong <cinifr@gmail.com>

Please be more verbose here, especially on the consequences it has.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH V3: Add Smp support for Allwinner A20. 3/3] add arch count timer node in dts for Allwinner A20(sunxi 7i).

[Maxime Ripard]

Hi Fang,

On Sun, Sep 22, 2013 at 08:21:28PM +0800, Fan Rong wrote:
> Signed-off-by: Fan Rong <cinifr@gmail.com>

Please be more verbose here, especially on the consequences it has.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Maxime Ripard]

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Hi Fang,

On Sun, Sep 22, 2013 at 08:21:26PM +0800, Fan Rong wrote:
> Signed-off-by: Fan Rong <cinifr@gmail.com>
> ---
>  arch/arm/mach-sunxi/Makefile  |  2 +
>  arch/arm/mach-sunxi/headsmp.S | 17 +++++++++
>  arch/arm/mach-sunxi/platsmp.c | 86 +++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-sunxi/sunxi.c   | 31 ++++++++++++++++
>  4 files changed, 136 insertions(+)
>  create mode 100644 arch/arm/mach-sunxi/headsmp.S
>  create mode 100644 arch/arm/mach-sunxi/platsmp.c
> 
> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
> index 93bebfc..d7f1ef4 100644
> --- a/arch/arm/mach-sunxi/Makefile
> +++ b/arch/arm/mach-sunxi/Makefile
> @@ -1 +1,3 @@
>  obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
> +obj-$(CONFIG_ARCH_SUNXI) += platsmp.o
> +obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
> diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> new file mode 100644
> index 0000000..5899399
> --- /dev/null
> +++ b/arch/arm/mach-sunxi/headsmp.S
> @@ -0,0 +1,17 @@
> +/*
> + * SMP support for A20
> + *
> + *  Copyright (C) 2013 Fan Rong <cinifr@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/linkage.h>
> +#include <linux/init.h>
> +
> +.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
> +msr cpsr_fsxc,
> +#0xd3
> +b secondary_startup ENDPROC(sun7i_secondary_startup)
> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
> new file mode 100644
> index 0000000..5e3e994
> --- /dev/null
> +++ b/arch/arm/mach-sunxi/platsmp.c
> @@ -0,0 +1,86 @@
> +/*
> + *  linux/arch/arm/mach-sun7i/platsmp.c
> + *
> + *  Copyright (C) 2013 Fan Rong <cinifr@gmail.com>
> + *  All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/smp.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/smp.h>
> +
> +extern void __iomem *sunxi7i_cc_base;

Please use sun7i here as well.

> +void sun7i_secondary_startup(void);
> +
> +/*
> + * CPUCFG
> + */
> +#define SUN7I_CPUCFG_BOOTADDR	0x01a4
> +
> +#define SUN7I_CPUCFG_GENCTL	0x0184
> +#define SUN7I_CPUCFG_DBGCTL0	0x01e0
> +#define SUN7I_CPUCFG_DBGCTL1	0x01e4
> +
> +#define SUN7I_CPU1_PWR_CLAMP	0x01b0
> +#define SUN7I_CPU1_PWROFF_REG	0x01b4
> +#define SUN7I_CPUX_RESET_CTL(x)	(0x40 + (x)*0x40)
> +
> +static int sun7i_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> +	long paddr;
> +	uint32_t pwr_reg;
> +	uint32_t j = 0xff << 1;
> +	if (!sunxi7i_cc_base) {
> +		pr_debug("error map cpu configure\n");
> +		return -ENOSYS;
> +	}
> +	/* Set boot addr */
> +	paddr = virt_to_phys(sun7i_secondary_startup);
> +	writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
> +
> +	/* Assert cpu core reset */
> +	writel(0, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
> +
> +	/* Ensure CPU reset also invalidates L1 caches */
> +	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
> +	pwr_reg &= ~ BIT(cpu);
> +	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
> +
> +	/* DBGPWRDUP hold low */
> +	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +	pwr_reg &= ~ BIT(cpu);
> +	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +
> +	/* Ramp up power to CPU1 */
> +	do {
> +		writel(j, sunxi7i_cc_base + SUN7I_CPU1_PWR_CLAMP);
> +		j = j >> 1;
> +	} while (j != 0);
> +
> +	mdelay(10);
> +
> +	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
> +	pwr_reg &= ~1;
> +	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
> +	mdelay(1);
> +
> +	/* Release CPU reset */
> +	writel(3, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
> +
> +	/* Unlock CPU */
> +	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +	pwr_reg |= BIT(cpu);
> +	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +
> +	return 0;
> +}
> +
> +struct smp_operations sun7i_smp_ops __initdata = {
> +	.smp_boot_secondary = sun7i_boot_secondary,
> +};
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index e79fb34..a692350 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -26,6 +26,8 @@
>  #include <asm/mach/map.h>
>  #include <asm/system_misc.h>
>  
> +extern struct smp_operations sun7i_smp_ops;
> +
>  #define SUN4I_WATCHDOG_CTRL_REG		0x00
>  #define SUN4I_WATCHDOG_CTRL_RESTART		BIT(0)
>  #define SUN4I_WATCHDOG_MODE_REG		0x04
> @@ -42,6 +44,14 @@
>  #define SUN6I_WATCHDOG1_MODE_ENABLE		BIT(0)
>  
>  static void __iomem *wdt_base;
> +/*
> + * CPU Configure module support
> + * 1: Software reset for smp cpus
> + * 2: Configure for smp cpus including boot.
> + * 3: Three 64-bit idle counters and two 64-bit common counters
> + * it is needed for smp cpus
> + */
> +void __iomem *sunxi7i_cc_base; /*CPU Configure Base*/
>  
>  static void sun4i_restart(enum reboot_mode mode, const char *cmd)
>  {
> @@ -98,6 +108,11 @@ static struct of_device_id sunxi_restart_ids[] = {
>  	{ /*sentinel*/ }
>  };
>  
> +static struct of_device_id sunxi_cc_ids[] = {
> +	{ .compatible = "allwinner,sun7i-a20-cpuconfig"},
> +	{ /*sentinel*/ }
> +};
> +
>  static void sunxi_setup_restart(void)
>  {
>  	const struct of_device_id *of_id;
> @@ -138,7 +153,23 @@ static const char * const sunxi_board_dt_compat[] = {
>  	NULL,
>  };
>  
> +static int __init sunxi_init_cpuconfig_map(void)
> +{
> +	struct device_node *np;
> +
> +	np = of_find_matching_node(NULL, sunxi_cc_ids);
> +	if (WARN(!np, "unable to setup cup configure"))
> +		return -ENOSYS;
> +	sunxi7i_cc_base = of_iomap(np, 0);
> +	if (WARN(!sunxi7i_cc_base, "failed to map cup configure base address"))
> +		return -ENOSYS;
> +	return 0;
> +}
> +
> +early_initcall(sunxi_init_cpuconfig_map);

You still haven't said why you don't want to use smp_init_cpus there.

> +
>  DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
> +	.smp	= smp_ops(sun7i_smp_ops),

Please align the "=" with the rest of the structure, and please rebase
on top of my "ARM: sunxi: Split out the DT machines for sun6i and sun7i"
patch.

Thanks a lot,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Maxime Ripard]

Hi Fang,

On Sun, Sep 22, 2013 at 08:21:26PM +0800, Fan Rong wrote:
> Signed-off-by: Fan Rong <cinifr@gmail.com>
> ---
>  arch/arm/mach-sunxi/Makefile  |  2 +
>  arch/arm/mach-sunxi/headsmp.S | 17 +++++++++
>  arch/arm/mach-sunxi/platsmp.c | 86 +++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-sunxi/sunxi.c   | 31 ++++++++++++++++
>  4 files changed, 136 insertions(+)
>  create mode 100644 arch/arm/mach-sunxi/headsmp.S
>  create mode 100644 arch/arm/mach-sunxi/platsmp.c
> 
> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
> index 93bebfc..d7f1ef4 100644
> --- a/arch/arm/mach-sunxi/Makefile
> +++ b/arch/arm/mach-sunxi/Makefile
> @@ -1 +1,3 @@
>  obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
> +obj-$(CONFIG_ARCH_SUNXI) += platsmp.o
> +obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
> diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> new file mode 100644
> index 0000000..5899399
> --- /dev/null
> +++ b/arch/arm/mach-sunxi/headsmp.S
> @@ -0,0 +1,17 @@
> +/*
> + * SMP support for A20
> + *
> + *  Copyright (C) 2013 Fan Rong <cinifr@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/linkage.h>
> +#include <linux/init.h>
> +
> +.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
> +msr cpsr_fsxc,
> +#0xd3
> +b secondary_startup ENDPROC(sun7i_secondary_startup)
> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
> new file mode 100644
> index 0000000..5e3e994
> --- /dev/null
> +++ b/arch/arm/mach-sunxi/platsmp.c
> @@ -0,0 +1,86 @@
> +/*
> + *  linux/arch/arm/mach-sun7i/platsmp.c
> + *
> + *  Copyright (C) 2013 Fan Rong <cinifr@gmail.com>
> + *  All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/smp.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/smp.h>
> +
> +extern void __iomem *sunxi7i_cc_base;

Please use sun7i here as well.

> +void sun7i_secondary_startup(void);
> +
> +/*
> + * CPUCFG
> + */
> +#define SUN7I_CPUCFG_BOOTADDR	0x01a4
> +
> +#define SUN7I_CPUCFG_GENCTL	0x0184
> +#define SUN7I_CPUCFG_DBGCTL0	0x01e0
> +#define SUN7I_CPUCFG_DBGCTL1	0x01e4
> +
> +#define SUN7I_CPU1_PWR_CLAMP	0x01b0
> +#define SUN7I_CPU1_PWROFF_REG	0x01b4
> +#define SUN7I_CPUX_RESET_CTL(x)	(0x40 + (x)*0x40)
> +
> +static int sun7i_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> +	long paddr;
> +	uint32_t pwr_reg;
> +	uint32_t j = 0xff << 1;
> +	if (!sunxi7i_cc_base) {
> +		pr_debug("error map cpu configure\n");
> +		return -ENOSYS;
> +	}
> +	/* Set boot addr */
> +	paddr = virt_to_phys(sun7i_secondary_startup);
> +	writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
> +
> +	/* Assert cpu core reset */
> +	writel(0, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
> +
> +	/* Ensure CPU reset also invalidates L1 caches */
> +	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
> +	pwr_reg &= ~ BIT(cpu);
> +	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
> +
> +	/* DBGPWRDUP hold low */
> +	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +	pwr_reg &= ~ BIT(cpu);
> +	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +
> +	/* Ramp up power to CPU1 */
> +	do {
> +		writel(j, sunxi7i_cc_base + SUN7I_CPU1_PWR_CLAMP);
> +		j = j >> 1;
> +	} while (j != 0);
> +
> +	mdelay(10);
> +
> +	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
> +	pwr_reg &= ~1;
> +	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
> +	mdelay(1);
> +
> +	/* Release CPU reset */
> +	writel(3, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
> +
> +	/* Unlock CPU */
> +	pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +	pwr_reg |= BIT(cpu);
> +	writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +
> +	return 0;
> +}
> +
> +struct smp_operations sun7i_smp_ops __initdata = {
> +	.smp_boot_secondary = sun7i_boot_secondary,
> +};
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index e79fb34..a692350 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -26,6 +26,8 @@
>  #include <asm/mach/map.h>
>  #include <asm/system_misc.h>
>  
> +extern struct smp_operations sun7i_smp_ops;
> +
>  #define SUN4I_WATCHDOG_CTRL_REG		0x00
>  #define SUN4I_WATCHDOG_CTRL_RESTART		BIT(0)
>  #define SUN4I_WATCHDOG_MODE_REG		0x04
> @@ -42,6 +44,14 @@
>  #define SUN6I_WATCHDOG1_MODE_ENABLE		BIT(0)
>  
>  static void __iomem *wdt_base;
> +/*
> + * CPU Configure module support
> + * 1: Software reset for smp cpus
> + * 2: Configure for smp cpus including boot.
> + * 3: Three 64-bit idle counters and two 64-bit common counters
> + * it is needed for smp cpus
> + */
> +void __iomem *sunxi7i_cc_base; /*CPU Configure Base*/
>  
>  static void sun4i_restart(enum reboot_mode mode, const char *cmd)
>  {
> @@ -98,6 +108,11 @@ static struct of_device_id sunxi_restart_ids[] = {
>  	{ /*sentinel*/ }
>  };
>  
> +static struct of_device_id sunxi_cc_ids[] = {
> +	{ .compatible = "allwinner,sun7i-a20-cpuconfig"},
> +	{ /*sentinel*/ }
> +};
> +
>  static void sunxi_setup_restart(void)
>  {
>  	const struct of_device_id *of_id;
> @@ -138,7 +153,23 @@ static const char * const sunxi_board_dt_compat[] = {
>  	NULL,
>  };
>  
> +static int __init sunxi_init_cpuconfig_map(void)
> +{
> +	struct device_node *np;
> +
> +	np = of_find_matching_node(NULL, sunxi_cc_ids);
> +	if (WARN(!np, "unable to setup cup configure"))
> +		return -ENOSYS;
> +	sunxi7i_cc_base = of_iomap(np, 0);
> +	if (WARN(!sunxi7i_cc_base, "failed to map cup configure base address"))
> +		return -ENOSYS;
> +	return 0;
> +}
> +
> +early_initcall(sunxi_init_cpuconfig_map);

You still haven't said why you don't want to use smp_init_cpus there.

> +
>  DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
> +	.smp	= smp_ops(sun7i_smp_ops),

Please align the "=" with the rest of the structure, and please rebase
on top of my "ARM: sunxi: Split out the DT machines for sun6i and sun7i"
patch.

Thanks a lot,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH 1/3] Add smp support for Allwinner A20(sunxi 7i).

[maxime.ripard]

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Hi,

On Mon, Sep 23, 2013 at 10:43:55PM +0800, cinifr wrote:
> > In which case this kernel patch needs instead to speak the bootloader
> > wakeup protocol instead of speaking to the h/w directly like you've done
> > here, right?
> >
> > Or is it possible for the bootloader to set these things up and then put
> > the CPU back to sleep such that it both retains any settings and is
> > wakable by this patch? This code contains core resets and power control,
> > which makes me suspect not.
> 
> And I think secondary cpus  remains setting after h/w boot.
> >> > Wouldn't it be better to do all this stuff in the bootloader and
> >> either
> >> > implement PSCI or have the bootloader do the traditional holding pen
> >> and
> >> > mbox address thing?
> Uboot doesnot support PSCI, it use  traditional holding pen for sunxi
> platform now.
> 
> >> >
> >> I have modified uboot to set cntfrq and cntvoff in all smp cpus,and it
> >> works well. I guess kernel should believe all cpu should be all same
> >> when kernel boot. Bootloader should do it to ensure that.
> >
> > Yes, I think all CPUs must be in the same state at boot.
> >
> > But if you've done all that then what is this patch for?
> >
> > Do you have links to your u-boot patches?
> >
> > Ian.
> Yes, This is my patch for uboot.
> My working uboot code is in https://github.com/linux-sunxi/u-boot-sunxi.git
> Note this is only test patch. I have not commit it  formally for uboot.

Please do so. I'd like very much to avoid ending up in a situation where
we would break the mainline kernel for the A20, without any bootloader
we can point the users to to fix the issues.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH 1/3] Add smp support for Allwinner A20(sunxi 7i).

[maxime.ripard at free-electrons.com]

Hi,

On Mon, Sep 23, 2013 at 10:43:55PM +0800, cinifr wrote:
> > In which case this kernel patch needs instead to speak the bootloader
> > wakeup protocol instead of speaking to the h/w directly like you've done
> > here, right?
> >
> > Or is it possible for the bootloader to set these things up and then put
> > the CPU back to sleep such that it both retains any settings and is
> > wakable by this patch? This code contains core resets and power control,
> > which makes me suspect not.
> 
> And I think secondary cpus  remains setting after h/w boot.
> >> > Wouldn't it be better to do all this stuff in the bootloader and
> >> either
> >> > implement PSCI or have the bootloader do the traditional holding pen
> >> and
> >> > mbox address thing?
> Uboot doesnot support PSCI, it use  traditional holding pen for sunxi
> platform now.
> 
> >> >
> >> I have modified uboot to set cntfrq and cntvoff in all smp cpus,and it
> >> works well. I guess kernel should believe all cpu should be all same
> >> when kernel boot. Bootloader should do it to ensure that.
> >
> > Yes, I think all CPUs must be in the same state at boot.
> >
> > But if you've done all that then what is this patch for?
> >
> > Do you have links to your u-boot patches?
> >
> > Ian.
> Yes, This is my patch for uboot.
> My working uboot code is in https://github.com/linux-sunxi/u-boot-sunxi.git
> Note this is only test patch. I have not commit it  formally for uboot.

Please do so. I'd like very much to avoid ending up in a situation where
we would break the mainline kernel for the A20, without any bootloader
we can point the users to to fix the issues.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[cinifr]

>
> Please use sun7i here as well.
>
Ok, it will be modified by next patch.

>> +early_initcall(sunxi_init_cpuconfig_map);
>
> You still haven't said why you don't want to use smp_init_cpus there.
I find that of_funcation liking of_find_matching_node and of_iomap can
not run well in smp_init_cpus. It cause kernel crash. So I have to use
early_initcall.

Fan

[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[cinifr]

>
> Please use sun7i here as well.
>
Ok, it will be modified by next patch.

>> +early_initcall(sunxi_init_cpuconfig_map);
>
> You still haven't said why you don't want to use smp_init_cpus there.
I find that of_funcation liking of_find_matching_node and of_iomap can
not run well in smp_init_cpus. It cause kernel crash. So I have to use
early_initcall.

Fan

Re: [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 742 bytes --]

Hi Fan,

On Wed, Sep 25, 2013 at 12:22:44AM +0800, cinifr wrote:
> > You still haven't said why you don't want to use smp_init_cpus there.
> I find that of_funcation liking of_find_matching_node and of_iomap can
> not run well in smp_init_cpus. It cause kernel crash. So I have to use
> early_initcall.

Ah, right.

Then, can't we use smp_prepare_cpus for this? it looks to be late enough
so that we can use ioremap there.

I don't want it to be an initcall. The code will be different on the
A31, and we don't want it to be run on all the other machines whenever
we boot a multiplatform kernel anyway.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Maxime Ripard]

Hi Fan,

On Wed, Sep 25, 2013 at 12:22:44AM +0800, cinifr wrote:
> > You still haven't said why you don't want to use smp_init_cpus there.
> I find that of_funcation liking of_find_matching_node and of_iomap can
> not run well in smp_init_cpus. It cause kernel crash. So I have to use
> early_initcall.

Ah, right.

Then, can't we use smp_prepare_cpus for this? it looks to be late enough
so that we can use ioremap there.

I don't want it to be an initcall. The code will be different on the
A31, and we don't want it to be run on all the other machines whenever
we boot a multiplatform kernel anyway.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[linux-sunxi] [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Ben Dooks]

On 22/09/13 15:44, Ian Campbell wrote:
> On Sun, 2013-09-22 at 20:21 +0800, Fan Rong wrote:
>
>> +	/* Set boot addr */
>> +	paddr = virt_to_phys(sun7i_secondary_startup);
>> +	writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
>
> This means that the secondary cores will miss out on any setup which the
> bootloader might have done for the primary CPU, e.g. switching to NS HYP
> mode, setting the CNTFRQ etc.
>
> Wouldn't it be better to do all this stuff in the bootloader and either
> implement PSCI or have the bootloader do the traditional holding pen and
> mbox address thing?

Out of interest, where is PSCI defined?

Does this also mean it is very difficult or impossible to actually
power down CPU cores?

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[cinifr]

Hi  Maxime,
    I have test it, but I found it does not work. If using
smp_prepare_cpus, the kernenl cannot find the secondary cpus because
that smp_prepare_cpus semms not be excuted before kernel is booting
secondary cpus. So I have to use early_initcall.

Fan.

On 26 September 2013 02:44, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Fan,
>
> On Wed, Sep 25, 2013 at 12:22:44AM +0800, cinifr wrote:
>> > You still haven't said why you don't want to use smp_init_cpus there.
>> I find that of_funcation liking of_find_matching_node and of_iomap can
>> not run well in smp_init_cpus. It cause kernel crash. So I have to use
>> early_initcall.
>
> Ah, right.
>
> Then, can't we use smp_prepare_cpus for this? it looks to be late enough
> so that we can use ioremap there.
>
> I don't want it to be an initcall. The code will be different on the
> A31, and we don't want it to be run on all the other machines whenever
> we boot a multiplatform kernel anyway.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[cinifr]

Hi  Maxime,
    I have test it, but I found it does not work. If using
smp_prepare_cpus, the kernenl cannot find the secondary cpus because
that smp_prepare_cpus semms not be excuted before kernel is booting
secondary cpus. So I have to use early_initcall.

Fan.

On 26 September 2013 02:44, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Fan,
>
> On Wed, Sep 25, 2013 at 12:22:44AM +0800, cinifr wrote:
>> > You still haven't said why you don't want to use smp_init_cpus there.
>> I find that of_funcation liking of_find_matching_node and of_iomap can
>> not run well in smp_init_cpus. It cause kernel crash. So I have to use
>> early_initcall.
>
> Ah, right.
>
> Then, can't we use smp_prepare_cpus for this? it looks to be late enough
> so that we can use ioremap there.
>
> I don't want it to be an initcall. The code will be different on the
> A31, and we don't want it to be run on all the other machines whenever
> we boot a multiplatform kernel anyway.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

Re: [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 583 bytes --]

Hi Fan,

On Sat, Sep 28, 2013 at 09:48:11PM +0800, cinifr wrote:
> Hi  Maxime,
>     I have test it, but I found it does not work. If using
> smp_prepare_cpus, the kernenl cannot find the secondary cpus because
> that smp_prepare_cpus semms not be excuted before kernel is booting
> secondary cpus. So I have to use early_initcall.

At least two other platforms (sti and rockchip) do it like that.

And an early_initcall is not an option.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Maxime Ripard]

Hi Fan,

On Sat, Sep 28, 2013 at 09:48:11PM +0800, cinifr wrote:
> Hi  Maxime,
>     I have test it, but I found it does not work. If using
> smp_prepare_cpus, the kernenl cannot find the secondary cpus because
> that smp_prepare_cpus semms not be excuted before kernel is booting
> secondary cpus. So I have to use early_initcall.

At least two other platforms (sti and rockchip) do it like that.

And an early_initcall is not an option.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Russell King - ARM Linux]

On Sat, Sep 28, 2013 at 09:48:11PM +0800, cinifr wrote:
> Hi  Maxime,
>     I have test it, but I found it does not work. If using
> smp_prepare_cpus, the kernenl cannot find the secondary cpus because
> that smp_prepare_cpus semms not be excuted before kernel is booting
> secondary cpus. So I have to use early_initcall.

Please don't do this - you're hacking around what could be a real problem.
Instead, please investigate what is going on and why your smp_prepare_cpus()
function never gets called.

Quite honestly, whenever I see crap like the above, it just makes me want
to tell the ARM-SoC people to forever /dev/null your emails because you
really don't know how to deal with the Linux kernel.

Always *fully* investigate a problem that you find to determine whether
it's your problem or some as yet undiscovered kernel bug.  Never hack
around it and then submit a patch suggesting that your workaround is
something that "has" to be done.

[PATCH V3: Add Smp support for Allwinner A20. 1/3] Add smp support for Allwinner A20(sunxi 7i).

[Russell King - ARM Linux]

On Sat, Sep 28, 2013 at 09:48:11PM +0800, cinifr wrote:
> Hi  Maxime,
>     I have test it, but I found it does not work. If using
> smp_prepare_cpus, the kernenl cannot find the secondary cpus because
> that smp_prepare_cpus semms not be excuted before kernel is booting
> secondary cpus. So I have to use early_initcall.

Please don't do this - you're hacking around what could be a real problem.
Instead, please investigate what is going on and why your smp_prepare_cpus()
function never gets called.

Quite honestly, whenever I see crap like the above, it just makes me want
to tell the ARM-SoC people to forever /dev/null your emails because you
really don't know how to deal with the Linux kernel.

Always *fully* investigate a problem that you find to determine whether
it's your problem or some as yet undiscovered kernel bug.  Never hack
around it and then submit a patch suggesting that your workaround is
something that "has" to be done.