From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> To: Anshuman Khandual <khandual@linux.vnet.ibm.com> Cc: linux-kernel@vger.kernel.org, linuxppc-dev@ozlabs.org, Stephane Eranian <eranian@google.com>, Michael Ellerman <michaele@au1.ibm.com>, Paul Mackerras <paulus@samba.org> Subject: Re: [PATCH 8/8][v4] powerpc/perf: Export Power7 memory hierarchy info to user space. Date: Tue, 24 Sep 2013 15:30:18 -0700 [thread overview] Message-ID: <20130924223018.GA21644@us.ibm.com> (raw) In-Reply-To: <523AB8B2.1060202@linux.vnet.ibm.com> Anshuman Khandual [khandual@linux.vnet.ibm.com] wrote: | On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote: | > +static void power7_get_mem_data_src(union perf_mem_data_src *dsrc, | > + struct pt_regs *regs) | > +{ | > + u64 idx; | > + u64 mmcra = regs->dsisr; | > + u64 addr; | > + int ret; | > + unsigned int instr; | > + | > + if (mmcra & POWER7_MMCRA_DCACHE_MISS) { | > + idx = mmcra & POWER7_MMCRA_DCACHE_SRC_MASK; | > + idx >>= POWER7_MMCRA_DCACHE_SRC_SHIFT; | > + | > + dsrc->val |= dcache_src_map[idx]; | > + return; | > + } | > + | > + instr = 0; | > + addr = perf_instruction_pointer(regs); | > + | > + if (is_kernel_addr(addr)) | > + instr = *(unsigned int *)addr; | > + else { | > + pagefault_disable(); | > + ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | > + pagefault_enable(); | > + if (ret) | > + instr = 0; | > + } | > + if (instr && instr_is_load_store(&instr)) | | | Wondering if there is any possibility of getting positive values for | "(mmcra & POWER7_MMCRA_DCACHE_SRC_MASK) >> POWER7_MMCRA_DCACHE_SRC_SHIFT" | when the marked instruction did not have MMCRA[POWER7_MMCRA_DCACHE_MISS] | bit set. In that case we should actually compute dsrc->val as in the previous | case. I did couple of experiments on a P7 box, but was not able to find a | instance for a marked instruction whose MMCRA[POWER7_MMCRA_DCACHE_MISS] bit | not set and have a positive value POWER7_MMCRA_DCACHE_SRC field. Confirmed again with the hardware team that if there was no DCACHE_MISS, the DCACHE_SRC field will be clear. Thanks, Sukadev
WARNING: multiple messages have this Message-ID (diff)
From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> To: Anshuman Khandual <khandual@linux.vnet.ibm.com> Cc: linuxppc-dev@ozlabs.org, Michael Ellerman <michaele@au1.ibm.com>, Paul Mackerras <paulus@samba.org>, linux-kernel@vger.kernel.org, Stephane Eranian <eranian@google.com> Subject: Re: [PATCH 8/8][v4] powerpc/perf: Export Power7 memory hierarchy info to user space. Date: Tue, 24 Sep 2013 15:30:18 -0700 [thread overview] Message-ID: <20130924223018.GA21644@us.ibm.com> (raw) In-Reply-To: <523AB8B2.1060202@linux.vnet.ibm.com> Anshuman Khandual [khandual@linux.vnet.ibm.com] wrote: | On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote: | > +static void power7_get_mem_data_src(union perf_mem_data_src *dsrc, | > + struct pt_regs *regs) | > +{ | > + u64 idx; | > + u64 mmcra = regs->dsisr; | > + u64 addr; | > + int ret; | > + unsigned int instr; | > + | > + if (mmcra & POWER7_MMCRA_DCACHE_MISS) { | > + idx = mmcra & POWER7_MMCRA_DCACHE_SRC_MASK; | > + idx >>= POWER7_MMCRA_DCACHE_SRC_SHIFT; | > + | > + dsrc->val |= dcache_src_map[idx]; | > + return; | > + } | > + | > + instr = 0; | > + addr = perf_instruction_pointer(regs); | > + | > + if (is_kernel_addr(addr)) | > + instr = *(unsigned int *)addr; | > + else { | > + pagefault_disable(); | > + ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | > + pagefault_enable(); | > + if (ret) | > + instr = 0; | > + } | > + if (instr && instr_is_load_store(&instr)) | | | Wondering if there is any possibility of getting positive values for | "(mmcra & POWER7_MMCRA_DCACHE_SRC_MASK) >> POWER7_MMCRA_DCACHE_SRC_SHIFT" | when the marked instruction did not have MMCRA[POWER7_MMCRA_DCACHE_MISS] | bit set. In that case we should actually compute dsrc->val as in the previous | case. I did couple of experiments on a P7 box, but was not able to find a | instance for a marked instruction whose MMCRA[POWER7_MMCRA_DCACHE_MISS] bit | not set and have a positive value POWER7_MMCRA_DCACHE_SRC field. Confirmed again with the hardware team that if there was no DCACHE_MISS, the DCACHE_SRC field will be clear. Thanks, Sukadev
next prev parent reply other threads:[~2013-09-24 22:30 UTC|newest] Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-09-14 0:49 [PATCH 0/8][v4] powerpc/perf: Export memory hierarchy level in Power7/8 Sukadev Bhattiprolu 2013-09-14 0:49 ` Sukadev Bhattiprolu 2013-09-14 0:49 ` [PATCH 1/8][v4] powerpc/perf: Rename Power8 macros to start with PME Sukadev Bhattiprolu 2013-09-14 0:49 ` Sukadev Bhattiprolu 2013-09-18 5:24 ` Anshuman Khandual 2013-09-18 5:24 ` Anshuman Khandual 2013-09-14 0:49 ` [PATCH 2/8][v4] powerpc/perf: Export Power8 generic events in sysfs Sukadev Bhattiprolu 2013-09-14 0:49 ` Sukadev Bhattiprolu 2013-09-14 0:49 ` [PATCH 3/8][v4] powerpc/perf: Add PM_MRK_GRP_CMPL event to sysfs Sukadev Bhattiprolu 2013-09-14 0:49 ` Sukadev Bhattiprolu 2013-09-14 0:49 ` [PATCH 4/8][v4] powerpc/perf: Define big-endian version of perf_mem_data_src Sukadev Bhattiprolu 2013-09-14 0:49 ` Sukadev Bhattiprolu 2013-09-14 0:49 ` [PATCH 5/8][v4] powerpc/perf: Export Power8 memory hierarchy info to user space Sukadev Bhattiprolu 2013-09-14 0:49 ` Sukadev Bhattiprolu 2013-09-14 0:49 ` [PATCH 6/8][v4] powerpc: Rename branch_opcode() to instr_opcode() Sukadev Bhattiprolu 2013-09-14 0:49 ` Sukadev Bhattiprolu 2013-09-14 0:49 ` [PATCH 7/8][v4] power: implement is_instr_load_store() Sukadev Bhattiprolu 2013-09-14 0:49 ` Sukadev Bhattiprolu 2013-09-16 12:22 ` Tom Musta 2013-09-14 0:49 ` [PATCH 8/8][v4] powerpc/perf: Export Power7 memory hierarchy info to user space Sukadev Bhattiprolu 2013-09-14 0:49 ` Sukadev Bhattiprolu 2013-09-18 10:47 ` Anshuman Khandual 2013-09-18 10:47 ` Anshuman Khandual 2013-09-19 8:41 ` Anshuman Khandual 2013-09-19 8:41 ` Anshuman Khandual 2013-09-24 22:30 ` Sukadev Bhattiprolu [this message] 2013-09-24 22:30 ` Sukadev Bhattiprolu
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