* [Qemu-devel] [PATCH] target-ppc: Little Endian Correction to Load/Store Vector Element
@ 2013-09-25 7:42 Anton Blanchard
2013-09-25 12:38 ` Alexander Graf
0 siblings, 1 reply; 2+ messages in thread
From: Anton Blanchard @ 2013-09-25 7:42 UTC (permalink / raw)
To: agraf; +Cc: tommusta, qemu-ppc, qemu-devel
From: Tom Musta <tommusta@gmail.com>
The Load Vector Element (lve*x) and Store Vector Element (stve*x)
instructions not only byte-swap in Little Endian mode, they also
invert the element that is accessed. For example, the RTL for
lvehx contains this:
eb <-- EA[60:63]
if Big-Endian byte ordering then
VRT[8*eb:8*eb+15] <-- MEM(EA,2)
else
VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2)
This patch adds the element inversion, as described in the last line
of the RTL.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Anton Blanchard <anton@samba.org>
---
Index: b/target-ppc/mem_helper.c
===================================================================
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -212,6 +212,7 @@ target_ulong helper_lscbx(CPUPPCState *e
int index = (addr & 0xf) >> sh; \
\
if (msr_le) { \
+ index = n_elems - index - 1; \
r->element[LO_IDX ? index : (adjust - index)] = \
swap(access(env, addr)); \
} else { \
@@ -236,6 +237,7 @@ LVE(lvewx, cpu_ldl_data, bswap32, u32)
int index = (addr & 0xf) >> sh; \
\
if (msr_le) { \
+ index = n_elems - index - 1; \
access(env, addr, swap(r->element[LO_IDX ? index : \
(adjust - index)])); \
} else { \
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH] target-ppc: Little Endian Correction to Load/Store Vector Element
2013-09-25 7:42 [Qemu-devel] [PATCH] target-ppc: Little Endian Correction to Load/Store Vector Element Anton Blanchard
@ 2013-09-25 12:38 ` Alexander Graf
0 siblings, 0 replies; 2+ messages in thread
From: Alexander Graf @ 2013-09-25 12:38 UTC (permalink / raw)
To: Anton Blanchard; +Cc: tommusta, qemu-ppc, qemu-devel
On 25.09.2013, at 09:42, Anton Blanchard wrote:
> From: Tom Musta <tommusta@gmail.com>
>
> The Load Vector Element (lve*x) and Store Vector Element (stve*x)
> instructions not only byte-swap in Little Endian mode, they also
> invert the element that is accessed. For example, the RTL for
> lvehx contains this:
>
> eb <-- EA[60:63]
> if Big-Endian byte ordering then
> VRT[8*eb:8*eb+15] <-- MEM(EA,2)
> else
> VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2)
>
> This patch adds the element inversion, as described in the last line
> of the RTL.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> Reviewed-by: Anton Blanchard <anton@samba.org>
Thanks, applied to ppc-next.
For the future, you probably want to make this a SoB instead of a Reviewed-by line :).
Alex
^ permalink raw reply [flat|nested] 2+ messages in thread
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2013-09-25 7:42 [Qemu-devel] [PATCH] target-ppc: Little Endian Correction to Load/Store Vector Element Anton Blanchard
2013-09-25 12:38 ` Alexander Graf
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