* [PATCH RFC 0/2] Initial Solid Run Cubox-i carrier-1 support
@ 2013-10-05 11:21 ` Russell King - ARM Linux
0 siblings, 0 replies; 24+ messages in thread
From: Russell King - ARM Linux @ 2013-10-05 11:21 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Ian Campbell, Mark Rutland, Pawel Moll, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Warren
This is where I am at the moment with the SolidRun Cubox-i Carrier-1
board support with v3.12-rc3. What's included and tested here is:
- Consumer IR
- SD card slot
- AR8035 ethernet phy
- HDMI DDC I2C
- USB
What isn't included:
- RTC (commented out) since the chip is not fitted to developer boards yet
- HDMI output
- SPDIF output
- Audio output (codec not fitted)
- Wireless (not fitted)
I'm sending this out as an RFC as it's not at the point for merging, but
those with the developer board should find it useful to get their boards
up and running with recent kernels.
--
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 0/2] Initial Solid Run Cubox-i carrier-1 support
@ 2013-10-05 11:21 ` Russell King - ARM Linux
0 siblings, 0 replies; 24+ messages in thread
From: Russell King - ARM Linux @ 2013-10-05 11:21 UTC (permalink / raw)
To: linux-arm-kernel
This is where I am at the moment with the SolidRun Cubox-i Carrier-1
board support with v3.12-rc3. What's included and tested here is:
- Consumer IR
- SD card slot
- AR8035 ethernet phy
- HDMI DDC I2C
- USB
What isn't included:
- RTC (commented out) since the chip is not fitted to developer boards yet
- HDMI output
- SPDIF output
- Audio output (codec not fitted)
- Wireless (not fitted)
I'm sending this out as an RFC as it's not at the point for merging, but
those with the developer board should find it useful to get their boards
up and running with recent kernels.
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-05 11:21 ` Russell King - ARM Linux
@ 2013-10-05 11:22 ` Russell King
-1 siblings, 0 replies; 24+ messages in thread
From: Russell King @ 2013-10-05 11:22 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren, Ian Campbell
DAT3 needs to be pulled down if the USDHC card detection facility is
used rather than GPIO mode. This is due to there being two methods
to detect a card - one via the card detect signal, and the other via
DAT3 being pulled up by the inserted card via an internal 50k resistor.
This requires DAT3 to be pulled down to hold the signal in the "no
card" state, using a 100k pull down setting.
Provide pinctrl settings for this for all USDHC controllers.
Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl.dtsi | 104 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 104 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index ccd55c2..199fdab 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1138,6 +1138,32 @@
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
+ MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_2_dat3cd: usdhc1grp-4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
+ >;
+ };
};
usdhc2 {
@@ -1166,6 +1192,32 @@
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc2_1_dat3cd: usdhc2grp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_2_dat3cd: usdhc2grp-4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+ >;
+ };
};
usdhc3 {
@@ -1194,6 +1246,32 @@
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc3_1_dat3cd: usdhc3grp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_2_dat3cd: usdhc3grp-4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
+ >;
+ };
};
usdhc4 {
@@ -1222,6 +1300,32 @@
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc4_1_dat3cd: usdhc4grp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc4_2_dat3cd: usdhc4grp-4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
+ >;
+ };
};
weim {
--
1.7.4.4
--
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-05 11:22 ` Russell King
0 siblings, 0 replies; 24+ messages in thread
From: Russell King @ 2013-10-05 11:22 UTC (permalink / raw)
To: linux-arm-kernel
DAT3 needs to be pulled down if the USDHC card detection facility is
used rather than GPIO mode. This is due to there being two methods
to detect a card - one via the card detect signal, and the other via
DAT3 being pulled up by the inserted card via an internal 50k resistor.
This requires DAT3 to be pulled down to hold the signal in the "no
card" state, using a 100k pull down setting.
Provide pinctrl settings for this for all USDHC controllers.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/boot/dts/imx6qdl.dtsi | 104 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 104 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index ccd55c2..199fdab 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1138,6 +1138,32 @@
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
+ MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_2_dat3cd: usdhc1grp-4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
+ >;
+ };
};
usdhc2 {
@@ -1166,6 +1192,32 @@
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc2_1_dat3cd: usdhc2grp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_2_dat3cd: usdhc2grp-4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+ >;
+ };
};
usdhc3 {
@@ -1194,6 +1246,32 @@
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc3_1_dat3cd: usdhc3grp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_2_dat3cd: usdhc3grp-4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
+ >;
+ };
};
usdhc4 {
@@ -1222,6 +1300,32 @@
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc4_1_dat3cd: usdhc4grp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc4_2_dat3cd: usdhc4grp-4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
+ >;
+ };
};
weim {
--
1.7.4.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH RFC 2/2] ARM: imx: initial IMX6 Cubox-i carrier-1 support
2013-10-05 11:21 ` Russell King - ARM Linux
@ 2013-10-05 11:23 ` Russell King
-1 siblings, 0 replies; 24+ messages in thread
From: Russell King @ 2013-10-05 11:23 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Shawn Guo, Sascha Hauer
Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts | 64 +++++++++++
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi | 54 +++++++++
arch/arm/boot/dts/imx6qdl-microsom.dtsi | 137 ++++++++++++++++++++++++
arch/arm/mach-imx/mach-imx6q.c | 35 ++++++
5 files changed, 291 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-microsom.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e95af3f..8e0fb04 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -131,6 +131,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx53-mba53.dtb \
imx53-qsb.dtb \
imx53-smd.dtb \
+ imx6dl-cubox-i-carrier-1.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-wandboard.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts b/arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts
new file mode 100644
index 0000000..2e160c7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013 Russell King
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License version 2.
+ */
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-microsom.dtsi"
+#include "imx6qdl-microsom-ar8035.dtsi"
+
+/ {
+ model = "SolidRun Cubox-i DL/Solo Carrier-1 Board";
+ compatible = "solidrun,cubox-i-carrier-1", "fsl,imx6dl";
+
+ ir_recv: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio1 2 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1_2_carrier_1>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_1>;
+
+ /*
+ * Not fitted on Carrier-1 board... yet
+ status = "okay";
+
+ rtc: pcf8523@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+ */
+};
+
+&iomuxc {
+ ir_recv {
+ pinctrl_gpio1_2_carrier_1: gpio1_2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
+ >;
+ };
+ };
+
+ usbhc2 {
+ pinctrl_usdhc2_cd_wp: usdhc2_cd_wp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1f071
+ >;
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_2_dat3cd &pinctrl_usdhc2_cd_wp>;
+ vmmc-supply = <®_3p3v>;
+ fsl,cd-controller;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
new file mode 100644
index 0000000..73f20a2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2013 Russell King
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License version 2.
+ *
+ * This describes the hookup for an AR8035 to the IMX6 on the Cubox-i
+ * MicroSOM.
+ */
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_1_ar8035>;
+ phy-mode = "rgmii";
+ phy-reset-duration = <2>;
+ phy-reset-gpios = <&gpio4 15 0>;
+ status = "okay";
+};
+
+&iomuxc {
+ enet {
+ pinctrl_enet_1_ar8035: enetgrp-ar8035 {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ /* AR8035 reset */
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
+ /* AR8035 interrupt */
+ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000
+ /* GPIO16 -> AR8035 25MHz */
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
+ /* AR8035 pin strapping: IO voltage: pull up */
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ /* AR8035 pin strapping: PHYADDR#0: pull down */
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
+ /* AR8035 pin strapping: PHYADDR#1: pull down */
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
+ /* AR8035 pin strapping: MODE#1: pull up */
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ /* AR8035 pin strapping: MODE#3: pull up */
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ /* AR8035 pin strapping: MODE#0: pull down */
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
+ >;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
new file mode 100644
index 0000000..3db6046
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -0,0 +1,137 @@
+/*
+ * Copyright 2013 Russell King
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License version 2.
+ */
+/ {
+ regulators {
+ compatible = "simple-bus";
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: usb_otg_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 0>;
+ enable-active-high;
+ };
+
+ reg_usb_h1_vbus: usb_h1_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 0 0>;
+ enable-active-high;
+ };
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1_2>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_2>;
+ status = "okay";
+
+ /* HDMI @0x50 */
+};
+
+&iomuxc {
+ pinctrl_spdif_2_out_only: spdifgrp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+ >;
+ };
+
+ usbotg {
+ pinctrl_usbotg_cubox: usbotggrp-3 {
+ /*
+ * Similar to pinctrl_usbotg_2, but we want it
+ * pulled down for a fixed host connection.
+ */
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
+ >;
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg_cubox>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+/* experimental stuff */
+
+/* USDHC1 - Connected to BRCM Wifi/BT/FM */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_2>;
+ status = "okay";
+};
+
+/* SPDIF out */
+
+/* CAN1 */
+/* CCM */
+
+/* ECSPI2 */
+
+/* I2C1 */
+/* I2C2 - HDMI DDC */
+
+/* I2C3 */
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_1>;
+ status = "okay";
+};
+
+/* PWM */
+
+/* UART2 */
+
+/* USB OC pin */
+
+/* USDHC2 */
+
+/* USDHC3 */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3_1>;
+ status = "disabled";
+};
+
+/* USDHC4 */
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4_1>;
+ status = "disabled";
+};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 90372a2..222edbd 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -164,6 +164,39 @@ static int ar8031_phy_fixup(struct phy_device *dev)
#define PHY_ID_AR8031 0x004dd074
+static int ar8035_phy_fixup(struct phy_device *dev)
+{
+ u16 val;
+
+ /* Ar803x phy SmartEEE feature cause link status generates glitch,
+ * which cause ethernet link down/up issue, so disable SmartEEE
+ */
+ phy_write(dev, 0xd, 0x3);
+ phy_write(dev, 0xe, 0x805d);
+ phy_write(dev, 0xd, 0x4003);
+
+ val = phy_read(dev, 0xe);
+ phy_write(dev, 0xe, val & ~(1 << 8));
+
+ /*
+ * Enable 125MHz clock from CLK_25M on the AR8031. This
+ * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
+ * Also, introduce a tx clock delay.
+ *
+ * This is the same as is the AR8031 fixup.
+ */
+ ar8031_phy_fixup(dev);
+
+ /*check phy power*/
+ val = phy_read(dev, 0x0);
+ if (val & BMCR_PDOWN)
+ phy_write(dev, 0x0, val & ~BMCR_PDOWN);
+
+ return 0;
+}
+
+#define PHY_ID_AR8035 0x004dd072
+
static void __init imx6q_enet_phy_init(void)
{
if (IS_BUILTIN(CONFIG_PHYLIB)) {
@@ -173,6 +206,8 @@ static void __init imx6q_enet_phy_init(void)
ksz9031rn_phy_fixup);
phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
ar8031_phy_fixup);
+ phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
+ ar8035_phy_fixup);
}
}
--
1.7.4.4
--
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH RFC 2/2] ARM: imx: initial IMX6 Cubox-i carrier-1 support
@ 2013-10-05 11:23 ` Russell King
0 siblings, 0 replies; 24+ messages in thread
From: Russell King @ 2013-10-05 11:23 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts | 64 +++++++++++
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi | 54 +++++++++
arch/arm/boot/dts/imx6qdl-microsom.dtsi | 137 ++++++++++++++++++++++++
arch/arm/mach-imx/mach-imx6q.c | 35 ++++++
5 files changed, 291 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-microsom.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e95af3f..8e0fb04 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -131,6 +131,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx53-mba53.dtb \
imx53-qsb.dtb \
imx53-smd.dtb \
+ imx6dl-cubox-i-carrier-1.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-wandboard.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts b/arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts
new file mode 100644
index 0000000..2e160c7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-cubox-i-carrier-1.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013 Russell King
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License version 2.
+ */
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-microsom.dtsi"
+#include "imx6qdl-microsom-ar8035.dtsi"
+
+/ {
+ model = "SolidRun Cubox-i DL/Solo Carrier-1 Board";
+ compatible = "solidrun,cubox-i-carrier-1", "fsl,imx6dl";
+
+ ir_recv: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio1 2 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1_2_carrier_1>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_1>;
+
+ /*
+ * Not fitted on Carrier-1 board... yet
+ status = "okay";
+
+ rtc: pcf8523 at 68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+ */
+};
+
+&iomuxc {
+ ir_recv {
+ pinctrl_gpio1_2_carrier_1: gpio1_2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
+ >;
+ };
+ };
+
+ usbhc2 {
+ pinctrl_usdhc2_cd_wp: usdhc2_cd_wp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1f071
+ >;
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_2_dat3cd &pinctrl_usdhc2_cd_wp>;
+ vmmc-supply = <®_3p3v>;
+ fsl,cd-controller;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
new file mode 100644
index 0000000..73f20a2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2013 Russell King
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License version 2.
+ *
+ * This describes the hookup for an AR8035 to the IMX6 on the Cubox-i
+ * MicroSOM.
+ */
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_1_ar8035>;
+ phy-mode = "rgmii";
+ phy-reset-duration = <2>;
+ phy-reset-gpios = <&gpio4 15 0>;
+ status = "okay";
+};
+
+&iomuxc {
+ enet {
+ pinctrl_enet_1_ar8035: enetgrp-ar8035 {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ /* AR8035 reset */
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
+ /* AR8035 interrupt */
+ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000
+ /* GPIO16 -> AR8035 25MHz */
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
+ /* AR8035 pin strapping: IO voltage: pull up */
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ /* AR8035 pin strapping: PHYADDR#0: pull down */
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
+ /* AR8035 pin strapping: PHYADDR#1: pull down */
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
+ /* AR8035 pin strapping: MODE#1: pull up */
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ /* AR8035 pin strapping: MODE#3: pull up */
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ /* AR8035 pin strapping: MODE#0: pull down */
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
+ >;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
new file mode 100644
index 0000000..3db6046
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -0,0 +1,137 @@
+/*
+ * Copyright 2013 Russell King
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License version 2.
+ */
+/ {
+ regulators {
+ compatible = "simple-bus";
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: usb_otg_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 0>;
+ enable-active-high;
+ };
+
+ reg_usb_h1_vbus: usb_h1_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 0 0>;
+ enable-active-high;
+ };
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1_2>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_2>;
+ status = "okay";
+
+ /* HDMI @0x50 */
+};
+
+&iomuxc {
+ pinctrl_spdif_2_out_only: spdifgrp-3 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+ >;
+ };
+
+ usbotg {
+ pinctrl_usbotg_cubox: usbotggrp-3 {
+ /*
+ * Similar to pinctrl_usbotg_2, but we want it
+ * pulled down for a fixed host connection.
+ */
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
+ >;
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg_cubox>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+/* experimental stuff */
+
+/* USDHC1 - Connected to BRCM Wifi/BT/FM */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_2>;
+ status = "okay";
+};
+
+/* SPDIF out */
+
+/* CAN1 */
+/* CCM */
+
+/* ECSPI2 */
+
+/* I2C1 */
+/* I2C2 - HDMI DDC */
+
+/* I2C3 */
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_1>;
+ status = "okay";
+};
+
+/* PWM */
+
+/* UART2 */
+
+/* USB OC pin */
+
+/* USDHC2 */
+
+/* USDHC3 */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3_1>;
+ status = "disabled";
+};
+
+/* USDHC4 */
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4_1>;
+ status = "disabled";
+};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 90372a2..222edbd 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -164,6 +164,39 @@ static int ar8031_phy_fixup(struct phy_device *dev)
#define PHY_ID_AR8031 0x004dd074
+static int ar8035_phy_fixup(struct phy_device *dev)
+{
+ u16 val;
+
+ /* Ar803x phy SmartEEE feature cause link status generates glitch,
+ * which cause ethernet link down/up issue, so disable SmartEEE
+ */
+ phy_write(dev, 0xd, 0x3);
+ phy_write(dev, 0xe, 0x805d);
+ phy_write(dev, 0xd, 0x4003);
+
+ val = phy_read(dev, 0xe);
+ phy_write(dev, 0xe, val & ~(1 << 8));
+
+ /*
+ * Enable 125MHz clock from CLK_25M on the AR8031. This
+ * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
+ * Also, introduce a tx clock delay.
+ *
+ * This is the same as is the AR8031 fixup.
+ */
+ ar8031_phy_fixup(dev);
+
+ /*check phy power*/
+ val = phy_read(dev, 0x0);
+ if (val & BMCR_PDOWN)
+ phy_write(dev, 0x0, val & ~BMCR_PDOWN);
+
+ return 0;
+}
+
+#define PHY_ID_AR8035 0x004dd072
+
static void __init imx6q_enet_phy_init(void)
{
if (IS_BUILTIN(CONFIG_PHYLIB)) {
@@ -173,6 +206,8 @@ static void __init imx6q_enet_phy_init(void)
ksz9031rn_phy_fixup);
phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
ar8031_phy_fixup);
+ phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
+ ar8035_phy_fixup);
}
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-05 11:22 ` Russell King
@ 2013-10-07 5:53 ` Shawn Guo
-1 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-07 5:53 UTC (permalink / raw)
To: Russell King
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Ian Campbell, Pawel Moll, Rob Herring, Stephen Warren
On Sat, Oct 05, 2013 at 12:22:17PM +0100, Russell King wrote:
> DAT3 needs to be pulled down if the USDHC card detection facility is
> used rather than GPIO mode. This is due to there being two methods
> to detect a card - one via the card detect signal, and the other via
> DAT3 being pulled up by the inserted card via an internal 50k resistor.
>
> This requires DAT3 to be pulled down to hold the signal in the "no
> card" state, using a 100k pull down setting.
>
> Provide pinctrl settings for this for all USDHC controllers.
>
> Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
> ---
> arch/arm/boot/dts/imx6qdl.dtsi | 104 ++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 104 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index ccd55c2..199fdab 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -1138,6 +1138,32 @@
> MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
> + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
> + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
> + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
> + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
> + >;
> + };
I think we can redefine only pad DAT3 in pinctrl_usdhc1_1_dat3cd, and
overwrite the DAT3 configuration in pinctrl_usdhc1_1 to save the
redundant data of other pads, something like the following.
pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
>;
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
...
status = "okay";
};
Shawn
> +
> + pinctrl_usdhc1_2_dat3cd: usdhc1grp-4 {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
> + >;
> + };
> };
>
> usdhc2 {
> @@ -1166,6 +1192,32 @@
> MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc2_1_dat3cd: usdhc2grp-3 {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
> + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
> + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
> + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
> + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc2_2_dat3cd: usdhc2grp-4 {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
> + >;
> + };
> };
>
> usdhc3 {
> @@ -1194,6 +1246,32 @@
> MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc3_1_dat3cd: usdhc3grp-3 {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_2_dat3cd: usdhc3grp-4 {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
> + >;
> + };
> };
>
> usdhc4 {
> @@ -1222,6 +1300,32 @@
> MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc4_1_dat3cd: usdhc4grp-3 {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc4_2_dat3cd: usdhc4grp-4 {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
> + >;
> + };
> };
>
> weim {
> --
> 1.7.4.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-07 5:53 ` Shawn Guo
0 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-07 5:53 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Oct 05, 2013 at 12:22:17PM +0100, Russell King wrote:
> DAT3 needs to be pulled down if the USDHC card detection facility is
> used rather than GPIO mode. This is due to there being two methods
> to detect a card - one via the card detect signal, and the other via
> DAT3 being pulled up by the inserted card via an internal 50k resistor.
>
> This requires DAT3 to be pulled down to hold the signal in the "no
> card" state, using a 100k pull down setting.
>
> Provide pinctrl settings for this for all USDHC controllers.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
> arch/arm/boot/dts/imx6qdl.dtsi | 104 ++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 104 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index ccd55c2..199fdab 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -1138,6 +1138,32 @@
> MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
> + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
> + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
> + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
> + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
> + >;
> + };
I think we can redefine only pad DAT3 in pinctrl_usdhc1_1_dat3cd, and
overwrite the DAT3 configuration in pinctrl_usdhc1_1 to save the
redundant data of other pads, something like the following.
pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
>;
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
...
status = "okay";
};
Shawn
> +
> + pinctrl_usdhc1_2_dat3cd: usdhc1grp-4 {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
> + >;
> + };
> };
>
> usdhc2 {
> @@ -1166,6 +1192,32 @@
> MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc2_1_dat3cd: usdhc2grp-3 {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
> + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
> + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
> + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
> + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc2_2_dat3cd: usdhc2grp-4 {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
> + >;
> + };
> };
>
> usdhc3 {
> @@ -1194,6 +1246,32 @@
> MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc3_1_dat3cd: usdhc3grp-3 {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_2_dat3cd: usdhc3grp-4 {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
> + >;
> + };
> };
>
> usdhc4 {
> @@ -1222,6 +1300,32 @@
> MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> >;
> };
> +
> + pinctrl_usdhc4_1_dat3cd: usdhc4grp-3 {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc4_2_dat3cd: usdhc4grp-4 {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
> + >;
> + };
> };
>
> weim {
> --
> 1.7.4.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-07 5:53 ` Shawn Guo
@ 2013-10-07 18:03 ` Russell King - ARM Linux
-1 siblings, 0 replies; 24+ messages in thread
From: Russell King - ARM Linux @ 2013-10-07 18:03 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Ian Campbell, Pawel Moll, Rob Herring, Stephen Warren
On Mon, Oct 07, 2013 at 01:53:43PM +0800, Shawn Guo wrote:
> I think we can redefine only pad DAT3 in pinctrl_usdhc1_1_dat3cd, and
> overwrite the DAT3 configuration in pinctrl_usdhc1_1 to save the
> redundant data of other pads, something like the following.
>
> pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
> fsl,pins = <
> MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
> >;
> };
>
> &usdhc1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> ...
> status = "okay";
> };
Are you sure that this will always be the case? This would assume that
the pinctrl entries are always processed sequentially.
--
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-07 18:03 ` Russell King - ARM Linux
0 siblings, 0 replies; 24+ messages in thread
From: Russell King - ARM Linux @ 2013-10-07 18:03 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Oct 07, 2013 at 01:53:43PM +0800, Shawn Guo wrote:
> I think we can redefine only pad DAT3 in pinctrl_usdhc1_1_dat3cd, and
> overwrite the DAT3 configuration in pinctrl_usdhc1_1 to save the
> redundant data of other pads, something like the following.
>
> pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
> fsl,pins = <
> MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
> >;
> };
>
> &usdhc1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> ...
> status = "okay";
> };
Are you sure that this will always be the case? This would assume that
the pinctrl entries are always processed sequentially.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-07 18:03 ` Russell King - ARM Linux
@ 2013-10-08 1:54 ` Shawn Guo
-1 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-08 1:54 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Ian Campbell, Pawel Moll, Rob Herring, Stephen Warren
On Mon, Oct 07, 2013 at 07:03:57PM +0100, Russell King - ARM Linux wrote:
> On Mon, Oct 07, 2013 at 01:53:43PM +0800, Shawn Guo wrote:
> > I think we can redefine only pad DAT3 in pinctrl_usdhc1_1_dat3cd, and
> > overwrite the DAT3 configuration in pinctrl_usdhc1_1 to save the
> > redundant data of other pads, something like the following.
> >
> > pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
> > fsl,pins = <
> > MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
> > >;
> > };
> >
> > &usdhc1 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> > ...
> > status = "okay";
> > };
>
> Are you sure that this will always be the case? This would assume that
> the pinctrl entries are always processed sequentially.
That will always be the case per my understanding. Otherwise, I would
be so surprised. Are you seeing any case that the entries are not
processed sequentially?
Shawn
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-08 1:54 ` Shawn Guo
0 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-08 1:54 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Oct 07, 2013 at 07:03:57PM +0100, Russell King - ARM Linux wrote:
> On Mon, Oct 07, 2013 at 01:53:43PM +0800, Shawn Guo wrote:
> > I think we can redefine only pad DAT3 in pinctrl_usdhc1_1_dat3cd, and
> > overwrite the DAT3 configuration in pinctrl_usdhc1_1 to save the
> > redundant data of other pads, something like the following.
> >
> > pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
> > fsl,pins = <
> > MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
> > >;
> > };
> >
> > &usdhc1 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> > ...
> > status = "okay";
> > };
>
> Are you sure that this will always be the case? This would assume that
> the pinctrl entries are always processed sequentially.
That will always be the case per my understanding. Otherwise, I would
be so surprised. Are you seeing any case that the entries are not
processed sequentially?
Shawn
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-08 1:54 ` Shawn Guo
@ 2013-10-08 2:52 ` Stephen Warren
-1 siblings, 0 replies; 24+ messages in thread
From: Stephen Warren @ 2013-10-08 2:52 UTC (permalink / raw)
To: Shawn Guo, Russell King - ARM Linux
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Ian Campbell, Pawel Moll, Rob Herring
On 10/07/2013 07:54 PM, Shawn Guo wrote:
> On Mon, Oct 07, 2013 at 07:03:57PM +0100, Russell King - ARM Linux wrote:
>> On Mon, Oct 07, 2013 at 01:53:43PM +0800, Shawn Guo wrote:
>>> I think we can redefine only pad DAT3 in pinctrl_usdhc1_1_dat3cd, and
>>> overwrite the DAT3 configuration in pinctrl_usdhc1_1 to save the
>>> redundant data of other pads, something like the following.
>>>
>>> pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
>>> fsl,pins = <
>>> MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
>>> >;
>>> };
>>>
>>> &usdhc1 {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
>>> ...
>>> status = "okay";
>>> };
>>
>> Are you sure that this will always be the case? This would assume that
>> the pinctrl entries are always processed sequentially.
>
> That will always be the case per my understanding. Otherwise, I would
> be so surprised. Are you seeing any case that the entries are not
> processed sequentially?
Given the way the Linux code currently works, I think that will
currently happen in practice. However, there's nothing in the pinctrl DT
binding documentation that guarantees (or even mentions) such semantics.
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-08 2:52 ` Stephen Warren
0 siblings, 0 replies; 24+ messages in thread
From: Stephen Warren @ 2013-10-08 2:52 UTC (permalink / raw)
To: linux-arm-kernel
On 10/07/2013 07:54 PM, Shawn Guo wrote:
> On Mon, Oct 07, 2013 at 07:03:57PM +0100, Russell King - ARM Linux wrote:
>> On Mon, Oct 07, 2013 at 01:53:43PM +0800, Shawn Guo wrote:
>>> I think we can redefine only pad DAT3 in pinctrl_usdhc1_1_dat3cd, and
>>> overwrite the DAT3 configuration in pinctrl_usdhc1_1 to save the
>>> redundant data of other pads, something like the following.
>>>
>>> pinctrl_usdhc1_1_dat3cd: usdhc1grp-3 {
>>> fsl,pins = <
>>> MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
>>> >;
>>> };
>>>
>>> &usdhc1 {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
>>> ...
>>> status = "okay";
>>> };
>>
>> Are you sure that this will always be the case? This would assume that
>> the pinctrl entries are always processed sequentially.
>
> That will always be the case per my understanding. Otherwise, I would
> be so surprised. Are you seeing any case that the entries are not
> processed sequentially?
Given the way the Linux code currently works, I think that will
currently happen in practice. However, there's nothing in the pinctrl DT
binding documentation that guarantees (or even mentions) such semantics.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-08 2:52 ` Stephen Warren
@ 2013-10-08 3:40 ` Shawn Guo
-1 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-08 3:40 UTC (permalink / raw)
To: Stephen Warren
Cc: Russell King - ARM Linux, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Ian Campbell, Pawel Moll, Rob Herring
On Mon, Oct 07, 2013 at 08:52:40PM -0600, Stephen Warren wrote:
> >>> &usdhc1 {
> >>> pinctrl-names = "default";
> >>> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> >>> ...
> >>> status = "okay";
> >>> };
> >>
> >> Are you sure that this will always be the case? This would assume that
> >> the pinctrl entries are always processed sequentially.
> >
> > That will always be the case per my understanding. Otherwise, I would
> > be so surprised. Are you seeing any case that the entries are not
> > processed sequentially?
>
> Given the way the Linux code currently works, I think that will
> currently happen in practice. However, there's nothing in the pinctrl DT
> binding documentation that guarantees (or even mentions) such semantics.
Ah, that's Russell's point, I guess. I think it makes perfect sense to
make this clear in the binding doc, as this "overwrite mechanism" can be
very helpful. I will send a patch for it.
Shawn
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-08 3:40 ` Shawn Guo
0 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-08 3:40 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Oct 07, 2013 at 08:52:40PM -0600, Stephen Warren wrote:
> >>> &usdhc1 {
> >>> pinctrl-names = "default";
> >>> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> >>> ...
> >>> status = "okay";
> >>> };
> >>
> >> Are you sure that this will always be the case? This would assume that
> >> the pinctrl entries are always processed sequentially.
> >
> > That will always be the case per my understanding. Otherwise, I would
> > be so surprised. Are you seeing any case that the entries are not
> > processed sequentially?
>
> Given the way the Linux code currently works, I think that will
> currently happen in practice. However, there's nothing in the pinctrl DT
> binding documentation that guarantees (or even mentions) such semantics.
Ah, that's Russell's point, I guess. I think it makes perfect sense to
make this clear in the binding doc, as this "overwrite mechanism" can be
very helpful. I will send a patch for it.
Shawn
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-08 3:40 ` Shawn Guo
@ 2013-10-08 9:00 ` Russell King - ARM Linux
-1 siblings, 0 replies; 24+ messages in thread
From: Russell King - ARM Linux @ 2013-10-08 9:00 UTC (permalink / raw)
To: Shawn Guo
Cc: Stephen Warren, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Ian Campbell, Pawel Moll, Rob Herring
On Tue, Oct 08, 2013 at 11:40:51AM +0800, Shawn Guo wrote:
> On Mon, Oct 07, 2013 at 08:52:40PM -0600, Stephen Warren wrote:
> > >>> &usdhc1 {
> > >>> pinctrl-names = "default";
> > >>> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> > >>> ...
> > >>> status = "okay";
> > >>> };
> > >>
> > >> Are you sure that this will always be the case? This would assume that
> > >> the pinctrl entries are always processed sequentially.
> > >
> > > That will always be the case per my understanding. Otherwise, I would
> > > be so surprised. Are you seeing any case that the entries are not
> > > processed sequentially?
> >
> > Given the way the Linux code currently works, I think that will
> > currently happen in practice. However, there's nothing in the pinctrl DT
> > binding documentation that guarantees (or even mentions) such semantics.
>
> Ah, that's Russell's point, I guess. I think it makes perfect sense to
> make this clear in the binding doc, as this "overwrite mechanism" can be
> very helpful. I will send a patch for it.
Exactly - otherwise we're just relying on implementation details.
There's nothing at present which mandates starting at the first entry
and working through sequentially to the last entry, which means another
implementation can choose to operate in the opposite order. If it does,
what you're suggesting won't work so well.
However, there's another point to consider. In cases like this, we will
cause a glitch on the pin. When we process the initial set, we will set
the pull-up high, and then later set it low. That may not be a problem
in this case, but that's not to say it won't be in every case, and that's
something which also needs to be considered.
--
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-08 9:00 ` Russell King - ARM Linux
0 siblings, 0 replies; 24+ messages in thread
From: Russell King - ARM Linux @ 2013-10-08 9:00 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Oct 08, 2013 at 11:40:51AM +0800, Shawn Guo wrote:
> On Mon, Oct 07, 2013 at 08:52:40PM -0600, Stephen Warren wrote:
> > >>> &usdhc1 {
> > >>> pinctrl-names = "default";
> > >>> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> > >>> ...
> > >>> status = "okay";
> > >>> };
> > >>
> > >> Are you sure that this will always be the case? This would assume that
> > >> the pinctrl entries are always processed sequentially.
> > >
> > > That will always be the case per my understanding. Otherwise, I would
> > > be so surprised. Are you seeing any case that the entries are not
> > > processed sequentially?
> >
> > Given the way the Linux code currently works, I think that will
> > currently happen in practice. However, there's nothing in the pinctrl DT
> > binding documentation that guarantees (or even mentions) such semantics.
>
> Ah, that's Russell's point, I guess. I think it makes perfect sense to
> make this clear in the binding doc, as this "overwrite mechanism" can be
> very helpful. I will send a patch for it.
Exactly - otherwise we're just relying on implementation details.
There's nothing at present which mandates starting at the first entry
and working through sequentially to the last entry, which means another
implementation can choose to operate in the opposite order. If it does,
what you're suggesting won't work so well.
However, there's another point to consider. In cases like this, we will
cause a glitch on the pin. When we process the initial set, we will set
the pull-up high, and then later set it low. That may not be a problem
in this case, but that's not to say it won't be in every case, and that's
something which also needs to be considered.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-08 9:00 ` Russell King - ARM Linux
@ 2013-10-19 15:05 ` Russell King - ARM Linux
-1 siblings, 0 replies; 24+ messages in thread
From: Russell King - ARM Linux @ 2013-10-19 15:05 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Pawel Moll, Stephen Warren,
Ian Campbell, Rob Herring, linux-arm-kernel
On Tue, Oct 08, 2013 at 10:00:15AM +0100, Russell King - ARM Linux wrote:
> On Tue, Oct 08, 2013 at 11:40:51AM +0800, Shawn Guo wrote:
> > On Mon, Oct 07, 2013 at 08:52:40PM -0600, Stephen Warren wrote:
> > > >>> &usdhc1 {
> > > >>> pinctrl-names = "default";
> > > >>> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> > > >>> ...
> > > >>> status = "okay";
> > > >>> };
> > > >>
> > > >> Are you sure that this will always be the case? This would assume that
> > > >> the pinctrl entries are always processed sequentially.
> > > >
> > > > That will always be the case per my understanding. Otherwise, I would
> > > > be so surprised. Are you seeing any case that the entries are not
> > > > processed sequentially?
> > >
> > > Given the way the Linux code currently works, I think that will
> > > currently happen in practice. However, there's nothing in the pinctrl DT
> > > binding documentation that guarantees (or even mentions) such semantics.
> >
> > Ah, that's Russell's point, I guess. I think it makes perfect sense to
> > make this clear in the binding doc, as this "overwrite mechanism" can be
> > very helpful. I will send a patch for it.
>
> Exactly - otherwise we're just relying on implementation details.
> There's nothing at present which mandates starting at the first entry
> and working through sequentially to the last entry, which means another
> implementation can choose to operate in the opposite order. If it does,
> what you're suggesting won't work so well.
>
> However, there's another point to consider. In cases like this, we will
> cause a glitch on the pin. When we process the initial set, we will set
> the pull-up high, and then later set it low. That may not be a problem
> in this case, but that's not to say it won't be in every case, and that's
> something which also needs to be considered.
I can't find what the result of this discussion was, but from what I
remember, we decided that we weren't going to do this override thing,
and instead we were going to separate out the configuration of DAT3.
Who's going to do that? I'd rather not, because it means editing
quite a number of DT files which I have no way to test, and the
chances of messing this up are quite high. I've already developed
a deep seated hatred for DT in general through my involvement with
IMX, particularly how it's very easy to make an undetected mistake
and then spend hours debugging it.
Until this is resolved, I'm sticking with my own method of redefining
the entire pinctrl set for DAT3 pull-down, which I've tested as working.
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-19 15:05 ` Russell King - ARM Linux
0 siblings, 0 replies; 24+ messages in thread
From: Russell King - ARM Linux @ 2013-10-19 15:05 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Oct 08, 2013 at 10:00:15AM +0100, Russell King - ARM Linux wrote:
> On Tue, Oct 08, 2013 at 11:40:51AM +0800, Shawn Guo wrote:
> > On Mon, Oct 07, 2013 at 08:52:40PM -0600, Stephen Warren wrote:
> > > >>> &usdhc1 {
> > > >>> pinctrl-names = "default";
> > > >>> pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd>;
> > > >>> ...
> > > >>> status = "okay";
> > > >>> };
> > > >>
> > > >> Are you sure that this will always be the case? This would assume that
> > > >> the pinctrl entries are always processed sequentially.
> > > >
> > > > That will always be the case per my understanding. Otherwise, I would
> > > > be so surprised. Are you seeing any case that the entries are not
> > > > processed sequentially?
> > >
> > > Given the way the Linux code currently works, I think that will
> > > currently happen in practice. However, there's nothing in the pinctrl DT
> > > binding documentation that guarantees (or even mentions) such semantics.
> >
> > Ah, that's Russell's point, I guess. I think it makes perfect sense to
> > make this clear in the binding doc, as this "overwrite mechanism" can be
> > very helpful. I will send a patch for it.
>
> Exactly - otherwise we're just relying on implementation details.
> There's nothing at present which mandates starting at the first entry
> and working through sequentially to the last entry, which means another
> implementation can choose to operate in the opposite order. If it does,
> what you're suggesting won't work so well.
>
> However, there's another point to consider. In cases like this, we will
> cause a glitch on the pin. When we process the initial set, we will set
> the pull-up high, and then later set it low. That may not be a problem
> in this case, but that's not to say it won't be in every case, and that's
> something which also needs to be considered.
I can't find what the result of this discussion was, but from what I
remember, we decided that we weren't going to do this override thing,
and instead we were going to separate out the configuration of DAT3.
Who's going to do that? I'd rather not, because it means editing
quite a number of DT files which I have no way to test, and the
chances of messing this up are quite high. I've already developed
a deep seated hatred for DT in general through my involvement with
IMX, particularly how it's very easy to make an undetected mistake
and then spend hours debugging it.
Until this is resolved, I'm sticking with my own method of redefining
the entire pinctrl set for DAT3 pull-down, which I've tested as working.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-19 15:05 ` Russell King - ARM Linux
@ 2013-10-21 0:46 ` Shawn Guo
-1 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-21 0:46 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll,
Ian Campbell, Stephen Warren, Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Sat, Oct 19, 2013 at 04:05:56PM +0100, Russell King - ARM Linux wrote:
> I can't find what the result of this discussion was, but from what I
> remember, we decided that we weren't going to do this override thing,
> and instead we were going to separate out the configuration of DAT3.
>
> Who's going to do that?
I'm going to do that. Thanks for reminding :)
Shawn
> I'd rather not, because it means editing
> quite a number of DT files which I have no way to test, and the
> chances of messing this up are quite high. I've already developed
> a deep seated hatred for DT in general through my involvement with
> IMX, particularly how it's very easy to make an undetected mistake
> and then spend hours debugging it.
>
> Until this is resolved, I'm sticking with my own method of redefining
> the entire pinctrl set for DAT3 pull-down, which I've tested as working.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-21 0:46 ` Shawn Guo
0 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-21 0:46 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Oct 19, 2013 at 04:05:56PM +0100, Russell King - ARM Linux wrote:
> I can't find what the result of this discussion was, but from what I
> remember, we decided that we weren't going to do this override thing,
> and instead we were going to separate out the configuration of DAT3.
>
> Who's going to do that?
I'm going to do that. Thanks for reminding :)
Shawn
> I'd rather not, because it means editing
> quite a number of DT files which I have no way to test, and the
> chances of messing this up are quite high. I've already developed
> a deep seated hatred for DT in general through my involvement with
> IMX, particularly how it's very easy to make an undetected mistake
> and then spend hours debugging it.
>
> Until this is resolved, I'm sticking with my own method of redefining
> the entire pinctrl set for DAT3 pull-down, which I've tested as working.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
2013-10-21 0:46 ` Shawn Guo
@ 2013-10-25 2:16 ` Shawn Guo
-1 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-25 2:16 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll,
Stephen Warren, Ian Campbell, Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matt Sealey
On Mon, Oct 21, 2013 at 08:46:12AM +0800, Shawn Guo wrote:
> On Sat, Oct 19, 2013 at 04:05:56PM +0100, Russell King - ARM Linux wrote:
> > I can't find what the result of this discussion was, but from what I
> > remember, we decided that we weren't going to do this override thing,
> > and instead we were going to separate out the configuration of DAT3.
> >
> > Who's going to do that?
>
> I'm going to do that. Thanks for reminding :)
Okay, here is what I got so far. However, looking at the changes on
imx6qdl.dtsi, I start being concerned by the point that Matt raises
recently - the device tree blob for particular board is bloated with a
lot of pinctrl setting nodes that the board does not use. The situation
will become even worse when we have more pinctrl nodes to be added just
for cases like this usdhc DAT3 thing. Thus, I'm considering to adopt
Matt's proposal to avoid this problem. Will post a RFC patch to
demonstrate the solution soon.
Shawn
--------8<----------------------
arch/arm/boot/dts/imx6q-arm2.dts | 3 +-
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 2 +-
arch/arm/boot/dts/imx6q-sabrelite.dts | 2 +-
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 6 +--
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl.dtsi | 74 +++++++++++++++++++++++++---
7 files changed, 79 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index edf1bd9..b804cf7 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -85,6 +85,7 @@
vmmc-supply = <®_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1
+ &pinctrl_usdhc3_dat3
&pinctrl_usdhc3_arm2>;
status = "okay";
};
@@ -93,7 +94,7 @@
non-removable;
vmmc-supply = <®_3p3v>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4_1>;
+ pinctrl-0 = <&pinctrl_usdhc4_1 &pinctrl_usdhc4_dat3>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index 1a3b50d..01df035 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -164,7 +164,7 @@
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_2>;
+ pinctrl-0 = <&pinctrl_usdhc2_2 &pinctrl_usdhc2_dat3>;
cd-gpios = <&gpio1 4 0>;
wp-gpios = <&gpio1 2 0>;
status = "disabled";
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index f004913..b1bffa8 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -192,7 +192,7 @@
&usdhc4 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4_2>;
+ pinctrl-0 = <&pinctrl_usdhc4_2 &pinctrl_usdhc4_dat3>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <®_3p3v>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index ff6f1e8..5421c8e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -76,9 +76,9 @@
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3_1>;
- pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
+ pinctrl-0 = <&pinctrl_usdhc3_1 &pinctrl_usdhc3_dat3>;
+ pinctrl-1 = <&pinctrl_usdhc3_1_100mhz &pinctrl_usdhc3_dat3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_1_200mhz &pinctrl_usdhc3_dat3_200mhz>;
cd-gpios = <&gpio6 15 0>;
wp-gpios = <&gpio1 13 0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index e75e11b..c4b7fda 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -244,7 +244,7 @@
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_1>;
+ pinctrl-0 = <&pinctrl_usdhc2_1 &pinctrl_usdhc2_dat3>;
bus-width = <8>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
@@ -253,7 +253,7 @@
&usdhc3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_1>;
+ pinctrl-0 = <&pinctrl_usdhc3_1 &pinctrl_usdhc3_dat3>;
bus-width = <8>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 35f5479..b1b84ec 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -140,14 +140,14 @@
&usdhc1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1_2>;
+ pinctrl-0 = <&pinctrl_usdhc1_2 &pinctrl_usdhc1_dat3>;
cd-gpios = <&gpio1 2 0>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_2>;
+ pinctrl-0 = <&pinctrl_usdhc2_2 &pinctrl_usdhc2_dat3>;
non-removable;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 59154dc..b918d5f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1157,7 +1157,6 @@
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
@@ -1172,9 +1171,20 @@
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_dat3: usdhc1dat3 {
+ fsl,pins = <
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc1_dat3cd: usdhc1dat3cd {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
+ >;
+ };
};
usdhc2 {
@@ -1185,7 +1195,6 @@
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
@@ -1200,9 +1209,20 @@
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_dat3: usdhc2dat3 {
+ fsl,pins = <
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc2_dat3cd: usdhc2dat3cd {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+ >;
+ };
};
usdhc3 {
@@ -1213,7 +1233,6 @@
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
@@ -1228,7 +1247,6 @@
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
@@ -1243,7 +1261,6 @@
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
@@ -1258,9 +1275,44 @@
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_dat3: usdhc3dat3 {
+ fsl,pins = <
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc3_dat3_100mhz: usdhc3dat3-100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_dat3_200mhz: usdhc3dat3-200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_dat3cd: usdhc3dat3cd {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
+ >;
+ };
+
+ pinctrl_usdhc3_dat3cd_100mhz: usdhc3dat3cd-100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x130b9
+ >;
+ };
+
+ pinctrl_usdhc3_dat3cd_200mhz: usdhc3dat3cd-200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x130f9
+ >;
+ };
};
usdhc4 {
@@ -1271,7 +1323,6 @@
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
@@ -1286,9 +1337,20 @@
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ >;
+ };
+
+ pinctrl_usdhc4_dat3: usdhc4dat3 {
+ fsl,pins = <
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc4_dat3cd: usdhc4dat3cd {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
+ >;
+ };
};
weim {
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down
@ 2013-10-25 2:16 ` Shawn Guo
0 siblings, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2013-10-25 2:16 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Oct 21, 2013 at 08:46:12AM +0800, Shawn Guo wrote:
> On Sat, Oct 19, 2013 at 04:05:56PM +0100, Russell King - ARM Linux wrote:
> > I can't find what the result of this discussion was, but from what I
> > remember, we decided that we weren't going to do this override thing,
> > and instead we were going to separate out the configuration of DAT3.
> >
> > Who's going to do that?
>
> I'm going to do that. Thanks for reminding :)
Okay, here is what I got so far. However, looking at the changes on
imx6qdl.dtsi, I start being concerned by the point that Matt raises
recently - the device tree blob for particular board is bloated with a
lot of pinctrl setting nodes that the board does not use. The situation
will become even worse when we have more pinctrl nodes to be added just
for cases like this usdhc DAT3 thing. Thus, I'm considering to adopt
Matt's proposal to avoid this problem. Will post a RFC patch to
demonstrate the solution soon.
Shawn
--------8<----------------------
arch/arm/boot/dts/imx6q-arm2.dts | 3 +-
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 2 +-
arch/arm/boot/dts/imx6q-sabrelite.dts | 2 +-
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 6 +--
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 4 +-
arch/arm/boot/dts/imx6qdl.dtsi | 74 +++++++++++++++++++++++++---
7 files changed, 79 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index edf1bd9..b804cf7 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -85,6 +85,7 @@
vmmc-supply = <®_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1
+ &pinctrl_usdhc3_dat3
&pinctrl_usdhc3_arm2>;
status = "okay";
};
@@ -93,7 +94,7 @@
non-removable;
vmmc-supply = <®_3p3v>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4_1>;
+ pinctrl-0 = <&pinctrl_usdhc4_1 &pinctrl_usdhc4_dat3>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index 1a3b50d..01df035 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -164,7 +164,7 @@
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_2>;
+ pinctrl-0 = <&pinctrl_usdhc2_2 &pinctrl_usdhc2_dat3>;
cd-gpios = <&gpio1 4 0>;
wp-gpios = <&gpio1 2 0>;
status = "disabled";
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index f004913..b1bffa8 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -192,7 +192,7 @@
&usdhc4 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4_2>;
+ pinctrl-0 = <&pinctrl_usdhc4_2 &pinctrl_usdhc4_dat3>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <®_3p3v>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index ff6f1e8..5421c8e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -76,9 +76,9 @@
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3_1>;
- pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
+ pinctrl-0 = <&pinctrl_usdhc3_1 &pinctrl_usdhc3_dat3>;
+ pinctrl-1 = <&pinctrl_usdhc3_1_100mhz &pinctrl_usdhc3_dat3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_1_200mhz &pinctrl_usdhc3_dat3_200mhz>;
cd-gpios = <&gpio6 15 0>;
wp-gpios = <&gpio1 13 0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index e75e11b..c4b7fda 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -244,7 +244,7 @@
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_1>;
+ pinctrl-0 = <&pinctrl_usdhc2_1 &pinctrl_usdhc2_dat3>;
bus-width = <8>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
@@ -253,7 +253,7 @@
&usdhc3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_1>;
+ pinctrl-0 = <&pinctrl_usdhc3_1 &pinctrl_usdhc3_dat3>;
bus-width = <8>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 35f5479..b1b84ec 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -140,14 +140,14 @@
&usdhc1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1_2>;
+ pinctrl-0 = <&pinctrl_usdhc1_2 &pinctrl_usdhc1_dat3>;
cd-gpios = <&gpio1 2 0>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_2>;
+ pinctrl-0 = <&pinctrl_usdhc2_2 &pinctrl_usdhc2_dat3>;
non-removable;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 59154dc..b918d5f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1157,7 +1157,6 @@
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
@@ -1172,9 +1171,20 @@
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_dat3: usdhc1dat3 {
+ fsl,pins = <
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc1_dat3cd: usdhc1dat3cd {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059
+ >;
+ };
};
usdhc2 {
@@ -1185,7 +1195,6 @@
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
@@ -1200,9 +1209,20 @@
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_dat3: usdhc2dat3 {
+ fsl,pins = <
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc2_dat3cd: usdhc2dat3cd {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+ >;
+ };
};
usdhc3 {
@@ -1213,7 +1233,6 @@
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
@@ -1228,7 +1247,6 @@
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
@@ -1243,7 +1261,6 @@
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
@@ -1258,9 +1275,44 @@
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_dat3: usdhc3dat3 {
+ fsl,pins = <
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc3_dat3_100mhz: usdhc3dat3-100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_dat3_200mhz: usdhc3dat3-200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_dat3cd: usdhc3dat3cd {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x13059
+ >;
+ };
+
+ pinctrl_usdhc3_dat3cd_100mhz: usdhc3dat3cd-100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x130b9
+ >;
+ };
+
+ pinctrl_usdhc3_dat3cd_200mhz: usdhc3dat3cd-200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x130f9
+ >;
+ };
};
usdhc4 {
@@ -1271,7 +1323,6 @@
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
@@ -1286,9 +1337,20 @@
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ >;
+ };
+
+ pinctrl_usdhc4_dat3: usdhc4dat3 {
+ fsl,pins = <
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc4_dat3cd: usdhc4dat3cd {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x13059
+ >;
+ };
};
weim {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread
end of thread, other threads:[~2013-10-25 2:16 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-10-05 11:21 [PATCH RFC 0/2] Initial Solid Run Cubox-i carrier-1 support Russell King - ARM Linux
2013-10-05 11:21 ` Russell King - ARM Linux
[not found] ` <20131005112147.GX12758-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2013-10-05 11:22 ` [PATCH RFC 1/2] ARM: imx6qdl: provide pinctrl configurations for DAT3 pull-down Russell King
2013-10-05 11:22 ` Russell King
[not found] ` <E1VSPw9-0004Ug-BF-eh5Bv4kxaXIANfyc6IWni62ZND6+EDdj@public.gmane.org>
2013-10-07 5:53 ` Shawn Guo
2013-10-07 5:53 ` Shawn Guo
[not found] ` <20131007055340.GB3739-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
2013-10-07 18:03 ` Russell King - ARM Linux
2013-10-07 18:03 ` Russell King - ARM Linux
[not found] ` <20131007180357.GS12758-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2013-10-08 1:54 ` Shawn Guo
2013-10-08 1:54 ` Shawn Guo
[not found] ` <20131008015426.GA7480-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
2013-10-08 2:52 ` Stephen Warren
2013-10-08 2:52 ` Stephen Warren
[not found] ` <52537378.1020904-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-10-08 3:40 ` Shawn Guo
2013-10-08 3:40 ` Shawn Guo
[not found] ` <20131008034048.GB7480-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
2013-10-08 9:00 ` Russell King - ARM Linux
2013-10-08 9:00 ` Russell King - ARM Linux
2013-10-19 15:05 ` Russell King - ARM Linux
2013-10-19 15:05 ` Russell King - ARM Linux
[not found] ` <20131019150556.GI25034-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2013-10-21 0:46 ` Shawn Guo
2013-10-21 0:46 ` Shawn Guo
[not found] ` <20131021004610.GB17165-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
2013-10-25 2:16 ` Shawn Guo
2013-10-25 2:16 ` Shawn Guo
2013-10-05 11:23 ` [PATCH RFC 2/2] ARM: imx: initial IMX6 Cubox-i carrier-1 support Russell King
2013-10-05 11:23 ` Russell King
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