[PATCH 1/4] tests: Add a test for the command parser

[PATCH 1/4] tests: Add a test for the command parser

[bradley.d.volkin]

From: Brad Volkin <bradley.d.volkin@intel.com>

Start with a simple testcase that should pass.

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
 tests/.gitignore       |   1 +
 tests/Makefile.sources |   1 +
 tests/gem_exec_parse.c | 140 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 142 insertions(+)
 create mode 100644 tests/gem_exec_parse.c

diff --git a/tests/.gitignore b/tests/.gitignore
index e835a5a..ec7f526 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -35,6 +35,7 @@ gem_exec_blt
 gem_exec_faulting_reloc
 gem_exec_lut_handle
 gem_exec_nop
+gem_exec_parse
 gem_fenced_exec_thrash
 gem_fence_thrash
 gem_flink
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index a02b93d..c90e5aa 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -25,6 +25,7 @@ TESTS_progs_M = \
 	gem_evict_everything \
 	gem_exec_bad_domains \
 	gem_exec_nop \
+	gem_exec_parse \
 	gem_fenced_exec_thrash \
 	gem_fence_thrash \
 	gem_flink \
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
new file mode 100644
index 0000000..a17929f
--- /dev/null
+++ b/tests/gem_exec_parse.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "drm.h"
+#include "i915_drm.h"
+#include "drmtest.h"
+
+#ifndef I915_PARAM_HAS_CMD_PARSER
+#define I915_PARAM_HAS_CMD_PARSER	 28
+#endif
+
+static int exec_batch_patched(int fd, uint32_t cmd_bo, uint32_t *cmds,
+			      int size, int patch_offset, uint64_t expected_value)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct drm_i915_gem_exec_object2 objs[2];
+	struct drm_i915_gem_relocation_entry reloc[1];
+
+	uint32_t target_bo = gem_create(fd, 4096);
+	uint64_t actual_value = 0;
+
+	gem_write(fd, cmd_bo, 0, cmds, size);
+
+	reloc[0].offset = patch_offset;
+	reloc[0].delta = 0;
+	reloc[0].target_handle = target_bo;
+	reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+	reloc[0].presumed_offset = 0;
+
+	objs[0].handle = target_bo;
+	objs[0].relocation_count = 0;
+	objs[0].relocs_ptr = 0;
+	objs[0].alignment = 0;
+	objs[0].offset = 0;
+	objs[0].flags = 0;
+	objs[0].rsvd1 = 0;
+	objs[0].rsvd2 = 0;
+
+	objs[1].handle = cmd_bo;
+	objs[1].relocation_count = 1;
+	objs[1].relocs_ptr = (uintptr_t)reloc;
+	objs[1].alignment = 0;
+	objs[1].offset = 0;
+	objs[1].flags = 0;
+	objs[1].rsvd1 = 0;
+	objs[1].rsvd2 = 0;
+
+	execbuf.buffers_ptr = (uintptr_t)objs;
+	execbuf.buffer_count = 2;
+	execbuf.batch_start_offset = 0;
+	execbuf.batch_len = size;
+	execbuf.cliprects_ptr = 0;
+	execbuf.num_cliprects = 0;
+	execbuf.DR1 = 0;
+	execbuf.DR4 = 0;
+	execbuf.flags = I915_EXEC_RENDER;
+	i915_execbuffer2_set_context_id(execbuf, 0);
+	execbuf.rsvd2 = 0;
+
+	gem_execbuf(fd, &execbuf);
+	gem_sync(fd, cmd_bo);
+
+	gem_read(fd,target_bo, 0, &actual_value, sizeof(actual_value));
+	igt_assert(expected_value == actual_value);
+
+	gem_close(fd, target_bo);
+
+	return 1;
+}
+
+uint32_t handle;
+int fd;
+
+#define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
+#define   PIPE_CONTROL_QW_WRITE	(1<<14)
+
+igt_main
+{
+	igt_fixture {
+		int has_secparser = 0;
+                drm_i915_getparam_t gp;
+		int rc;
+
+		fd = drm_open_any();
+
+		gp.param = I915_PARAM_HAS_CMD_PARSER;
+		gp.value = &has_secparser;
+		rc = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+		igt_require(!rc && has_secparser);
+
+		handle = gem_create(fd, 4096);
+	}
+
+	igt_subtest("basic-allowed") {
+		uint32_t pc[] = {
+			GFX_OP_PIPE_CONTROL,
+			PIPE_CONTROL_QW_WRITE,
+			0, // To be patched
+			0x12000000,
+			0,
+			MI_BATCH_BUFFER_END,
+		};
+		igt_assert(
+			exec_batch_patched(fd, handle,
+					   pc, sizeof(pc),
+					   8, // patch offset,
+					   0x12000000));
+	}
+
+	igt_fixture {
+		gem_close(fd, handle);
+
+		close(fd);
+	}
+}
-- 
1.8.4.4

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[PATCH 2/4] tests/gem_exec_parse: Add tests for rejected commands

[bradley.d.volkin]

From: Brad Volkin <bradley.d.volkin@intel.com>

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
 tests/gem_exec_parse.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index a17929f..b34fe1b 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -93,9 +93,55 @@ static int exec_batch_patched(int fd, uint32_t cmd_bo, uint32_t *cmds,
 	return 1;
 }
 
+static int exec_batch(int fd, uint32_t cmd_bo, uint32_t *cmds,
+		      int size, int ring, int expected_ret)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct drm_i915_gem_exec_object2 objs[1];
+	int ret;
+
+	gem_write(fd, cmd_bo, 0, cmds, size);
+
+	objs[0].handle = cmd_bo;
+	objs[0].relocation_count = 0;
+	objs[0].relocs_ptr = 0;
+	objs[0].alignment = 0;
+	objs[0].offset = 0;
+	objs[0].flags = 0;
+	objs[0].rsvd1 = 0;
+	objs[0].rsvd2 = 0;
+
+	execbuf.buffers_ptr = (uintptr_t)objs;
+	execbuf.buffer_count = 1;
+	execbuf.batch_start_offset = 0;
+	execbuf.batch_len = size;
+	execbuf.cliprects_ptr = 0;
+	execbuf.num_cliprects = 0;
+	execbuf.DR1 = 0;
+	execbuf.DR4 = 0;
+	execbuf.flags = ring;
+	i915_execbuffer2_set_context_id(execbuf, 0);
+	execbuf.rsvd2 = 0;
+
+	ret = drmIoctl(fd,
+		       DRM_IOCTL_I915_GEM_EXECBUFFER2,
+		       &execbuf);
+	if (ret == 0)
+		igt_assert(expected_ret == 0);
+	else
+		igt_assert(-errno == expected_ret);
+
+	gem_sync(fd, cmd_bo);
+
+	return 1;
+}
+
 uint32_t handle;
 int fd;
 
+#define MI_ARB_ON_OFF (0x8 << 23)
+#define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
+
 #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
 #define   PIPE_CONTROL_QW_WRITE	(1<<14)
 
@@ -132,6 +178,41 @@ igt_main
 					   0x12000000));
 	}
 
+	igt_subtest("basic-rejected") {
+		uint32_t arb_on_off[] = {
+			MI_ARB_ON_OFF,
+			MI_BATCH_BUFFER_END,
+		};
+		uint32_t display_flip[] = {
+			MI_DISPLAY_FLIP,
+			0, 0, 0,
+			MI_BATCH_BUFFER_END,
+			0
+		};
+		igt_assert(
+			   exec_batch(fd, handle,
+				      arb_on_off, sizeof(arb_on_off),
+				      I915_EXEC_RENDER,
+				      -EINVAL));
+		igt_assert(
+			   exec_batch(fd, handle,
+				      arb_on_off, sizeof(arb_on_off),
+				      I915_EXEC_BSD,
+				      -EINVAL));
+		if (gem_has_vebox(fd)) {
+			igt_assert(
+				   exec_batch(fd, handle,
+					      arb_on_off, sizeof(arb_on_off),
+					      I915_EXEC_VEBOX,
+					      -EINVAL));
+		}
+		igt_assert(
+			   exec_batch(fd, handle,
+				      display_flip, sizeof(display_flip),
+				      I915_EXEC_BLT,
+				      -EINVAL));
+	}
+
 	igt_fixture {
 		gem_close(fd, handle);
 
-- 
1.8.4.4

[PATCH 3/4] tests/gem_exec_parse: Add tests for register whitelist

[bradley.d.volkin]

From: Brad Volkin <bradley.d.volkin@intel.com>

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
 tests/gem_exec_parse.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index b34fe1b..d4136db 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -141,6 +141,7 @@ int fd;
 
 #define MI_ARB_ON_OFF (0x8 << 23)
 #define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
+#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
 
 #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
 #define   PIPE_CONTROL_QW_WRITE	(1<<14)
@@ -213,6 +214,31 @@ igt_main
 				      -EINVAL));
 	}
 
+	igt_subtest("registers") {
+		uint32_t lri_bad[] = {
+			MI_LOAD_REGISTER_IMM,
+			0, // disallowed register address
+			0x12000000,
+			MI_BATCH_BUFFER_END,
+		};
+		uint32_t lri_ok[] = {
+			MI_LOAD_REGISTER_IMM,
+			0x5280, // allowed register address (SO_WRITE_OFFSET[0])
+			0x1,
+			MI_BATCH_BUFFER_END,
+		};
+		igt_assert(
+			   exec_batch(fd, handle,
+				      lri_bad, sizeof(lri_bad),
+				      I915_EXEC_RENDER,
+				      -EINVAL));
+		igt_assert(
+			   exec_batch(fd, handle,
+				      lri_ok, sizeof(lri_ok),
+				      I915_EXEC_RENDER,
+				      0));
+	}
+
 	igt_fixture {
 		gem_close(fd, handle);
 
-- 
1.8.4.4

[PATCH 4/4] tests/gem_exec_parse: Add tests for bitmask checks

[bradley.d.volkin]

From: Brad Volkin <bradley.d.volkin@intel.com>

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
 tests/gem_exec_parse.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index d4136db..0eb328c 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -145,6 +145,7 @@ int fd;
 
 #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
 #define   PIPE_CONTROL_QW_WRITE	(1<<14)
+#define   PIPE_CONTROL_LRI_POST_OP (1<<23)
 
 igt_main
 {
@@ -239,6 +240,23 @@ igt_main
 				      0));
 	}
 
+	igt_subtest("bitmasks") {
+		uint32_t pc[] = {
+			GFX_OP_PIPE_CONTROL,
+			(PIPE_CONTROL_QW_WRITE |
+			 PIPE_CONTROL_LRI_POST_OP),
+			0, // To be patched
+			0x12000000,
+			0,
+			MI_BATCH_BUFFER_END,
+		};
+		igt_assert(
+			   exec_batch(fd, handle,
+				      pc, sizeof(pc),
+				      I915_EXEC_RENDER,
+				      -EINVAL));
+	}
+
 	igt_fixture {
 		gem_close(fd, handle);
 
-- 
1.8.4.4

Re: [PATCH 1/4] tests: Add a test for the command parser

[Daniel Vetter]

On Tue, Nov 26, 2013 at 08:53:52AM -0800, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
> 
> Start with a simple testcase that should pass.
> 
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>

Tests look nice, on top of the additional testcases I've mentioned in my
reply to the overview mail maybe split the per-ring tests up into
subtests. But that's a bikeshed, I'm ok either way.
-Daniel

> ---
>  tests/.gitignore       |   1 +
>  tests/Makefile.sources |   1 +
>  tests/gem_exec_parse.c | 140 +++++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 142 insertions(+)
>  create mode 100644 tests/gem_exec_parse.c
> 
> diff --git a/tests/.gitignore b/tests/.gitignore
> index e835a5a..ec7f526 100644
> --- a/tests/.gitignore
> +++ b/tests/.gitignore
> @@ -35,6 +35,7 @@ gem_exec_blt
>  gem_exec_faulting_reloc
>  gem_exec_lut_handle
>  gem_exec_nop
> +gem_exec_parse
>  gem_fenced_exec_thrash
>  gem_fence_thrash
>  gem_flink
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index a02b93d..c90e5aa 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -25,6 +25,7 @@ TESTS_progs_M = \
>  	gem_evict_everything \
>  	gem_exec_bad_domains \
>  	gem_exec_nop \
> +	gem_exec_parse \
>  	gem_fenced_exec_thrash \
>  	gem_fence_thrash \
>  	gem_flink \
> diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
> new file mode 100644
> index 0000000..a17929f
> --- /dev/null
> +++ b/tests/gem_exec_parse.c
> @@ -0,0 +1,140 @@
> +/*
> + * Copyright © 2013 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include <stdlib.h>
> +#include <stdint.h>
> +#include <stdio.h>
> +#include "drm.h"
> +#include "i915_drm.h"
> +#include "drmtest.h"
> +
> +#ifndef I915_PARAM_HAS_CMD_PARSER
> +#define I915_PARAM_HAS_CMD_PARSER	 28
> +#endif
> +
> +static int exec_batch_patched(int fd, uint32_t cmd_bo, uint32_t *cmds,
> +			      int size, int patch_offset, uint64_t expected_value)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	struct drm_i915_gem_exec_object2 objs[2];
> +	struct drm_i915_gem_relocation_entry reloc[1];
> +
> +	uint32_t target_bo = gem_create(fd, 4096);
> +	uint64_t actual_value = 0;
> +
> +	gem_write(fd, cmd_bo, 0, cmds, size);
> +
> +	reloc[0].offset = patch_offset;
> +	reloc[0].delta = 0;
> +	reloc[0].target_handle = target_bo;
> +	reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
> +	reloc[0].presumed_offset = 0;
> +
> +	objs[0].handle = target_bo;
> +	objs[0].relocation_count = 0;
> +	objs[0].relocs_ptr = 0;
> +	objs[0].alignment = 0;
> +	objs[0].offset = 0;
> +	objs[0].flags = 0;
> +	objs[0].rsvd1 = 0;
> +	objs[0].rsvd2 = 0;
> +
> +	objs[1].handle = cmd_bo;
> +	objs[1].relocation_count = 1;
> +	objs[1].relocs_ptr = (uintptr_t)reloc;
> +	objs[1].alignment = 0;
> +	objs[1].offset = 0;
> +	objs[1].flags = 0;
> +	objs[1].rsvd1 = 0;
> +	objs[1].rsvd2 = 0;
> +
> +	execbuf.buffers_ptr = (uintptr_t)objs;
> +	execbuf.buffer_count = 2;
> +	execbuf.batch_start_offset = 0;
> +	execbuf.batch_len = size;
> +	execbuf.cliprects_ptr = 0;
> +	execbuf.num_cliprects = 0;
> +	execbuf.DR1 = 0;
> +	execbuf.DR4 = 0;
> +	execbuf.flags = I915_EXEC_RENDER;
> +	i915_execbuffer2_set_context_id(execbuf, 0);
> +	execbuf.rsvd2 = 0;
> +
> +	gem_execbuf(fd, &execbuf);
> +	gem_sync(fd, cmd_bo);
> +
> +	gem_read(fd,target_bo, 0, &actual_value, sizeof(actual_value));
> +	igt_assert(expected_value == actual_value);
> +
> +	gem_close(fd, target_bo);
> +
> +	return 1;
> +}
> +
> +uint32_t handle;
> +int fd;
> +
> +#define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
> +#define   PIPE_CONTROL_QW_WRITE	(1<<14)
> +
> +igt_main
> +{
> +	igt_fixture {
> +		int has_secparser = 0;
> +                drm_i915_getparam_t gp;
> +		int rc;
> +
> +		fd = drm_open_any();
> +
> +		gp.param = I915_PARAM_HAS_CMD_PARSER;
> +		gp.value = &has_secparser;
> +		rc = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> +		igt_require(!rc && has_secparser);
> +
> +		handle = gem_create(fd, 4096);
> +	}
> +
> +	igt_subtest("basic-allowed") {
> +		uint32_t pc[] = {
> +			GFX_OP_PIPE_CONTROL,
> +			PIPE_CONTROL_QW_WRITE,
> +			0, // To be patched
> +			0x12000000,
> +			0,
> +			MI_BATCH_BUFFER_END,
> +		};
> +		igt_assert(
> +			exec_batch_patched(fd, handle,
> +					   pc, sizeof(pc),
> +					   8, // patch offset,
> +					   0x12000000));
> +	}
> +
> +	igt_fixture {
> +		gem_close(fd, handle);
> +
> +		close(fd);
> +	}
> +}
> -- 
> 1.8.4.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch