* [PATCH 01/13] drm/i915: Refactor shmem pread setup
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-01-30 8:36 ` Daniel Vetter
2014-01-29 21:55 ` [PATCH 02/13] drm/i915: Implement command buffer parsing logic bradley.d.volkin
` (13 subsequent siblings)
14 siblings, 1 reply; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
The command parser is going to need the same synchronization and
setup logic, so factor it out for reuse.
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_gem.c | 48 +++++++++++++++++++++++++++++------------
2 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3673ba1..bfb30df 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2045,6 +2045,9 @@ void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
void i915_gem_lastclose(struct drm_device *dev);
+int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
+ int *needs_clflush);
+
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
{
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 39770f7..fdc1f40 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -332,6 +332,39 @@ __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
return 0;
}
+/*
+ * Pins the specified object's pages and synchronizes the object with
+ * GPU accesses. Sets needs_clflush to non-zero if the caller should
+ * flush the object from the CPU cache.
+ */
+int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
+ int *needs_clflush)
+{
+ int ret;
+
+ *needs_clflush = 0;
+
+ if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
+ /* If we're not in the cpu read domain, set ourself into the gtt
+ * read domain and manually flush cachelines (if required). This
+ * optimizes for the case when the gpu will dirty the data
+ * anyway again before the next pread happens. */
+ *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
+ obj->cache_level);
+ ret = i915_gem_object_wait_rendering(obj, true);
+ if (ret)
+ return ret;
+ }
+
+ ret = i915_gem_object_get_pages(obj);
+ if (ret)
+ return ret;
+
+ i915_gem_object_pin_pages(obj);
+
+ return ret;
+}
+
/* Per-page copy function for the shmem pread fastpath.
* Flushes invalid cachelines before reading the target if
* needs_clflush is set. */
@@ -429,23 +462,10 @@ i915_gem_shmem_pread(struct drm_device *dev,
obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
- if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
- /* If we're not in the cpu read domain, set ourself into the gtt
- * read domain and manually flush cachelines (if required). This
- * optimizes for the case when the gpu will dirty the data
- * anyway again before the next pread happens. */
- needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
- ret = i915_gem_object_wait_rendering(obj, true);
- if (ret)
- return ret;
- }
-
- ret = i915_gem_object_get_pages(obj);
+ ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
if (ret)
return ret;
- i915_gem_object_pin_pages(obj);
-
offset = args->offset;
for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 01/13] drm/i915: Refactor shmem pread setup
2014-01-29 21:55 ` [PATCH 01/13] drm/i915: Refactor shmem pread setup bradley.d.volkin
@ 2014-01-30 8:36 ` Daniel Vetter
0 siblings, 0 replies; 138+ messages in thread
From: Daniel Vetter @ 2014-01-30 8:36 UTC (permalink / raw)
To: bradley.d.volkin; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 01:55:02PM -0800, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> The command parser is going to need the same synchronization and
> setup logic, so factor it out for reuse.
>
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/i915_gem.c | 48 +++++++++++++++++++++++++++++------------
> 2 files changed, 37 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3673ba1..bfb30df 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2045,6 +2045,9 @@ void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
> void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
> void i915_gem_lastclose(struct drm_device *dev);
>
> +int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
> + int *needs_clflush);
> +
> int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
> static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
> {
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 39770f7..fdc1f40 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -332,6 +332,39 @@ __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
> return 0;
> }
>
> +/*
> + * Pins the specified object's pages and synchronizes the object with
> + * GPU accesses. Sets needs_clflush to non-zero if the caller should
> + * flush the object from the CPU cache.
> + */
> +int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
> + int *needs_clflush)
> +{
> + int ret;
I think for safety reasons (userspace can blow up the kernel otherwise
with the execbuf cmd parser) we need to replicate the "is this really
shmem backed" check from i915_gem_pread_ioctl to this place here.
-Daniel
> +
> + *needs_clflush = 0;
> +
> + if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
> + /* If we're not in the cpu read domain, set ourself into the gtt
> + * read domain and manually flush cachelines (if required). This
> + * optimizes for the case when the gpu will dirty the data
> + * anyway again before the next pread happens. */
> + *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
> + obj->cache_level);
> + ret = i915_gem_object_wait_rendering(obj, true);
> + if (ret)
> + return ret;
> + }
> +
> + ret = i915_gem_object_get_pages(obj);
> + if (ret)
> + return ret;
> +
> + i915_gem_object_pin_pages(obj);
> +
> + return ret;
> +}
> +
> /* Per-page copy function for the shmem pread fastpath.
> * Flushes invalid cachelines before reading the target if
> * needs_clflush is set. */
> @@ -429,23 +462,10 @@ i915_gem_shmem_pread(struct drm_device *dev,
>
> obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
>
> - if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
> - /* If we're not in the cpu read domain, set ourself into the gtt
> - * read domain and manually flush cachelines (if required). This
> - * optimizes for the case when the gpu will dirty the data
> - * anyway again before the next pread happens. */
> - needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
> - ret = i915_gem_object_wait_rendering(obj, true);
> - if (ret)
> - return ret;
> - }
> -
> - ret = i915_gem_object_get_pages(obj);
> + ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
> if (ret)
> return ret;
>
> - i915_gem_object_pin_pages(obj);
> -
> offset = args->offset;
>
> for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
2014-01-29 21:55 ` [PATCH 01/13] drm/i915: Refactor shmem pread setup bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-01-29 22:28 ` Chris Wilson
` (3 more replies)
2014-01-29 21:55 ` [PATCH 03/13] drm/i915: Initial command parser table definitions bradley.d.volkin
` (12 subsequent siblings)
14 siblings, 4 replies; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
The command parser scans batch buffers submitted via execbuffer ioctls before
the driver submits them to hardware. At a high level, it looks for several
things:
1) Commands which are explicitly defined as privileged or which should only be
used by the kernel driver. The parser generally rejects such commands, with
the provision that it may allow some from the drm master process.
2) Commands which access registers. To support correct/enhanced userspace
functionality, particularly certain OpenGL extensions, the parser provides a
whitelist of registers which userspace may safely access (for both normal and
drm master processes).
3) Commands which access privileged memory (i.e. GGTT, HWS page, etc). The
parser always rejects such commands.
Each ring maintains tables of commands and registers which the parser uses in
scanning batch buffers submitted to that ring.
The set of commands that the parser must check for is significantly smaller
than the number of commands supported, especially on the render ring. As such,
the parser tables (built up in subsequent patches) contain only those commands
required by the parser. This generally works because command opcode ranges have
standard command length encodings. So for commands that the parser does not need
to check, it can easily skip them. This is implementated via a per-ring length
decoding vfunc.
Unfortunately, there are a number of commands that do not follow the standard
length encoding for their opcode range, primarily amongst the MI_* commands. To
handle this, the parser provides a way to define explicit "skip" entries in the
per-ring command tables.
Other command table entries will map fairly directly to high level categories
mentioned above: rejected, master-only, register whitelist. A number of checks,
including the privileged memory checks, are implemented via a general bitmasking
mechanism.
OTC-Tracker: AXIA-4631
Change-Id: I50b98c71c6655893291c78a2d1b8954577b37a30
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_cmd_parser.c | 404 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 94 +++++++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 17 ++
drivers/gpu/drm/i915/i915_params.c | 5 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 32 +++
7 files changed, 556 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_cmd_parser.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4850494..2da81bf 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -47,7 +47,8 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
dvo_tfp410.o \
dvo_sil164.o \
dvo_ns2501.o \
- i915_gem_dmabuf.o
+ i915_gem_dmabuf.o \
+ i915_cmd_parser.o
i915-$(CONFIG_COMPAT) += i915_ioc32.o
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
new file mode 100644
index 0000000..7639dbc
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -0,0 +1,404 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Brad Volkin <bradley.d.volkin@intel.com>
+ *
+ */
+
+#include "i915_drv.h"
+
+#define CLIENT_MASK 0xE0000000
+#define SUBCLIENT_MASK 0x18000000
+#define MI_CLIENT 0x00000000
+#define RC_CLIENT 0x60000000
+#define BC_CLIENT 0x40000000
+#define MEDIA_SUBCLIENT 0x10000000
+
+static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
+{
+ u32 client = cmd_header & CLIENT_MASK;
+ u32 subclient = cmd_header & SUBCLIENT_MASK;
+
+ if (client == MI_CLIENT)
+ return 0x3F;
+ else if (client == RC_CLIENT) {
+ if (subclient == MEDIA_SUBCLIENT)
+ return 0xFFFF;
+ else
+ return 0xFF;
+ }
+
+ DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
+ return 0;
+}
+
+static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
+{
+ u32 client = cmd_header & CLIENT_MASK;
+ u32 subclient = cmd_header & SUBCLIENT_MASK;
+
+ if (client == MI_CLIENT)
+ return 0x3F;
+ else if (client == RC_CLIENT) {
+ if (subclient == MEDIA_SUBCLIENT)
+ return 0xFFF;
+ else
+ return 0xFF;
+ }
+
+ DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
+ return 0;
+}
+
+static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
+{
+ u32 client = cmd_header & CLIENT_MASK;
+
+ if (client == MI_CLIENT)
+ return 0x3F;
+ else if (client == BC_CLIENT)
+ return 0xFF;
+
+ DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
+ return 0;
+}
+
+static void validate_cmds_sorted(struct intel_ring_buffer *ring)
+{
+ int i;
+
+ if (!ring->cmd_tables || ring->cmd_table_count == 0)
+ return;
+
+ for (i = 0; i < ring->cmd_table_count; i++) {
+ const struct drm_i915_cmd_table *table = &ring->cmd_tables[i];
+ u32 previous = 0;
+ int j;
+
+ for (j = 0; j < table->count; j++) {
+ const struct drm_i915_cmd_descriptor *desc =
+ &table->table[i];
+ u32 curr = desc->cmd.value & desc->cmd.mask;
+
+ if (curr < previous) {
+ DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X\n",
+ ring->id, i, j, curr);
+ return;
+ }
+
+ previous = curr;
+ }
+ }
+}
+
+static void check_sorted(int ring_id, const u32 *reg_table, int reg_count)
+{
+ int i;
+ u32 previous = 0;
+
+ for (i = 0; i < reg_count; i++) {
+ u32 curr = reg_table[i];
+
+ if (curr < previous) {
+ DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X\n",
+ ring_id, i, curr);
+ return;
+ }
+
+ previous = curr;
+ }
+}
+
+static void validate_regs_sorted(struct intel_ring_buffer *ring)
+{
+ if (ring->reg_table && ring->reg_count > 0)
+ check_sorted(ring->id, ring->reg_table, ring->reg_count);
+
+ if (ring->master_reg_table && ring->master_reg_count > 0)
+ check_sorted(ring->id, ring->master_reg_table,
+ ring->master_reg_count);
+}
+
+void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
+{
+ if (!IS_GEN7(ring->dev))
+ return;
+
+ switch (ring->id) {
+ case RCS:
+ ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
+ break;
+ case VCS:
+ ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
+ break;
+ case BCS:
+ ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
+ break;
+ case VECS:
+ /* VECS can use the same length_mask function as VCS */
+ ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
+ break;
+ default:
+ DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
+ ring->id);
+ }
+
+ validate_cmds_sorted(ring);
+ validate_regs_sorted(ring);
+}
+
+static const struct drm_i915_cmd_descriptor*
+find_cmd_in_table(const struct drm_i915_cmd_table *table,
+ u32 cmd_header)
+{
+ int i;
+
+ for (i = 0; i < table->count; i++) {
+ const struct drm_i915_cmd_descriptor *desc = &table->table[i];
+ u32 masked_cmd = desc->cmd.mask & cmd_header;
+ u32 masked_value = desc->cmd.value & desc->cmd.mask;
+
+ if (masked_cmd == masked_value)
+ return desc;
+ }
+
+ return NULL;
+}
+
+/*
+ * Returns a pointer to a descriptor for the command specified by cmd_header.
+ *
+ * The caller must supply space for a default descriptor via the default_desc
+ * parameter. If no descriptor for the specified command exists in the ring's
+ * command parser tables, this function fills in default_desc based on the
+ * ring's default length encoding and returns default_desc.
+ */
+static const struct drm_i915_cmd_descriptor*
+find_cmd(struct intel_ring_buffer *ring,
+ u32 cmd_header,
+ struct drm_i915_cmd_descriptor *default_desc)
+{
+ u32 mask;
+ int i;
+
+ for (i = 0; i < ring->cmd_table_count; i++) {
+ const struct drm_i915_cmd_descriptor *desc;
+
+ desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
+ if (desc)
+ return desc;
+ }
+
+ mask = ring->get_cmd_length_mask(cmd_header);
+ if (!mask)
+ return NULL;
+
+ BUG_ON(!default_desc);
+ default_desc->flags = CMD_DESC_SKIP;
+ default_desc->length.mask = mask;
+
+ return default_desc;
+}
+
+static int valid_reg(const u32 *table, int count, u32 addr)
+{
+ if (table && count != 0) {
+ int i;
+
+ for (i = 0; i < count; i++) {
+ if (table[i] == addr)
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static u32 *vmap_batch(struct drm_i915_gem_object *obj)
+{
+ int i;
+ void *addr = NULL;
+ struct sg_page_iter sg_iter;
+ struct page **pages;
+
+ pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
+ if (pages == NULL) {
+ DRM_DEBUG_DRIVER("Failed to get space for pages\n");
+ goto finish;
+ }
+
+ i = 0;
+ for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
+ pages[i] = sg_page_iter_page(&sg_iter);
+ i++;
+ }
+
+ addr = vmap(pages, i, 0, PAGE_KERNEL);
+ if (addr == NULL) {
+ DRM_DEBUG_DRIVER("Failed to vmap pages\n");
+ goto finish;
+ }
+
+finish:
+ if (pages)
+ drm_free_large(pages);
+ return (u32*)addr;
+}
+
+int i915_needs_cmd_parser(struct intel_ring_buffer *ring)
+{
+ /* No command tables indicates a platform without parsing */
+ if (!ring->cmd_tables)
+ return 0;
+
+ return i915.enable_cmd_parser;
+}
+
+#define LENGTH_BIAS 2
+
+int i915_parse_cmds(struct intel_ring_buffer *ring,
+ struct drm_i915_gem_object *batch_obj,
+ u32 batch_start_offset,
+ bool is_master)
+{
+ int ret = 0;
+ u32 *cmd, *batch_base, *batch_end;
+ struct drm_i915_cmd_descriptor default_desc = { 0 };
+ int needs_clflush = 0;
+
+ ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
+ if (ret) {
+ DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
+ return ret;
+ }
+
+ batch_base = vmap_batch(batch_obj);
+ if (!batch_base) {
+ DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
+ i915_gem_object_unpin_pages(batch_obj);
+ return -ENOMEM;
+ }
+
+ if (needs_clflush)
+ drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
+
+ cmd = batch_base + (batch_start_offset / sizeof(*cmd));
+ batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
+
+ while (cmd < batch_end) {
+ const struct drm_i915_cmd_descriptor *desc;
+ u32 length;
+
+ if (*cmd == MI_BATCH_BUFFER_END)
+ break;
+
+ desc = find_cmd(ring, *cmd, &default_desc);
+ if (!desc) {
+ DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
+ *cmd);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (desc->flags & CMD_DESC_FIXED)
+ length = desc->length.fixed;
+ else
+ length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
+
+ if ((batch_end - cmd) < length) {
+ DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%ld\n",
+ *cmd,
+ length,
+ batch_end - cmd);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (desc->flags & CMD_DESC_REJECT) {
+ DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
+ ret = -EINVAL;
+ break;
+ }
+
+ if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
+ DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
+ *cmd);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (desc->flags & CMD_DESC_REGISTER) {
+ u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
+
+ if (!valid_reg(ring->reg_table,
+ ring->reg_count, reg_addr)) {
+ if (!is_master ||
+ !valid_reg(ring->master_reg_table,
+ ring->master_reg_count,
+ reg_addr)) {
+ DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
+ reg_addr,
+ *cmd,
+ ring->id);
+ ret = -EINVAL;
+ break;
+ }
+ }
+ }
+
+ if (desc->flags & CMD_DESC_BITMASK) {
+ int i;
+
+ for (i = 0; i < desc->bits_count; i++) {
+ u32 dword = cmd[desc->bits[i].offset] &
+ desc->bits[i].mask;
+
+ if (dword != desc->bits[i].expected) {
+ DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
+ *cmd,
+ desc->bits[i].mask,
+ desc->bits[i].expected,
+ dword, ring->id);
+ ret = -EINVAL;
+ break;
+ }
+ }
+
+ if (ret)
+ break;
+ }
+
+ cmd += length;
+ }
+
+ if (cmd >= batch_end) {
+ DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
+ ret = -EINVAL;
+ }
+
+ vunmap(batch_base);
+
+ i915_gem_object_unpin_pages(batch_obj);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bfb30df..8aed80f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1765,6 +1765,91 @@ struct drm_i915_file_private {
atomic_t rps_wait_boost;
};
+/**
+ * A command that requires special handling by the command parser.
+ */
+struct drm_i915_cmd_descriptor {
+ /**
+ * Flags describing how the command parser processes the command.
+ *
+ * CMD_DESC_FIXED: The command has a fixed length if this is set,
+ * a length mask if not set
+ * CMD_DESC_SKIP: The command is allowed but does not follow the
+ * standard length encoding for the opcode range in
+ * which it falls
+ * CMD_DESC_REJECT: The command is never allowed
+ * CMD_DESC_REGISTER: The command should be checked against the
+ * register whitelist for the appropriate ring
+ * CMD_DESC_MASTER: The command is allowed if the submitting process
+ * is the DRM master
+ */
+ u32 flags;
+#define CMD_DESC_FIXED (1<<0)
+#define CMD_DESC_SKIP (1<<1)
+#define CMD_DESC_REJECT (1<<2)
+#define CMD_DESC_REGISTER (1<<3)
+#define CMD_DESC_BITMASK (1<<4)
+#define CMD_DESC_MASTER (1<<5)
+
+ /**
+ * The command's unique identification bits and the bitmask to get them.
+ * This isn't strictly the opcode field as defined in the spec and may
+ * also include type, subtype, and/or subop fields.
+ */
+ struct {
+ u32 value;
+ u32 mask;
+ } cmd;
+
+ /**
+ * The command's length. The command is either fixed length (i.e. does
+ * not include a length field) or has a length field mask. The flag
+ * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
+ * a length mask. All command entries in a command table must include
+ * length information.
+ */
+ union {
+ u32 fixed;
+ u32 mask;
+ } length;
+
+ /**
+ * Describes where to find a register address in the command to check
+ * against the ring's register whitelist. Only valid if flags has the
+ * CMD_DESC_REGISTER bit set.
+ */
+ struct {
+ u32 offset;
+ u32 mask;
+ } reg;
+
+#define MAX_CMD_DESC_BITMASKS 3
+ /**
+ * Describes command checks where a particular dword is masked and
+ * compared against an expected value. If the command does not match
+ * the expected value, the parser rejects it. Only valid if flags has
+ * the CMD_DESC_BITMASK bit set.
+ */
+ struct {
+ u32 offset;
+ u32 mask;
+ u32 expected;
+ } bits[MAX_CMD_DESC_BITMASKS];
+ /** Number of valid entries in the bits array */
+ int bits_count;
+};
+
+/**
+ * A table of commands requiring special handling by the command parser.
+ *
+ * Each ring has an array of tables. Each table consists of an array of command
+ * descriptors, which must be sorted with command opcodes in ascending order.
+ */
+struct drm_i915_cmd_table {
+ const struct drm_i915_cmd_descriptor *table;
+ int count;
+};
+
#define INTEL_INFO(dev) (to_i915(dev)->info)
#define IS_I830(dev) ((dev)->pdev->device == 0x3577)
@@ -1923,6 +2008,7 @@ struct i915_params {
bool prefault_disable;
bool reset;
int invert_brightness;
+ int enable_cmd_parser;
};
extern struct i915_params i915 __read_mostly;
@@ -2428,6 +2514,14 @@ void i915_destroy_error_state(struct drm_device *dev);
void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
const char *i915_cache_level_str(int type);
+/* i915_cmd_parser.c */
+void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
+int i915_needs_cmd_parser(struct intel_ring_buffer *ring);
+int i915_parse_cmds(struct intel_ring_buffer *ring,
+ struct drm_i915_gem_object *batch_obj,
+ u32 batch_start_offset,
+ bool is_master);
+
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 032def9..c953445 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1180,6 +1180,23 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
}
batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
+ if (i915_needs_cmd_parser(ring)) {
+ ret = i915_parse_cmds(ring,
+ batch_obj,
+ args->batch_start_offset,
+ file->is_master);
+ if (ret)
+ goto err;
+
+ /*
+ * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit
+ * from MI_BATCH_BUFFER_START commands issued in the
+ * dispatch_execbuffer implementations. We specifically don't
+ * want that set when the command parser is enabled.
+ */
+ flags |= I915_DISPATCH_SECURE;
+ }
+
/* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
* batch" bit. Hence we need to pin secure batches into the global gtt.
* hsw should have this fixed, but bdw mucks it up again. */
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index c743057..6d3d906 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.reset = true,
.invert_brightness = 0,
+ .enable_cmd_parser = 0
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -153,3 +154,7 @@ MODULE_PARM_DESC(invert_brightness,
"report PCI device ID, subsystem vendor and subsystem device ID "
"to dri-devel@lists.freedesktop.org, if your machine needs it. "
"It will then be included in an upcoming module version.");
+
+module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
+MODULE_PARM_DESC(enable_cmd_parser,
+ "Enable command parsing (default: false)");
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a0d61f8..77fc61d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1388,6 +1388,8 @@ static int intel_init_ring_buffer(struct drm_device *dev,
if (IS_I830(ring->dev) || IS_845G(ring->dev))
ring->effective_size -= 128;
+ i915_cmd_parser_init_ring(ring);
+
return 0;
err_unmap:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 71a73f4..cff2b35 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -162,6 +162,38 @@ struct intel_ring_buffer {
u32 gtt_offset;
volatile u32 *cpu_page;
} scratch;
+
+ /**
+ * Tables of commands the command parser needs to know about
+ * for this ring.
+ */
+ const struct drm_i915_cmd_table *cmd_tables;
+ int cmd_table_count;
+
+ /**
+ * Table of registers allowed in commands that read/write registers.
+ */
+ const u32 *reg_table;
+ int reg_count;
+
+ /**
+ * Table of registers allowed in commands that read/write registers, but
+ * only from the DRM master.
+ */
+ const u32 *master_reg_table;
+ int master_reg_count;
+
+ /**
+ * Returns the bitmask for the length field of the specified command.
+ * Return 0 for an unrecognized/invalid command.
+ *
+ * If the command parser finds an entry for a command in the ring's
+ * cmd_tables, it gets the command's length based on the table entry.
+ * If not, it calls this function to determine the per-ring length field
+ * encoding for the command (i.e. certain opcode ranges use certain bits
+ * to encode the command length in the header).
+ */
+ u32 (*get_cmd_length_mask)(u32 cmd_header);
};
static inline bool
--
1.8.5.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-29 21:55 ` [PATCH 02/13] drm/i915: Implement command buffer parsing logic bradley.d.volkin
@ 2014-01-29 22:28 ` Chris Wilson
2014-01-30 8:53 ` Daniel Vetter
2014-01-30 9:07 ` Daniel Vetter
` (2 subsequent siblings)
3 siblings, 1 reply; 138+ messages in thread
From: Chris Wilson @ 2014-01-29 22:28 UTC (permalink / raw)
To: bradley.d.volkin; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> +/*
> + * Returns a pointer to a descriptor for the command specified by cmd_header.
> + *
> + * The caller must supply space for a default descriptor via the default_desc
> + * parameter. If no descriptor for the specified command exists in the ring's
> + * command parser tables, this function fills in default_desc based on the
> + * ring's default length encoding and returns default_desc.
> + */
> +static const struct drm_i915_cmd_descriptor*
> +find_cmd(struct intel_ring_buffer *ring,
> + u32 cmd_header,
> + struct drm_i915_cmd_descriptor *default_desc)
> +{
> + u32 mask;
> + int i;
> +
> + for (i = 0; i < ring->cmd_table_count; i++) {
> + const struct drm_i915_cmd_descriptor *desc;
> +
> + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> + if (desc)
> + return desc;
> + }
> +
> + mask = ring->get_cmd_length_mask(cmd_header);
> + if (!mask)
> + return NULL;
> +
> + BUG_ON(!default_desc);
> + default_desc->flags = CMD_DESC_SKIP;
> + default_desc->length.mask = mask;
If we turn off all hw validation (through use of the secure bit) should
we not default to a whitelist of commands? Otherwise it just seems to be
a case of running a fuzzer until we kill the machine.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-29 22:28 ` Chris Wilson
@ 2014-01-30 8:53 ` Daniel Vetter
2014-01-30 9:05 ` Daniel Vetter
0 siblings, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-01-30 8:53 UTC (permalink / raw)
To: Chris Wilson, bradley.d.volkin, intel-gfx
On Wed, Jan 29, 2014 at 10:28:36PM +0000, Chris Wilson wrote:
> On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > +/*
> > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > + *
> > + * The caller must supply space for a default descriptor via the default_desc
> > + * parameter. If no descriptor for the specified command exists in the ring's
> > + * command parser tables, this function fills in default_desc based on the
> > + * ring's default length encoding and returns default_desc.
> > + */
> > +static const struct drm_i915_cmd_descriptor*
> > +find_cmd(struct intel_ring_buffer *ring,
> > + u32 cmd_header,
> > + struct drm_i915_cmd_descriptor *default_desc)
> > +{
> > + u32 mask;
> > + int i;
> > +
> > + for (i = 0; i < ring->cmd_table_count; i++) {
> > + const struct drm_i915_cmd_descriptor *desc;
> > +
> > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > + if (desc)
> > + return desc;
> > + }
> > +
> > + mask = ring->get_cmd_length_mask(cmd_header);
> > + if (!mask)
> > + return NULL;
> > +
> > + BUG_ON(!default_desc);
> > + default_desc->flags = CMD_DESC_SKIP;
> > + default_desc->length.mask = mask;
>
> If we turn off all hw validation (through use of the secure bit) should
> we not default to a whitelist of commands? Otherwise it just seems to be
> a case of running a fuzzer until we kill the machine.
Preventing hangs and dos is imo not the attack model, gpus are too fickle
for that. The attach model here is to prevent priveledge escalation and
information leaks. I.e. we want just containement of all read/write access
to the gtt space.
I think for that purpose an explicit whitelist of commands which target
things outside of the (pp)gtt is sufficient. radeon's checker design is
completely different, but pretty much the only command they have is
to load register values. Intel gpus otoh have a big set of special-purpose
commands to load (most) of the rendering pipeline state. So we have
hw built-in register whitelists for all that stuff since you just can't
load arbitrary registers and state with those commands.
Also note that for raw register access Bradley's scanner _is_ whitelist
based. And for general reads/writes gpu designers confirmed that those are
all MI_ commands (with very few specific exceptions like PIPE_CONTROL), so
as long as we check for the exceptions and otherwise only whitelist MI_
commands we know about we should be covered.
So I think this is sound.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-30 8:53 ` Daniel Vetter
@ 2014-01-30 9:05 ` Daniel Vetter
2014-01-30 9:12 ` Daniel Vetter
0 siblings, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-01-30 9:05 UTC (permalink / raw)
To: Chris Wilson, bradley.d.volkin, intel-gfx
On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> On Wed, Jan 29, 2014 at 10:28:36PM +0000, Chris Wilson wrote:
> > On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > > +/*
> > > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > > + *
> > > + * The caller must supply space for a default descriptor via the default_desc
> > > + * parameter. If no descriptor for the specified command exists in the ring's
> > > + * command parser tables, this function fills in default_desc based on the
> > > + * ring's default length encoding and returns default_desc.
> > > + */
> > > +static const struct drm_i915_cmd_descriptor*
> > > +find_cmd(struct intel_ring_buffer *ring,
> > > + u32 cmd_header,
> > > + struct drm_i915_cmd_descriptor *default_desc)
> > > +{
> > > + u32 mask;
> > > + int i;
> > > +
> > > + for (i = 0; i < ring->cmd_table_count; i++) {
> > > + const struct drm_i915_cmd_descriptor *desc;
> > > +
> > > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > > + if (desc)
> > > + return desc;
> > > + }
> > > +
> > > + mask = ring->get_cmd_length_mask(cmd_header);
> > > + if (!mask)
> > > + return NULL;
> > > +
> > > + BUG_ON(!default_desc);
> > > + default_desc->flags = CMD_DESC_SKIP;
> > > + default_desc->length.mask = mask;
> >
> > If we turn off all hw validation (through use of the secure bit) should
> > we not default to a whitelist of commands? Otherwise it just seems to be
> > a case of running a fuzzer until we kill the machine.
>
> Preventing hangs and dos is imo not the attack model, gpus are too fickle
> for that. The attach model here is to prevent priveledge escalation and
> information leaks. I.e. we want just containement of all read/write access
> to the gtt space.
>
> I think for that purpose an explicit whitelist of commands which target
> things outside of the (pp)gtt is sufficient. radeon's checker design is
> completely different, but pretty much the only command they have is
> to load register values. Intel gpus otoh have a big set of special-purpose
> commands to load (most) of the rendering pipeline state. So we have
> hw built-in register whitelists for all that stuff since you just can't
> load arbitrary registers and state with those commands.
>
> Also note that for raw register access Bradley's scanner _is_ whitelist
> based. And for general reads/writes gpu designers confirmed that those are
> all MI_ commands (with very few specific exceptions like PIPE_CONTROL), so
> as long as we check for the exceptions and otherwise only whitelist MI_
> commands we know about we should be covered.
>
> So I think this is sound.
Hm, but while scrolling through the checker I haven't spotted a "reject
everything unknown" for MI_CLIENT commands. Bradley, have I missed that?
I think submitting an invented MI_CLIENT command would also be a good
testcase.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-30 9:05 ` Daniel Vetter
@ 2014-01-30 9:12 ` Daniel Vetter
2014-01-30 11:07 ` Daniel Vetter
2014-01-30 17:55 ` Volkin, Bradley D
0 siblings, 2 replies; 138+ messages in thread
From: Daniel Vetter @ 2014-01-30 9:12 UTC (permalink / raw)
To: Chris Wilson, bradley.d.volkin, intel-gfx
On Thu, Jan 30, 2014 at 10:05:28AM +0100, Daniel Vetter wrote:
> On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> > On Wed, Jan 29, 2014 at 10:28:36PM +0000, Chris Wilson wrote:
> > > On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > > > +/*
> > > > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > > > + *
> > > > + * The caller must supply space for a default descriptor via the default_desc
> > > > + * parameter. If no descriptor for the specified command exists in the ring's
> > > > + * command parser tables, this function fills in default_desc based on the
> > > > + * ring's default length encoding and returns default_desc.
> > > > + */
> > > > +static const struct drm_i915_cmd_descriptor*
> > > > +find_cmd(struct intel_ring_buffer *ring,
> > > > + u32 cmd_header,
> > > > + struct drm_i915_cmd_descriptor *default_desc)
> > > > +{
> > > > + u32 mask;
> > > > + int i;
> > > > +
> > > > + for (i = 0; i < ring->cmd_table_count; i++) {
> > > > + const struct drm_i915_cmd_descriptor *desc;
> > > > +
> > > > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > > > + if (desc)
> > > > + return desc;
> > > > + }
> > > > +
> > > > + mask = ring->get_cmd_length_mask(cmd_header);
> > > > + if (!mask)
> > > > + return NULL;
> > > > +
> > > > + BUG_ON(!default_desc);
> > > > + default_desc->flags = CMD_DESC_SKIP;
> > > > + default_desc->length.mask = mask;
> > >
> > > If we turn off all hw validation (through use of the secure bit) should
> > > we not default to a whitelist of commands? Otherwise it just seems to be
> > > a case of running a fuzzer until we kill the machine.
> >
> > Preventing hangs and dos is imo not the attack model, gpus are too fickle
> > for that. The attach model here is to prevent priveledge escalation and
> > information leaks. I.e. we want just containement of all read/write access
> > to the gtt space.
> >
> > I think for that purpose an explicit whitelist of commands which target
> > things outside of the (pp)gtt is sufficient. radeon's checker design is
> > completely different, but pretty much the only command they have is
> > to load register values. Intel gpus otoh have a big set of special-purpose
> > commands to load (most) of the rendering pipeline state. So we have
> > hw built-in register whitelists for all that stuff since you just can't
> > load arbitrary registers and state with those commands.
> >
> > Also note that for raw register access Bradley's scanner _is_ whitelist
> > based. And for general reads/writes gpu designers confirmed that those are
> > all MI_ commands (with very few specific exceptions like PIPE_CONTROL), so
> > as long as we check for the exceptions and otherwise only whitelist MI_
> > commands we know about we should be covered.
> >
> > So I think this is sound.
>
> Hm, but while scrolling through the checker I haven't spotted a "reject
> everything unknown" for MI_CLIENT commands. Bradley, have I missed that?
>
> I think submitting an invented MI_CLIENT command would also be a good
> testcase.
One more: I think it would be good to have an overview comment at the top
of i915_cmd_parser.c which details the security attack model and the
overall blacklist/whitelist design of the checker. We don't (yet) have
autogenerated documentation for i915, but that's something I'm working on.
And the kerneldoc system can also pull in multi-paragraph overview
comments besides the usual api documentation, so it's good to have things
ready.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-30 9:12 ` Daniel Vetter
@ 2014-01-30 11:07 ` Daniel Vetter
2014-01-30 18:05 ` Volkin, Bradley D
2014-01-30 17:55 ` Volkin, Bradley D
1 sibling, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-01-30 11:07 UTC (permalink / raw)
To: Chris Wilson, bradley.d.volkin, intel-gfx
On Thu, Jan 30, 2014 at 10:12:06AM +0100, Daniel Vetter wrote:
> On Thu, Jan 30, 2014 at 10:05:28AM +0100, Daniel Vetter wrote:
> > On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> > > On Wed, Jan 29, 2014 at 10:28:36PM +0000, Chris Wilson wrote:
> > > > On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > > > > +/*
> > > > > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > > > > + *
> > > > > + * The caller must supply space for a default descriptor via the default_desc
> > > > > + * parameter. If no descriptor for the specified command exists in the ring's
> > > > > + * command parser tables, this function fills in default_desc based on the
> > > > > + * ring's default length encoding and returns default_desc.
> > > > > + */
> > > > > +static const struct drm_i915_cmd_descriptor*
> > > > > +find_cmd(struct intel_ring_buffer *ring,
> > > > > + u32 cmd_header,
> > > > > + struct drm_i915_cmd_descriptor *default_desc)
> > > > > +{
> > > > > + u32 mask;
> > > > > + int i;
> > > > > +
> > > > > + for (i = 0; i < ring->cmd_table_count; i++) {
> > > > > + const struct drm_i915_cmd_descriptor *desc;
> > > > > +
> > > > > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > > > > + if (desc)
> > > > > + return desc;
> > > > > + }
> > > > > +
> > > > > + mask = ring->get_cmd_length_mask(cmd_header);
> > > > > + if (!mask)
> > > > > + return NULL;
> > > > > +
> > > > > + BUG_ON(!default_desc);
> > > > > + default_desc->flags = CMD_DESC_SKIP;
> > > > > + default_desc->length.mask = mask;
> > > >
> > > > If we turn off all hw validation (through use of the secure bit) should
> > > > we not default to a whitelist of commands? Otherwise it just seems to be
> > > > a case of running a fuzzer until we kill the machine.
> > >
> > > Preventing hangs and dos is imo not the attack model, gpus are too fickle
> > > for that. The attach model here is to prevent priveledge escalation and
> > > information leaks. I.e. we want just containement of all read/write access
> > > to the gtt space.
> > >
> > > I think for that purpose an explicit whitelist of commands which target
> > > things outside of the (pp)gtt is sufficient. radeon's checker design is
> > > completely different, but pretty much the only command they have is
> > > to load register values. Intel gpus otoh have a big set of special-purpose
> > > commands to load (most) of the rendering pipeline state. So we have
> > > hw built-in register whitelists for all that stuff since you just can't
> > > load arbitrary registers and state with those commands.
> > >
> > > Also note that for raw register access Bradley's scanner _is_ whitelist
> > > based. And for general reads/writes gpu designers confirmed that those are
> > > all MI_ commands (with very few specific exceptions like PIPE_CONTROL), so
> > > as long as we check for the exceptions and otherwise only whitelist MI_
> > > commands we know about we should be covered.
> > >
> > > So I think this is sound.
> >
> > Hm, but while scrolling through the checker I haven't spotted a "reject
> > everything unknown" for MI_CLIENT commands. Bradley, have I missed that?
> >
> > I think submitting an invented MI_CLIENT command would also be a good
> > testcase.
>
> One more: I think it would be good to have an overview comment at the top
> of i915_cmd_parser.c which details the security attack model and the
> overall blacklist/whitelist design of the checker. We don't (yet) have
> autogenerated documentation for i915, but that's something I'm working on.
> And the kerneldoc system can also pull in multi-paragraph overview
> comments besides the usual api documentation, so it's good to have things
> ready.
Chatted with Chris a bit more on irc about this, and for more paranoia I
guess we should also reject any unknown client and media subclient
commands.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-30 11:07 ` Daniel Vetter
@ 2014-01-30 18:05 ` Volkin, Bradley D
2014-02-03 23:00 ` Volkin, Bradley D
0 siblings, 1 reply; 138+ messages in thread
From: Volkin, Bradley D @ 2014-01-30 18:05 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 30, 2014 at 03:07:15AM -0800, Daniel Vetter wrote:
> On Thu, Jan 30, 2014 at 10:12:06AM +0100, Daniel Vetter wrote:
> > On Thu, Jan 30, 2014 at 10:05:28AM +0100, Daniel Vetter wrote:
> > > On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> > > > On Wed, Jan 29, 2014 at 10:28:36PM +0000, Chris Wilson wrote:
> > > > > On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > > > > > +/*
> > > > > > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > > > > > + *
> > > > > > + * The caller must supply space for a default descriptor via the default_desc
> > > > > > + * parameter. If no descriptor for the specified command exists in the ring's
> > > > > > + * command parser tables, this function fills in default_desc based on the
> > > > > > + * ring's default length encoding and returns default_desc.
> > > > > > + */
> > > > > > +static const struct drm_i915_cmd_descriptor*
> > > > > > +find_cmd(struct intel_ring_buffer *ring,
> > > > > > + u32 cmd_header,
> > > > > > + struct drm_i915_cmd_descriptor *default_desc)
> > > > > > +{
> > > > > > + u32 mask;
> > > > > > + int i;
> > > > > > +
> > > > > > + for (i = 0; i < ring->cmd_table_count; i++) {
> > > > > > + const struct drm_i915_cmd_descriptor *desc;
> > > > > > +
> > > > > > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > > > > > + if (desc)
> > > > > > + return desc;
> > > > > > + }
> > > > > > +
> > > > > > + mask = ring->get_cmd_length_mask(cmd_header);
> > > > > > + if (!mask)
> > > > > > + return NULL;
> > > > > > +
> > > > > > + BUG_ON(!default_desc);
> > > > > > + default_desc->flags = CMD_DESC_SKIP;
> > > > > > + default_desc->length.mask = mask;
> > > > >
> > > > > If we turn off all hw validation (through use of the secure bit) should
> > > > > we not default to a whitelist of commands? Otherwise it just seems to be
> > > > > a case of running a fuzzer until we kill the machine.
> > > >
> > > > Preventing hangs and dos is imo not the attack model, gpus are too fickle
> > > > for that. The attach model here is to prevent priveledge escalation and
> > > > information leaks. I.e. we want just containement of all read/write access
> > > > to the gtt space.
> > > >
> > > > I think for that purpose an explicit whitelist of commands which target
> > > > things outside of the (pp)gtt is sufficient. radeon's checker design is
> > > > completely different, but pretty much the only command they have is
> > > > to load register values. Intel gpus otoh have a big set of special-purpose
> > > > commands to load (most) of the rendering pipeline state. So we have
> > > > hw built-in register whitelists for all that stuff since you just can't
> > > > load arbitrary registers and state with those commands.
> > > >
> > > > Also note that for raw register access Bradley's scanner _is_ whitelist
> > > > based. And for general reads/writes gpu designers confirmed that those are
> > > > all MI_ commands (with very few specific exceptions like PIPE_CONTROL), so
> > > > as long as we check for the exceptions and otherwise only whitelist MI_
> > > > commands we know about we should be covered.
> > > >
> > > > So I think this is sound.
> > >
> > > Hm, but while scrolling through the checker I haven't spotted a "reject
> > > everything unknown" for MI_CLIENT commands. Bradley, have I missed that?
> > >
> > > I think submitting an invented MI_CLIENT command would also be a good
> > > testcase.
> >
> > One more: I think it would be good to have an overview comment at the top
> > of i915_cmd_parser.c which details the security attack model and the
> > overall blacklist/whitelist design of the checker. We don't (yet) have
> > autogenerated documentation for i915, but that's something I'm working on.
> > And the kerneldoc system can also pull in multi-paragraph overview
> > comments besides the usual api documentation, so it's good to have things
> > ready.
>
> Chatted with Chris a bit more on irc about this, and for more paranoia I
> guess we should also reject any unknown client and media subclient
> commands.
Hmm, not sure I follow. Can you elaborate?
Are you suggesting we add all the MI and Media commands to the tables and reject
any command from those client/subclients that is not found in the table? Or that
we look at the client and subclient fields of the command and reject if they are
not from a set of expected values? Or other?
- Brad
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-30 18:05 ` Volkin, Bradley D
@ 2014-02-03 23:00 ` Volkin, Bradley D
2014-02-04 10:20 ` Daniel Vetter
0 siblings, 1 reply; 138+ messages in thread
From: Volkin, Bradley D @ 2014-02-03 23:00 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
Ping. Daniel or Chris, can one of you clarify this request? Thanks.
On Thu, Jan 30, 2014 at 10:05:27AM -0800, Volkin, Bradley D wrote:
> On Thu, Jan 30, 2014 at 03:07:15AM -0800, Daniel Vetter wrote:
> > On Thu, Jan 30, 2014 at 10:12:06AM +0100, Daniel Vetter wrote:
> > > On Thu, Jan 30, 2014 at 10:05:28AM +0100, Daniel Vetter wrote:
> > > > On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> > > > > On Wed, Jan 29, 2014 at 10:28:36PM +0000, Chris Wilson wrote:
> > > > > > On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > > > > > > +/*
> > > > > > > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > > > > > > + *
> > > > > > > + * The caller must supply space for a default descriptor via the default_desc
> > > > > > > + * parameter. If no descriptor for the specified command exists in the ring's
> > > > > > > + * command parser tables, this function fills in default_desc based on the
> > > > > > > + * ring's default length encoding and returns default_desc.
> > > > > > > + */
> > > > > > > +static const struct drm_i915_cmd_descriptor*
> > > > > > > +find_cmd(struct intel_ring_buffer *ring,
> > > > > > > + u32 cmd_header,
> > > > > > > + struct drm_i915_cmd_descriptor *default_desc)
> > > > > > > +{
> > > > > > > + u32 mask;
> > > > > > > + int i;
> > > > > > > +
> > > > > > > + for (i = 0; i < ring->cmd_table_count; i++) {
> > > > > > > + const struct drm_i915_cmd_descriptor *desc;
> > > > > > > +
> > > > > > > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > > > > > > + if (desc)
> > > > > > > + return desc;
> > > > > > > + }
> > > > > > > +
> > > > > > > + mask = ring->get_cmd_length_mask(cmd_header);
> > > > > > > + if (!mask)
> > > > > > > + return NULL;
> > > > > > > +
> > > > > > > + BUG_ON(!default_desc);
> > > > > > > + default_desc->flags = CMD_DESC_SKIP;
> > > > > > > + default_desc->length.mask = mask;
> > > > > >
> > > > > > If we turn off all hw validation (through use of the secure bit) should
> > > > > > we not default to a whitelist of commands? Otherwise it just seems to be
> > > > > > a case of running a fuzzer until we kill the machine.
> > > > >
> > > > > Preventing hangs and dos is imo not the attack model, gpus are too fickle
> > > > > for that. The attach model here is to prevent priveledge escalation and
> > > > > information leaks. I.e. we want just containement of all read/write access
> > > > > to the gtt space.
> > > > >
> > > > > I think for that purpose an explicit whitelist of commands which target
> > > > > things outside of the (pp)gtt is sufficient. radeon's checker design is
> > > > > completely different, but pretty much the only command they have is
> > > > > to load register values. Intel gpus otoh have a big set of special-purpose
> > > > > commands to load (most) of the rendering pipeline state. So we have
> > > > > hw built-in register whitelists for all that stuff since you just can't
> > > > > load arbitrary registers and state with those commands.
> > > > >
> > > > > Also note that for raw register access Bradley's scanner _is_ whitelist
> > > > > based. And for general reads/writes gpu designers confirmed that those are
> > > > > all MI_ commands (with very few specific exceptions like PIPE_CONTROL), so
> > > > > as long as we check for the exceptions and otherwise only whitelist MI_
> > > > > commands we know about we should be covered.
> > > > >
> > > > > So I think this is sound.
> > > >
> > > > Hm, but while scrolling through the checker I haven't spotted a "reject
> > > > everything unknown" for MI_CLIENT commands. Bradley, have I missed that?
> > > >
> > > > I think submitting an invented MI_CLIENT command would also be a good
> > > > testcase.
> > >
> > > One more: I think it would be good to have an overview comment at the top
> > > of i915_cmd_parser.c which details the security attack model and the
> > > overall blacklist/whitelist design of the checker. We don't (yet) have
> > > autogenerated documentation for i915, but that's something I'm working on.
> > > And the kerneldoc system can also pull in multi-paragraph overview
> > > comments besides the usual api documentation, so it's good to have things
> > > ready.
> >
> > Chatted with Chris a bit more on irc about this, and for more paranoia I
> > guess we should also reject any unknown client and media subclient
> > commands.
>
> Hmm, not sure I follow. Can you elaborate?
>
> Are you suggesting we add all the MI and Media commands to the tables and reject
> any command from those client/subclients that is not found in the table? Or that
> we look at the client and subclient fields of the command and reject if they are
> not from a set of expected values? Or other?
>
> - Brad
>
> > -Daniel
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-02-03 23:00 ` Volkin, Bradley D
@ 2014-02-04 10:20 ` Daniel Vetter
2014-02-04 18:45 ` Volkin, Bradley D
0 siblings, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-02-04 10:20 UTC (permalink / raw)
To: Volkin, Bradley D; +Cc: intel-gfx
On Mon, Feb 03, 2014 at 03:00:19PM -0800, Volkin, Bradley D wrote:
> Ping. Daniel or Chris, can one of you clarify this request? Thanks.
I've been enjoying fosdem ...
> On Thu, Jan 30, 2014 at 10:05:27AM -0800, Volkin, Bradley D wrote:
> > On Thu, Jan 30, 2014 at 03:07:15AM -0800, Daniel Vetter wrote:
> > > On Thu, Jan 30, 2014 at 10:12:06AM +0100, Daniel Vetter wrote:
> > > > On Thu, Jan 30, 2014 at 10:05:28AM +0100, Daniel Vetter wrote:
> > > > > On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> > > > > > On Wed, Jan 29, 2014 at 10:28:36PM +0000, Chris Wilson wrote:
> > > > > > > On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > > > > > > > +/*
> > > > > > > > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > > > > > > > + *
> > > > > > > > + * The caller must supply space for a default descriptor via the default_desc
> > > > > > > > + * parameter. If no descriptor for the specified command exists in the ring's
> > > > > > > > + * command parser tables, this function fills in default_desc based on the
> > > > > > > > + * ring's default length encoding and returns default_desc.
> > > > > > > > + */
> > > > > > > > +static const struct drm_i915_cmd_descriptor*
> > > > > > > > +find_cmd(struct intel_ring_buffer *ring,
> > > > > > > > + u32 cmd_header,
> > > > > > > > + struct drm_i915_cmd_descriptor *default_desc)
> > > > > > > > +{
> > > > > > > > + u32 mask;
> > > > > > > > + int i;
> > > > > > > > +
> > > > > > > > + for (i = 0; i < ring->cmd_table_count; i++) {
> > > > > > > > + const struct drm_i915_cmd_descriptor *desc;
> > > > > > > > +
> > > > > > > > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > > > > > > > + if (desc)
> > > > > > > > + return desc;
> > > > > > > > + }
> > > > > > > > +
> > > > > > > > + mask = ring->get_cmd_length_mask(cmd_header);
> > > > > > > > + if (!mask)
> > > > > > > > + return NULL;
> > > > > > > > +
> > > > > > > > + BUG_ON(!default_desc);
> > > > > > > > + default_desc->flags = CMD_DESC_SKIP;
> > > > > > > > + default_desc->length.mask = mask;
> > > > > > >
> > > > > > > If we turn off all hw validation (through use of the secure bit) should
> > > > > > > we not default to a whitelist of commands? Otherwise it just seems to be
> > > > > > > a case of running a fuzzer until we kill the machine.
> > > > > >
> > > > > > Preventing hangs and dos is imo not the attack model, gpus are too fickle
> > > > > > for that. The attach model here is to prevent priveledge escalation and
> > > > > > information leaks. I.e. we want just containement of all read/write access
> > > > > > to the gtt space.
> > > > > >
> > > > > > I think for that purpose an explicit whitelist of commands which target
> > > > > > things outside of the (pp)gtt is sufficient. radeon's checker design is
> > > > > > completely different, but pretty much the only command they have is
> > > > > > to load register values. Intel gpus otoh have a big set of special-purpose
> > > > > > commands to load (most) of the rendering pipeline state. So we have
> > > > > > hw built-in register whitelists for all that stuff since you just can't
> > > > > > load arbitrary registers and state with those commands.
> > > > > >
> > > > > > Also note that for raw register access Bradley's scanner _is_ whitelist
> > > > > > based. And for general reads/writes gpu designers confirmed that those are
> > > > > > all MI_ commands (with very few specific exceptions like PIPE_CONTROL), so
> > > > > > as long as we check for the exceptions and otherwise only whitelist MI_
> > > > > > commands we know about we should be covered.
> > > > > >
> > > > > > So I think this is sound.
> > > > >
> > > > > Hm, but while scrolling through the checker I haven't spotted a "reject
> > > > > everything unknown" for MI_CLIENT commands. Bradley, have I missed that?
> > > > >
> > > > > I think submitting an invented MI_CLIENT command would also be a good
> > > > > testcase.
> > > >
> > > > One more: I think it would be good to have an overview comment at the top
> > > > of i915_cmd_parser.c which details the security attack model and the
> > > > overall blacklist/whitelist design of the checker. We don't (yet) have
> > > > autogenerated documentation for i915, but that's something I'm working on.
> > > > And the kerneldoc system can also pull in multi-paragraph overview
> > > > comments besides the usual api documentation, so it's good to have things
> > > > ready.
> > >
> > > Chatted with Chris a bit more on irc about this, and for more paranoia I
> > > guess we should also reject any unknown client and media subclient
> > > commands.
> >
> > Hmm, not sure I follow. Can you elaborate?
> >
> > Are you suggesting we add all the MI and Media commands to the tables and reject
> > any command from those client/subclients that is not found in the table? Or that
> > we look at the client and subclient fields of the command and reject if they are
> > not from a set of expected values? Or other?
Yeah, I think we should check the client/subclient fields for know values,
but not have explicit lists for each command. So overall control-flow
would be:
1. Check client/subclient against whitelist (per-ring obviously, so reject
blitter commands on non-blt rings ofc).
2. If the client indicates an MI command, check against MI_ whitelist.
3. For all other clients check against blacklist/greylist (e.g.
pipe_control where we just need to forbid global gtt writes).
Iirc we need a special-cases list for blitter commands anyway due to their
irregular lenght, so maybe we could do a full whitelist for that one, too.
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-02-04 10:20 ` Daniel Vetter
@ 2014-02-04 18:45 ` Volkin, Bradley D
2014-02-04 19:33 ` Daniel Vetter
0 siblings, 1 reply; 138+ messages in thread
From: Volkin, Bradley D @ 2014-02-04 18:45 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Feb 04, 2014 at 02:20:36AM -0800, Daniel Vetter wrote:
> On Mon, Feb 03, 2014 at 03:00:19PM -0800, Volkin, Bradley D wrote:
> > Ping. Daniel or Chris, can one of you clarify this request? Thanks.
>
> I've been enjoying fosdem ...
>
> > On Thu, Jan 30, 2014 at 10:05:27AM -0800, Volkin, Bradley D wrote:
> > > On Thu, Jan 30, 2014 at 03:07:15AM -0800, Daniel Vetter wrote:
> > > > On Thu, Jan 30, 2014 at 10:12:06AM +0100, Daniel Vetter wrote:
> > > > > On Thu, Jan 30, 2014 at 10:05:28AM +0100, Daniel Vetter wrote:
> > > > > > On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> > > > > > > On Wed, Jan 29, 2014 at 10:28:36PM +0000, Chris Wilson wrote:
> > > > > > > > On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > > > > > > > > +/*
> > > > > > > > > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > > > > > > > > + *
> > > > > > > > > + * The caller must supply space for a default descriptor via the default_desc
> > > > > > > > > + * parameter. If no descriptor for the specified command exists in the ring's
> > > > > > > > > + * command parser tables, this function fills in default_desc based on the
> > > > > > > > > + * ring's default length encoding and returns default_desc.
> > > > > > > > > + */
> > > > > > > > > +static const struct drm_i915_cmd_descriptor*
> > > > > > > > > +find_cmd(struct intel_ring_buffer *ring,
> > > > > > > > > + u32 cmd_header,
> > > > > > > > > + struct drm_i915_cmd_descriptor *default_desc)
> > > > > > > > > +{
> > > > > > > > > + u32 mask;
> > > > > > > > > + int i;
> > > > > > > > > +
> > > > > > > > > + for (i = 0; i < ring->cmd_table_count; i++) {
> > > > > > > > > + const struct drm_i915_cmd_descriptor *desc;
> > > > > > > > > +
> > > > > > > > > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > > > > > > > > + if (desc)
> > > > > > > > > + return desc;
> > > > > > > > > + }
> > > > > > > > > +
> > > > > > > > > + mask = ring->get_cmd_length_mask(cmd_header);
> > > > > > > > > + if (!mask)
> > > > > > > > > + return NULL;
> > > > > > > > > +
> > > > > > > > > + BUG_ON(!default_desc);
> > > > > > > > > + default_desc->flags = CMD_DESC_SKIP;
> > > > > > > > > + default_desc->length.mask = mask;
> > > > > > > >
> > > > > > > > If we turn off all hw validation (through use of the secure bit) should
> > > > > > > > we not default to a whitelist of commands? Otherwise it just seems to be
> > > > > > > > a case of running a fuzzer until we kill the machine.
> > > > > > >
> > > > > > > Preventing hangs and dos is imo not the attack model, gpus are too fickle
> > > > > > > for that. The attach model here is to prevent priveledge escalation and
> > > > > > > information leaks. I.e. we want just containement of all read/write access
> > > > > > > to the gtt space.
> > > > > > >
> > > > > > > I think for that purpose an explicit whitelist of commands which target
> > > > > > > things outside of the (pp)gtt is sufficient. radeon's checker design is
> > > > > > > completely different, but pretty much the only command they have is
> > > > > > > to load register values. Intel gpus otoh have a big set of special-purpose
> > > > > > > commands to load (most) of the rendering pipeline state. So we have
> > > > > > > hw built-in register whitelists for all that stuff since you just can't
> > > > > > > load arbitrary registers and state with those commands.
> > > > > > >
> > > > > > > Also note that for raw register access Bradley's scanner _is_ whitelist
> > > > > > > based. And for general reads/writes gpu designers confirmed that those are
> > > > > > > all MI_ commands (with very few specific exceptions like PIPE_CONTROL), so
> > > > > > > as long as we check for the exceptions and otherwise only whitelist MI_
> > > > > > > commands we know about we should be covered.
> > > > > > >
> > > > > > > So I think this is sound.
> > > > > >
> > > > > > Hm, but while scrolling through the checker I haven't spotted a "reject
> > > > > > everything unknown" for MI_CLIENT commands. Bradley, have I missed that?
> > > > > >
> > > > > > I think submitting an invented MI_CLIENT command would also be a good
> > > > > > testcase.
> > > > >
> > > > > One more: I think it would be good to have an overview comment at the top
> > > > > of i915_cmd_parser.c which details the security attack model and the
> > > > > overall blacklist/whitelist design of the checker. We don't (yet) have
> > > > > autogenerated documentation for i915, but that's something I'm working on.
> > > > > And the kerneldoc system can also pull in multi-paragraph overview
> > > > > comments besides the usual api documentation, so it's good to have things
> > > > > ready.
> > > >
> > > > Chatted with Chris a bit more on irc about this, and for more paranoia I
> > > > guess we should also reject any unknown client and media subclient
> > > > commands.
> > >
> > > Hmm, not sure I follow. Can you elaborate?
> > >
> > > Are you suggesting we add all the MI and Media commands to the tables and reject
> > > any command from those client/subclients that is not found in the table? Or that
> > > we look at the client and subclient fields of the command and reject if they are
> > > not from a set of expected values? Or other?
>
> Yeah, I think we should check the client/subclient fields for know values,
> but not have explicit lists for each command. So overall control-flow
> would be:
>
> 1. Check client/subclient against whitelist (per-ring obviously, so reject
> blitter commands on non-blt rings ofc).
Ok, that's easy enough. I'm not sure the benefit is that large, but I can add this.
>
> 2. If the client indicates an MI command, check against MI_ whitelist.
>
> 3. For all other clients check against blacklist/greylist (e.g.
> pipe_control where we just need to forbid global gtt writes).
I'm a bit concerned about 2 and 3 because the behavior and table structures seem
fairly different from what we have now. I'm hesitant to make too big a change here
so close to having something functional.
Please correct me if I've missed or misunderstood anything, but my thinking is...
The current table structure is that we have tables per-ring and per-gen (plus the table
for common MI commands) and all tables are treated as blacklist/greylist. The proposed
flow here would indicate that we need tables per-ring, per-client, per-gen and that some
would be treated as a whitelist and some as a blacklist/greylist.
I think the benefit to these changes amounts to preventing clients from issuing invalid
MI commands, but clients can do that today, so it's not a regression right? It could also
make it easier to safely cover new platforms if MI commands were added, though the parser
is strictly limited to gen7 today and would need additional work to enable it for new gens.
The set of MI commands for current gens is small compared to the other command ranges.
On the one hand, that makes it easier to create a whitelist of the commands. On the other
hand, it also makes it easy to just audit the commands in the spec and validate that the
blacklist/greylist covers the potential issues.
So, if we maintain the conservative parser enabling and re-audit the lists when enabling
new gens, and if we can live with clients issuing totally invalid commands (and I get the
feeling that we have to), then I think the current solution gets us the benefits we want
with less complexity.
Let me know what you think. I'll continue working through the other feedback either way.
>
> Iirc we need a special-cases list for blitter commands anyway due to their
> irregular lenght, so maybe we could do a full whitelist for that one, too.
All rings have commands with irregular length encodings. I believe they also all have
commands with non-fixed lengths (e.g. XY_TEXT_IMMEDIATE_BLT on blt, MEDIA_OBJECT on render).
Thanks,
Brad
>
> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-02-04 18:45 ` Volkin, Bradley D
@ 2014-02-04 19:33 ` Daniel Vetter
2014-02-05 0:56 ` Volkin, Bradley D
0 siblings, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-02-04 19:33 UTC (permalink / raw)
To: Volkin, Bradley D; +Cc: intel-gfx
On Tue, Feb 04, 2014 at 10:45:45AM -0800, Volkin, Bradley D wrote:
> The current table structure is that we have tables per-ring and per-gen (plus the table
> for common MI commands) and all tables are treated as blacklist/greylist. The proposed
> flow here would indicate that we need tables per-ring, per-client, per-gen and that some
> would be treated as a whitelist and some as a blacklist/greylist.
>
> I think the benefit to these changes amounts to preventing clients from issuing invalid
> MI commands, but clients can do that today, so it's not a regression right? It could also
> make it easier to safely cover new platforms if MI commands were added, though the parser
> is strictly limited to gen7 today and would need additional work to enable it for new gens.
The benefit is in enabling future platforms - with an explicit MI
whitelist we'd forced to re-audit MI_ commands fully and there's no chance
to miss something. Also the MI_ commands are the tricky ones, so if one
slips through we have a problem.
Relying on the command streamer hw to catch invalid opcodes is something
we need to, so no benefit for that really.
> The set of MI commands for current gens is small compared to the other command ranges.
> On the one hand, that makes it easier to create a whitelist of the commands. On the other
> hand, it also makes it easy to just audit the commands in the spec and validate that the
> blacklist/greylist covers the potential issues.
Since we only care about the set of allowed MI commands the list probably
even shrinks a bit.
> So, if we maintain the conservative parser enabling and re-audit the lists when enabling
> new gens, and if we can live with clients issuing totally invalid commands (and I get the
> feeling that we have to), then I think the current solution gets us the benefits we want
> with less complexity.
>
> Let me know what you think. I'll continue working through the other feedback either way.
I didn't really consider that the MI whitelist would have a bigger impact
on the code really. So if you expect this change to cause a bit a delay in
getting the next round ready then we can postpone this a bit - for me the
important part is to get the parser in soonish so that we can start to
catch regressions (if there are any we haven't considered yet). But
longer-term I think switching to a whiteliste for MI commands is the right
approach.
> > Iirc we need a special-cases list for blitter commands anyway due to their
> > irregular lenght, so maybe we could do a full whitelist for that one, too.
>
> All rings have commands with irregular length encodings. I believe they also all have
> commands with non-fixed lengths (e.g. XY_TEXT_IMMEDIATE_BLT on blt, MEDIA_OBJECT on render).
Yeah, variable length commands are everywhere, but I've thought commands
which don't use the usual lenght-2 encoding (i.e. those which are just 1
dword) are restricted to MI commands and the blitter. Am I mistaken on
this?
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-02-04 19:33 ` Daniel Vetter
@ 2014-02-05 0:56 ` Volkin, Bradley D
0 siblings, 0 replies; 138+ messages in thread
From: Volkin, Bradley D @ 2014-02-05 0:56 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Feb 04, 2014 at 11:33:31AM -0800, Daniel Vetter wrote:
> On Tue, Feb 04, 2014 at 10:45:45AM -0800, Volkin, Bradley D wrote:
> > The current table structure is that we have tables per-ring and per-gen (plus the table
> > for common MI commands) and all tables are treated as blacklist/greylist. The proposed
> > flow here would indicate that we need tables per-ring, per-client, per-gen and that some
> > would be treated as a whitelist and some as a blacklist/greylist.
> >
> > I think the benefit to these changes amounts to preventing clients from issuing invalid
> > MI commands, but clients can do that today, so it's not a regression right? It could also
> > make it easier to safely cover new platforms if MI commands were added, though the parser
> > is strictly limited to gen7 today and would need additional work to enable it for new gens.
>
> The benefit is in enabling future platforms - with an explicit MI
> whitelist we'd forced to re-audit MI_ commands fully and there's no chance
> to miss something. Also the MI_ commands are the tricky ones, so if one
> slips through we have a problem.
>
> Relying on the command streamer hw to catch invalid opcodes is something
> we need to, so no benefit for that really.
>
> > The set of MI commands for current gens is small compared to the other command ranges.
> > On the one hand, that makes it easier to create a whitelist of the commands. On the other
> > hand, it also makes it easy to just audit the commands in the spec and validate that the
> > blacklist/greylist covers the potential issues.
>
> Since we only care about the set of allowed MI commands the list probably
> even shrinks a bit.
>
> > So, if we maintain the conservative parser enabling and re-audit the lists when enabling
> > new gens, and if we can live with clients issuing totally invalid commands (and I get the
> > feeling that we have to), then I think the current solution gets us the benefits we want
> > with less complexity.
> >
> > Let me know what you think. I'll continue working through the other feedback either way.
>
> I didn't really consider that the MI whitelist would have a bigger impact
> on the code really. So if you expect this change to cause a bit a delay in
> getting the next round ready then we can postpone this a bit - for me the
> important part is to get the parser in soonish so that we can start to
> catch regressions (if there are any we haven't considered yet). But
> longer-term I think switching to a whiteliste for MI commands is the right
> approach.
Ok, let me get the next round out and then I'll look at this in more detail.
>
> > > Iirc we need a special-cases list for blitter commands anyway due to their
> > > irregular lenght, so maybe we could do a full whitelist for that one, too.
> >
> > All rings have commands with irregular length encodings. I believe they also all have
> > commands with non-fixed lengths (e.g. XY_TEXT_IMMEDIATE_BLT on blt, MEDIA_OBJECT on render).
>
> Yeah, variable length commands are everywhere, but I've thought commands
> which don't use the usual lenght-2 encoding (i.e. those which are just 1
> dword) are restricted to MI commands and the blitter. Am I mistaken on
> this?
>From what I see, there's the 1-dword MI commands on all rings. MFX_WAIT uses
length-1 on VCS. The blitter looks like length-2 everywhere.
Also, the MI commands and a few places on RCS and BCS use more/fewer bits for
the length field than other commands for that client/subclient.
-Brad
>
> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-30 9:12 ` Daniel Vetter
2014-01-30 11:07 ` Daniel Vetter
@ 2014-01-30 17:55 ` Volkin, Bradley D
1 sibling, 0 replies; 138+ messages in thread
From: Volkin, Bradley D @ 2014-01-30 17:55 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 30, 2014 at 01:12:06AM -0800, Daniel Vetter wrote:
> On Thu, Jan 30, 2014 at 10:05:28AM +0100, Daniel Vetter wrote:
> > On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> > > On Wed, Jan 29, 2014 at 10:28:36PM +0000, Chris Wilson wrote:
> > > > On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > > > > +/*
> > > > > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > > > > + *
> > > > > + * The caller must supply space for a default descriptor via the default_desc
> > > > > + * parameter. If no descriptor for the specified command exists in the ring's
> > > > > + * command parser tables, this function fills in default_desc based on the
> > > > > + * ring's default length encoding and returns default_desc.
> > > > > + */
> > > > > +static const struct drm_i915_cmd_descriptor*
> > > > > +find_cmd(struct intel_ring_buffer *ring,
> > > > > + u32 cmd_header,
> > > > > + struct drm_i915_cmd_descriptor *default_desc)
> > > > > +{
> > > > > + u32 mask;
> > > > > + int i;
> > > > > +
> > > > > + for (i = 0; i < ring->cmd_table_count; i++) {
> > > > > + const struct drm_i915_cmd_descriptor *desc;
> > > > > +
> > > > > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > > > > + if (desc)
> > > > > + return desc;
> > > > > + }
> > > > > +
> > > > > + mask = ring->get_cmd_length_mask(cmd_header);
> > > > > + if (!mask)
> > > > > + return NULL;
> > > > > +
> > > > > + BUG_ON(!default_desc);
> > > > > + default_desc->flags = CMD_DESC_SKIP;
> > > > > + default_desc->length.mask = mask;
> > > >
> > > > If we turn off all hw validation (through use of the secure bit) should
> > > > we not default to a whitelist of commands? Otherwise it just seems to be
> > > > a case of running a fuzzer until we kill the machine.
> > >
> > > Preventing hangs and dos is imo not the attack model, gpus are too fickle
> > > for that. The attach model here is to prevent priveledge escalation and
> > > information leaks. I.e. we want just containement of all read/write access
> > > to the gtt space.
> > >
> > > I think for that purpose an explicit whitelist of commands which target
> > > things outside of the (pp)gtt is sufficient. radeon's checker design is
> > > completely different, but pretty much the only command they have is
> > > to load register values. Intel gpus otoh have a big set of special-purpose
> > > commands to load (most) of the rendering pipeline state. So we have
> > > hw built-in register whitelists for all that stuff since you just can't
> > > load arbitrary registers and state with those commands.
> > >
> > > Also note that for raw register access Bradley's scanner _is_ whitelist
> > > based. And for general reads/writes gpu designers confirmed that those are
> > > all MI_ commands (with very few specific exceptions like PIPE_CONTROL), so
> > > as long as we check for the exceptions and otherwise only whitelist MI_
> > > commands we know about we should be covered.
> > >
> > > So I think this is sound.
> >
> > Hm, but while scrolling through the checker I haven't spotted a "reject
> > everything unknown" for MI_CLIENT commands. Bradley, have I missed that?
> >
> > I think submitting an invented MI_CLIENT command would also be a good
> > testcase.
>
> One more: I think it would be good to have an overview comment at the top
> of i915_cmd_parser.c which details the security attack model and the
> overall blacklist/whitelist design of the checker. We don't (yet) have
> autogenerated documentation for i915, but that's something I'm working on.
> And the kerneldoc system can also pull in multi-paragraph overview
> comments besides the usual api documentation, so it's good to have things
> ready.
Ok, I'll add that and maybe kerneldoc for the non-static functions to the
next revision.
- Brad
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-29 21:55 ` [PATCH 02/13] drm/i915: Implement command buffer parsing logic bradley.d.volkin
2014-01-29 22:28 ` Chris Wilson
@ 2014-01-30 9:07 ` Daniel Vetter
2014-01-30 10:57 ` Chris Wilson
2014-02-05 15:15 ` Jani Nikula
2014-02-07 13:58 ` Jani Nikula
3 siblings, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-01-30 9:07 UTC (permalink / raw)
To: bradley.d.volkin; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> The command parser scans batch buffers submitted via execbuffer ioctls before
> the driver submits them to hardware. At a high level, it looks for several
> things:
>
> 1) Commands which are explicitly defined as privileged or which should only be
> used by the kernel driver. The parser generally rejects such commands, with
> the provision that it may allow some from the drm master process.
> 2) Commands which access registers. To support correct/enhanced userspace
> functionality, particularly certain OpenGL extensions, the parser provides a
> whitelist of registers which userspace may safely access (for both normal and
> drm master processes).
> 3) Commands which access privileged memory (i.e. GGTT, HWS page, etc). The
> parser always rejects such commands.
>
> Each ring maintains tables of commands and registers which the parser uses in
> scanning batch buffers submitted to that ring.
>
> The set of commands that the parser must check for is significantly smaller
> than the number of commands supported, especially on the render ring. As such,
> the parser tables (built up in subsequent patches) contain only those commands
> required by the parser. This generally works because command opcode ranges have
> standard command length encodings. So for commands that the parser does not need
> to check, it can easily skip them. This is implementated via a per-ring length
> decoding vfunc.
>
> Unfortunately, there are a number of commands that do not follow the standard
> length encoding for their opcode range, primarily amongst the MI_* commands. To
> handle this, the parser provides a way to define explicit "skip" entries in the
> per-ring command tables.
>
> Other command table entries will map fairly directly to high level categories
> mentioned above: rejected, master-only, register whitelist. A number of checks,
> including the privileged memory checks, are implemented via a general bitmasking
> mechanism.
>
> OTC-Tracker: AXIA-4631
> Change-Id: I50b98c71c6655893291c78a2d1b8954577b37a30
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> +#include "i915_drv.h"
> +
> +#define CLIENT_MASK 0xE0000000
> +#define SUBCLIENT_MASK 0x18000000
> +#define MI_CLIENT 0x00000000
> +#define RC_CLIENT 0x60000000
> +#define BC_CLIENT 0x40000000
> +#define MEDIA_SUBCLIENT 0x10000000
I think these would fit neatly right next to all the other MI_* #defines
in i915_reg.h. The other idea that just crossed my mind is to extract all
the command #defines into a new i915_cmd.h (included by i915_drv.h by
default) since i915_reg.h is already giant.
But that should be done as a follow-up patch to avoid patch shuffling
hell.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-30 9:07 ` Daniel Vetter
@ 2014-01-30 10:57 ` Chris Wilson
0 siblings, 0 replies; 138+ messages in thread
From: Chris Wilson @ 2014-01-30 10:57 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 30, 2014 at 10:07:42AM +0100, Daniel Vetter wrote:
> On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.volkin@intel.com wrote:
> > From: Brad Volkin <bradley.d.volkin@intel.com>
> >
> > The command parser scans batch buffers submitted via execbuffer ioctls before
> > the driver submits them to hardware. At a high level, it looks for several
> > things:
> >
> > 1) Commands which are explicitly defined as privileged or which should only be
> > used by the kernel driver. The parser generally rejects such commands, with
> > the provision that it may allow some from the drm master process.
> > 2) Commands which access registers. To support correct/enhanced userspace
> > functionality, particularly certain OpenGL extensions, the parser provides a
> > whitelist of registers which userspace may safely access (for both normal and
> > drm master processes).
> > 3) Commands which access privileged memory (i.e. GGTT, HWS page, etc). The
> > parser always rejects such commands.
> >
> > Each ring maintains tables of commands and registers which the parser uses in
> > scanning batch buffers submitted to that ring.
> >
> > The set of commands that the parser must check for is significantly smaller
> > than the number of commands supported, especially on the render ring. As such,
> > the parser tables (built up in subsequent patches) contain only those commands
> > required by the parser. This generally works because command opcode ranges have
> > standard command length encodings. So for commands that the parser does not need
> > to check, it can easily skip them. This is implementated via a per-ring length
> > decoding vfunc.
> >
> > Unfortunately, there are a number of commands that do not follow the standard
> > length encoding for their opcode range, primarily amongst the MI_* commands. To
> > handle this, the parser provides a way to define explicit "skip" entries in the
> > per-ring command tables.
> >
> > Other command table entries will map fairly directly to high level categories
> > mentioned above: rejected, master-only, register whitelist. A number of checks,
> > including the privileged memory checks, are implemented via a general bitmasking
> > mechanism.
> >
> > OTC-Tracker: AXIA-4631
> > Change-Id: I50b98c71c6655893291c78a2d1b8954577b37a30
> > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
>
>
> > +#include "i915_drv.h"
> > +
> > +#define CLIENT_MASK 0xE0000000
> > +#define SUBCLIENT_MASK 0x18000000
> > +#define MI_CLIENT 0x00000000
> > +#define RC_CLIENT 0x60000000
> > +#define BC_CLIENT 0x40000000
> > +#define MEDIA_SUBCLIENT 0x10000000
>
> I think these would fit neatly right next to all the other MI_* #defines
> in i915_reg.h. The other idea that just crossed my mind is to extract all
> the command #defines into a new i915_cmd.h (included by i915_drv.h by
> default) since i915_reg.h is already giant.
i915_cmd.h please. (i915_cs.h? i915_command_stream.h?)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-29 21:55 ` [PATCH 02/13] drm/i915: Implement command buffer parsing logic bradley.d.volkin
2014-01-29 22:28 ` Chris Wilson
2014-01-30 9:07 ` Daniel Vetter
@ 2014-02-05 15:15 ` Jani Nikula
2014-02-05 18:36 ` Volkin, Bradley D
2014-02-07 13:58 ` Jani Nikula
3 siblings, 1 reply; 138+ messages in thread
From: Jani Nikula @ 2014-02-05 15:15 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> The command parser scans batch buffers submitted via execbuffer ioctls before
> the driver submits them to hardware. At a high level, it looks for several
> things:
>
> 1) Commands which are explicitly defined as privileged or which should only be
> used by the kernel driver. The parser generally rejects such commands, with
> the provision that it may allow some from the drm master process.
> 2) Commands which access registers. To support correct/enhanced userspace
> functionality, particularly certain OpenGL extensions, the parser provides a
> whitelist of registers which userspace may safely access (for both normal and
> drm master processes).
> 3) Commands which access privileged memory (i.e. GGTT, HWS page, etc). The
> parser always rejects such commands.
>
> Each ring maintains tables of commands and registers which the parser uses in
> scanning batch buffers submitted to that ring.
>
> The set of commands that the parser must check for is significantly smaller
> than the number of commands supported, especially on the render ring. As such,
> the parser tables (built up in subsequent patches) contain only those commands
> required by the parser. This generally works because command opcode ranges have
> standard command length encodings. So for commands that the parser does not need
> to check, it can easily skip them. This is implementated via a per-ring length
> decoding vfunc.
>
> Unfortunately, there are a number of commands that do not follow the standard
> length encoding for their opcode range, primarily amongst the MI_* commands. To
> handle this, the parser provides a way to define explicit "skip" entries in the
> per-ring command tables.
>
> Other command table entries will map fairly directly to high level categories
> mentioned above: rejected, master-only, register whitelist. A number of checks,
> including the privileged memory checks, are implemented via a general bitmasking
> mechanism.
>
> OTC-Tracker: AXIA-4631
> Change-Id: I50b98c71c6655893291c78a2d1b8954577b37a30
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/i915_cmd_parser.c | 404 +++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 94 +++++++
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 17 ++
> drivers/gpu/drm/i915/i915_params.c | 5 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +
> drivers/gpu/drm/i915/intel_ringbuffer.h | 32 +++
> 7 files changed, 556 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/i915_cmd_parser.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 4850494..2da81bf 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -47,7 +47,8 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
> dvo_tfp410.o \
> dvo_sil164.o \
> dvo_ns2501.o \
> - i915_gem_dmabuf.o
> + i915_gem_dmabuf.o \
> + i915_cmd_parser.o
If you add this anywhere but last, you only need to touch one line
instead of two. It's nitpicky, but helps with things like git blame
(which would now point at you for i915_gem_dmabuf.o too ;).
>
> i915-$(CONFIG_COMPAT) += i915_ioc32.o
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> new file mode 100644
> index 0000000..7639dbc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -0,0 +1,404 @@
> +/*
> + * Copyright © 2013 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + * Brad Volkin <bradley.d.volkin@intel.com>
> + *
> + */
> +
> +#include "i915_drv.h"
> +
> +#define CLIENT_MASK 0xE0000000
> +#define SUBCLIENT_MASK 0x18000000
> +#define MI_CLIENT 0x00000000
> +#define RC_CLIENT 0x60000000
> +#define BC_CLIENT 0x40000000
> +#define MEDIA_SUBCLIENT 0x10000000
> +
> +static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
> +{
> + u32 client = cmd_header & CLIENT_MASK;
> + u32 subclient = cmd_header & SUBCLIENT_MASK;
> +
> + if (client == MI_CLIENT)
> + return 0x3F;
> + else if (client == RC_CLIENT) {
> + if (subclient == MEDIA_SUBCLIENT)
> + return 0xFFFF;
> + else
> + return 0xFF;
> + }
> +
> + DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
> + return 0;
> +}
> +
> +static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
> +{
> + u32 client = cmd_header & CLIENT_MASK;
> + u32 subclient = cmd_header & SUBCLIENT_MASK;
> +
> + if (client == MI_CLIENT)
> + return 0x3F;
> + else if (client == RC_CLIENT) {
> + if (subclient == MEDIA_SUBCLIENT)
> + return 0xFFF;
> + else
> + return 0xFF;
> + }
> +
> + DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
> + return 0;
> +}
> +
> +static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
> +{
> + u32 client = cmd_header & CLIENT_MASK;
> +
> + if (client == MI_CLIENT)
> + return 0x3F;
> + else if (client == BC_CLIENT)
> + return 0xFF;
> +
> + DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
> + return 0;
> +}
> +
> +static void validate_cmds_sorted(struct intel_ring_buffer *ring)
> +{
> + int i;
> +
> + if (!ring->cmd_tables || ring->cmd_table_count == 0)
> + return;
> +
> + for (i = 0; i < ring->cmd_table_count; i++) {
> + const struct drm_i915_cmd_table *table = &ring->cmd_tables[i];
> + u32 previous = 0;
> + int j;
> +
> + for (j = 0; j < table->count; j++) {
> + const struct drm_i915_cmd_descriptor *desc =
> + &table->table[i];
> + u32 curr = desc->cmd.value & desc->cmd.mask;
> +
> + if (curr < previous) {
> + DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X\n",
> + ring->id, i, j, curr);
> + return;
So this checks the hand-filled tables, right?
I think this should not stop at the first error, but rather scan the
whole table and DRM_ERROR all cases where curr < previous, and after the
full scan BUG_ON() if there were any errors.
> + }
> +
> + previous = curr;
> + }
> + }
> +}
> +
> +static void check_sorted(int ring_id, const u32 *reg_table, int reg_count)
> +{
> + int i;
> + u32 previous = 0;
> +
> + for (i = 0; i < reg_count; i++) {
> + u32 curr = reg_table[i];
> +
> + if (curr < previous) {
> + DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X\n",
> + ring_id, i, curr);
> + return;
Same here.
> + }
> +
> + previous = curr;
> + }
> +}
> +
> +static void validate_regs_sorted(struct intel_ring_buffer *ring)
> +{
> + if (ring->reg_table && ring->reg_count > 0)
> + check_sorted(ring->id, ring->reg_table, ring->reg_count);
> +
> + if (ring->master_reg_table && ring->master_reg_count > 0)
> + check_sorted(ring->id, ring->master_reg_table,
> + ring->master_reg_count);
Somehow I think the ifs here are redundant. check_sorted() is a no-op if
reg_count == 0, and if reg_count > 0 while reg_table == NULL, it
deserves to oops!
> +}
> +
> +void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
> +{
> + if (!IS_GEN7(ring->dev))
> + return;
> +
> + switch (ring->id) {
> + case RCS:
> + ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
> + break;
> + case VCS:
> + ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
> + break;
> + case BCS:
> + ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
> + break;
> + case VECS:
> + /* VECS can use the same length_mask function as VCS */
> + ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
> + break;
> + default:
> + DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
> + ring->id);
You'll oops later for calling NULL ring->get_cmd_length_mask(), so might
as well BUG() here.
> + }
> +
> + validate_cmds_sorted(ring);
> + validate_regs_sorted(ring);
> +}
> +
> +static const struct drm_i915_cmd_descriptor*
> +find_cmd_in_table(const struct drm_i915_cmd_table *table,
> + u32 cmd_header)
> +{
> + int i;
> +
> + for (i = 0; i < table->count; i++) {
> + const struct drm_i915_cmd_descriptor *desc = &table->table[i];
> + u32 masked_cmd = desc->cmd.mask & cmd_header;
> + u32 masked_value = desc->cmd.value & desc->cmd.mask;
> +
> + if (masked_cmd == masked_value)
> + return desc;
> + }
> +
> + return NULL;
> +}
> +
> +/*
> + * Returns a pointer to a descriptor for the command specified by cmd_header.
> + *
> + * The caller must supply space for a default descriptor via the default_desc
> + * parameter. If no descriptor for the specified command exists in the ring's
> + * command parser tables, this function fills in default_desc based on the
> + * ring's default length encoding and returns default_desc.
> + */
> +static const struct drm_i915_cmd_descriptor*
> +find_cmd(struct intel_ring_buffer *ring,
> + u32 cmd_header,
> + struct drm_i915_cmd_descriptor *default_desc)
> +{
> + u32 mask;
> + int i;
> +
> + for (i = 0; i < ring->cmd_table_count; i++) {
> + const struct drm_i915_cmd_descriptor *desc;
> +
> + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> + if (desc)
> + return desc;
> + }
> +
> + mask = ring->get_cmd_length_mask(cmd_header);
> + if (!mask)
> + return NULL;
> +
> + BUG_ON(!default_desc);
> + default_desc->flags = CMD_DESC_SKIP;
> + default_desc->length.mask = mask;
> +
> + return default_desc;
> +}
> +
> +static int valid_reg(const u32 *table, int count, u32 addr)
I like bools for boolean stuff.
> +{
> + if (table && count != 0) {
> + int i;
> +
> + for (i = 0; i < count; i++) {
> + if (table[i] == addr)
> + return 1;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static u32 *vmap_batch(struct drm_i915_gem_object *obj)
> +{
> + int i;
> + void *addr = NULL;
> + struct sg_page_iter sg_iter;
> + struct page **pages;
> +
> + pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
> + if (pages == NULL) {
> + DRM_DEBUG_DRIVER("Failed to get space for pages\n");
> + goto finish;
> + }
> +
> + i = 0;
> + for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
> + pages[i] = sg_page_iter_page(&sg_iter);
> + i++;
> + }
> +
> + addr = vmap(pages, i, 0, PAGE_KERNEL);
> + if (addr == NULL) {
> + DRM_DEBUG_DRIVER("Failed to vmap pages\n");
> + goto finish;
> + }
> +
> +finish:
> + if (pages)
> + drm_free_large(pages);
> + return (u32*)addr;
> +}
> +
> +int i915_needs_cmd_parser(struct intel_ring_buffer *ring)
bool
> +{
> + /* No command tables indicates a platform without parsing */
> + if (!ring->cmd_tables)
> + return 0;
> +
> + return i915.enable_cmd_parser;
> +}
> +
> +#define LENGTH_BIAS 2
> +
> +int i915_parse_cmds(struct intel_ring_buffer *ring,
> + struct drm_i915_gem_object *batch_obj,
> + u32 batch_start_offset,
> + bool is_master)
> +{
> + int ret = 0;
> + u32 *cmd, *batch_base, *batch_end;
> + struct drm_i915_cmd_descriptor default_desc = { 0 };
> + int needs_clflush = 0;
> +
> + ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
> + if (ret) {
> + DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
> + return ret;
> + }
> +
> + batch_base = vmap_batch(batch_obj);
> + if (!batch_base) {
> + DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
> + i915_gem_object_unpin_pages(batch_obj);
> + return -ENOMEM;
> + }
> +
> + if (needs_clflush)
> + drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
> +
> + cmd = batch_base + (batch_start_offset / sizeof(*cmd));
> + batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
> +
> + while (cmd < batch_end) {
> + const struct drm_i915_cmd_descriptor *desc;
> + u32 length;
> +
> + if (*cmd == MI_BATCH_BUFFER_END)
> + break;
> +
> + desc = find_cmd(ring, *cmd, &default_desc);
> + if (!desc) {
> + DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
> + *cmd);
> + ret = -EINVAL;
> + break;
> + }
> +
> + if (desc->flags & CMD_DESC_FIXED)
> + length = desc->length.fixed;
> + else
> + length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
> +
> + if ((batch_end - cmd) < length) {
> + DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%ld\n",
> + *cmd,
> + length,
> + batch_end - cmd);
> + ret = -EINVAL;
> + break;
> + }
> +
> + if (desc->flags & CMD_DESC_REJECT) {
> + DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
> + ret = -EINVAL;
> + break;
> + }
> +
> + if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
> + DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
> + *cmd);
> + ret = -EINVAL;
> + break;
> + }
> +
> + if (desc->flags & CMD_DESC_REGISTER) {
> + u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
> +
> + if (!valid_reg(ring->reg_table,
> + ring->reg_count, reg_addr)) {
> + if (!is_master ||
> + !valid_reg(ring->master_reg_table,
> + ring->master_reg_count,
> + reg_addr)) {
> + DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
> + reg_addr,
> + *cmd,
> + ring->id);
> + ret = -EINVAL;
> + break;
> + }
> + }
> + }
> +
> + if (desc->flags & CMD_DESC_BITMASK) {
> + int i;
> +
> + for (i = 0; i < desc->bits_count; i++) {
> + u32 dword = cmd[desc->bits[i].offset] &
> + desc->bits[i].mask;
> +
> + if (dword != desc->bits[i].expected) {
> + DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
> + *cmd,
> + desc->bits[i].mask,
> + desc->bits[i].expected,
> + dword, ring->id);
> + ret = -EINVAL;
> + break;
> + }
> + }
> +
> + if (ret)
> + break;
> + }
> +
> + cmd += length;
> + }
> +
> + if (cmd >= batch_end) {
> + DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
> + ret = -EINVAL;
> + }
> +
> + vunmap(batch_base);
> +
> + i915_gem_object_unpin_pages(batch_obj);
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bfb30df..8aed80f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1765,6 +1765,91 @@ struct drm_i915_file_private {
> atomic_t rps_wait_boost;
> };
>
> +/**
> + * A command that requires special handling by the command parser.
> + */
You have plenty of kernel-doc comments here and in other patches. They
do expect a certain format, however. Please either make them regular
comments (the easy way) or adhere to proper kernel-doc format.
> +struct drm_i915_cmd_descriptor {
> + /**
> + * Flags describing how the command parser processes the command.
> + *
> + * CMD_DESC_FIXED: The command has a fixed length if this is set,
> + * a length mask if not set
> + * CMD_DESC_SKIP: The command is allowed but does not follow the
> + * standard length encoding for the opcode range in
> + * which it falls
> + * CMD_DESC_REJECT: The command is never allowed
> + * CMD_DESC_REGISTER: The command should be checked against the
> + * register whitelist for the appropriate ring
> + * CMD_DESC_MASTER: The command is allowed if the submitting process
> + * is the DRM master
> + */
> + u32 flags;
> +#define CMD_DESC_FIXED (1<<0)
> +#define CMD_DESC_SKIP (1<<1)
> +#define CMD_DESC_REJECT (1<<2)
> +#define CMD_DESC_REGISTER (1<<3)
> +#define CMD_DESC_BITMASK (1<<4)
> +#define CMD_DESC_MASTER (1<<5)
Feels like flags should be named FLAG, not DESC. *shrug*.
> +
> + /**
> + * The command's unique identification bits and the bitmask to get them.
> + * This isn't strictly the opcode field as defined in the spec and may
> + * also include type, subtype, and/or subop fields.
> + */
> + struct {
> + u32 value;
> + u32 mask;
> + } cmd;
> +
> + /**
> + * The command's length. The command is either fixed length (i.e. does
> + * not include a length field) or has a length field mask. The flag
> + * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
> + * a length mask. All command entries in a command table must include
> + * length information.
> + */
> + union {
> + u32 fixed;
> + u32 mask;
> + } length;
> +
> + /**
> + * Describes where to find a register address in the command to check
> + * against the ring's register whitelist. Only valid if flags has the
> + * CMD_DESC_REGISTER bit set.
> + */
> + struct {
> + u32 offset;
> + u32 mask;
> + } reg;
> +
> +#define MAX_CMD_DESC_BITMASKS 3
> + /**
> + * Describes command checks where a particular dword is masked and
> + * compared against an expected value. If the command does not match
> + * the expected value, the parser rejects it. Only valid if flags has
> + * the CMD_DESC_BITMASK bit set.
> + */
> + struct {
> + u32 offset;
> + u32 mask;
> + u32 expected;
> + } bits[MAX_CMD_DESC_BITMASKS];
> + /** Number of valid entries in the bits array */
> + int bits_count;
> +};
> +
> +/**
> + * A table of commands requiring special handling by the command parser.
> + *
> + * Each ring has an array of tables. Each table consists of an array of command
> + * descriptors, which must be sorted with command opcodes in ascending order.
> + */
> +struct drm_i915_cmd_table {
> + const struct drm_i915_cmd_descriptor *table;
> + int count;
> +};
> +
> #define INTEL_INFO(dev) (to_i915(dev)->info)
>
> #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
> @@ -1923,6 +2008,7 @@ struct i915_params {
> bool prefault_disable;
> bool reset;
> int invert_brightness;
> + int enable_cmd_parser;
> };
> extern struct i915_params i915 __read_mostly;
>
> @@ -2428,6 +2514,14 @@ void i915_destroy_error_state(struct drm_device *dev);
> void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
> const char *i915_cache_level_str(int type);
>
> +/* i915_cmd_parser.c */
> +void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
> +int i915_needs_cmd_parser(struct intel_ring_buffer *ring);
> +int i915_parse_cmds(struct intel_ring_buffer *ring,
> + struct drm_i915_gem_object *batch_obj,
> + u32 batch_start_offset,
> + bool is_master);
> +
> /* i915_suspend.c */
> extern int i915_save_state(struct drm_device *dev);
> extern int i915_restore_state(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 032def9..c953445 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1180,6 +1180,23 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
> }
> batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
>
> + if (i915_needs_cmd_parser(ring)) {
> + ret = i915_parse_cmds(ring,
> + batch_obj,
> + args->batch_start_offset,
> + file->is_master);
> + if (ret)
> + goto err;
> +
> + /*
> + * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit
> + * from MI_BATCH_BUFFER_START commands issued in the
> + * dispatch_execbuffer implementations. We specifically don't
> + * want that set when the command parser is enabled.
> + */
> + flags |= I915_DISPATCH_SECURE;
> + }
> +
> /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
> * batch" bit. Hence we need to pin secure batches into the global gtt.
> * hsw should have this fixed, but bdw mucks it up again. */
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index c743057..6d3d906 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
> .prefault_disable = 0,
> .reset = true,
> .invert_brightness = 0,
> + .enable_cmd_parser = 0
Please add a comma in the end so the next addition won't have to, just
like this doesn't have to touch the previous line.
> };
>
> module_param_named(modeset, i915.modeset, int, 0400);
> @@ -153,3 +154,7 @@ MODULE_PARM_DESC(invert_brightness,
> "report PCI device ID, subsystem vendor and subsystem device ID "
> "to dri-devel@lists.freedesktop.org, if your machine needs it. "
> "It will then be included in an upcoming module version.");
> +
> +module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
> +MODULE_PARM_DESC(enable_cmd_parser,
> + "Enable command parsing (default: false)");
If it's a bool, make it a bool, or change the default text to 0.
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a0d61f8..77fc61d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1388,6 +1388,8 @@ static int intel_init_ring_buffer(struct drm_device *dev,
> if (IS_I830(ring->dev) || IS_845G(ring->dev))
> ring->effective_size -= 128;
>
> + i915_cmd_parser_init_ring(ring);
> +
> return 0;
>
> err_unmap:
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 71a73f4..cff2b35 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -162,6 +162,38 @@ struct intel_ring_buffer {
> u32 gtt_offset;
> volatile u32 *cpu_page;
> } scratch;
> +
> + /**
> + * Tables of commands the command parser needs to know about
> + * for this ring.
> + */
> + const struct drm_i915_cmd_table *cmd_tables;
> + int cmd_table_count;
> +
> + /**
> + * Table of registers allowed in commands that read/write registers.
> + */
> + const u32 *reg_table;
> + int reg_count;
> +
> + /**
> + * Table of registers allowed in commands that read/write registers, but
> + * only from the DRM master.
> + */
> + const u32 *master_reg_table;
> + int master_reg_count;
> +
> + /**
> + * Returns the bitmask for the length field of the specified command.
> + * Return 0 for an unrecognized/invalid command.
> + *
> + * If the command parser finds an entry for a command in the ring's
> + * cmd_tables, it gets the command's length based on the table entry.
> + * If not, it calls this function to determine the per-ring length field
> + * encoding for the command (i.e. certain opcode ranges use certain bits
> + * to encode the command length in the header).
> + */
> + u32 (*get_cmd_length_mask)(u32 cmd_header);
> };
Plenty of non-conforming kernel-doc comments here too.
>
> static inline bool
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-02-05 15:15 ` Jani Nikula
@ 2014-02-05 18:36 ` Volkin, Bradley D
0 siblings, 0 replies; 138+ messages in thread
From: Volkin, Bradley D @ 2014-02-05 18:36 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Feb 05, 2014 at 07:15:35AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> > From: Brad Volkin <bradley.d.volkin@intel.com>
> >
> > The command parser scans batch buffers submitted via execbuffer ioctls before
> > the driver submits them to hardware. At a high level, it looks for several
> > things:
> >
> > 1) Commands which are explicitly defined as privileged or which should only be
> > used by the kernel driver. The parser generally rejects such commands, with
> > the provision that it may allow some from the drm master process.
> > 2) Commands which access registers. To support correct/enhanced userspace
> > functionality, particularly certain OpenGL extensions, the parser provides a
> > whitelist of registers which userspace may safely access (for both normal and
> > drm master processes).
> > 3) Commands which access privileged memory (i.e. GGTT, HWS page, etc). The
> > parser always rejects such commands.
> >
> > Each ring maintains tables of commands and registers which the parser uses in
> > scanning batch buffers submitted to that ring.
> >
> > The set of commands that the parser must check for is significantly smaller
> > than the number of commands supported, especially on the render ring. As such,
> > the parser tables (built up in subsequent patches) contain only those commands
> > required by the parser. This generally works because command opcode ranges have
> > standard command length encodings. So for commands that the parser does not need
> > to check, it can easily skip them. This is implementated via a per-ring length
> > decoding vfunc.
> >
> > Unfortunately, there are a number of commands that do not follow the standard
> > length encoding for their opcode range, primarily amongst the MI_* commands. To
> > handle this, the parser provides a way to define explicit "skip" entries in the
> > per-ring command tables.
> >
> > Other command table entries will map fairly directly to high level categories
> > mentioned above: rejected, master-only, register whitelist. A number of checks,
> > including the privileged memory checks, are implemented via a general bitmasking
> > mechanism.
> >
> > OTC-Tracker: AXIA-4631
> > Change-Id: I50b98c71c6655893291c78a2d1b8954577b37a30
> > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> > ---
> > drivers/gpu/drm/i915/Makefile | 3 +-
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 404 +++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_drv.h | 94 +++++++
> > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 17 ++
> > drivers/gpu/drm/i915/i915_params.c | 5 +
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +
> > drivers/gpu/drm/i915/intel_ringbuffer.h | 32 +++
> > 7 files changed, 556 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/i915/i915_cmd_parser.c
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 4850494..2da81bf 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -47,7 +47,8 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
> > dvo_tfp410.o \
> > dvo_sil164.o \
> > dvo_ns2501.o \
> > - i915_gem_dmabuf.o
> > + i915_gem_dmabuf.o \
> > + i915_cmd_parser.o
>
> If you add this anywhere but last, you only need to touch one line
> instead of two. It's nitpicky, but helps with things like git blame
> (which would now point at you for i915_gem_dmabuf.o too ;).
Sounds good
>
> >
> > i915-$(CONFIG_COMPAT) += i915_ioc32.o
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > new file mode 100644
> > index 0000000..7639dbc
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -0,0 +1,404 @@
> > +/*
> > + * Copyright © 2013 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the next
> > + * paragraph) shall be included in all copies or substantial portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + * Authors:
> > + * Brad Volkin <bradley.d.volkin@intel.com>
> > + *
> > + */
> > +
> > +#include "i915_drv.h"
> > +
> > +#define CLIENT_MASK 0xE0000000
> > +#define SUBCLIENT_MASK 0x18000000
> > +#define MI_CLIENT 0x00000000
> > +#define RC_CLIENT 0x60000000
> > +#define BC_CLIENT 0x40000000
> > +#define MEDIA_SUBCLIENT 0x10000000
> > +
> > +static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
> > +{
> > + u32 client = cmd_header & CLIENT_MASK;
> > + u32 subclient = cmd_header & SUBCLIENT_MASK;
> > +
> > + if (client == MI_CLIENT)
> > + return 0x3F;
> > + else if (client == RC_CLIENT) {
> > + if (subclient == MEDIA_SUBCLIENT)
> > + return 0xFFFF;
> > + else
> > + return 0xFF;
> > + }
> > +
> > + DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
> > + return 0;
> > +}
> > +
> > +static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
> > +{
> > + u32 client = cmd_header & CLIENT_MASK;
> > + u32 subclient = cmd_header & SUBCLIENT_MASK;
> > +
> > + if (client == MI_CLIENT)
> > + return 0x3F;
> > + else if (client == RC_CLIENT) {
> > + if (subclient == MEDIA_SUBCLIENT)
> > + return 0xFFF;
> > + else
> > + return 0xFF;
> > + }
> > +
> > + DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
> > + return 0;
> > +}
> > +
> > +static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
> > +{
> > + u32 client = cmd_header & CLIENT_MASK;
> > +
> > + if (client == MI_CLIENT)
> > + return 0x3F;
> > + else if (client == BC_CLIENT)
> > + return 0xFF;
> > +
> > + DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
> > + return 0;
> > +}
> > +
> > +static void validate_cmds_sorted(struct intel_ring_buffer *ring)
> > +{
> > + int i;
> > +
> > + if (!ring->cmd_tables || ring->cmd_table_count == 0)
> > + return;
> > +
> > + for (i = 0; i < ring->cmd_table_count; i++) {
> > + const struct drm_i915_cmd_table *table = &ring->cmd_tables[i];
> > + u32 previous = 0;
> > + int j;
> > +
> > + for (j = 0; j < table->count; j++) {
> > + const struct drm_i915_cmd_descriptor *desc =
> > + &table->table[i];
> > + u32 curr = desc->cmd.value & desc->cmd.mask;
> > +
> > + if (curr < previous) {
> > + DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X\n",
> > + ring->id, i, j, curr);
> > + return;
>
> So this checks the hand-filled tables, right?
>
> I think this should not stop at the first error, but rather scan the
> whole table and DRM_ERROR all cases where curr < previous, and after the
> full scan BUG_ON() if there were any errors.
Will change, and below
>
> > + }
> > +
> > + previous = curr;
> > + }
> > + }
> > +}
> > +
> > +static void check_sorted(int ring_id, const u32 *reg_table, int reg_count)
> > +{
> > + int i;
> > + u32 previous = 0;
> > +
> > + for (i = 0; i < reg_count; i++) {
> > + u32 curr = reg_table[i];
> > +
> > + if (curr < previous) {
> > + DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X\n",
> > + ring_id, i, curr);
> > + return;
>
> Same here.
>
> > + }
> > +
> > + previous = curr;
> > + }
> > +}
> > +
> > +static void validate_regs_sorted(struct intel_ring_buffer *ring)
> > +{
> > + if (ring->reg_table && ring->reg_count > 0)
> > + check_sorted(ring->id, ring->reg_table, ring->reg_count);
> > +
> > + if (ring->master_reg_table && ring->master_reg_count > 0)
> > + check_sorted(ring->id, ring->master_reg_table,
> > + ring->master_reg_count);
>
> Somehow I think the ifs here are redundant. check_sorted() is a no-op if
> reg_count == 0, and if reg_count > 0 while reg_table == NULL, it
> deserves to oops!
Agreed
>
> > +}
> > +
> > +void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
> > +{
> > + if (!IS_GEN7(ring->dev))
> > + return;
> > +
> > + switch (ring->id) {
> > + case RCS:
> > + ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
> > + break;
> > + case VCS:
> > + ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
> > + break;
> > + case BCS:
> > + ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
> > + break;
> > + case VECS:
> > + /* VECS can use the same length_mask function as VCS */
> > + ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
> > + break;
> > + default:
> > + DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
> > + ring->id);
>
> You'll oops later for calling NULL ring->get_cmd_length_mask(), so might
> as well BUG() here.
Agreed
>
> > + }
> > +
> > + validate_cmds_sorted(ring);
> > + validate_regs_sorted(ring);
> > +}
> > +
> > +static const struct drm_i915_cmd_descriptor*
> > +find_cmd_in_table(const struct drm_i915_cmd_table *table,
> > + u32 cmd_header)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < table->count; i++) {
> > + const struct drm_i915_cmd_descriptor *desc = &table->table[i];
> > + u32 masked_cmd = desc->cmd.mask & cmd_header;
> > + u32 masked_value = desc->cmd.value & desc->cmd.mask;
> > +
> > + if (masked_cmd == masked_value)
> > + return desc;
> > + }
> > +
> > + return NULL;
> > +}
> > +
> > +/*
> > + * Returns a pointer to a descriptor for the command specified by cmd_header.
> > + *
> > + * The caller must supply space for a default descriptor via the default_desc
> > + * parameter. If no descriptor for the specified command exists in the ring's
> > + * command parser tables, this function fills in default_desc based on the
> > + * ring's default length encoding and returns default_desc.
> > + */
> > +static const struct drm_i915_cmd_descriptor*
> > +find_cmd(struct intel_ring_buffer *ring,
> > + u32 cmd_header,
> > + struct drm_i915_cmd_descriptor *default_desc)
> > +{
> > + u32 mask;
> > + int i;
> > +
> > + for (i = 0; i < ring->cmd_table_count; i++) {
> > + const struct drm_i915_cmd_descriptor *desc;
> > +
> > + desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
> > + if (desc)
> > + return desc;
> > + }
> > +
> > + mask = ring->get_cmd_length_mask(cmd_header);
> > + if (!mask)
> > + return NULL;
> > +
> > + BUG_ON(!default_desc);
> > + default_desc->flags = CMD_DESC_SKIP;
> > + default_desc->length.mask = mask;
> > +
> > + return default_desc;
> > +}
> > +
> > +static int valid_reg(const u32 *table, int count, u32 addr)
>
> I like bools for boolean stuff.
I'll reevaluate int vs bool throughout. I think the use is a bit inconsistent
throughout the driver at the moment, but I don't mind improving it.
>
> > +{
> > + if (table && count != 0) {
> > + int i;
> > +
> > + for (i = 0; i < count; i++) {
> > + if (table[i] == addr)
> > + return 1;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static u32 *vmap_batch(struct drm_i915_gem_object *obj)
> > +{
> > + int i;
> > + void *addr = NULL;
> > + struct sg_page_iter sg_iter;
> > + struct page **pages;
> > +
> > + pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
> > + if (pages == NULL) {
> > + DRM_DEBUG_DRIVER("Failed to get space for pages\n");
> > + goto finish;
> > + }
> > +
> > + i = 0;
> > + for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
> > + pages[i] = sg_page_iter_page(&sg_iter);
> > + i++;
> > + }
> > +
> > + addr = vmap(pages, i, 0, PAGE_KERNEL);
> > + if (addr == NULL) {
> > + DRM_DEBUG_DRIVER("Failed to vmap pages\n");
> > + goto finish;
> > + }
> > +
> > +finish:
> > + if (pages)
> > + drm_free_large(pages);
> > + return (u32*)addr;
> > +}
> > +
> > +int i915_needs_cmd_parser(struct intel_ring_buffer *ring)
>
> bool
>
> > +{
> > + /* No command tables indicates a platform without parsing */
> > + if (!ring->cmd_tables)
> > + return 0;
> > +
> > + return i915.enable_cmd_parser;
> > +}
> > +
> > +#define LENGTH_BIAS 2
> > +
> > +int i915_parse_cmds(struct intel_ring_buffer *ring,
> > + struct drm_i915_gem_object *batch_obj,
> > + u32 batch_start_offset,
> > + bool is_master)
> > +{
> > + int ret = 0;
> > + u32 *cmd, *batch_base, *batch_end;
> > + struct drm_i915_cmd_descriptor default_desc = { 0 };
> > + int needs_clflush = 0;
> > +
> > + ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
> > + if (ret) {
> > + DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
> > + return ret;
> > + }
> > +
> > + batch_base = vmap_batch(batch_obj);
> > + if (!batch_base) {
> > + DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
> > + i915_gem_object_unpin_pages(batch_obj);
> > + return -ENOMEM;
> > + }
> > +
> > + if (needs_clflush)
> > + drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
> > +
> > + cmd = batch_base + (batch_start_offset / sizeof(*cmd));
> > + batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
> > +
> > + while (cmd < batch_end) {
> > + const struct drm_i915_cmd_descriptor *desc;
> > + u32 length;
> > +
> > + if (*cmd == MI_BATCH_BUFFER_END)
> > + break;
> > +
> > + desc = find_cmd(ring, *cmd, &default_desc);
> > + if (!desc) {
> > + DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
> > + *cmd);
> > + ret = -EINVAL;
> > + break;
> > + }
> > +
> > + if (desc->flags & CMD_DESC_FIXED)
> > + length = desc->length.fixed;
> > + else
> > + length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
> > +
> > + if ((batch_end - cmd) < length) {
> > + DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%ld\n",
> > + *cmd,
> > + length,
> > + batch_end - cmd);
> > + ret = -EINVAL;
> > + break;
> > + }
> > +
> > + if (desc->flags & CMD_DESC_REJECT) {
> > + DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
> > + ret = -EINVAL;
> > + break;
> > + }
> > +
> > + if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
> > + DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
> > + *cmd);
> > + ret = -EINVAL;
> > + break;
> > + }
> > +
> > + if (desc->flags & CMD_DESC_REGISTER) {
> > + u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
> > +
> > + if (!valid_reg(ring->reg_table,
> > + ring->reg_count, reg_addr)) {
> > + if (!is_master ||
> > + !valid_reg(ring->master_reg_table,
> > + ring->master_reg_count,
> > + reg_addr)) {
> > + DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
> > + reg_addr,
> > + *cmd,
> > + ring->id);
> > + ret = -EINVAL;
> > + break;
> > + }
> > + }
> > + }
> > +
> > + if (desc->flags & CMD_DESC_BITMASK) {
> > + int i;
> > +
> > + for (i = 0; i < desc->bits_count; i++) {
> > + u32 dword = cmd[desc->bits[i].offset] &
> > + desc->bits[i].mask;
> > +
> > + if (dword != desc->bits[i].expected) {
> > + DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
> > + *cmd,
> > + desc->bits[i].mask,
> > + desc->bits[i].expected,
> > + dword, ring->id);
> > + ret = -EINVAL;
> > + break;
> > + }
> > + }
> > +
> > + if (ret)
> > + break;
> > + }
> > +
> > + cmd += length;
> > + }
> > +
> > + if (cmd >= batch_end) {
> > + DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
> > + ret = -EINVAL;
> > + }
> > +
> > + vunmap(batch_base);
> > +
> > + i915_gem_object_unpin_pages(batch_obj);
> > +
> > + return ret;
> > +}
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index bfb30df..8aed80f 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1765,6 +1765,91 @@ struct drm_i915_file_private {
> > atomic_t rps_wait_boost;
> > };
> >
> > +/**
> > + * A command that requires special handling by the command parser.
> > + */
>
> You have plenty of kernel-doc comments here and in other patches. They
> do expect a certain format, however. Please either make them regular
> comments (the easy way) or adhere to proper kernel-doc format.
Again, current use is inconsistent in the driver, but I'll reevaluate throughout.
>
> > +struct drm_i915_cmd_descriptor {
> > + /**
> > + * Flags describing how the command parser processes the command.
> > + *
> > + * CMD_DESC_FIXED: The command has a fixed length if this is set,
> > + * a length mask if not set
> > + * CMD_DESC_SKIP: The command is allowed but does not follow the
> > + * standard length encoding for the opcode range in
> > + * which it falls
> > + * CMD_DESC_REJECT: The command is never allowed
> > + * CMD_DESC_REGISTER: The command should be checked against the
> > + * register whitelist for the appropriate ring
> > + * CMD_DESC_MASTER: The command is allowed if the submitting process
> > + * is the DRM master
> > + */
> > + u32 flags;
> > +#define CMD_DESC_FIXED (1<<0)
> > +#define CMD_DESC_SKIP (1<<1)
> > +#define CMD_DESC_REJECT (1<<2)
> > +#define CMD_DESC_REGISTER (1<<3)
> > +#define CMD_DESC_BITMASK (1<<4)
> > +#define CMD_DESC_MASTER (1<<5)
>
> Feels like flags should be named FLAG, not DESC. *shrug*.
>
> > +
> > + /**
> > + * The command's unique identification bits and the bitmask to get them.
> > + * This isn't strictly the opcode field as defined in the spec and may
> > + * also include type, subtype, and/or subop fields.
> > + */
> > + struct {
> > + u32 value;
> > + u32 mask;
> > + } cmd;
> > +
> > + /**
> > + * The command's length. The command is either fixed length (i.e. does
> > + * not include a length field) or has a length field mask. The flag
> > + * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
> > + * a length mask. All command entries in a command table must include
> > + * length information.
> > + */
> > + union {
> > + u32 fixed;
> > + u32 mask;
> > + } length;
> > +
> > + /**
> > + * Describes where to find a register address in the command to check
> > + * against the ring's register whitelist. Only valid if flags has the
> > + * CMD_DESC_REGISTER bit set.
> > + */
> > + struct {
> > + u32 offset;
> > + u32 mask;
> > + } reg;
> > +
> > +#define MAX_CMD_DESC_BITMASKS 3
> > + /**
> > + * Describes command checks where a particular dword is masked and
> > + * compared against an expected value. If the command does not match
> > + * the expected value, the parser rejects it. Only valid if flags has
> > + * the CMD_DESC_BITMASK bit set.
> > + */
> > + struct {
> > + u32 offset;
> > + u32 mask;
> > + u32 expected;
> > + } bits[MAX_CMD_DESC_BITMASKS];
> > + /** Number of valid entries in the bits array */
> > + int bits_count;
> > +};
> > +
> > +/**
> > + * A table of commands requiring special handling by the command parser.
> > + *
> > + * Each ring has an array of tables. Each table consists of an array of command
> > + * descriptors, which must be sorted with command opcodes in ascending order.
> > + */
> > +struct drm_i915_cmd_table {
> > + const struct drm_i915_cmd_descriptor *table;
> > + int count;
> > +};
> > +
> > #define INTEL_INFO(dev) (to_i915(dev)->info)
> >
> > #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
> > @@ -1923,6 +2008,7 @@ struct i915_params {
> > bool prefault_disable;
> > bool reset;
> > int invert_brightness;
> > + int enable_cmd_parser;
> > };
> > extern struct i915_params i915 __read_mostly;
> >
> > @@ -2428,6 +2514,14 @@ void i915_destroy_error_state(struct drm_device *dev);
> > void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
> > const char *i915_cache_level_str(int type);
> >
> > +/* i915_cmd_parser.c */
> > +void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
> > +int i915_needs_cmd_parser(struct intel_ring_buffer *ring);
> > +int i915_parse_cmds(struct intel_ring_buffer *ring,
> > + struct drm_i915_gem_object *batch_obj,
> > + u32 batch_start_offset,
> > + bool is_master);
> > +
> > /* i915_suspend.c */
> > extern int i915_save_state(struct drm_device *dev);
> > extern int i915_restore_state(struct drm_device *dev);
> > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > index 032def9..c953445 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > @@ -1180,6 +1180,23 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
> > }
> > batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
> >
> > + if (i915_needs_cmd_parser(ring)) {
> > + ret = i915_parse_cmds(ring,
> > + batch_obj,
> > + args->batch_start_offset,
> > + file->is_master);
> > + if (ret)
> > + goto err;
> > +
> > + /*
> > + * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit
> > + * from MI_BATCH_BUFFER_START commands issued in the
> > + * dispatch_execbuffer implementations. We specifically don't
> > + * want that set when the command parser is enabled.
> > + */
> > + flags |= I915_DISPATCH_SECURE;
> > + }
> > +
> > /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
> > * batch" bit. Hence we need to pin secure batches into the global gtt.
> > * hsw should have this fixed, but bdw mucks it up again. */
> > diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> > index c743057..6d3d906 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
> > .prefault_disable = 0,
> > .reset = true,
> > .invert_brightness = 0,
> > + .enable_cmd_parser = 0
>
> Please add a comma in the end so the next addition won't have to, just
> like this doesn't have to touch the previous line.
Will do throughout
>
> > };
> >
> > module_param_named(modeset, i915.modeset, int, 0400);
> > @@ -153,3 +154,7 @@ MODULE_PARM_DESC(invert_brightness,
> > "report PCI device ID, subsystem vendor and subsystem device ID "
> > "to dri-devel@lists.freedesktop.org, if your machine needs it. "
> > "It will then be included in an upcoming module version.");
> > +
> > +module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
> > +MODULE_PARM_DESC(enable_cmd_parser,
> > + "Enable command parsing (default: false)");
>
> If it's a bool, make it a bool, or change the default text to 0.
I'll change it to 0 for now. We might want to do the -1/0/1 style thing at some
point, though I don't necessarily have a good case for it right now.
- Brad
>
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index a0d61f8..77fc61d 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -1388,6 +1388,8 @@ static int intel_init_ring_buffer(struct drm_device *dev,
> > if (IS_I830(ring->dev) || IS_845G(ring->dev))
> > ring->effective_size -= 128;
> >
> > + i915_cmd_parser_init_ring(ring);
> > +
> > return 0;
> >
> > err_unmap:
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index 71a73f4..cff2b35 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -162,6 +162,38 @@ struct intel_ring_buffer {
> > u32 gtt_offset;
> > volatile u32 *cpu_page;
> > } scratch;
> > +
> > + /**
> > + * Tables of commands the command parser needs to know about
> > + * for this ring.
> > + */
> > + const struct drm_i915_cmd_table *cmd_tables;
> > + int cmd_table_count;
> > +
> > + /**
> > + * Table of registers allowed in commands that read/write registers.
> > + */
> > + const u32 *reg_table;
> > + int reg_count;
> > +
> > + /**
> > + * Table of registers allowed in commands that read/write registers, but
> > + * only from the DRM master.
> > + */
> > + const u32 *master_reg_table;
> > + int master_reg_count;
> > +
> > + /**
> > + * Returns the bitmask for the length field of the specified command.
> > + * Return 0 for an unrecognized/invalid command.
> > + *
> > + * If the command parser finds an entry for a command in the ring's
> > + * cmd_tables, it gets the command's length based on the table entry.
> > + * If not, it calls this function to determine the per-ring length field
> > + * encoding for the command (i.e. certain opcode ranges use certain bits
> > + * to encode the command length in the header).
> > + */
> > + u32 (*get_cmd_length_mask)(u32 cmd_header);
> > };
>
> Plenty of non-conforming kernel-doc comments here too.
>
> >
> > static inline bool
> > --
> > 1.8.5.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
>
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-01-29 21:55 ` [PATCH 02/13] drm/i915: Implement command buffer parsing logic bradley.d.volkin
` (2 preceding siblings ...)
2014-02-05 15:15 ` Jani Nikula
@ 2014-02-07 13:58 ` Jani Nikula
2014-02-07 14:45 ` Daniel Vetter
3 siblings, 1 reply; 138+ messages in thread
From: Jani Nikula @ 2014-02-07 13:58 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> +static int valid_reg(const u32 *table, int count, u32 addr)
> +{
> + if (table && count != 0) {
> + int i;
> +
> + for (i = 0; i < count; i++) {
> + if (table[i] == addr)
> + return 1;
> + }
> + }
You go to great lengths to validate the register tables are sorted, but
in the end you don't take advantage of this fact by bailing out early if
the lookup goes past the addr.
Is this optimization the main reason for having the tables sorted, or
are there other reasons too (I couldn't find any)?
I'm beginning to wonder if this is a premature optimization that adds
extra code. For master restricted registers you will always scan the
regular reg table completely first. Perhaps a better option would be to
have all registers in the same table, with a separate master flag,
ordered by how frequently they are expected to be used. We do want to
optimize for the happy day scenario. But maybe it's too early to tell.
I'm inclined to ripping out the sort requirement and check, if the sole
purpose is optimization, for simplicity's sake.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-02-07 13:58 ` Jani Nikula
@ 2014-02-07 14:45 ` Daniel Vetter
2014-02-11 18:12 ` Volkin, Bradley D
0 siblings, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-02-07 14:45 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Fri, Feb 07, 2014 at 03:58:46PM +0200, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> > +static int valid_reg(const u32 *table, int count, u32 addr)
> > +{
> > + if (table && count != 0) {
> > + int i;
> > +
> > + for (i = 0; i < count; i++) {
> > + if (table[i] == addr)
> > + return 1;
> > + }
> > + }
>
> You go to great lengths to validate the register tables are sorted, but
> in the end you don't take advantage of this fact by bailing out early if
> the lookup goes past the addr.
>
> Is this optimization the main reason for having the tables sorted, or
> are there other reasons too (I couldn't find any)?
>
> I'm beginning to wonder if this is a premature optimization that adds
> extra code. For master restricted registers you will always scan the
> regular reg table completely first. Perhaps a better option would be to
> have all registers in the same table, with a separate master flag,
> ordered by how frequently they are expected to be used. We do want to
> optimize for the happy day scenario. But maybe it's too early to tell.
>
> I'm inclined to ripping out the sort requirement and check, if the sole
> purpose is optimization, for simplicity's sake.
tbh I don't mind the sorting requirement, and iirc Brad has patches
already for binary search. Once we start to rely on the sorting we can
easily add a little functions which checks for that at ring
initialization, so I also don't see any concerns wrt code fragility.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-02-07 14:45 ` Daniel Vetter
@ 2014-02-11 18:12 ` Volkin, Bradley D
2014-02-11 18:21 ` Jani Nikula
0 siblings, 1 reply; 138+ messages in thread
From: Volkin, Bradley D @ 2014-02-11 18:12 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Fri, Feb 07, 2014 at 06:45:48AM -0800, Daniel Vetter wrote:
> On Fri, Feb 07, 2014 at 03:58:46PM +0200, Jani Nikula wrote:
> > On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> > > +static int valid_reg(const u32 *table, int count, u32 addr)
> > > +{
> > > + if (table && count != 0) {
> > > + int i;
> > > +
> > > + for (i = 0; i < count; i++) {
> > > + if (table[i] == addr)
> > > + return 1;
> > > + }
> > > + }
> >
> > You go to great lengths to validate the register tables are sorted, but
> > in the end you don't take advantage of this fact by bailing out early if
> > the lookup goes past the addr.
> >
> > Is this optimization the main reason for having the tables sorted, or
> > are there other reasons too (I couldn't find any)?
> >
> > I'm beginning to wonder if this is a premature optimization that adds
> > extra code. For master restricted registers you will always scan the
> > regular reg table completely first. Perhaps a better option would be to
> > have all registers in the same table, with a separate master flag,
> > ordered by how frequently they are expected to be used. We do want to
> > optimize for the happy day scenario. But maybe it's too early to tell.
> >
> > I'm inclined to ripping out the sort requirement and check, if the sole
> > purpose is optimization, for simplicity's sake.
>
> tbh I don't mind the sorting requirement, and iirc Brad has patches
> already for binary search. Once we start to rely on the sorting we can
> easily add a little functions which checks for that at ring
> initialization, so I also don't see any concerns wrt code fragility.
Sorry for the delayed response. The background here is that I originally
just had the tables sorted with a comment to say as much. The idea was that
if the linear search became an issue, switching algorithms would be easier.
Chris suggested just moving to bsearch and checking that the tables are sorted
as part of the v1 series review. I implemented bsearch and found that the perf
change was the same to slightly worse. So I added the sorting check and kept
the linear search until we have better data.
Thanks,
Brad
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 02/13] drm/i915: Implement command buffer parsing logic
2014-02-11 18:12 ` Volkin, Bradley D
@ 2014-02-11 18:21 ` Jani Nikula
0 siblings, 0 replies; 138+ messages in thread
From: Jani Nikula @ 2014-02-11 18:21 UTC (permalink / raw)
To: Volkin, Bradley D, Daniel Vetter; +Cc: intel-gfx
On Tue, 11 Feb 2014, "Volkin, Bradley D" <bradley.d.volkin@intel.com> wrote:
> On Fri, Feb 07, 2014 at 06:45:48AM -0800, Daniel Vetter wrote:
>> On Fri, Feb 07, 2014 at 03:58:46PM +0200, Jani Nikula wrote:
>> > On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
>> > > +static int valid_reg(const u32 *table, int count, u32 addr)
>> > > +{
>> > > + if (table && count != 0) {
>> > > + int i;
>> > > +
>> > > + for (i = 0; i < count; i++) {
>> > > + if (table[i] == addr)
>> > > + return 1;
>> > > + }
>> > > + }
>> >
>> > You go to great lengths to validate the register tables are sorted, but
>> > in the end you don't take advantage of this fact by bailing out early if
>> > the lookup goes past the addr.
>> >
>> > Is this optimization the main reason for having the tables sorted, or
>> > are there other reasons too (I couldn't find any)?
>> >
>> > I'm beginning to wonder if this is a premature optimization that adds
>> > extra code. For master restricted registers you will always scan the
>> > regular reg table completely first. Perhaps a better option would be to
>> > have all registers in the same table, with a separate master flag,
>> > ordered by how frequently they are expected to be used. We do want to
>> > optimize for the happy day scenario. But maybe it's too early to tell.
>> >
>> > I'm inclined to ripping out the sort requirement and check, if the sole
>> > purpose is optimization, for simplicity's sake.
>>
>> tbh I don't mind the sorting requirement, and iirc Brad has patches
>> already for binary search. Once we start to rely on the sorting we can
>> easily add a little functions which checks for that at ring
>> initialization, so I also don't see any concerns wrt code fragility.
>
> Sorry for the delayed response. The background here is that I originally
> just had the tables sorted with a comment to say as much. The idea was that
> if the linear search became an issue, switching algorithms would be easier.
> Chris suggested just moving to bsearch and checking that the tables are sorted
> as part of the v1 series review. I implemented bsearch and found that the perf
> change was the same to slightly worse. So I added the sorting check and kept
> the linear search until we have better data.
Ok. For the linear search I think you could add the check if you've
iterated past the register and bail out early, and gather the data with
that.
BR,
Jani.
>
> Thanks,
> Brad
>
>> -Daniel
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 03/13] drm/i915: Initial command parser table definitions
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
2014-01-29 21:55 ` [PATCH 01/13] drm/i915: Refactor shmem pread setup bradley.d.volkin
2014-01-29 21:55 ` [PATCH 02/13] drm/i915: Implement command buffer parsing logic bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-02-05 14:22 ` Jani Nikula
2014-01-29 21:55 ` [PATCH 04/13] drm/i915: Reject privileged commands bradley.d.volkin
` (11 subsequent siblings)
14 siblings, 1 reply; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
Add command tables defining irregular length commands for each ring.
This requires a few new command opcode definitions.
OTC-Tracker: AXIA-4631
Change-Id: I064bceb457e15f46928058352afe76d918c58ef5
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 157 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 46 ++++++++++
2 files changed, 203 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 7639dbc..2e27bad 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -27,6 +27,148 @@
#include "i915_drv.h"
+#define STD_MI_OPCODE_MASK 0xFF800000
+#define STD_3D_OPCODE_MASK 0xFFFF0000
+#define STD_2D_OPCODE_MASK 0xFFC00000
+#define STD_MFX_OPCODE_MASK 0xFFFF0000
+
+#define CMD(op, opm, f, lm, fl, ...) \
+ { \
+ .flags = (fl) | (f), \
+ .cmd = { (op), (opm) }, \
+ .length = { (lm) }, \
+ __VA_ARGS__ \
+ }
+
+/* Convenience macros to compress the tables */
+#define SMI STD_MI_OPCODE_MASK
+#define S3D STD_3D_OPCODE_MASK
+#define S2D STD_2D_OPCODE_MASK
+#define SMFX STD_MFX_OPCODE_MASK
+#define F CMD_DESC_FIXED
+#define S CMD_DESC_SKIP
+#define R CMD_DESC_REJECT
+#define W CMD_DESC_REGISTER
+#define B CMD_DESC_BITMASK
+#define M CMD_DESC_MASTER
+
+/* Command Mask Fixed Len Action
+ ---------------------------------------------------------- */
+static const struct drm_i915_cmd_descriptor common_cmds[] = {
+ CMD( MI_NOOP, SMI, F, 1, S ),
+ CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
+ CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),
+ CMD( MI_ARB_CHECK, SMI, F, 1, S ),
+ CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
+ CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
+ CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, S ),
+ CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, S ),
+ CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, S ),
+ CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, S ),
+ CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, S ),
+ CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
+};
+
+static const struct drm_i915_cmd_descriptor render_cmds[] = {
+ CMD( MI_FLUSH, SMI, F, 1, S ),
+ CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
+ CMD( MI_PREDICATE, SMI, F, 1, S ),
+ CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
+ CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ),
+ CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, S ),
+ CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
+ CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, S ),
+ CMD( MI_CLFLUSH, SMI, !F, 0x3FF, S ),
+ CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
+ CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
+ CMD( PIPELINE_SELECT, S3D, F, 1, S ),
+ CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
+ CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
+ CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
+};
+
+static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
+ CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
+ CMD( MI_RS_CONTROL, SMI, F, 1, S ),
+ CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
+ CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
+ CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, S ),
+ CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
+ CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
+ CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
+ CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
+ CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
+
+ CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
+ CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
+ CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
+ CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
+ CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
+};
+
+static const struct drm_i915_cmd_descriptor video_cmds[] = {
+ CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
+ CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
+ CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
+ /*
+ * MFX_WAIT doesn't fit the way we handle length for most commands.
+ * It has a length field but it uses a non-standard length bias.
+ * It is always 1 dword though, so just treat it as fixed length.
+ */
+ CMD( MFX_WAIT, SMFX, F, 1, S ),
+};
+
+static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
+ CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
+ CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
+ CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
+};
+
+static const struct drm_i915_cmd_descriptor blt_cmds[] = {
+ CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ),
+ CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
+ CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
+ CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
+};
+
+#undef CMD
+#undef SMI
+#undef S3D
+#undef S2D
+#undef SMFX
+#undef F
+#undef S
+#undef R
+#undef W
+#undef B
+#undef M
+
+static const struct drm_i915_cmd_table gen7_render_cmds[] = {
+ { common_cmds, ARRAY_SIZE(common_cmds) },
+ { render_cmds, ARRAY_SIZE(render_cmds) },
+};
+
+static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
+ { common_cmds, ARRAY_SIZE(common_cmds) },
+ { render_cmds, ARRAY_SIZE(render_cmds) },
+ { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
+};
+
+static const struct drm_i915_cmd_table gen7_video_cmds[] = {
+ { common_cmds, ARRAY_SIZE(common_cmds) },
+ { video_cmds, ARRAY_SIZE(video_cmds) },
+};
+
+static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
+ { common_cmds, ARRAY_SIZE(common_cmds) },
+ { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
+};
+
+static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
+ { common_cmds, ARRAY_SIZE(common_cmds) },
+ { blt_cmds, ARRAY_SIZE(blt_cmds) },
+};
+
#define CLIENT_MASK 0xE0000000
#define SUBCLIENT_MASK 0x18000000
#define MI_CLIENT 0x00000000
@@ -146,15 +288,30 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
switch (ring->id) {
case RCS:
+ if (IS_HASWELL(ring->dev)) {
+ ring->cmd_tables = hsw_render_ring_cmds;
+ ring->cmd_table_count =
+ ARRAY_SIZE(hsw_render_ring_cmds);
+ } else {
+ ring->cmd_tables = gen7_render_cmds;
+ ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
+ }
+
ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
break;
case VCS:
+ ring->cmd_tables = gen7_video_cmds;
+ ring->cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
break;
case BCS:
+ ring->cmd_tables = gen7_blt_cmds;
+ ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
break;
case VECS:
+ ring->cmd_tables = hsw_vebox_cmds;
+ ring->cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
/* VECS can use the same length_mask function as VCS */
ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbbaf26..13ed6ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -336,6 +336,52 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+/*
+ * Commands used only by the command parser
+ */
+#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
+#define MI_ARB_CHECK MI_INSTR(0x05, 0)
+#define MI_RS_CONTROL MI_INSTR(0x06, 0)
+#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
+#define MI_PREDICATE MI_INSTR(0x0C, 0)
+#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
+#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
+#define MI_URB_CLEAR MI_INSTR(0x19, 0)
+#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
+#define MI_CLFLUSH MI_INSTR(0x27, 0)
+#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
+#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
+#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
+#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
+#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
+#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
+
+#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
+#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
+#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
+#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
+#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
+#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
+#define GFX_OP_3DSTATE_SO_DECL_LIST \
+ ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
+
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
+#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
+ ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
+
+#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
+
+#define COLOR_BLT ((0x2<<29)|(0x40<<22))
+#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
/*
* Reset registers
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 03/13] drm/i915: Initial command parser table definitions
2014-01-29 21:55 ` [PATCH 03/13] drm/i915: Initial command parser table definitions bradley.d.volkin
@ 2014-02-05 14:22 ` Jani Nikula
0 siblings, 0 replies; 138+ messages in thread
From: Jani Nikula @ 2014-02-05 14:22 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
N.B. I'll likely make multiple passes on the patches while reviewing,
for example I did not check any of the #define values here.
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> Add command tables defining irregular length commands for each ring.
> This requires a few new command opcode definitions.
>
> OTC-Tracker: AXIA-4631
> Change-Id: I064bceb457e15f46928058352afe76d918c58ef5
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 157 +++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 46 ++++++++++
> 2 files changed, 203 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 7639dbc..2e27bad 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -27,6 +27,148 @@
>
> #include "i915_drv.h"
>
> +#define STD_MI_OPCODE_MASK 0xFF800000
> +#define STD_3D_OPCODE_MASK 0xFFFF0000
> +#define STD_2D_OPCODE_MASK 0xFFC00000
> +#define STD_MFX_OPCODE_MASK 0xFFFF0000
> +
> +#define CMD(op, opm, f, lm, fl, ...) \
> + { \
> + .flags = (fl) | (f), \
Sparse gives me
drivers/gpu/drm/i915/i915_cmd_parser.c:64:9: warning: dubious: x | !y
for the !F cases (bitwise OR with a logical NOT). I can see it's not a
bug here, but we want to keep those warnings down. Maybe just s/!F/0/ in
the tables? Or make the f argument to CMD a boolean, and make that
.flags = (fl) | (f ? CMD_DESC_FIXED : 0),
> + .cmd = { (op), (opm) }, \
> + .length = { (lm) }, \
> + __VA_ARGS__ \
> + }
> +
> +/* Convenience macros to compress the tables */
> +#define SMI STD_MI_OPCODE_MASK
> +#define S3D STD_3D_OPCODE_MASK
> +#define S2D STD_2D_OPCODE_MASK
> +#define SMFX STD_MFX_OPCODE_MASK
> +#define F CMD_DESC_FIXED
> +#define S CMD_DESC_SKIP
> +#define R CMD_DESC_REJECT
> +#define W CMD_DESC_REGISTER
> +#define B CMD_DESC_BITMASK
> +#define M CMD_DESC_MASTER
> +
> +/* Command Mask Fixed Len Action
> + ---------------------------------------------------------- */
> +static const struct drm_i915_cmd_descriptor common_cmds[] = {
> + CMD( MI_NOOP, SMI, F, 1, S ),
> + CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
> + CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),
> + CMD( MI_ARB_CHECK, SMI, F, 1, S ),
> + CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
> + CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
> + CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, S ),
> + CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, S ),
> + CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, S ),
> + CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, S ),
> + CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, S ),
> + CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
> +};
> +
> +static const struct drm_i915_cmd_descriptor render_cmds[] = {
> + CMD( MI_FLUSH, SMI, F, 1, S ),
> + CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
> + CMD( MI_PREDICATE, SMI, F, 1, S ),
> + CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
> + CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ),
> + CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, S ),
> + CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
> + CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, S ),
> + CMD( MI_CLFLUSH, SMI, !F, 0x3FF, S ),
> + CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> + CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
> + CMD( PIPELINE_SELECT, S3D, F, 1, S ),
> + CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
> + CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
> + CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
> +};
> +
> +static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
> + CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
> + CMD( MI_RS_CONTROL, SMI, F, 1, S ),
> + CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
> + CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
> + CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, S ),
> + CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
> + CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
> + CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
> + CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
> + CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
> +
> + CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
> + CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
> + CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
> + CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
> + CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
> +};
> +
> +static const struct drm_i915_cmd_descriptor video_cmds[] = {
> + CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
> + CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
> + CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> + /*
> + * MFX_WAIT doesn't fit the way we handle length for most commands.
> + * It has a length field but it uses a non-standard length bias.
> + * It is always 1 dword though, so just treat it as fixed length.
> + */
> + CMD( MFX_WAIT, SMFX, F, 1, S ),
> +};
> +
> +static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
> + CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
> + CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
> + CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> +};
> +
> +static const struct drm_i915_cmd_descriptor blt_cmds[] = {
> + CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ),
> + CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
> + CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
> + CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
> +};
> +
> +#undef CMD
> +#undef SMI
> +#undef S3D
> +#undef S2D
> +#undef SMFX
> +#undef F
> +#undef S
> +#undef R
> +#undef W
> +#undef B
> +#undef M
> +
> +static const struct drm_i915_cmd_table gen7_render_cmds[] = {
> + { common_cmds, ARRAY_SIZE(common_cmds) },
> + { render_cmds, ARRAY_SIZE(render_cmds) },
> +};
> +
> +static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
> + { common_cmds, ARRAY_SIZE(common_cmds) },
> + { render_cmds, ARRAY_SIZE(render_cmds) },
> + { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
> +};
> +
> +static const struct drm_i915_cmd_table gen7_video_cmds[] = {
> + { common_cmds, ARRAY_SIZE(common_cmds) },
> + { video_cmds, ARRAY_SIZE(video_cmds) },
> +};
> +
> +static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
> + { common_cmds, ARRAY_SIZE(common_cmds) },
> + { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
> +};
> +
> +static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
> + { common_cmds, ARRAY_SIZE(common_cmds) },
> + { blt_cmds, ARRAY_SIZE(blt_cmds) },
> +};
A thought, if you added an end-of-array cell to all of these tables, I
think a lot of the initialization would be neater. If that seems like
too much trouble for too little gain, feel free to file this in the
bikeshedding bin.
> +
> #define CLIENT_MASK 0xE0000000
> #define SUBCLIENT_MASK 0x18000000
> #define MI_CLIENT 0x00000000
> @@ -146,15 +288,30 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
>
> switch (ring->id) {
> case RCS:
> + if (IS_HASWELL(ring->dev)) {
> + ring->cmd_tables = hsw_render_ring_cmds;
> + ring->cmd_table_count =
> + ARRAY_SIZE(hsw_render_ring_cmds);
> + } else {
> + ring->cmd_tables = gen7_render_cmds;
> + ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
> + }
> +
> ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
> break;
> case VCS:
> + ring->cmd_tables = gen7_video_cmds;
> + ring->cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
> ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
> break;
> case BCS:
> + ring->cmd_tables = gen7_blt_cmds;
> + ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
> ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
> break;
> case VECS:
> + ring->cmd_tables = hsw_vebox_cmds;
> + ring->cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
> /* VECS can use the same length_mask function as VCS */
> ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cbbaf26..13ed6ed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -336,6 +336,52 @@
> #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
> #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
>
> +/*
> + * Commands used only by the command parser
> + */
> +#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
> +#define MI_ARB_CHECK MI_INSTR(0x05, 0)
> +#define MI_RS_CONTROL MI_INSTR(0x06, 0)
> +#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
> +#define MI_PREDICATE MI_INSTR(0x0C, 0)
> +#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
> +#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
> +#define MI_URB_CLEAR MI_INSTR(0x19, 0)
> +#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
> +#define MI_CLFLUSH MI_INSTR(0x27, 0)
> +#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
> +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
> +#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
> +#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
> +#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
> +#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
> +
> +#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
> +#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
> +#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
> +#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
> +#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
> + ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
> +#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
> + ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
> +#define GFX_OP_3DSTATE_SO_DECL_LIST \
> + ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
> +
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
> + ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
> + ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
> + ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
> + ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
> +#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
> + ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
> +
> +#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
> +
> +#define COLOR_BLT ((0x2<<29)|(0x40<<22))
> +#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
>
> /*
> * Reset registers
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 04/13] drm/i915: Reject privileged commands
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (2 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 03/13] drm/i915: Initial command parser table definitions bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-02-05 15:22 ` Jani Nikula
2014-01-29 21:55 ` [PATCH 05/13] drm/i915: Allow some privileged commands from master bradley.d.volkin
` (10 subsequent siblings)
14 siblings, 1 reply; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
The spec defines most of these commands as privileged. A few others,
like the semaphore mbox command and some display commands, are also
reserved for the driver's use. Subsequent patches relax some of
these restrictions.
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 54 ++++++++++++++++++++++++----------
drivers/gpu/drm/i915/i915_reg.h | 31 +++++++++----------
2 files changed, 54 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 2e27bad..cc2f68c 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -57,27 +57,27 @@
static const struct drm_i915_cmd_descriptor common_cmds[] = {
CMD( MI_NOOP, SMI, F, 1, S ),
CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
- CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),
+ CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),
CMD( MI_ARB_CHECK, SMI, F, 1, S ),
CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
- CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, S ),
- CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, S ),
- CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, S ),
- CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, S ),
- CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, S ),
+ CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
+ CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
+ CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, R ),
+ CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, R ),
+ CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, R ),
CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
};
static const struct drm_i915_cmd_descriptor render_cmds[] = {
CMD( MI_FLUSH, SMI, F, 1, S ),
- CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
+ CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
CMD( MI_PREDICATE, SMI, F, 1, S ),
CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
- CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ),
- CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, S ),
+ CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
+ CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
- CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, S ),
+ CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
CMD( MI_CLFLUSH, SMI, !F, 0x3FF, S ),
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
@@ -92,7 +92,9 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
CMD( MI_RS_CONTROL, SMI, F, 1, S ),
CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
- CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, S ),
+ CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
+ CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
+ CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ),
CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
@@ -107,8 +109,9 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
};
static const struct drm_i915_cmd_descriptor video_cmds[] = {
- CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
+ CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
+ CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
/*
* MFX_WAIT doesn't fit the way we handle length for most commands.
@@ -119,18 +122,25 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = {
};
static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
- CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
+ CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
+ CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
};
static const struct drm_i915_cmd_descriptor blt_cmds[] = {
- CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ),
+ CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
+ CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
};
+static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
+ CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
+ CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
+};
+
#undef CMD
#undef SMI
#undef S3D
@@ -169,6 +179,12 @@ static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
{ blt_cmds, ARRAY_SIZE(blt_cmds) },
};
+static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
+ { common_cmds, ARRAY_SIZE(common_cmds) },
+ { blt_cmds, ARRAY_SIZE(blt_cmds) },
+ { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
+};
+
#define CLIENT_MASK 0xE0000000
#define SUBCLIENT_MASK 0x18000000
#define MI_CLIENT 0x00000000
@@ -305,8 +321,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
break;
case BCS:
- ring->cmd_tables = gen7_blt_cmds;
- ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
+ if (IS_HASWELL(ring->dev)) {
+ ring->cmd_tables = hsw_blt_ring_cmds;
+ ring->cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
+ } else {
+ ring->cmd_tables = gen7_blt_cmds;
+ ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
+ }
+
ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
break;
case VECS:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 13ed6ed..2b7c26e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -339,21 +339,22 @@
/*
* Commands used only by the command parser
*/
-#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
-#define MI_ARB_CHECK MI_INSTR(0x05, 0)
-#define MI_RS_CONTROL MI_INSTR(0x06, 0)
-#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
-#define MI_PREDICATE MI_INSTR(0x0C, 0)
-#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
-#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
-#define MI_URB_CLEAR MI_INSTR(0x19, 0)
-#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
-#define MI_CLFLUSH MI_INSTR(0x27, 0)
-#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
-#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
-#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
-#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
+#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
+#define MI_ARB_CHECK MI_INSTR(0x05, 0)
+#define MI_RS_CONTROL MI_INSTR(0x06, 0)
+#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
+#define MI_PREDICATE MI_INSTR(0x0C, 0)
+#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
+#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
+#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
+#define MI_URB_CLEAR MI_INSTR(0x19, 0)
+#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
+#define MI_CLFLUSH MI_INSTR(0x27, 0)
+#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
+#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
+#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
+#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
+#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 04/13] drm/i915: Reject privileged commands
2014-01-29 21:55 ` [PATCH 04/13] drm/i915: Reject privileged commands bradley.d.volkin
@ 2014-02-05 15:22 ` Jani Nikula
2014-02-05 18:42 ` Volkin, Bradley D
0 siblings, 1 reply; 138+ messages in thread
From: Jani Nikula @ 2014-02-05 15:22 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> The spec defines most of these commands as privileged. A few others,
> like the semaphore mbox command and some display commands, are also
> reserved for the driver's use. Subsequent patches relax some of
> these restrictions.
>
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 54 ++++++++++++++++++++++++----------
> drivers/gpu/drm/i915/i915_reg.h | 31 +++++++++----------
> 2 files changed, 54 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 2e27bad..cc2f68c 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -57,27 +57,27 @@
> static const struct drm_i915_cmd_descriptor common_cmds[] = {
> CMD( MI_NOOP, SMI, F, 1, S ),
> CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
> - CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),
> + CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),
> CMD( MI_ARB_CHECK, SMI, F, 1, S ),
> CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
> CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
> - CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, S ),
> - CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, S ),
> - CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, S ),
> - CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, S ),
> - CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, S ),
> + CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
> + CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
> + CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, R ),
> + CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, R ),
> + CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, R ),
> CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
> };
>
> static const struct drm_i915_cmd_descriptor render_cmds[] = {
> CMD( MI_FLUSH, SMI, F, 1, S ),
> - CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
> + CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
> CMD( MI_PREDICATE, SMI, F, 1, S ),
> CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
> - CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ),
> - CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, S ),
> + CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
> + CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
> CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
> - CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, S ),
> + CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
> CMD( MI_CLFLUSH, SMI, !F, 0x3FF, S ),
> CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
> @@ -92,7 +92,9 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
> CMD( MI_RS_CONTROL, SMI, F, 1, S ),
> CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
> CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
> - CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, S ),
> + CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
> + CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
> + CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ),
> CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
> CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
> CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
> @@ -107,8 +109,9 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
> };
>
> static const struct drm_i915_cmd_descriptor video_cmds[] = {
> - CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
> + CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
> CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
> + CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
> CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> /*
> * MFX_WAIT doesn't fit the way we handle length for most commands.
> @@ -119,18 +122,25 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = {
> };
>
> static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
> - CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
> + CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
> CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
> + CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
> CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> };
>
> static const struct drm_i915_cmd_descriptor blt_cmds[] = {
> - CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ),
> + CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
> CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
> + CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
> CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
> CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
> };
>
> +static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
> + CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
> + CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
> +};
> +
> #undef CMD
> #undef SMI
> #undef S3D
> @@ -169,6 +179,12 @@ static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
> { blt_cmds, ARRAY_SIZE(blt_cmds) },
> };
>
> +static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
> + { common_cmds, ARRAY_SIZE(common_cmds) },
> + { blt_cmds, ARRAY_SIZE(blt_cmds) },
> + { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
> +};
> +
> #define CLIENT_MASK 0xE0000000
> #define SUBCLIENT_MASK 0x18000000
> #define MI_CLIENT 0x00000000
> @@ -305,8 +321,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
> ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
> break;
> case BCS:
> - ring->cmd_tables = gen7_blt_cmds;
> - ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
> + if (IS_HASWELL(ring->dev)) {
> + ring->cmd_tables = hsw_blt_ring_cmds;
> + ring->cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
> + } else {
> + ring->cmd_tables = gen7_blt_cmds;
> + ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
> + }
> +
> ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
> break;
> case VECS:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 13ed6ed..2b7c26e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -339,21 +339,22 @@
> /*
> * Commands used only by the command parser
> */
> -#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
> -#define MI_ARB_CHECK MI_INSTR(0x05, 0)
> -#define MI_RS_CONTROL MI_INSTR(0x06, 0)
> -#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
> -#define MI_PREDICATE MI_INSTR(0x0C, 0)
> -#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
> -#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
> -#define MI_URB_CLEAR MI_INSTR(0x19, 0)
> -#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
> -#define MI_CLFLUSH MI_INSTR(0x27, 0)
> -#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
> -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
> -#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
> -#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
> -#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
> +#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
> +#define MI_ARB_CHECK MI_INSTR(0x05, 0)
> +#define MI_RS_CONTROL MI_INSTR(0x06, 0)
> +#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
> +#define MI_PREDICATE MI_INSTR(0x0C, 0)
> +#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
> +#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
> +#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
> +#define MI_URB_CLEAR MI_INSTR(0x19, 0)
> +#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
> +#define MI_CLFLUSH MI_INSTR(0x27, 0)
> +#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
> +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
> +#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
> +#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
> +#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
Superfluous whitespace change hunk.
> #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
>
> #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 04/13] drm/i915: Reject privileged commands
2014-02-05 15:22 ` Jani Nikula
@ 2014-02-05 18:42 ` Volkin, Bradley D
0 siblings, 0 replies; 138+ messages in thread
From: Volkin, Bradley D @ 2014-02-05 18:42 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[snip]
On Wed, Feb 05, 2014 at 07:22:33AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 13ed6ed..2b7c26e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -339,21 +339,22 @@
> > /*
> > * Commands used only by the command parser
> > */
> > -#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
> > -#define MI_ARB_CHECK MI_INSTR(0x05, 0)
> > -#define MI_RS_CONTROL MI_INSTR(0x06, 0)
> > -#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
> > -#define MI_PREDICATE MI_INSTR(0x0C, 0)
> > -#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
> > -#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
> > -#define MI_URB_CLEAR MI_INSTR(0x19, 0)
> > -#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
> > -#define MI_CLFLUSH MI_INSTR(0x27, 0)
> > -#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
> > -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
> > -#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
> > -#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
> > -#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
> > +#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
> > +#define MI_ARB_CHECK MI_INSTR(0x05, 0)
> > +#define MI_RS_CONTROL MI_INSTR(0x06, 0)
> > +#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
> > +#define MI_PREDICATE MI_INSTR(0x0C, 0)
> > +#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
> > +#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
> > +#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
> > +#define MI_URB_CLEAR MI_INSTR(0x19, 0)
> > +#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
> > +#define MI_CLFLUSH MI_INSTR(0x27, 0)
> > +#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
> > +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
> > +#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
> > +#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
> > +#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
>
> Superfluous whitespace change hunk.
It adds MI_LOAD_SCAN_LINES_EXCL and adjusts the whitespace to line up. I see
that the whitespace change makes the actual change less obvious. I'll try to
clean that up.
- Brad
>
>
> > #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
> >
> > #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
> > --
> > 1.8.5.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 05/13] drm/i915: Allow some privileged commands from master
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (3 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 04/13] drm/i915: Reject privileged commands bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-01-29 21:55 ` [PATCH 06/13] drm/i915: Add register whitelists for mesa bradley.d.volkin
` (9 subsequent siblings)
14 siblings, 0 replies; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
The Intel DDX uses these to implement scanline waits in the X server.
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index cc2f68c..88456638 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -57,7 +57,7 @@
static const struct drm_i915_cmd_descriptor common_cmds[] = {
CMD( MI_NOOP, SMI, F, 1, S ),
CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
- CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),
+ CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ),
CMD( MI_ARB_CHECK, SMI, F, 1, S ),
CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
@@ -92,7 +92,7 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
CMD( MI_RS_CONTROL, SMI, F, 1, S ),
CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
- CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
+ CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ),
CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
@@ -137,7 +137,7 @@ static const struct drm_i915_cmd_descriptor blt_cmds[] = {
};
static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
- CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
+ CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
};
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* [PATCH 06/13] drm/i915: Add register whitelists for mesa
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (4 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 05/13] drm/i915: Allow some privileged commands from master bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-02-05 15:29 ` Jani Nikula
2014-01-29 21:55 ` [PATCH 07/13] drm/i915: Add register whitelist for DRM master bradley.d.volkin
` (8 subsequent siblings)
14 siblings, 1 reply; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
These registers are currently used by mesa for blitting,
transform feedback extensions, and performance monitoring
extensions.
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 55 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++++
2 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 88456638..18d5b05 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -185,6 +185,55 @@ static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
{ hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
};
+/*
+ * Register whitelists, sorted by increasing register offset.
+ *
+ * Some registers that userspace accesses are 64 bits. The register
+ * access commands only allow 32-bit accesses. Hence, we have to include
+ * entries for both halves of the 64-bit registers.
+ */
+
+static const u32 gen7_render_regs[] = {
+ HS_INVOCATION_COUNT,
+ HS_INVOCATION_COUNT + sizeof(u32),
+ DS_INVOCATION_COUNT,
+ DS_INVOCATION_COUNT + sizeof(u32),
+ IA_VERTICES_COUNT,
+ IA_VERTICES_COUNT + sizeof(u32),
+ IA_PRIMITIVES_COUNT,
+ IA_PRIMITIVES_COUNT + sizeof(u32),
+ VS_INVOCATION_COUNT,
+ VS_INVOCATION_COUNT + sizeof(u32),
+ GS_INVOCATION_COUNT,
+ GS_INVOCATION_COUNT + sizeof(u32),
+ GS_PRIMITIVES_COUNT,
+ GS_PRIMITIVES_COUNT + sizeof(u32),
+ CL_INVOCATION_COUNT,
+ CL_INVOCATION_COUNT + sizeof(u32),
+ CL_PRIMITIVES_COUNT,
+ CL_PRIMITIVES_COUNT + sizeof(u32),
+ PS_INVOCATION_COUNT,
+ PS_INVOCATION_COUNT + sizeof(u32),
+ PS_DEPTH_COUNT,
+ PS_DEPTH_COUNT + sizeof(u32),
+ GEN7_SO_NUM_PRIMS_WRITTEN(0),
+ GEN7_SO_NUM_PRIMS_WRITTEN(0) + sizeof(u32),
+ GEN7_SO_NUM_PRIMS_WRITTEN(1),
+ GEN7_SO_NUM_PRIMS_WRITTEN(1) + sizeof(u32),
+ GEN7_SO_NUM_PRIMS_WRITTEN(2),
+ GEN7_SO_NUM_PRIMS_WRITTEN(2) + sizeof(u32),
+ GEN7_SO_NUM_PRIMS_WRITTEN(3),
+ GEN7_SO_NUM_PRIMS_WRITTEN(3) + sizeof(u32),
+ GEN7_SO_WRITE_OFFSET(0),
+ GEN7_SO_WRITE_OFFSET(1),
+ GEN7_SO_WRITE_OFFSET(2),
+ GEN7_SO_WRITE_OFFSET(3),
+};
+
+static const u32 gen7_blt_regs[] = {
+ BCS_SWCTRL,
+};
+
#define CLIENT_MASK 0xE0000000
#define SUBCLIENT_MASK 0x18000000
#define MI_CLIENT 0x00000000
@@ -313,6 +362,9 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
}
+ ring->reg_table = gen7_render_regs;
+ ring->reg_count = ARRAY_SIZE(gen7_render_regs);
+
ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
break;
case VCS:
@@ -329,6 +381,9 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
}
+ ring->reg_table = gen7_blt_regs;
+ ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
+
ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
break;
case VECS:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b7c26e..b99bacf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -385,6 +385,26 @@
#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
/*
+ * Registers used only by the command parser
+ */
+#define BCS_SWCTRL 0x22200
+
+#define HS_INVOCATION_COUNT 0x2300
+#define DS_INVOCATION_COUNT 0x2308
+#define IA_VERTICES_COUNT 0x2310
+#define IA_PRIMITIVES_COUNT 0x2318
+#define VS_INVOCATION_COUNT 0x2320
+#define GS_INVOCATION_COUNT 0x2328
+#define GS_PRIMITIVES_COUNT 0x2330
+#define CL_INVOCATION_COUNT 0x2338
+#define CL_PRIMITIVES_COUNT 0x2340
+#define PS_INVOCATION_COUNT 0x2348
+#define PS_DEPTH_COUNT 0x2350
+
+/* There are the 4 64-bit counter registers, one for each stream output */
+#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
+
+/*
* Reset registers
*/
#define DEBUG_RESET_I830 0x6070
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 06/13] drm/i915: Add register whitelists for mesa
2014-01-29 21:55 ` [PATCH 06/13] drm/i915: Add register whitelists for mesa bradley.d.volkin
@ 2014-02-05 15:29 ` Jani Nikula
2014-02-05 18:47 ` Volkin, Bradley D
0 siblings, 1 reply; 138+ messages in thread
From: Jani Nikula @ 2014-02-05 15:29 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> These registers are currently used by mesa for blitting,
> transform feedback extensions, and performance monitoring
> extensions.
>
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 55 ++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++++
> 2 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 88456638..18d5b05 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -185,6 +185,55 @@ static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
> { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
> };
>
> +/*
> + * Register whitelists, sorted by increasing register offset.
> + *
> + * Some registers that userspace accesses are 64 bits. The register
> + * access commands only allow 32-bit accesses. Hence, we have to include
> + * entries for both halves of the 64-bit registers.
> + */
Seems like it would be useful to have a helper macro here.
#define FOO64(addr) (addr), (addr + 4)
With a better name, hopefully. My imagination fails me now.
> +
> +static const u32 gen7_render_regs[] = {
> + HS_INVOCATION_COUNT,
> + HS_INVOCATION_COUNT + sizeof(u32),
> + DS_INVOCATION_COUNT,
> + DS_INVOCATION_COUNT + sizeof(u32),
> + IA_VERTICES_COUNT,
> + IA_VERTICES_COUNT + sizeof(u32),
> + IA_PRIMITIVES_COUNT,
> + IA_PRIMITIVES_COUNT + sizeof(u32),
> + VS_INVOCATION_COUNT,
> + VS_INVOCATION_COUNT + sizeof(u32),
> + GS_INVOCATION_COUNT,
> + GS_INVOCATION_COUNT + sizeof(u32),
> + GS_PRIMITIVES_COUNT,
> + GS_PRIMITIVES_COUNT + sizeof(u32),
> + CL_INVOCATION_COUNT,
> + CL_INVOCATION_COUNT + sizeof(u32),
> + CL_PRIMITIVES_COUNT,
> + CL_PRIMITIVES_COUNT + sizeof(u32),
> + PS_INVOCATION_COUNT,
> + PS_INVOCATION_COUNT + sizeof(u32),
> + PS_DEPTH_COUNT,
> + PS_DEPTH_COUNT + sizeof(u32),
> + GEN7_SO_NUM_PRIMS_WRITTEN(0),
> + GEN7_SO_NUM_PRIMS_WRITTEN(0) + sizeof(u32),
> + GEN7_SO_NUM_PRIMS_WRITTEN(1),
> + GEN7_SO_NUM_PRIMS_WRITTEN(1) + sizeof(u32),
> + GEN7_SO_NUM_PRIMS_WRITTEN(2),
> + GEN7_SO_NUM_PRIMS_WRITTEN(2) + sizeof(u32),
> + GEN7_SO_NUM_PRIMS_WRITTEN(3),
> + GEN7_SO_NUM_PRIMS_WRITTEN(3) + sizeof(u32),
> + GEN7_SO_WRITE_OFFSET(0),
> + GEN7_SO_WRITE_OFFSET(1),
> + GEN7_SO_WRITE_OFFSET(2),
> + GEN7_SO_WRITE_OFFSET(3),
> +};
> +
> +static const u32 gen7_blt_regs[] = {
> + BCS_SWCTRL,
> +};
> +
> #define CLIENT_MASK 0xE0000000
> #define SUBCLIENT_MASK 0x18000000
> #define MI_CLIENT 0x00000000
> @@ -313,6 +362,9 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
> ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
> }
>
> + ring->reg_table = gen7_render_regs;
> + ring->reg_count = ARRAY_SIZE(gen7_render_regs);
> +
> ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
> break;
> case VCS:
> @@ -329,6 +381,9 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
> ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
> }
>
> + ring->reg_table = gen7_blt_regs;
> + ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
> +
> ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
> break;
> case VECS:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2b7c26e..b99bacf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -385,6 +385,26 @@
> #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
>
> /*
> + * Registers used only by the command parser
> + */
> +#define BCS_SWCTRL 0x22200
> +
> +#define HS_INVOCATION_COUNT 0x2300
> +#define DS_INVOCATION_COUNT 0x2308
> +#define IA_VERTICES_COUNT 0x2310
> +#define IA_PRIMITIVES_COUNT 0x2318
> +#define VS_INVOCATION_COUNT 0x2320
> +#define GS_INVOCATION_COUNT 0x2328
> +#define GS_PRIMITIVES_COUNT 0x2330
> +#define CL_INVOCATION_COUNT 0x2338
> +#define CL_PRIMITIVES_COUNT 0x2340
> +#define PS_INVOCATION_COUNT 0x2348
> +#define PS_DEPTH_COUNT 0x2350
> +
> +/* There are the 4 64-bit counter registers, one for each stream output */
> +#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
> +
> +/*
> * Reset registers
> */
> #define DEBUG_RESET_I830 0x6070
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 06/13] drm/i915: Add register whitelists for mesa
2014-02-05 15:29 ` Jani Nikula
@ 2014-02-05 18:47 ` Volkin, Bradley D
0 siblings, 0 replies; 138+ messages in thread
From: Volkin, Bradley D @ 2014-02-05 18:47 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Feb 05, 2014 at 07:29:12AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> > From: Brad Volkin <bradley.d.volkin@intel.com>
> >
> > These registers are currently used by mesa for blitting,
> > transform feedback extensions, and performance monitoring
> > extensions.
> >
> > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 55 ++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++++
> > 2 files changed, 75 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index 88456638..18d5b05 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -185,6 +185,55 @@ static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
> > { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
> > };
> >
> > +/*
> > + * Register whitelists, sorted by increasing register offset.
> > + *
> > + * Some registers that userspace accesses are 64 bits. The register
> > + * access commands only allow 32-bit accesses. Hence, we have to include
> > + * entries for both halves of the 64-bit registers.
> > + */
>
> Seems like it would be useful to have a helper macro here.
>
> #define FOO64(addr) (addr), (addr + 4)
>
> With a better name, hopefully. My imagination fails me now.
REG64(addr)?
Or maybe just
#define REG_UPPER_DW(addr) (addr + 4)
- Brad
>
> > +
> > +static const u32 gen7_render_regs[] = {
> > + HS_INVOCATION_COUNT,
> > + HS_INVOCATION_COUNT + sizeof(u32),
> > + DS_INVOCATION_COUNT,
> > + DS_INVOCATION_COUNT + sizeof(u32),
> > + IA_VERTICES_COUNT,
> > + IA_VERTICES_COUNT + sizeof(u32),
> > + IA_PRIMITIVES_COUNT,
> > + IA_PRIMITIVES_COUNT + sizeof(u32),
> > + VS_INVOCATION_COUNT,
> > + VS_INVOCATION_COUNT + sizeof(u32),
> > + GS_INVOCATION_COUNT,
> > + GS_INVOCATION_COUNT + sizeof(u32),
> > + GS_PRIMITIVES_COUNT,
> > + GS_PRIMITIVES_COUNT + sizeof(u32),
> > + CL_INVOCATION_COUNT,
> > + CL_INVOCATION_COUNT + sizeof(u32),
> > + CL_PRIMITIVES_COUNT,
> > + CL_PRIMITIVES_COUNT + sizeof(u32),
> > + PS_INVOCATION_COUNT,
> > + PS_INVOCATION_COUNT + sizeof(u32),
> > + PS_DEPTH_COUNT,
> > + PS_DEPTH_COUNT + sizeof(u32),
> > + GEN7_SO_NUM_PRIMS_WRITTEN(0),
> > + GEN7_SO_NUM_PRIMS_WRITTEN(0) + sizeof(u32),
> > + GEN7_SO_NUM_PRIMS_WRITTEN(1),
> > + GEN7_SO_NUM_PRIMS_WRITTEN(1) + sizeof(u32),
> > + GEN7_SO_NUM_PRIMS_WRITTEN(2),
> > + GEN7_SO_NUM_PRIMS_WRITTEN(2) + sizeof(u32),
> > + GEN7_SO_NUM_PRIMS_WRITTEN(3),
> > + GEN7_SO_NUM_PRIMS_WRITTEN(3) + sizeof(u32),
> > + GEN7_SO_WRITE_OFFSET(0),
> > + GEN7_SO_WRITE_OFFSET(1),
> > + GEN7_SO_WRITE_OFFSET(2),
> > + GEN7_SO_WRITE_OFFSET(3),
> > +};
> > +
> > +static const u32 gen7_blt_regs[] = {
> > + BCS_SWCTRL,
> > +};
> > +
> > #define CLIENT_MASK 0xE0000000
> > #define SUBCLIENT_MASK 0x18000000
> > #define MI_CLIENT 0x00000000
> > @@ -313,6 +362,9 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
> > ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
> > }
> >
> > + ring->reg_table = gen7_render_regs;
> > + ring->reg_count = ARRAY_SIZE(gen7_render_regs);
> > +
> > ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
> > break;
> > case VCS:
> > @@ -329,6 +381,9 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
> > ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
> > }
> >
> > + ring->reg_table = gen7_blt_regs;
> > + ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
> > +
> > ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
> > break;
> > case VECS:
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 2b7c26e..b99bacf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -385,6 +385,26 @@
> > #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
> >
> > /*
> > + * Registers used only by the command parser
> > + */
> > +#define BCS_SWCTRL 0x22200
> > +
> > +#define HS_INVOCATION_COUNT 0x2300
> > +#define DS_INVOCATION_COUNT 0x2308
> > +#define IA_VERTICES_COUNT 0x2310
> > +#define IA_PRIMITIVES_COUNT 0x2318
> > +#define VS_INVOCATION_COUNT 0x2320
> > +#define GS_INVOCATION_COUNT 0x2328
> > +#define GS_PRIMITIVES_COUNT 0x2330
> > +#define CL_INVOCATION_COUNT 0x2338
> > +#define CL_PRIMITIVES_COUNT 0x2340
> > +#define PS_INVOCATION_COUNT 0x2348
> > +#define PS_DEPTH_COUNT 0x2350
> > +
> > +/* There are the 4 64-bit counter registers, one for each stream output */
> > +#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
> > +
> > +/*
> > * Reset registers
> > */
> > #define DEBUG_RESET_I830 0x6070
> > --
> > 1.8.5.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 07/13] drm/i915: Add register whitelist for DRM master
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (5 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 06/13] drm/i915: Add register whitelists for mesa bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-01-29 22:37 ` Chris Wilson
2014-01-29 21:55 ` [PATCH 08/13] drm/i915: Enable register whitelist checks bradley.d.volkin
` (7 subsequent siblings)
14 siblings, 1 reply; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
These are used to implement scanline waits in the X server.
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 18d5b05..296e322 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -234,6 +234,20 @@ static const u32 gen7_blt_regs[] = {
BCS_SWCTRL,
};
+/* Whitelists for the DRM master. Magic numbers are taken from sna, to match. */
+static const u32 ivb_master_regs[] = {
+ 0xa188, /* FORCEWAKE_MT */
+ 0x44050, /* DERRMR */
+ 0x70068,
+ 0x71068,
+ 0x72068,
+};
+
+static const u32 hsw_master_regs[] = {
+ 0xa188, /* FORCEWAKE_MT */
+ 0x44050, /* DERRMR */
+};
+
#define CLIENT_MASK 0xE0000000
#define SUBCLIENT_MASK 0x18000000
#define MI_CLIENT 0x00000000
@@ -365,6 +379,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
ring->reg_table = gen7_render_regs;
ring->reg_count = ARRAY_SIZE(gen7_render_regs);
+ if (IS_HASWELL(ring->dev)) {
+ ring->master_reg_table = hsw_master_regs;
+ ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
+ } else {
+ ring->master_reg_table = ivb_master_regs;
+ ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
+ }
+
ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
break;
case VCS:
@@ -384,6 +406,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
ring->reg_table = gen7_blt_regs;
ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
+ if (IS_HASWELL(ring->dev)) {
+ ring->master_reg_table = hsw_master_regs;
+ ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
+ } else {
+ ring->master_reg_table = ivb_master_regs;
+ ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
+ }
+
ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
break;
case VECS:
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 07/13] drm/i915: Add register whitelist for DRM master
2014-01-29 21:55 ` [PATCH 07/13] drm/i915: Add register whitelist for DRM master bradley.d.volkin
@ 2014-01-29 22:37 ` Chris Wilson
2014-01-29 23:18 ` Volkin, Bradley D
0 siblings, 1 reply; 138+ messages in thread
From: Chris Wilson @ 2014-01-29 22:37 UTC (permalink / raw)
To: bradley.d.volkin; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 01:55:08PM -0800, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> These are used to implement scanline waits in the X server.
>
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 18d5b05..296e322 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -234,6 +234,20 @@ static const u32 gen7_blt_regs[] = {
> BCS_SWCTRL,
> };
>
> +/* Whitelists for the DRM master. Magic numbers are taken from sna, to match. */
It would be wiser to use the kernel defines, makes it look like we are
actually in charge. ;-)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 07/13] drm/i915: Add register whitelist for DRM master
2014-01-29 22:37 ` Chris Wilson
@ 2014-01-29 23:18 ` Volkin, Bradley D
2014-01-30 9:02 ` Daniel Vetter
0 siblings, 1 reply; 138+ messages in thread
From: Volkin, Bradley D @ 2014-01-29 23:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 02:37:25PM -0800, Chris Wilson wrote:
> On Wed, Jan 29, 2014 at 01:55:08PM -0800, bradley.d.volkin@intel.com wrote:
> > From: Brad Volkin <bradley.d.volkin@intel.com>
> >
> > These are used to implement scanline waits in the X server.
> >
> > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++++++++++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index 18d5b05..296e322 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -234,6 +234,20 @@ static const u32 gen7_blt_regs[] = {
> > BCS_SWCTRL,
> > };
> >
> > +/* Whitelists for the DRM master. Magic numbers are taken from sna, to match. */
>
> It would be wiser to use the kernel defines, makes it look like we are
> actually in charge. ;-)
Will fix, though based on the sna commit history, it looks like you're in charge
either way :)
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 07/13] drm/i915: Add register whitelist for DRM master
2014-01-29 23:18 ` Volkin, Bradley D
@ 2014-01-30 9:02 ` Daniel Vetter
[not found] ` <20140130172206.GA26611@vpg-ubuntu-bdvolkin>
0 siblings, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-01-30 9:02 UTC (permalink / raw)
To: Volkin, Bradley D; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 03:18:21PM -0800, Volkin, Bradley D wrote:
> On Wed, Jan 29, 2014 at 02:37:25PM -0800, Chris Wilson wrote:
> > On Wed, Jan 29, 2014 at 01:55:08PM -0800, bradley.d.volkin@intel.com wrote:
> > > From: Brad Volkin <bradley.d.volkin@intel.com>
> > >
> > > These are used to implement scanline waits in the X server.
> > >
> > > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++++++++++++++++++++++++++++++
> > > 1 file changed, 30 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > index 18d5b05..296e322 100644
> > > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > @@ -234,6 +234,20 @@ static const u32 gen7_blt_regs[] = {
> > > BCS_SWCTRL,
> > > };
> > >
> > > +/* Whitelists for the DRM master. Magic numbers are taken from sna, to match. */
> >
> > It would be wiser to use the kernel defines, makes it look like we are
> > actually in charge. ;-)
>
> Will fix, though based on the sna commit history, it looks like you're in charge
> either way :)
Yeah, for the register tables I think we really should use symbolic values
consistently, adding new ones if i915_reg.h has them lacking. At least as
long as the lists are this short.
Aside: The bkm for getting big feature work which adds lots of register
#defines like this is to split out patches with just the #defines. That
way those can be reviewed independently from any discussions about the
code itself and so merged early. Helps with rebasing pains ;-)
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 08/13] drm/i915: Enable register whitelist checks
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (6 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 07/13] drm/i915: Add register whitelist for DRM master bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-02-05 15:33 ` Jani Nikula
2014-01-29 21:55 ` [PATCH 09/13] drm/i915: Reject commands that explicitly generate interrupts bradley.d.volkin
` (6 subsequent siblings)
14 siblings, 1 reply; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
commands allow userspace access to registers. Only certain registers
should be allowed for such access, so enable checking for those commands.
Each ring gets its own register whitelist.
MI_LOAD_REGISTER_REG on HSW also allows register access but is currently
unused by userspace components. Leave it rejected.
PIPE_CONTROL and MEDIA_VFE_STATE allow register access based on certain
bits being set. Reject those as well.
OTC-Tracker: AXIA-4631
Change-Id: Ie614a2f0eb2e5917de809e5a17957175d24cc44f
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 23 ++++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 296e322..5d3e303 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -63,9 +63,12 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
- CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, R ),
- CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, R ),
- CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, R ),
+ CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
+ .reg = { .offset = 1, .mask = 0x007FFFFC } ),
+ CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W,
+ .reg = { .offset = 1, .mask = 0x007FFFFC } ),
+ CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W,
+ .reg = { .offset = 1, .mask = 0x007FFFFC } ),
CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
};
@@ -82,9 +85,23 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
CMD( PIPELINE_SELECT, S3D, F, 1, S ),
+ CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
+ .bits = {{
+ .offset = 2,
+ .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
+ CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
+ .bits = {{
+ .offset = 1,
+ .mask = PIPE_CONTROL_MMIO_WRITE,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
};
static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b99bacf..6592d0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -319,6 +319,7 @@
#define DISPLAY_PLANE_B (1<<20)
#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
+#define PIPE_CONTROL_MMIO_WRITE (1<<23)
#define PIPE_CONTROL_CS_STALL (1<<20)
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
#define PIPE_CONTROL_QW_WRITE (1<<14)
@@ -359,6 +360,8 @@
#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
+#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
+#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 08/13] drm/i915: Enable register whitelist checks
2014-01-29 21:55 ` [PATCH 08/13] drm/i915: Enable register whitelist checks bradley.d.volkin
@ 2014-02-05 15:33 ` Jani Nikula
2014-02-05 18:49 ` Volkin, Bradley D
0 siblings, 1 reply; 138+ messages in thread
From: Jani Nikula @ 2014-02-05 15:33 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
> commands allow userspace access to registers. Only certain registers
> should be allowed for such access, so enable checking for those commands.
> Each ring gets its own register whitelist.
>
> MI_LOAD_REGISTER_REG on HSW also allows register access but is currently
> unused by userspace components. Leave it rejected.
>
> PIPE_CONTROL and MEDIA_VFE_STATE allow register access based on certain
> bits being set. Reject those as well.
>
> OTC-Tracker: AXIA-4631
> Change-Id: Ie614a2f0eb2e5917de809e5a17957175d24cc44f
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 23 ++++++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 296e322..5d3e303 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -63,9 +63,12 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
> CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
> CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
> CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
> - CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, R ),
> - CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, R ),
> - CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, R ),
> + CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
> + .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> + CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W,
> + .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> + CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W,
> + .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
> };
>
> @@ -82,9 +85,23 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
> CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
> CMD( PIPELINE_SELECT, S3D, F, 1, S ),
> + CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
> + .bits = {{
> + .offset = 2,
> + .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
>From my bikeshedding dept.: here too I think it would be beneficial to
have the count decided by an empty element, or a .valid = 1 field or
something.
> CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
> CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
> CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
> + CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
> + .bits = {{
> + .offset = 1,
> + .mask = PIPE_CONTROL_MMIO_WRITE,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> };
>
> static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b99bacf..6592d0d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -319,6 +319,7 @@
> #define DISPLAY_PLANE_B (1<<20)
> #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
> #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
> +#define PIPE_CONTROL_MMIO_WRITE (1<<23)
> #define PIPE_CONTROL_CS_STALL (1<<20)
> #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
> #define PIPE_CONTROL_QW_WRITE (1<<14)
> @@ -359,6 +360,8 @@
>
> #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
> #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
> +#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
> +#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
> #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
> #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
> #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 08/13] drm/i915: Enable register whitelist checks
2014-02-05 15:33 ` Jani Nikula
@ 2014-02-05 18:49 ` Volkin, Bradley D
0 siblings, 0 replies; 138+ messages in thread
From: Volkin, Bradley D @ 2014-02-05 18:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Feb 05, 2014 at 07:33:28AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> > From: Brad Volkin <bradley.d.volkin@intel.com>
> >
> > MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
> > commands allow userspace access to registers. Only certain registers
> > should be allowed for such access, so enable checking for those commands.
> > Each ring gets its own register whitelist.
> >
> > MI_LOAD_REGISTER_REG on HSW also allows register access but is currently
> > unused by userspace components. Leave it rejected.
> >
> > PIPE_CONTROL and MEDIA_VFE_STATE allow register access based on certain
> > bits being set. Reject those as well.
> >
> > OTC-Tracker: AXIA-4631
> > Change-Id: Ie614a2f0eb2e5917de809e5a17957175d24cc44f
> > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 23 ++++++++++++++++++++---
> > drivers/gpu/drm/i915/i915_reg.h | 3 +++
> > 2 files changed, 23 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index 296e322..5d3e303 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -63,9 +63,12 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
> > CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
> > CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
> > CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
> > - CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, R ),
> > - CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, R ),
> > - CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, R ),
> > + CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
> > + .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> > + CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W,
> > + .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> > + CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W,
> > + .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> > CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
> > };
> >
> > @@ -82,9 +85,23 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
> > CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> > CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
> > CMD( PIPELINE_SELECT, S3D, F, 1, S ),
> > + CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
> > + .bits = {{
> > + .offset = 2,
> > + .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
> > + .expected = 0
> > + }},
> > + .bits_count = 1 ),
>
> From my bikeshedding dept.: here too I think it would be beneficial to
> have the count decided by an empty element, or a .valid = 1 field or
> something.
I see your point. I'll look at doing a .valid=1 or .mask!=0 check.
- Brad
>
>
> > CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
> > CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
> > CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
> > + CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
> > + .bits = {{
> > + .offset = 1,
> > + .mask = PIPE_CONTROL_MMIO_WRITE,
> > + .expected = 0
> > + }},
> > + .bits_count = 1 ),
> > };
> >
> > static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b99bacf..6592d0d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -319,6 +319,7 @@
> > #define DISPLAY_PLANE_B (1<<20)
> > #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
> > #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
> > +#define PIPE_CONTROL_MMIO_WRITE (1<<23)
> > #define PIPE_CONTROL_CS_STALL (1<<20)
> > #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
> > #define PIPE_CONTROL_QW_WRITE (1<<14)
> > @@ -359,6 +360,8 @@
> >
> > #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
> > #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
> > +#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
> > +#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
> > #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
> > #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
> > #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
> > --
> > 1.8.5.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 09/13] drm/i915: Reject commands that explicitly generate interrupts
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (7 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 08/13] drm/i915: Enable register whitelist checks bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-01-29 21:55 ` [PATCH 10/13] drm/i915: Enable PPGTT command parser checks bradley.d.volkin
` (5 subsequent siblings)
14 siblings, 0 replies; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
The driver leaves most interrupts masked during normal operation,
so there would have to be additional work to enable userspace to
safely request/receive an interrupt.
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 25 +++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 5d3e303..7de7c6a 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -56,7 +56,7 @@
---------------------------------------------------------- */
static const struct drm_i915_cmd_descriptor common_cmds[] = {
CMD( MI_NOOP, SMI, F, 1, S ),
- CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
+ CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ),
CMD( MI_ARB_CHECK, SMI, F, 1, S ),
CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
@@ -98,7 +98,7 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
.bits = {{
.offset = 1,
- .mask = PIPE_CONTROL_MMIO_WRITE,
+ .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
.expected = 0
}},
.bits_count = 1 ),
@@ -129,6 +129,13 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = {
CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
+ CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_FLUSH_DW_NOTIFY,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
/*
* MFX_WAIT doesn't fit the way we handle length for most commands.
@@ -142,6 +149,13 @@ static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
+ CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_FLUSH_DW_NOTIFY,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
};
@@ -149,6 +163,13 @@ static const struct drm_i915_cmd_descriptor blt_cmds[] = {
CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
+ CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_FLUSH_DW_NOTIFY,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6592d0d..c2e4898 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -258,6 +258,7 @@
#define MI_FLUSH_DW_STORE_INDEX (1<<21)
#define MI_INVALIDATE_TLB (1<<18)
#define MI_FLUSH_DW_OP_STOREDW (1<<14)
+#define MI_FLUSH_DW_NOTIFY (1<<8)
#define MI_INVALIDATE_BSD (1<<7)
#define MI_FLUSH_DW_USE_GTT (1<<2)
#define MI_FLUSH_DW_USE_PPGTT (0<<2)
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* [PATCH 10/13] drm/i915: Enable PPGTT command parser checks
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (8 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 09/13] drm/i915: Reject commands that explicitly generate interrupts bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-01-29 22:33 ` Chris Wilson
2014-02-05 15:37 ` Jani Nikula
2014-01-29 21:55 ` [PATCH 11/13] drm/i915: Reject commands that would store to global HWS page bradley.d.volkin
` (4 subsequent siblings)
14 siblings, 2 replies; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
Various commands that access memory have a bit to determine whether
the graphics address specified in the command should use the GGTT or
PPGTT for translation. These checks ensure that the bit indicates
PPGTT translation.
Most of these checks use the existing bit-checking infrastructure.
The PIPE_CONTROL and MI_FLUSH_DW commands, however, are multi-function
commands. The GGTT/PPGTT bit is only relevant for certain uses of the
command. As such, this change also extends the bit-checking code to
include a "condition" mask and offset. If the condition mask is non-zero
then the parser only performs the bit check when the bits specified by
the condition mask/offset are also non-zero.
NOTE: At this point in the series PPGTT must be enabled for the parser
to work correctly. If it's not enabled, userspace will not be setting
the PPGTT bits the way the parser requires. VLV is the only platform
where this is a problem, so at this point, we disable parsing for VLV.
OTC-Tracker: AXIA-4631
Change-Id: I3f4c76b6734f1956ec47e698230f97d0998ff92b
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 147 +++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 6 ++
3 files changed, 144 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 7de7c6a..26072a2 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -65,10 +65,22 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
.reg = { .offset = 1, .mask = 0x007FFFFC } ),
- CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W,
- .reg = { .offset = 1, .mask = 0x007FFFFC } ),
- CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W,
- .reg = { .offset = 1, .mask = 0x007FFFFC } ),
+ CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
+ .reg = { .offset = 1, .mask = 0x007FFFFC },
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
+ CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W | B,
+ .reg = { .offset = 1, .mask = 0x007FFFFC },
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
};
@@ -80,9 +92,35 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
+ CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
- CMD( MI_CLFLUSH, SMI, !F, 0x3FF, S ),
- CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
+ CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
+ CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
+ .bits = {{
+ .offset = 1,
+ .mask = MI_REPORT_PERF_COUNT_GGTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
+ CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
CMD( PIPELINE_SELECT, S3D, F, 1, S ),
CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
@@ -100,8 +138,15 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
.offset = 1,
.mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
.expected = 0
+ },
+ {
+ .offset = 1,
+ .mask = PIPE_CONTROL_GLOBAL_GTT_IVB,
+ .expected = 0,
+ .condition_offset = 1,
+ .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK
}},
- .bits_count = 1 ),
+ .bits_count = 2 ),
};
static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
@@ -127,16 +172,35 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
static const struct drm_i915_cmd_descriptor video_cmds[] = {
CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
- CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
+ CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
.bits = {{
.offset = 0,
.mask = MI_FLUSH_DW_NOTIFY,
.expected = 0
+ },
+ {
+ .offset = 1,
+ .mask = MI_FLUSH_DW_USE_GTT,
+ .expected = 0,
+ .condition_offset = 0,
+ .condition_mask = MI_FLUSH_DW_OP_MASK
}},
- .bits_count = 1 ),
- CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
+ .bits_count = 2 ),
+ CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
/*
* MFX_WAIT doesn't fit the way we handle length for most commands.
* It has a length field but it uses a non-standard length bias.
@@ -147,29 +211,61 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = {
static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
- CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
+ CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
.bits = {{
.offset = 0,
.mask = MI_FLUSH_DW_NOTIFY,
.expected = 0
+ },
+ {
+ .offset = 1,
+ .mask = MI_FLUSH_DW_USE_GTT,
+ .expected = 0,
+ .condition_offset = 0,
+ .condition_mask = MI_FLUSH_DW_OP_MASK
}},
- .bits_count = 1 ),
- CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
+ .bits_count = 2 ),
+ CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
};
static const struct drm_i915_cmd_descriptor blt_cmds[] = {
CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
- CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
+ CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
+ .bits = {{
+ .offset = 0,
+ .mask = MI_GLOBAL_GTT,
+ .expected = 0
+ }},
+ .bits_count = 1 ),
CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
.bits = {{
.offset = 0,
.mask = MI_FLUSH_DW_NOTIFY,
.expected = 0
+ },
+ {
+ .offset = 1,
+ .mask = MI_FLUSH_DW_USE_GTT,
+ .expected = 0,
+ .condition_offset = 0,
+ .condition_mask = MI_FLUSH_DW_OP_MASK
}},
- .bits_count = 1 ),
+ .bits_count = 2 ),
CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
};
@@ -569,10 +665,21 @@ finish:
int i915_needs_cmd_parser(struct intel_ring_buffer *ring)
{
+ drm_i915_private_t *dev_priv =
+ (drm_i915_private_t *)ring->dev->dev_private;
+
/* No command tables indicates a platform without parsing */
if (!ring->cmd_tables)
return 0;
+ /*
+ * XXX: VLV is Gen7 and therefore has cmd_tables, but has PPGTT
+ * disabled. That will cause all of the parser's PPGTT checks to
+ * fail. For now, disable parsing when PPGTT is off.
+ */
+ if(!dev_priv->mm.aliasing_ppgtt)
+ return 0;
+
return i915.enable_cmd_parser;
}
@@ -675,6 +782,16 @@ int i915_parse_cmds(struct intel_ring_buffer *ring,
u32 dword = cmd[desc->bits[i].offset] &
desc->bits[i].mask;
+ if (desc->bits[i].condition_mask != 0) {
+ u32 offset =
+ desc->bits[i].condition_offset;
+ u32 condition = cmd[offset] &
+ desc->bits[i].condition_mask;
+
+ if (condition == 0)
+ continue;
+ }
+
if (dword != desc->bits[i].expected) {
DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
*cmd,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8aed80f..2d1d2ef 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1829,11 +1829,17 @@ struct drm_i915_cmd_descriptor {
* compared against an expected value. If the command does not match
* the expected value, the parser rejects it. Only valid if flags has
* the CMD_DESC_BITMASK bit set.
+ *
+ * If the check specifies a non-zero condition_mask then the parser
+ * only performs the check when the bits specified by condition_mask
+ * are non-zero.
*/
struct {
u32 offset;
u32 mask;
u32 expected;
+ u32 condition_offset;
+ u32 condition_mask;
} bits[MAX_CMD_DESC_BITMASKS];
/** Number of valid entries in the bits array */
int bits_count;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2e4898..ff263f4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -179,6 +179,8 @@
* Memory interface instructions used by the kernel
*/
#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
+#define MI_GLOBAL_GTT (1<<22)
#define MI_NOOP MI_INSTR(0, 0)
#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
@@ -258,6 +260,7 @@
#define MI_FLUSH_DW_STORE_INDEX (1<<21)
#define MI_INVALIDATE_TLB (1<<18)
#define MI_FLUSH_DW_OP_STOREDW (1<<14)
+#define MI_FLUSH_DW_OP_MASK (3<<14)
#define MI_FLUSH_DW_NOTIFY (1<<8)
#define MI_INVALIDATE_BSD (1<<7)
#define MI_FLUSH_DW_USE_GTT (1<<2)
@@ -324,6 +327,7 @@
#define PIPE_CONTROL_CS_STALL (1<<20)
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
#define PIPE_CONTROL_QW_WRITE (1<<14)
+#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
#define PIPE_CONTROL_DEPTH_STALL (1<<13)
#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
@@ -352,6 +356,8 @@
#define MI_URB_CLEAR MI_INSTR(0x19, 0)
#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
#define MI_CLFLUSH MI_INSTR(0x27, 0)
+#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
+#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 10/13] drm/i915: Enable PPGTT command parser checks
2014-01-29 21:55 ` [PATCH 10/13] drm/i915: Enable PPGTT command parser checks bradley.d.volkin
@ 2014-01-29 22:33 ` Chris Wilson
2014-01-29 23:00 ` Volkin, Bradley D
2014-02-05 15:37 ` Jani Nikula
1 sibling, 1 reply; 138+ messages in thread
From: Chris Wilson @ 2014-01-29 22:33 UTC (permalink / raw)
To: bradley.d.volkin; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 01:55:11PM -0800, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> Various commands that access memory have a bit to determine whether
> the graphics address specified in the command should use the GGTT or
> PPGTT for translation. These checks ensure that the bit indicates
> PPGTT translation.
>
> Most of these checks use the existing bit-checking infrastructure.
> The PIPE_CONTROL and MI_FLUSH_DW commands, however, are multi-function
> commands. The GGTT/PPGTT bit is only relevant for certain uses of the
> command. As such, this change also extends the bit-checking code to
> include a "condition" mask and offset. If the condition mask is non-zero
> then the parser only performs the bit check when the bits specified by
> the condition mask/offset are also non-zero.
>
> NOTE: At this point in the series PPGTT must be enabled for the parser
> to work correctly. If it's not enabled, userspace will not be setting
> the PPGTT bits the way the parser requires. VLV is the only platform
> where this is a problem, so at this point, we disable parsing for VLV.
That doesn't make sense. Are we not verifying that userspace has set the
bits as appropriate for the hardware setup? So the value we expect
depends upon how we have enabled ppgtt (or not).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 10/13] drm/i915: Enable PPGTT command parser checks
2014-01-29 22:33 ` Chris Wilson
@ 2014-01-29 23:00 ` Volkin, Bradley D
2014-01-29 23:08 ` Chris Wilson
0 siblings, 1 reply; 138+ messages in thread
From: Volkin, Bradley D @ 2014-01-29 23:00 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 02:33:55PM -0800, Chris Wilson wrote:
> On Wed, Jan 29, 2014 at 01:55:11PM -0800, bradley.d.volkin@intel.com wrote:
> > From: Brad Volkin <bradley.d.volkin@intel.com>
> >
> > Various commands that access memory have a bit to determine whether
> > the graphics address specified in the command should use the GGTT or
> > PPGTT for translation. These checks ensure that the bit indicates
> > PPGTT translation.
> >
> > Most of these checks use the existing bit-checking infrastructure.
> > The PIPE_CONTROL and MI_FLUSH_DW commands, however, are multi-function
> > commands. The GGTT/PPGTT bit is only relevant for certain uses of the
> > command. As such, this change also extends the bit-checking code to
> > include a "condition" mask and offset. If the condition mask is non-zero
> > then the parser only performs the bit check when the bits specified by
> > the condition mask/offset are also non-zero.
> >
> > NOTE: At this point in the series PPGTT must be enabled for the parser
> > to work correctly. If it's not enabled, userspace will not be setting
> > the PPGTT bits the way the parser requires. VLV is the only platform
> > where this is a problem, so at this point, we disable parsing for VLV.
>
> That doesn't make sense. Are we not verifying that userspace has set the
> bits as appropriate for the hardware setup? So the value we expect
> depends upon how we have enabled ppgtt (or not).
We could but don't currently. I was under the impression the parser wasn't
seen as having as much benefit without ppgtt and that we're generally moving
towards ppgtt as the default for all relevant platforms.
- Brad
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 10/13] drm/i915: Enable PPGTT command parser checks
2014-01-29 23:00 ` Volkin, Bradley D
@ 2014-01-29 23:08 ` Chris Wilson
0 siblings, 0 replies; 138+ messages in thread
From: Chris Wilson @ 2014-01-29 23:08 UTC (permalink / raw)
To: Volkin, Bradley D; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 03:00:11PM -0800, Volkin, Bradley D wrote:
> On Wed, Jan 29, 2014 at 02:33:55PM -0800, Chris Wilson wrote:
> > On Wed, Jan 29, 2014 at 01:55:11PM -0800, bradley.d.volkin@intel.com wrote:
> > > From: Brad Volkin <bradley.d.volkin@intel.com>
> > >
> > > Various commands that access memory have a bit to determine whether
> > > the graphics address specified in the command should use the GGTT or
> > > PPGTT for translation. These checks ensure that the bit indicates
> > > PPGTT translation.
> > >
> > > Most of these checks use the existing bit-checking infrastructure.
> > > The PIPE_CONTROL and MI_FLUSH_DW commands, however, are multi-function
> > > commands. The GGTT/PPGTT bit is only relevant for certain uses of the
> > > command. As such, this change also extends the bit-checking code to
> > > include a "condition" mask and offset. If the condition mask is non-zero
> > > then the parser only performs the bit check when the bits specified by
> > > the condition mask/offset are also non-zero.
> > >
> > > NOTE: At this point in the series PPGTT must be enabled for the parser
> > > to work correctly. If it's not enabled, userspace will not be setting
> > > the PPGTT bits the way the parser requires. VLV is the only platform
> > > where this is a problem, so at this point, we disable parsing for VLV.
> >
> > That doesn't make sense. Are we not verifying that userspace has set the
> > bits as appropriate for the hardware setup? So the value we expect
> > depends upon how we have enabled ppgtt (or not).
>
> We could but don't currently. I was under the impression the parser wasn't
> seen as having as much benefit without ppgtt and that we're generally moving
> towards ppgtt as the default for all relevant platforms.
Oh, I remember that argument. It's just the way you phrased the note
made me think that it was a limitation of the patch.
Personally I would implement the checks against the hardware state as we
know it. It's a nice pedalogical example, and removes a buried
assumption from the code.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 10/13] drm/i915: Enable PPGTT command parser checks
2014-01-29 21:55 ` [PATCH 10/13] drm/i915: Enable PPGTT command parser checks bradley.d.volkin
2014-01-29 22:33 ` Chris Wilson
@ 2014-02-05 15:37 ` Jani Nikula
2014-02-05 18:54 ` Volkin, Bradley D
1 sibling, 1 reply; 138+ messages in thread
From: Jani Nikula @ 2014-02-05 15:37 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> Various commands that access memory have a bit to determine whether
> the graphics address specified in the command should use the GGTT or
> PPGTT for translation. These checks ensure that the bit indicates
> PPGTT translation.
>
> Most of these checks use the existing bit-checking infrastructure.
> The PIPE_CONTROL and MI_FLUSH_DW commands, however, are multi-function
> commands. The GGTT/PPGTT bit is only relevant for certain uses of the
> command. As such, this change also extends the bit-checking code to
> include a "condition" mask and offset. If the condition mask is non-zero
> then the parser only performs the bit check when the bits specified by
> the condition mask/offset are also non-zero.
>
> NOTE: At this point in the series PPGTT must be enabled for the parser
> to work correctly. If it's not enabled, userspace will not be setting
> the PPGTT bits the way the parser requires. VLV is the only platform
> where this is a problem, so at this point, we disable parsing for VLV.
>
> OTC-Tracker: AXIA-4631
> Change-Id: I3f4c76b6734f1956ec47e698230f97d0998ff92b
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 147 +++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> 3 files changed, 144 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 7de7c6a..26072a2 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -65,10 +65,22 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
> CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
> CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
> .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> - CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W,
> - .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> - CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W,
> - .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> + CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
> + .reg = { .offset = 1, .mask = 0x007FFFFC },
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
Not specific to this patch or this field, but all around I think you
should add the comma to the last line too. It's a pretty universal way
of doing things in the kernel, both for array and struct initialization.
> + }},
> + .bits_count = 1 ),
> + CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W | B,
> + .reg = { .offset = 1, .mask = 0x007FFFFC },
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
> };
>
> @@ -80,9 +92,35 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
> CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
> CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
> CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
> + CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
> - CMD( MI_CLFLUSH, SMI, !F, 0x3FF, S ),
> - CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> + CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> + CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
> + .bits = {{
> + .offset = 1,
> + .mask = MI_REPORT_PERF_COUNT_GGTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> + CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
> CMD( PIPELINE_SELECT, S3D, F, 1, S ),
> CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
> @@ -100,8 +138,15 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
> .offset = 1,
> .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
> .expected = 0
> + },
> + {
> + .offset = 1,
> + .mask = PIPE_CONTROL_GLOBAL_GTT_IVB,
> + .expected = 0,
> + .condition_offset = 1,
> + .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK
> }},
> - .bits_count = 1 ),
> + .bits_count = 2 ),
> };
>
> static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
> @@ -127,16 +172,35 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
>
> static const struct drm_i915_cmd_descriptor video_cmds[] = {
> CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
> - CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
> + CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
> CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
> .bits = {{
> .offset = 0,
> .mask = MI_FLUSH_DW_NOTIFY,
> .expected = 0
> + },
> + {
> + .offset = 1,
> + .mask = MI_FLUSH_DW_USE_GTT,
> + .expected = 0,
> + .condition_offset = 0,
> + .condition_mask = MI_FLUSH_DW_OP_MASK
> }},
> - .bits_count = 1 ),
> - CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> + .bits_count = 2 ),
> + CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> /*
> * MFX_WAIT doesn't fit the way we handle length for most commands.
> * It has a length field but it uses a non-standard length bias.
> @@ -147,29 +211,61 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = {
>
> static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
> CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
> - CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ),
> + CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
> CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
> .bits = {{
> .offset = 0,
> .mask = MI_FLUSH_DW_NOTIFY,
> .expected = 0
> + },
> + {
> + .offset = 1,
> + .mask = MI_FLUSH_DW_USE_GTT,
> + .expected = 0,
> + .condition_offset = 0,
> + .condition_mask = MI_FLUSH_DW_OP_MASK
> }},
> - .bits_count = 1 ),
> - CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> + .bits_count = 2 ),
> + CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> };
>
> static const struct drm_i915_cmd_descriptor blt_cmds[] = {
> CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
> - CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
> + CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
> + .bits = {{
> + .offset = 0,
> + .mask = MI_GLOBAL_GTT,
> + .expected = 0
> + }},
> + .bits_count = 1 ),
> CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
> CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
> .bits = {{
> .offset = 0,
> .mask = MI_FLUSH_DW_NOTIFY,
> .expected = 0
> + },
> + {
> + .offset = 1,
> + .mask = MI_FLUSH_DW_USE_GTT,
> + .expected = 0,
> + .condition_offset = 0,
> + .condition_mask = MI_FLUSH_DW_OP_MASK
> }},
> - .bits_count = 1 ),
> + .bits_count = 2 ),
> CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
> CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
> };
> @@ -569,10 +665,21 @@ finish:
>
> int i915_needs_cmd_parser(struct intel_ring_buffer *ring)
> {
> + drm_i915_private_t *dev_priv =
> + (drm_i915_private_t *)ring->dev->dev_private;
> +
> /* No command tables indicates a platform without parsing */
> if (!ring->cmd_tables)
> return 0;
>
> + /*
> + * XXX: VLV is Gen7 and therefore has cmd_tables, but has PPGTT
> + * disabled. That will cause all of the parser's PPGTT checks to
> + * fail. For now, disable parsing when PPGTT is off.
> + */
> + if(!dev_priv->mm.aliasing_ppgtt)
^ missing space.
> + return 0;
> +
Hmm, shouldn't this belong to some other patch, much earlier in the
series? Like patch 2 or 3?
> return i915.enable_cmd_parser;
> }
>
> @@ -675,6 +782,16 @@ int i915_parse_cmds(struct intel_ring_buffer *ring,
> u32 dword = cmd[desc->bits[i].offset] &
> desc->bits[i].mask;
>
> + if (desc->bits[i].condition_mask != 0) {
> + u32 offset =
> + desc->bits[i].condition_offset;
> + u32 condition = cmd[offset] &
> + desc->bits[i].condition_mask;
> +
> + if (condition == 0)
> + continue;
> + }
> +
> if (dword != desc->bits[i].expected) {
> DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
> *cmd,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8aed80f..2d1d2ef 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1829,11 +1829,17 @@ struct drm_i915_cmd_descriptor {
> * compared against an expected value. If the command does not match
> * the expected value, the parser rejects it. Only valid if flags has
> * the CMD_DESC_BITMASK bit set.
> + *
> + * If the check specifies a non-zero condition_mask then the parser
> + * only performs the check when the bits specified by condition_mask
> + * are non-zero.
> */
> struct {
> u32 offset;
> u32 mask;
> u32 expected;
> + u32 condition_offset;
> + u32 condition_mask;
> } bits[MAX_CMD_DESC_BITMASKS];
> /** Number of valid entries in the bits array */
> int bits_count;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2e4898..ff263f4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -179,6 +179,8 @@
> * Memory interface instructions used by the kernel
> */
> #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> +/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
> +#define MI_GLOBAL_GTT (1<<22)
>
> #define MI_NOOP MI_INSTR(0, 0)
> #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
> @@ -258,6 +260,7 @@
> #define MI_FLUSH_DW_STORE_INDEX (1<<21)
> #define MI_INVALIDATE_TLB (1<<18)
> #define MI_FLUSH_DW_OP_STOREDW (1<<14)
> +#define MI_FLUSH_DW_OP_MASK (3<<14)
> #define MI_FLUSH_DW_NOTIFY (1<<8)
> #define MI_INVALIDATE_BSD (1<<7)
> #define MI_FLUSH_DW_USE_GTT (1<<2)
> @@ -324,6 +327,7 @@
> #define PIPE_CONTROL_CS_STALL (1<<20)
> #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
> #define PIPE_CONTROL_QW_WRITE (1<<14)
> +#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
> #define PIPE_CONTROL_DEPTH_STALL (1<<13)
> #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
> #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
> @@ -352,6 +356,8 @@
> #define MI_URB_CLEAR MI_INSTR(0x19, 0)
> #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
> #define MI_CLFLUSH MI_INSTR(0x27, 0)
> +#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
> +#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
> #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
> #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
> #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 10/13] drm/i915: Enable PPGTT command parser checks
2014-02-05 15:37 ` Jani Nikula
@ 2014-02-05 18:54 ` Volkin, Bradley D
0 siblings, 0 replies; 138+ messages in thread
From: Volkin, Bradley D @ 2014-02-05 18:54 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[snip]
On Wed, Feb 05, 2014 at 07:37:51AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> > int i915_needs_cmd_parser(struct intel_ring_buffer *ring)
> > {
> > + drm_i915_private_t *dev_priv =
> > + (drm_i915_private_t *)ring->dev->dev_private;
> > +
> > /* No command tables indicates a platform without parsing */
> > if (!ring->cmd_tables)
> > return 0;
> >
> > + /*
> > + * XXX: VLV is Gen7 and therefore has cmd_tables, but has PPGTT
> > + * disabled. That will cause all of the parser's PPGTT checks to
> > + * fail. For now, disable parsing when PPGTT is off.
> > + */
> > + if(!dev_priv->mm.aliasing_ppgtt)
> ^ missing space.
Oops
>
> > + return 0;
> > +
>
> Hmm, shouldn't this belong to some other patch, much earlier in the
> series? Like patch 2 or 3?
Not necessarily. It's only because we've added the PPGTT checks without
somehow making them conditional on aliasing_ppgtt==true that we have a problem,
and that only happens with this patch. The parser works, though is less useful,
on !aliasing_ppgtt platforms up to this point.
Chris suggested that we just fix it up so that the PPGTT checks are conditional
on PPGTT actually enabled, so I'm going to look at that.
- Brad
>
> > return i915.enable_cmd_parser;
> > }
> >
> > @@ -675,6 +782,16 @@ int i915_parse_cmds(struct intel_ring_buffer *ring,
> > u32 dword = cmd[desc->bits[i].offset] &
> > desc->bits[i].mask;
> >
> > + if (desc->bits[i].condition_mask != 0) {
> > + u32 offset =
> > + desc->bits[i].condition_offset;
> > + u32 condition = cmd[offset] &
> > + desc->bits[i].condition_mask;
> > +
> > + if (condition == 0)
> > + continue;
> > + }
> > +
> > if (dword != desc->bits[i].expected) {
> > DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
> > *cmd,
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 8aed80f..2d1d2ef 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1829,11 +1829,17 @@ struct drm_i915_cmd_descriptor {
> > * compared against an expected value. If the command does not match
> > * the expected value, the parser rejects it. Only valid if flags has
> > * the CMD_DESC_BITMASK bit set.
> > + *
> > + * If the check specifies a non-zero condition_mask then the parser
> > + * only performs the check when the bits specified by condition_mask
> > + * are non-zero.
> > */
> > struct {
> > u32 offset;
> > u32 mask;
> > u32 expected;
> > + u32 condition_offset;
> > + u32 condition_mask;
> > } bits[MAX_CMD_DESC_BITMASKS];
> > /** Number of valid entries in the bits array */
> > int bits_count;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c2e4898..ff263f4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -179,6 +179,8 @@
> > * Memory interface instructions used by the kernel
> > */
> > #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> > +/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
> > +#define MI_GLOBAL_GTT (1<<22)
> >
> > #define MI_NOOP MI_INSTR(0, 0)
> > #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
> > @@ -258,6 +260,7 @@
> > #define MI_FLUSH_DW_STORE_INDEX (1<<21)
> > #define MI_INVALIDATE_TLB (1<<18)
> > #define MI_FLUSH_DW_OP_STOREDW (1<<14)
> > +#define MI_FLUSH_DW_OP_MASK (3<<14)
> > #define MI_FLUSH_DW_NOTIFY (1<<8)
> > #define MI_INVALIDATE_BSD (1<<7)
> > #define MI_FLUSH_DW_USE_GTT (1<<2)
> > @@ -324,6 +327,7 @@
> > #define PIPE_CONTROL_CS_STALL (1<<20)
> > #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
> > #define PIPE_CONTROL_QW_WRITE (1<<14)
> > +#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
> > #define PIPE_CONTROL_DEPTH_STALL (1<<13)
> > #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
> > #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
> > @@ -352,6 +356,8 @@
> > #define MI_URB_CLEAR MI_INSTR(0x19, 0)
> > #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
> > #define MI_CLFLUSH MI_INSTR(0x27, 0)
> > +#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
> > +#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
> > #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
> > #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
> > #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
> > --
> > 1.8.5.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 11/13] drm/i915: Reject commands that would store to global HWS page
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (9 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 10/13] drm/i915: Enable PPGTT command parser checks bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-02-05 15:39 ` Jani Nikula
2014-01-29 21:55 ` [PATCH 12/13] drm/i915: Add a CMD_PARSER_VERSION getparam bradley.d.volkin
` (3 subsequent siblings)
14 siblings, 1 reply; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
PIPE_CONTROL and MI_FLUSH_DW have bits that would write to the
hardware status page. The driver stores request tracking info
there, so don't let userspace overwrite it.
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 26072a2..b93df1c 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -141,7 +141,8 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
},
{
.offset = 1,
- .mask = PIPE_CONTROL_GLOBAL_GTT_IVB,
+ .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
+ PIPE_CONTROL_STORE_DATA_INDEX),
.expected = 0,
.condition_offset = 1,
.condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK
@@ -192,8 +193,15 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = {
.expected = 0,
.condition_offset = 0,
.condition_mask = MI_FLUSH_DW_OP_MASK
+ },
+ {
+ .offset = 0,
+ .mask = MI_FLUSH_DW_STORE_INDEX,
+ .expected = 0,
+ .condition_offset = 0,
+ .condition_mask = MI_FLUSH_DW_OP_MASK
}},
- .bits_count = 2 ),
+ .bits_count = 3 ),
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
.bits = {{
.offset = 0,
@@ -231,8 +239,15 @@ static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
.expected = 0,
.condition_offset = 0,
.condition_mask = MI_FLUSH_DW_OP_MASK
+ },
+ {
+ .offset = 0,
+ .mask = MI_FLUSH_DW_STORE_INDEX,
+ .expected = 0,
+ .condition_offset = 0,
+ .condition_mask = MI_FLUSH_DW_OP_MASK
}},
- .bits_count = 2 ),
+ .bits_count = 3 ),
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
.bits = {{
.offset = 0,
@@ -264,8 +279,15 @@ static const struct drm_i915_cmd_descriptor blt_cmds[] = {
.expected = 0,
.condition_offset = 0,
.condition_mask = MI_FLUSH_DW_OP_MASK
+ },
+ {
+ .offset = 0,
+ .mask = MI_FLUSH_DW_STORE_INDEX,
+ .expected = 0,
+ .condition_offset = 0,
+ .condition_mask = MI_FLUSH_DW_OP_MASK
}},
- .bits_count = 2 ),
+ .bits_count = 3 ),
CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ff263f4..5f77cb6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -324,6 +324,7 @@
#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
#define PIPE_CONTROL_MMIO_WRITE (1<<23)
+#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
#define PIPE_CONTROL_CS_STALL (1<<20)
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
#define PIPE_CONTROL_QW_WRITE (1<<14)
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 11/13] drm/i915: Reject commands that would store to global HWS page
2014-01-29 21:55 ` [PATCH 11/13] drm/i915: Reject commands that would store to global HWS page bradley.d.volkin
@ 2014-02-05 15:39 ` Jani Nikula
0 siblings, 0 replies; 138+ messages in thread
From: Jani Nikula @ 2014-02-05 15:39 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> PIPE_CONTROL and MI_FLUSH_DW have bits that would write to the
> hardware status page. The driver stores request tracking info
> there, so don't let userspace overwrite it.
>
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 26072a2..b93df1c 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -141,7 +141,8 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
> },
> {
> .offset = 1,
> - .mask = PIPE_CONTROL_GLOBAL_GTT_IVB,
> + .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
> + PIPE_CONTROL_STORE_DATA_INDEX),
> .expected = 0,
> .condition_offset = 1,
> .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK
> @@ -192,8 +193,15 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = {
> .expected = 0,
> .condition_offset = 0,
> .condition_mask = MI_FLUSH_DW_OP_MASK
> + },
> + {
> + .offset = 0,
> + .mask = MI_FLUSH_DW_STORE_INDEX,
> + .expected = 0,
> + .condition_offset = 0,
> + .condition_mask = MI_FLUSH_DW_OP_MASK
> }},
> - .bits_count = 2 ),
> + .bits_count = 3 ),
I'm disliking this separate .bits_count more at every change...
> CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
> .bits = {{
> .offset = 0,
> @@ -231,8 +239,15 @@ static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
> .expected = 0,
> .condition_offset = 0,
> .condition_mask = MI_FLUSH_DW_OP_MASK
> + },
> + {
> + .offset = 0,
> + .mask = MI_FLUSH_DW_STORE_INDEX,
> + .expected = 0,
> + .condition_offset = 0,
> + .condition_mask = MI_FLUSH_DW_OP_MASK
> }},
> - .bits_count = 2 ),
> + .bits_count = 3 ),
> CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
> .bits = {{
> .offset = 0,
> @@ -264,8 +279,15 @@ static const struct drm_i915_cmd_descriptor blt_cmds[] = {
> .expected = 0,
> .condition_offset = 0,
> .condition_mask = MI_FLUSH_DW_OP_MASK
> + },
> + {
> + .offset = 0,
> + .mask = MI_FLUSH_DW_STORE_INDEX,
> + .expected = 0,
> + .condition_offset = 0,
> + .condition_mask = MI_FLUSH_DW_OP_MASK
> }},
> - .bits_count = 2 ),
> + .bits_count = 3 ),
> CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
> CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
> };
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ff263f4..5f77cb6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -324,6 +324,7 @@
> #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
> #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
> #define PIPE_CONTROL_MMIO_WRITE (1<<23)
> +#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
> #define PIPE_CONTROL_CS_STALL (1<<20)
> #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
> #define PIPE_CONTROL_QW_WRITE (1<<14)
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 12/13] drm/i915: Add a CMD_PARSER_VERSION getparam
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (10 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 11/13] drm/i915: Reject commands that would store to global HWS page bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-01-30 9:19 ` Daniel Vetter
2014-01-29 21:55 ` [PATCH 13/13] drm/i915: Enable command parsing by default bradley.d.volkin
` (2 subsequent siblings)
14 siblings, 1 reply; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
So userspace can query the kernel for command parser support.
OTC-Tracker: AXIA-4631
Change-Id: I58af650db9f6753c2dcac9c54ab432fd31db302f
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 4 ++++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 258b1be..34ba199 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1013,6 +1013,10 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_EXEC_HANDLE_LUT:
value = 1;
break;
+ case I915_PARAM_CMD_PARSER_VERSION:
+ /* TODO: version info (e.g. what is allowed?) */
+ value = 1;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 126bfaa..8a3e4ef00 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -337,6 +337,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_EXEC_NO_RELOC 25
#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
#define I915_PARAM_HAS_WT 27
+#define I915_PARAM_CMD_PARSER_VERSION 28
typedef struct drm_i915_getparam {
int param;
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 12/13] drm/i915: Add a CMD_PARSER_VERSION getparam
2014-01-29 21:55 ` [PATCH 12/13] drm/i915: Add a CMD_PARSER_VERSION getparam bradley.d.volkin
@ 2014-01-30 9:19 ` Daniel Vetter
2014-01-30 17:25 ` Volkin, Bradley D
0 siblings, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-01-30 9:19 UTC (permalink / raw)
To: bradley.d.volkin; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 01:55:13PM -0800, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> So userspace can query the kernel for command parser support.
>
> OTC-Tracker: AXIA-4631
> Change-Id: I58af650db9f6753c2dcac9c54ab432fd31db302f
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 4 ++++
> include/uapi/drm/i915_drm.h | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 258b1be..34ba199 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1013,6 +1013,10 @@ static int i915_getparam(struct drm_device *dev, void *data,
> case I915_PARAM_HAS_EXEC_HANDLE_LUT:
> value = 1;
> break;
> + case I915_PARAM_CMD_PARSER_VERSION:
> + /* TODO: version info (e.g. what is allowed?) */
> + value = 1;
I think an increasing integer without any mean special grouping (like
major/minor) is good enough. What we need though is a small revision log
with one-line blurbs that explain what has been added, e.g.
1: Initial version.
2: Allow streamout related registers
3: Add gen8 support
...
I think it would be good to have this as a comment right next to the
parser code itself, so what about adding a i915_cmd_parser_get_version
function to i915_cmd_parser.c who's only job is to return and integer and
contain this comment?
-Daniel
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 126bfaa..8a3e4ef00 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -337,6 +337,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_HAS_EXEC_NO_RELOC 25
> #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
> #define I915_PARAM_HAS_WT 27
> +#define I915_PARAM_CMD_PARSER_VERSION 28
>
> typedef struct drm_i915_getparam {
> int param;
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 12/13] drm/i915: Add a CMD_PARSER_VERSION getparam
2014-01-30 9:19 ` Daniel Vetter
@ 2014-01-30 17:25 ` Volkin, Bradley D
0 siblings, 0 replies; 138+ messages in thread
From: Volkin, Bradley D @ 2014-01-30 17:25 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 30, 2014 at 01:19:15AM -0800, Daniel Vetter wrote:
> On Wed, Jan 29, 2014 at 01:55:13PM -0800, bradley.d.volkin@intel.com wrote:
> > From: Brad Volkin <bradley.d.volkin@intel.com>
> >
> > So userspace can query the kernel for command parser support.
> >
> > OTC-Tracker: AXIA-4631
> > Change-Id: I58af650db9f6753c2dcac9c54ab432fd31db302f
> > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 4 ++++
> > include/uapi/drm/i915_drm.h | 1 +
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index 258b1be..34ba199 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -1013,6 +1013,10 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > case I915_PARAM_HAS_EXEC_HANDLE_LUT:
> > value = 1;
> > break;
> > + case I915_PARAM_CMD_PARSER_VERSION:
> > + /* TODO: version info (e.g. what is allowed?) */
> > + value = 1;
>
> I think an increasing integer without any mean special grouping (like
> major/minor) is good enough. What we need though is a small revision log
> with one-line blurbs that explain what has been added, e.g.
>
> 1: Initial version.
> 2: Allow streamout related registers
> 3: Add gen8 support
>
> ...
>
> I think it would be good to have this as a comment right next to the
> parser code itself, so what about adding a i915_cmd_parser_get_version
> function to i915_cmd_parser.c who's only job is to return and integer and
> contain this comment?
> -Daniel
Agree on the revision log. I forgot that I left writing it as a todo.
I'll add i915_cmd_parser_get_version and fill that in.
- Brad
>
> > + break;
> > default:
> > DRM_DEBUG("Unknown parameter %d\n", param->param);
> > return -EINVAL;
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 126bfaa..8a3e4ef00 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -337,6 +337,7 @@ typedef struct drm_i915_irq_wait {
> > #define I915_PARAM_HAS_EXEC_NO_RELOC 25
> > #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
> > #define I915_PARAM_HAS_WT 27
> > +#define I915_PARAM_CMD_PARSER_VERSION 28
> >
> > typedef struct drm_i915_getparam {
> > int param;
> > --
> > 1.8.5.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread
* [PATCH 13/13] drm/i915: Enable command parsing by default
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (11 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 12/13] drm/i915: Add a CMD_PARSER_VERSION getparam bradley.d.volkin
@ 2014-01-29 21:55 ` bradley.d.volkin
2014-01-29 22:11 ` [PATCH 00/13] Gen7 batch buffer command parser Daniel Vetter
2014-02-05 15:41 ` Jani Nikula
14 siblings, 0 replies; 138+ messages in thread
From: bradley.d.volkin @ 2014-01-29 21:55 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
OTC-Tracker: AXIA-4631
Change-Id: I6747457e1fe7494bd42787af51198fcba398ad78
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 6d3d906..981b635 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -47,7 +47,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.reset = true,
.invert_brightness = 0,
- .enable_cmd_parser = 0
+ .enable_cmd_parser = 1
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -157,4 +157,4 @@ MODULE_PARM_DESC(invert_brightness,
module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
MODULE_PARM_DESC(enable_cmd_parser,
- "Enable command parsing (default: false)");
+ "Enable command parsing (default: true)");
--
1.8.5.2
^ permalink raw reply related [flat|nested] 138+ messages in thread* Re: [PATCH 00/13] Gen7 batch buffer command parser
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (12 preceding siblings ...)
2014-01-29 21:55 ` [PATCH 13/13] drm/i915: Enable command parsing by default bradley.d.volkin
@ 2014-01-29 22:11 ` Daniel Vetter
2014-01-29 22:22 ` Volkin, Bradley D
2014-02-05 15:41 ` Jani Nikula
14 siblings, 1 reply; 138+ messages in thread
From: Daniel Vetter @ 2014-01-29 22:11 UTC (permalink / raw)
To: bradley.d.volkin; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 01:55:01PM -0800, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
> 3) Coherency. I've found a coherency issue on VLV when reading the batch buffer
> from the CPU during execbuffer2. Userspace writes the batch via pwrite fast
> path before calling execbuffer2. The parser reads stale data. This works fine
> on IVB and HSW, so I believe it's an LLC vs. non-LLC issue. I'm just unclear
> on what the correct flushing or synchronization is for this scenario. This
> only matters if we get PPGTT working on VLV and enable the parser there.
Hm, adopting the shmem_read clflushing didn't help for this? That would be
fairly shocking, since it means our shmem read paths are broken. Which are
used e.g. by the libva readback code for the encoded bitstream.
One thing aside: When resending the complete series (even if it's just a
subset) it's better to start a new thread. We tend to use in-reply-to only
when resending individual patches, while the review discussion is still
ongoing. That way the discussion stays together. But when there's been a
bit a longer break it's imo better to start a new thread.
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread* Re: [PATCH 00/13] Gen7 batch buffer command parser
2014-01-29 22:11 ` [PATCH 00/13] Gen7 batch buffer command parser Daniel Vetter
@ 2014-01-29 22:22 ` Volkin, Bradley D
2014-01-29 23:31 ` Daniel Vetter
0 siblings, 1 reply; 138+ messages in thread
From: Volkin, Bradley D @ 2014-01-29 22:22 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 02:11:17PM -0800, Daniel Vetter wrote:
> On Wed, Jan 29, 2014 at 01:55:01PM -0800, bradley.d.volkin@intel.com wrote:
> > From: Brad Volkin <bradley.d.volkin@intel.com>
> > 3) Coherency. I've found a coherency issue on VLV when reading the batch buffer
> > from the CPU during execbuffer2. Userspace writes the batch via pwrite fast
> > path before calling execbuffer2. The parser reads stale data. This works fine
> > on IVB and HSW, so I believe it's an LLC vs. non-LLC issue. I'm just unclear
> > on what the correct flushing or synchronization is for this scenario. This
> > only matters if we get PPGTT working on VLV and enable the parser there.
>
> Hm, adopting the shmem_read clflushing didn't help for this? That would be
> fairly shocking, since it means our shmem read paths are broken. Which are
> used e.g. by the libva readback code for the encoded bitstream.
Sorry, not clear enough. I actually haven't retested that part with the clflushing
added since the opinion seemed to be that leaving the parser disabled for VLV was ok.
Just left the note for now so it doesn't get lost.
>
> One thing aside: When resending the complete series (even if it's just a
> subset) it's better to start a new thread. We tend to use in-reply-to only
> when resending individual patches, while the review discussion is still
> ongoing. That way the discussion stays together. But when there's been a
> bit a longer break it's imo better to start a new thread.
Ok, I thought it was more of a blanket thing. Noted.
-Brad
>
> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 00/13] Gen7 batch buffer command parser
2014-01-29 22:22 ` Volkin, Bradley D
@ 2014-01-29 23:31 ` Daniel Vetter
0 siblings, 0 replies; 138+ messages in thread
From: Daniel Vetter @ 2014-01-29 23:31 UTC (permalink / raw)
To: Volkin, Bradley D; +Cc: intel-gfx
On Wed, Jan 29, 2014 at 02:22:49PM -0800, Volkin, Bradley D wrote:
> On Wed, Jan 29, 2014 at 02:11:17PM -0800, Daniel Vetter wrote:
> > On Wed, Jan 29, 2014 at 01:55:01PM -0800, bradley.d.volkin@intel.com wrote:
> > > From: Brad Volkin <bradley.d.volkin@intel.com>
> > > 3) Coherency. I've found a coherency issue on VLV when reading the batch buffer
> > > from the CPU during execbuffer2. Userspace writes the batch via pwrite fast
> > > path before calling execbuffer2. The parser reads stale data. This works fine
> > > on IVB and HSW, so I believe it's an LLC vs. non-LLC issue. I'm just unclear
> > > on what the correct flushing or synchronization is for this scenario. This
> > > only matters if we get PPGTT working on VLV and enable the parser there.
> >
> > Hm, adopting the shmem_read clflushing didn't help for this? That would be
> > fairly shocking, since it means our shmem read paths are broken. Which are
> > used e.g. by the libva readback code for the encoded bitstream.
>
> Sorry, not clear enough. I actually haven't retested that part with the clflushing
> added since the opinion seemed to be that leaving the parser disabled for VLV was ok.
> Just left the note for now so it doesn't get lost.
Would be nice to give it spin though, since afaik this issue might persist
on vlv+1. And I guess we can't keep on sticking our heads into sand about
ppgtt not really working on soc platforms ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 138+ messages in thread
* Re: [PATCH 00/13] Gen7 batch buffer command parser
2014-01-29 21:55 ` [PATCH 00/13] " bradley.d.volkin
` (13 preceding siblings ...)
2014-01-29 22:11 ` [PATCH 00/13] Gen7 batch buffer command parser Daniel Vetter
@ 2014-02-05 15:41 ` Jani Nikula
14 siblings, 0 replies; 138+ messages in thread
From: Jani Nikula @ 2014-02-05 15:41 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
FYI, I did an initial review "sweep" of this. Will focus more on the
logic and registers etc. next.
BR,
Jani.
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> Certain OpenGL features (e.g. transform feedback, performance monitoring)
> require userspace code to submit batches containing commands such as
> MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
> generations of the hardware will noop these commands in "unsecure" batches
> (which includes all userspace batches submitted via i915) even though the
> commands may be safe and represent the intended programming model of the device.
>
> This series introduces a software command parser similar in operation to the
> command parsing done in hardware for unsecure batches. However, the software
> parser allows some operations that would be noop'd by hardware, if the parser
> determines the operation is safe, and submits the batch as "secure" to prevent
> hardware parsing. Currently the series implements this on IVB and HSW.
>
> The series has one piece of prep work, one patch for the parser logic, and a
> handful of patches to fill out the tables which drive the parser. There are
> follow-up patches to libdrm and to i-g-t. The i-g-t tests are basic and do not
> test all of the commands used by the parser on the assumption that I'm likely
> to make the same mistakes in both the parser and the test.
>
> WARNING!!!
> I've previously run the i-g-t gem_* tests, the piglit quick tests, and generally
> used Ubuntu 13.10 IVB and HSW systems with the parser running. Aside from a
> failure described below, I did not see any regressions. However, the series
> currently hits a BUG_ON() if you enable the parser due to a regression in secure
> batch handling on -nightly.
>
> At this point there are a couple of required/potential improvements.
>
> 1) Chained batches. The parser currently allows MI_BATCH_BUFFER_START commands
> in userspace batches without parsing them. The media driver uses chained
> batches, so a solution is required. I'm still working through the
> requirements but don't want to continue delaying the review process for what
> I have so far.
> 2) Command buffer copy. To avoid CPU modifications to buffers after parsing, and
> to avoid GPU modifications to buffers via EUs or commands in the batch, we
> should copy the userspace batch buffer to memory that userspace does not
> have access to, map it into GGTT, and execute that batch buffer. I have a
> sense of how to do this for 1st-level batches, but it may need changes to
> tie in with the chained batch parsing, so I've again held off.
> 3) Coherency. I've found a coherency issue on VLV when reading the batch buffer
> from the CPU during execbuffer2. Userspace writes the batch via pwrite fast
> path before calling execbuffer2. The parser reads stale data. This works fine
> on IVB and HSW, so I believe it's an LLC vs. non-LLC issue. I'm just unclear
> on what the correct flushing or synchronization is for this scenario. This
> only matters if we get PPGTT working on VLV and enable the parser there.
>
> v2:
> - Significantly reorder series
> - Scan secure batches (i.e. I915_EXEC_SECURE)
> - Check that parser tables are sorted during init
> - Fixed gem_cpu_reloc regression
> - HAS_CMD_PARSER -> CMD_PARSER_VERSION getparam
> - Additional tests
>
> Brad Volkin (13):
> drm/i915: Refactor shmem pread setup
> drm/i915: Implement command buffer parsing logic
> drm/i915: Initial command parser table definitions
> drm/i915: Reject privileged commands
> drm/i915: Allow some privileged commands from master
> drm/i915: Add register whitelists for mesa
> drm/i915: Add register whitelist for DRM master
> drm/i915: Enable register whitelist checks
> drm/i915: Reject commands that explicitly generate interrupts
> drm/i915: Enable PPGTT command parser checks
> drm/i915: Reject commands that would store to global HWS page
> drm/i915: Add a CMD_PARSER_VERSION getparam
> drm/i915: Enable command parsing by default
>
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/i915_cmd_parser.c | 845 +++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_dma.c | 4 +
> drivers/gpu/drm/i915/i915_drv.h | 103 ++++
> drivers/gpu/drm/i915/i915_gem.c | 48 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 17 +
> drivers/gpu/drm/i915/i915_params.c | 5 +
> drivers/gpu/drm/i915/i915_reg.h | 78 +++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +
> drivers/gpu/drm/i915/intel_ringbuffer.h | 32 ++
> include/uapi/drm/i915_drm.h | 1 +
> 11 files changed, 1123 insertions(+), 15 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/i915_cmd_parser.c
>
> --
> 1.8.5.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 138+ messages in thread