[PATCH 1/2] zynq: Do not explicitely enable icache

[PATCH 1/2] zynq: Do not explicitely enable icache

[Michal Simek]

icache is already enabled by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 board/xilinx/zynq/board.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 5119c09..7c1632f 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -49,8 +49,6 @@ int board_init(void)
 	}
 #endif

-	icache_enable();
-
 #ifdef CONFIG_FPGA
 	fpga_init();
 	fpga_add(fpga_xilinx, &fpga);
--
1.8.2.3

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[U-Boot] [PATCH 1/2] zynq: Do not explicitely enable icache

[Michal Simek]

icache is already enabled by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 board/xilinx/zynq/board.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 5119c09..7c1632f 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -49,8 +49,6 @@ int board_init(void)
 	}
 #endif

-	icache_enable();
-
 #ifdef CONFIG_FPGA
 	fpga_init();
 	fpga_add(fpga_xilinx, &fpga);
--
1.8.2.3

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[PATCH 2/2] zynq: Enable dcache support

[Michal Simek]

Enable dcache.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv7/zynq/cpu.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 9af340e..c771759 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -46,3 +46,11 @@ void reset_cpu(ulong addr)
 	while (1)
 		;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
--
1.8.2.3

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[U-Boot] [PATCH 2/2] zynq: Enable dcache support

[Michal Simek]

Enable dcache.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv7/zynq/cpu.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 9af340e..c771759 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -46,3 +46,11 @@ void reset_cpu(ulong addr)
 	while (1)
 		;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
--
1.8.2.3

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[PATCH 1/2] zynq: Do not explicitely enable icache

[Arnd Bergmann]

On Friday 03 January 2014, Michal Simek wrote:
> icache is already enabled by default.
> 
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> 
>  board/xilinx/zynq/board.c | 2 --
>  1 file changed, 2 deletions(-)

You had me confused for a bit. Please mark u-boot patches as such
when you send them to the kernel mailing list, and vice-versa.

	Arnd

[U-Boot] [PATCH 1/2] zynq: Do not explicitely enable icache

[Arnd Bergmann]

On Friday 03 January 2014, Michal Simek wrote:
> icache is already enabled by default.
> 
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> 
>  board/xilinx/zynq/board.c | 2 --
>  1 file changed, 2 deletions(-)

You had me confused for a bit. Please mark u-boot patches as such
when you send them to the kernel mailing list, and vice-versa.

	Arnd

[PATCH 1/2] zynq: Do not explicitely enable icache

[Michal Simek]

On 01/03/2014 01:52 PM, Arnd Bergmann wrote:
> On Friday 03 January 2014, Michal Simek wrote:
>> icache is already enabled by default.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>>  board/xilinx/zynq/board.c | 2 --
>>  1 file changed, 2 deletions(-)
> 
> You had me confused for a bit. Please mark u-boot patches as such
> when you send them to the kernel mailing list, and vice-versa.

oou. Patman (tools I use for sending patches to mailing list)
took arm prefix because of my bad setting.

Sorry for that.

Thanks,
Michal



-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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[PATCH 1/2] zynq: Do not explicitely enable icache

[Russell King - ARM Linux]

On Fri, Jan 03, 2014 at 01:52:51PM +0100, Arnd Bergmann wrote:
> On Friday 03 January 2014, Michal Simek wrote:
> > icache is already enabled by default.
> > 
> > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> > ---
> > 
> >  board/xilinx/zynq/board.c | 2 --
> >  1 file changed, 2 deletions(-)
> 
> You had me confused for a bit. Please mark u-boot patches as such
> when you send them to the kernel mailing list, and vice-versa.

Better still, they shouldn't be sent to the kernel mailing lists in the
first place - they're off-topic here.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[U-Boot] [PATCH 1/2] zynq: Do not explicitely enable icache

[Russell King - ARM Linux]

On Fri, Jan 03, 2014 at 01:52:51PM +0100, Arnd Bergmann wrote:
> On Friday 03 January 2014, Michal Simek wrote:
> > icache is already enabled by default.
> > 
> > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> > ---
> > 
> >  board/xilinx/zynq/board.c | 2 --
> >  1 file changed, 2 deletions(-)
> 
> You had me confused for a bit. Please mark u-boot patches as such
> when you send them to the kernel mailing list, and vice-versa.

Better still, they shouldn't be sent to the kernel mailing lists in the
first place - they're off-topic here.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".