[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

The following patch series moves code to setup the DMA hardware and
service interrupts from the hardware to the DMA engine driver.  This
reduces the dependency on the legacy DMA implementation.

This series does not remove the channel allocation/freeing hooks which
are used to manage the allocation of physical channels - this is the
next step in the evolution.

The patches which move the interrupt handling are currently less than
perfect since they're writing to ENABLE_L0 under a different spinlock,
and hence RFC only at the moment.

 arch/arm/mach-omap1/dma.c |  183 +++++--------
 arch/arm/mach-omap2/dma.c |  183 ++++++--------
 arch/arm/plat-omap/dma.c  |   17 +-
 drivers/dma/omap-dma.c    |  653 ++++++++++++++++++++++++++++++++++++++++-----
 include/linux/omap-dma.h  |   25 ++-
 5 files changed, 774 insertions(+), 287 deletions(-)

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

The following patch series moves code to setup the DMA hardware and
service interrupts from the hardware to the DMA engine driver.  This
reduces the dependency on the legacy DMA implementation.

This series does not remove the channel allocation/freeing hooks which
are used to manage the allocation of physical channels - this is the
next step in the evolution.

The patches which move the interrupt handling are currently less than
perfect since they're writing to ENABLE_L0 under a different spinlock,
and hence RFC only at the moment.

 arch/arm/mach-omap1/dma.c |  183 +++++--------
 arch/arm/mach-omap2/dma.c |  183 ++++++--------
 arch/arm/plat-omap/dma.c  |   17 +-
 drivers/dma/omap-dma.c    |  653 ++++++++++++++++++++++++++++++++++++++++-----
 include/linux/omap-dma.h  |   25 ++-
 5 files changed, 774 insertions(+), 287 deletions(-)

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 01/26] dmaengine: omap-dma: use devm_kzalloc() to allocate omap_dmadev.

[Russell King]

Use devm_kzalloc() to allocate omap_dmadev() so that we don't need
complex error cleanup paths.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 2f66cf4e54fe..d9349be33bdf 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -594,7 +594,6 @@ static void omap_dma_free(struct omap_dmadev *od)
 		tasklet_kill(&c->vc.task);
 		kfree(c);
 	}
-	kfree(od);
 }
 
 static int omap_dma_probe(struct platform_device *pdev)
@@ -602,7 +601,7 @@ static int omap_dma_probe(struct platform_device *pdev)
 	struct omap_dmadev *od;
 	int rc, i;
 
-	od = kzalloc(sizeof(*od), GFP_KERNEL);
+	od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 	if (!od)
 		return -ENOMEM;
 
-- 
1.7.4.4

[PATCH RFC 01/26] dmaengine: omap-dma: use devm_kzalloc() to allocate omap_dmadev.

[Russell King]

Use devm_kzalloc() to allocate omap_dmadev() so that we don't need
complex error cleanup paths.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 2f66cf4e54fe..d9349be33bdf 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -594,7 +594,6 @@ static void omap_dma_free(struct omap_dmadev *od)
 		tasklet_kill(&c->vc.task);
 		kfree(c);
 	}
-	kfree(od);
 }
 
 static int omap_dma_probe(struct platform_device *pdev)
@@ -602,7 +601,7 @@ static int omap_dma_probe(struct platform_device *pdev)
 	struct omap_dmadev *od;
 	int rc, i;
 
-	od = kzalloc(sizeof(*od), GFP_KERNEL);
+	od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 	if (!od)
 		return -ENOMEM;
 
-- 
1.7.4.4

[PATCH RFC 02/26] dmaengine: omap-dma: provide a hook to get the underlying DMA platform ops

[Russell King]

Provide and use a hook to obtain the underlying DMA platform operations
so that omap-dma.c can access the hardware more directly without
involving the legacy DMA driver.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/plat-omap/dma.c |    6 ++++++
 drivers/dma/omap-dma.c   |    7 +++++++
 include/linux/omap-dma.h |    2 ++
 3 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 01619c2910e3..d4d9a5e62152 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2000,6 +2000,12 @@ void omap_dma_global_context_restore(void)
 			omap_clear_dma(ch);
 }
 
+struct omap_system_dma_plat_info *omap_get_plat_info(void)
+{
+	return p;
+}
+EXPORT_SYMBOL_GPL(omap_get_plat_info);
+
 static int omap_system_dma_probe(struct platform_device *pdev)
 {
 	int ch, ret = 0;
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index d9349be33bdf..3c1bb34aad0a 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -26,11 +26,13 @@ struct omap_dmadev {
 	spinlock_t lock;
 	struct tasklet_struct task;
 	struct list_head pending;
+	struct omap_system_dma_plat_info *plat;
 };
 
 struct omap_chan {
 	struct virt_dma_chan vc;
 	struct list_head node;
+	struct omap_system_dma_plat_info *plat;
 
 	struct dma_slave_config	cfg;
 	unsigned dma_sig;
@@ -573,6 +575,7 @@ static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
 	if (!c)
 		return -ENOMEM;
 
+	c->plat = od->plat;
 	c->dma_sig = dma_sig;
 	c->vc.desc_free = omap_dma_desc_free;
 	vchan_init(&c->vc, &od->ddev);
@@ -605,6 +608,10 @@ static int omap_dma_probe(struct platform_device *pdev)
 	if (!od)
 		return -ENOMEM;
 
+	od->plat = omap_get_plat_info();
+	if (!od->plat)
+		return -EPROBE_DEFER;
+
 	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 	dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 	od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 7af25a9c9c51..14742fc2aefe 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -292,6 +292,8 @@ struct omap_system_dma_plat_info {
 #define dma_omap15xx()	((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
 #define dma_omap16xx()	((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
 
+extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
+
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
 			void (*callback)(int lch, u16 ch_status, void *data),
-- 
1.7.4.4

[PATCH RFC 02/26] dmaengine: omap-dma: provide a hook to get the underlying DMA platform ops

[Russell King]

Provide and use a hook to obtain the underlying DMA platform operations
so that omap-dma.c can access the hardware more directly without
involving the legacy DMA driver.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/plat-omap/dma.c |    6 ++++++
 drivers/dma/omap-dma.c   |    7 +++++++
 include/linux/omap-dma.h |    2 ++
 3 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 01619c2910e3..d4d9a5e62152 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2000,6 +2000,12 @@ void omap_dma_global_context_restore(void)
 			omap_clear_dma(ch);
 }
 
+struct omap_system_dma_plat_info *omap_get_plat_info(void)
+{
+	return p;
+}
+EXPORT_SYMBOL_GPL(omap_get_plat_info);
+
 static int omap_system_dma_probe(struct platform_device *pdev)
 {
 	int ch, ret = 0;
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index d9349be33bdf..3c1bb34aad0a 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -26,11 +26,13 @@ struct omap_dmadev {
 	spinlock_t lock;
 	struct tasklet_struct task;
 	struct list_head pending;
+	struct omap_system_dma_plat_info *plat;
 };
 
 struct omap_chan {
 	struct virt_dma_chan vc;
 	struct list_head node;
+	struct omap_system_dma_plat_info *plat;
 
 	struct dma_slave_config	cfg;
 	unsigned dma_sig;
@@ -573,6 +575,7 @@ static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
 	if (!c)
 		return -ENOMEM;
 
+	c->plat = od->plat;
 	c->dma_sig = dma_sig;
 	c->vc.desc_free = omap_dma_desc_free;
 	vchan_init(&c->vc, &od->ddev);
@@ -605,6 +608,10 @@ static int omap_dma_probe(struct platform_device *pdev)
 	if (!od)
 		return -ENOMEM;
 
+	od->plat = omap_get_plat_info();
+	if (!od->plat)
+		return -EPROBE_DEFER;
+
 	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 	dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 	od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 7af25a9c9c51..14742fc2aefe 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -292,6 +292,8 @@ struct omap_system_dma_plat_info {
 #define dma_omap15xx()	((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
 #define dma_omap16xx()	((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
 
+extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
+
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
 			void (*callback)(int lch, u16 ch_status, void *data),
-- 
1.7.4.4

[PATCH RFC 03/26] dmaengine: omap-dma: program hardware directly

[Russell King]

Program the transfer parameters directly into the hardware, rather
than using the functions in arch/arm/plat-omap/dma.c.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c   |  144 ++++++++++++++++++++++++++++++++++++++++-----
 include/linux/omap-dma.h |    6 +-
 2 files changed, 132 insertions(+), 18 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 3c1bb34aad0a..dd233ca2cf5a 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -99,16 +99,96 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	unsigned idx)
 {
 	struct omap_sg *sg = d->sg + idx;
+	uint32_t val;
+
+	if (d->dir == DMA_DEV_TO_MEM) {
+		if (dma_omap1()) {
+			val = c->plat->dma_read(CSDP, c->dma_ch);
+			val &= ~(0x1f << 9);
+			val |= OMAP_DMA_PORT_EMIFF << 9;
+			c->plat->dma_write(val, CSDP, c->dma_ch);
+		}
 
-	if (d->dir == DMA_DEV_TO_MEM)
-		omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
-			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
-	else
-		omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
-			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(0x03 << 14);
+		val |= OMAP_DMA_AMODE_POST_INC << 14;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
+		c->plat->dma_write(0, CDEI, c->dma_ch);
+		c->plat->dma_write(0, CDFI, c->dma_ch);
+	} else {
+		if (dma_omap1()) {
+			val = c->plat->dma_read(CSDP, c->dma_ch);
+			val &= ~(0x1f << 2);
+			val |= OMAP_DMA_PORT_EMIFF << 2;
+			c->plat->dma_write(val, CSDP, c->dma_ch);
+		}
+
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(0x03 << 12);
+		val |= OMAP_DMA_AMODE_POST_INC << 12;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
+		c->plat->dma_write(0, CSEI, c->dma_ch);
+		c->plat->dma_write(0, CSFI, c->dma_ch);
+	}
+
+	val = c->plat->dma_read(CSDP, c->dma_ch);
+	val &= ~0x03;
+	val |= d->es;
+	c->plat->dma_write(val, CSDP, c->dma_ch);
+
+	if (dma_omap1()) {
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(1 << 5);
+		if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
+			val |= 1 << 5;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		val = c->plat->dma_read(CCR2, c->dma_ch);
+		val &= ~(1 << 2);
+		if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
+			val |= 1 << 2;
+		c->plat->dma_write(val, CCR2, c->dma_ch);
+	}
+
+	if (dma_omap2plus() && c->dma_sig) {
+		val = c->plat->dma_read(CCR, c->dma_ch);
+
+		/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
+		val &= ~((1 << 23) | (3 << 19) | 0x1f);
+		val |= (c->dma_sig & ~0x1f) << 14;
+		val |= c->dma_sig & 0x1f;
+
+		if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
+			val |= 1 << 5;
+		else
+			val &= ~(1 << 5);
 
-	omap_set_dma_transfer_params(c->dma_ch, d->es, sg->en, sg->fn,
-		d->sync_mode, c->dma_sig, d->sync_type);
+		if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
+			val |= 1 << 18;
+		else
+			val &= ~(1 << 18);
+
+		switch (d->sync_type) {
+		case OMAP_DMA_DST_SYNC_PREFETCH:
+			val &= ~(1 << 24);	/* dest synch */
+			val |= 1 << 23;		/* Prefetch */
+			break;
+		case 0:
+			val &= ~(1 << 24);	/* dest synch */
+			break;
+		default:
+			val |= 1 << 24;		/* source synch */
+			break;
+		}
+		c->plat->dma_write(val, CCR, c->dma_ch);
+	}
+
+	c->plat->dma_write(sg->en, CEN, c->dma_ch);
+	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
 
 	omap_start_dma(c->dma_ch);
 }
@@ -117,6 +197,7 @@ static void omap_dma_start_desc(struct omap_chan *c)
 {
 	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 	struct omap_desc *d;
+	uint32_t val;
 
 	if (!vd) {
 		c->desc = NULL;
@@ -128,12 +209,39 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->desc = d = to_omap_dma_desc(&vd->tx);
 	c->sgidx = 0;
 
-	if (d->dir == DMA_DEV_TO_MEM)
-		omap_set_dma_src_params(c->dma_ch, d->periph_port,
-			OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
-	else
-		omap_set_dma_dest_params(c->dma_ch, d->periph_port,
-			OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
+	if (d->dir == DMA_DEV_TO_MEM) {
+		if (dma_omap1()) {
+			val = c->plat->dma_read(CSDP, c->dma_ch);
+			val &= ~(0x1f << 2);
+			val |= d->periph_port << 2;
+			c->plat->dma_write(val, CSDP, c->dma_ch);
+		}
+
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(0x03 << 12);
+		val |= OMAP_DMA_AMODE_CONSTANT << 12;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
+		c->plat->dma_write(0, CSEI, c->dma_ch);
+		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
+	} else {
+		if (dma_omap1()) {
+			val = c->plat->dma_read(CSDP, c->dma_ch);
+			val &= ~(0x1f << 9);
+			val |= d->periph_port << 9;
+			c->plat->dma_write(val, CSDP, c->dma_ch);
+		}
+
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(0x03 << 14);
+		val |= OMAP_DMA_AMODE_CONSTANT << 14;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
+		c->plat->dma_write(0, CDEI, c->dma_ch);
+		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
+	}
 
 	omap_dma_start_sg(c, d, 0);
 }
@@ -452,8 +560,12 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	}
 
 	if (dma_omap2plus()) {
-		omap_set_dma_src_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
-		omap_set_dma_dest_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
+		uint32_t val;
+
+		val = c->plat->dma_read(CSDP, c->dma_ch);
+		val |= 0x03 << 7; /* src burst mode 16 */
+		val |= 0x03 << 14; /* dst burst mode 16 */
+		c->plat->dma_write(val, CSDP, c->dma_ch);
 	}
 
 	return vchan_tx_prep(&c->vc, &d->vd, flags);
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 14742fc2aefe..d631658e2237 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -289,8 +289,10 @@ struct omap_system_dma_plat_info {
 #define dma_omap2plus()	0
 #endif
 #define dma_omap1()	(!dma_omap2plus())
-#define dma_omap15xx()	((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
-#define dma_omap16xx()	((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
+#define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
+#define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
+#define dma_omap15xx()	__dma_omap15xx(d)
+#define dma_omap16xx()	__dma_omap16xx(d)
 
 extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
 
-- 
1.7.4.4

[PATCH RFC 03/26] dmaengine: omap-dma: program hardware directly

[Russell King]

Program the transfer parameters directly into the hardware, rather
than using the functions in arch/arm/plat-omap/dma.c.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c   |  144 ++++++++++++++++++++++++++++++++++++++++-----
 include/linux/omap-dma.h |    6 +-
 2 files changed, 132 insertions(+), 18 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 3c1bb34aad0a..dd233ca2cf5a 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -99,16 +99,96 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	unsigned idx)
 {
 	struct omap_sg *sg = d->sg + idx;
+	uint32_t val;
+
+	if (d->dir == DMA_DEV_TO_MEM) {
+		if (dma_omap1()) {
+			val = c->plat->dma_read(CSDP, c->dma_ch);
+			val &= ~(0x1f << 9);
+			val |= OMAP_DMA_PORT_EMIFF << 9;
+			c->plat->dma_write(val, CSDP, c->dma_ch);
+		}
 
-	if (d->dir == DMA_DEV_TO_MEM)
-		omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
-			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
-	else
-		omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
-			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(0x03 << 14);
+		val |= OMAP_DMA_AMODE_POST_INC << 14;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
+		c->plat->dma_write(0, CDEI, c->dma_ch);
+		c->plat->dma_write(0, CDFI, c->dma_ch);
+	} else {
+		if (dma_omap1()) {
+			val = c->plat->dma_read(CSDP, c->dma_ch);
+			val &= ~(0x1f << 2);
+			val |= OMAP_DMA_PORT_EMIFF << 2;
+			c->plat->dma_write(val, CSDP, c->dma_ch);
+		}
+
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(0x03 << 12);
+		val |= OMAP_DMA_AMODE_POST_INC << 12;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
+		c->plat->dma_write(0, CSEI, c->dma_ch);
+		c->plat->dma_write(0, CSFI, c->dma_ch);
+	}
+
+	val = c->plat->dma_read(CSDP, c->dma_ch);
+	val &= ~0x03;
+	val |= d->es;
+	c->plat->dma_write(val, CSDP, c->dma_ch);
+
+	if (dma_omap1()) {
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(1 << 5);
+		if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
+			val |= 1 << 5;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		val = c->plat->dma_read(CCR2, c->dma_ch);
+		val &= ~(1 << 2);
+		if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
+			val |= 1 << 2;
+		c->plat->dma_write(val, CCR2, c->dma_ch);
+	}
+
+	if (dma_omap2plus() && c->dma_sig) {
+		val = c->plat->dma_read(CCR, c->dma_ch);
+
+		/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
+		val &= ~((1 << 23) | (3 << 19) | 0x1f);
+		val |= (c->dma_sig & ~0x1f) << 14;
+		val |= c->dma_sig & 0x1f;
+
+		if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
+			val |= 1 << 5;
+		else
+			val &= ~(1 << 5);
 
-	omap_set_dma_transfer_params(c->dma_ch, d->es, sg->en, sg->fn,
-		d->sync_mode, c->dma_sig, d->sync_type);
+		if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
+			val |= 1 << 18;
+		else
+			val &= ~(1 << 18);
+
+		switch (d->sync_type) {
+		case OMAP_DMA_DST_SYNC_PREFETCH:
+			val &= ~(1 << 24);	/* dest synch */
+			val |= 1 << 23;		/* Prefetch */
+			break;
+		case 0:
+			val &= ~(1 << 24);	/* dest synch */
+			break;
+		default:
+			val |= 1 << 24;		/* source synch */
+			break;
+		}
+		c->plat->dma_write(val, CCR, c->dma_ch);
+	}
+
+	c->plat->dma_write(sg->en, CEN, c->dma_ch);
+	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
 
 	omap_start_dma(c->dma_ch);
 }
@@ -117,6 +197,7 @@ static void omap_dma_start_desc(struct omap_chan *c)
 {
 	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 	struct omap_desc *d;
+	uint32_t val;
 
 	if (!vd) {
 		c->desc = NULL;
@@ -128,12 +209,39 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->desc = d = to_omap_dma_desc(&vd->tx);
 	c->sgidx = 0;
 
-	if (d->dir == DMA_DEV_TO_MEM)
-		omap_set_dma_src_params(c->dma_ch, d->periph_port,
-			OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
-	else
-		omap_set_dma_dest_params(c->dma_ch, d->periph_port,
-			OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
+	if (d->dir == DMA_DEV_TO_MEM) {
+		if (dma_omap1()) {
+			val = c->plat->dma_read(CSDP, c->dma_ch);
+			val &= ~(0x1f << 2);
+			val |= d->periph_port << 2;
+			c->plat->dma_write(val, CSDP, c->dma_ch);
+		}
+
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(0x03 << 12);
+		val |= OMAP_DMA_AMODE_CONSTANT << 12;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
+		c->plat->dma_write(0, CSEI, c->dma_ch);
+		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
+	} else {
+		if (dma_omap1()) {
+			val = c->plat->dma_read(CSDP, c->dma_ch);
+			val &= ~(0x1f << 9);
+			val |= d->periph_port << 9;
+			c->plat->dma_write(val, CSDP, c->dma_ch);
+		}
+
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~(0x03 << 14);
+		val |= OMAP_DMA_AMODE_CONSTANT << 14;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
+		c->plat->dma_write(0, CDEI, c->dma_ch);
+		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
+	}
 
 	omap_dma_start_sg(c, d, 0);
 }
@@ -452,8 +560,12 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	}
 
 	if (dma_omap2plus()) {
-		omap_set_dma_src_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
-		omap_set_dma_dest_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
+		uint32_t val;
+
+		val = c->plat->dma_read(CSDP, c->dma_ch);
+		val |= 0x03 << 7; /* src burst mode 16 */
+		val |= 0x03 << 14; /* dst burst mode 16 */
+		c->plat->dma_write(val, CSDP, c->dma_ch);
 	}
 
 	return vchan_tx_prep(&c->vc, &d->vd, flags);
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 14742fc2aefe..d631658e2237 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -289,8 +289,10 @@ struct omap_system_dma_plat_info {
 #define dma_omap2plus()	0
 #endif
 #define dma_omap1()	(!dma_omap2plus())
-#define dma_omap15xx()	((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
-#define dma_omap16xx()	((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
+#define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
+#define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
+#define dma_omap15xx()	__dma_omap15xx(d)
+#define dma_omap16xx()	__dma_omap16xx(d)
 
 extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
 
-- 
1.7.4.4

Re: [PATCH RFC 03/26] dmaengine: omap-dma: program hardware directly

[Sricharan R]

On Thursday 02 January 2014 08:39 PM, Russell King wrote:
> Program the transfer parameters directly into the hardware, rather
> than using the functions in arch/arm/plat-omap/dma.c.
> 
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  drivers/dma/omap-dma.c   |  144 ++++++++++++++++++++++++++++++++++++++++-----
>  include/linux/omap-dma.h |    6 +-
>  2 files changed, 132 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
> index 3c1bb34aad0a..dd233ca2cf5a 100644
> --- a/drivers/dma/omap-dma.c
> +++ b/drivers/dma/omap-dma.c
> @@ -99,16 +99,96 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
>  	unsigned idx)
>  {
>  	struct omap_sg *sg = d->sg + idx;
> +	uint32_t val;
> +
> +	if (d->dir == DMA_DEV_TO_MEM) {
> +		if (dma_omap1()) {
> +			val = c->plat->dma_read(CSDP, c->dma_ch);
> +			val &= ~(0x1f << 9);
> +			val |= OMAP_DMA_PORT_EMIFF << 9;
> +			c->plat->dma_write(val, CSDP, c->dma_ch);
> +		}
>  
> -	if (d->dir == DMA_DEV_TO_MEM)
> -		omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
> -			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
> -	else
> -		omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
> -			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
> +		val = c->plat->dma_read(CCR, c->dma_ch);
> +		val &= ~(0x03 << 14);
> +		val |= OMAP_DMA_AMODE_POST_INC << 14;
> +		c->plat->dma_write(val, CCR, c->dma_ch);
> +
> +		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
> +		c->plat->dma_write(0, CDEI, c->dma_ch);
> +		c->plat->dma_write(0, CDFI, c->dma_ch);
> +	} else {
> +		if (dma_omap1()) {
> +			val = c->plat->dma_read(CSDP, c->dma_ch);
> +			val &= ~(0x1f << 2);
> +			val |= OMAP_DMA_PORT_EMIFF << 2;
> +			c->plat->dma_write(val, CSDP, c->dma_ch);
> +		}
> +
> +		val = c->plat->dma_read(CCR, c->dma_ch);
> +		val &= ~(0x03 << 12);
> +		val |= OMAP_DMA_AMODE_POST_INC << 12;
> +		c->plat->dma_write(val, CCR, c->dma_ch);
> +
> +		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
> +		c->plat->dma_write(0, CSEI, c->dma_ch);
> +		c->plat->dma_write(0, CSFI, c->dma_ch);
> +	}
> +
EI and FI are always set to zero. So interleaved transfers support
have to enabled in omap-dma, as it was supported by the
legacy driver. It was not enabled because of no users of the feature,
 right  ?

Regards,
 Sricharan

[PATCH RFC 03/26] dmaengine: omap-dma: program hardware directly

[Sricharan R]

On Thursday 02 January 2014 08:39 PM, Russell King wrote:
> Program the transfer parameters directly into the hardware, rather
> than using the functions in arch/arm/plat-omap/dma.c.
> 
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  drivers/dma/omap-dma.c   |  144 ++++++++++++++++++++++++++++++++++++++++-----
>  include/linux/omap-dma.h |    6 +-
>  2 files changed, 132 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
> index 3c1bb34aad0a..dd233ca2cf5a 100644
> --- a/drivers/dma/omap-dma.c
> +++ b/drivers/dma/omap-dma.c
> @@ -99,16 +99,96 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
>  	unsigned idx)
>  {
>  	struct omap_sg *sg = d->sg + idx;
> +	uint32_t val;
> +
> +	if (d->dir == DMA_DEV_TO_MEM) {
> +		if (dma_omap1()) {
> +			val = c->plat->dma_read(CSDP, c->dma_ch);
> +			val &= ~(0x1f << 9);
> +			val |= OMAP_DMA_PORT_EMIFF << 9;
> +			c->plat->dma_write(val, CSDP, c->dma_ch);
> +		}
>  
> -	if (d->dir == DMA_DEV_TO_MEM)
> -		omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
> -			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
> -	else
> -		omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
> -			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
> +		val = c->plat->dma_read(CCR, c->dma_ch);
> +		val &= ~(0x03 << 14);
> +		val |= OMAP_DMA_AMODE_POST_INC << 14;
> +		c->plat->dma_write(val, CCR, c->dma_ch);
> +
> +		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
> +		c->plat->dma_write(0, CDEI, c->dma_ch);
> +		c->plat->dma_write(0, CDFI, c->dma_ch);
> +	} else {
> +		if (dma_omap1()) {
> +			val = c->plat->dma_read(CSDP, c->dma_ch);
> +			val &= ~(0x1f << 2);
> +			val |= OMAP_DMA_PORT_EMIFF << 2;
> +			c->plat->dma_write(val, CSDP, c->dma_ch);
> +		}
> +
> +		val = c->plat->dma_read(CCR, c->dma_ch);
> +		val &= ~(0x03 << 12);
> +		val |= OMAP_DMA_AMODE_POST_INC << 12;
> +		c->plat->dma_write(val, CCR, c->dma_ch);
> +
> +		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
> +		c->plat->dma_write(0, CSEI, c->dma_ch);
> +		c->plat->dma_write(0, CSFI, c->dma_ch);
> +	}
> +
EI and FI are always set to zero. So interleaved transfers support
have to enabled in omap-dma, as it was supported by the
legacy driver. It was not enabled because of no users of the feature,
 right  ?

Regards,
 Sricharan

Re: [PATCH RFC 03/26] dmaengine: omap-dma: program hardware directly

[Russell King - ARM Linux]

On Wed, Jan 22, 2014 at 06:24:33PM +0530, Sricharan R wrote:
> EI and FI are always set to zero. So interleaved transfers support
> have to enabled in omap-dma, as it was supported by the
> legacy driver. It was not enabled because of no users of the feature,
>  right  ?

None of the users of the legacy driver used this feature.  Moreover,
dmaengine doesn't have the interfaces to support this specialised
feature at present.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 03/26] dmaengine: omap-dma: program hardware directly

[Russell King - ARM Linux]

On Wed, Jan 22, 2014 at 06:24:33PM +0530, Sricharan R wrote:
> EI and FI are always set to zero. So interleaved transfers support
> have to enabled in omap-dma, as it was supported by the
> legacy driver. It was not enabled because of no users of the feature,
>  right  ?

None of the users of the legacy driver used this feature.  Moreover,
dmaengine doesn't have the interfaces to support this specialised
feature at present.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 04/26] dmaengine: omap-dma: consolidate writes to DMA registers

[Russell King]

There's no need to keep writing registers which don't change value in
omap_dma_start_sg().  Move this into omap_dma_start_desc() and merge
the register updates together.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  123 +++++++++++++++++++-----------------------------
 1 files changed, 48 insertions(+), 75 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index dd233ca2cf5a..602c98aebca8 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -99,40 +99,75 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	unsigned idx)
 {
 	struct omap_sg *sg = d->sg + idx;
+
+	if (d->dir == DMA_DEV_TO_MEM) {
+		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
+		c->plat->dma_write(0, CDEI, c->dma_ch);
+		c->plat->dma_write(0, CDFI, c->dma_ch);
+	} else {
+		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
+		c->plat->dma_write(0, CSEI, c->dma_ch);
+		c->plat->dma_write(0, CSFI, c->dma_ch);
+	}
+
+	c->plat->dma_write(sg->en, CEN, c->dma_ch);
+	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
+
+	omap_start_dma(c->dma_ch);
+}
+
+static void omap_dma_start_desc(struct omap_chan *c)
+{
+	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
+	struct omap_desc *d;
 	uint32_t val;
 
+	if (!vd) {
+		c->desc = NULL;
+		return;
+	}
+
+	list_del(&vd->node);
+
+	c->desc = d = to_omap_dma_desc(&vd->tx);
+	c->sgidx = 0;
+
 	if (d->dir == DMA_DEV_TO_MEM) {
 		if (dma_omap1()) {
 			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 9);
+			val &= ~(0x1f << 9 | 0x1f << 2);
 			val |= OMAP_DMA_PORT_EMIFF << 9;
+			val |= d->periph_port << 2;
 			c->plat->dma_write(val, CSDP, c->dma_ch);
 		}
 
 		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 14);
+		val &= ~(0x03 << 14 | 0x03 << 12);
 		val |= OMAP_DMA_AMODE_POST_INC << 14;
+		val |= OMAP_DMA_AMODE_CONSTANT << 12;
 		c->plat->dma_write(val, CCR, c->dma_ch);
 
-		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
-		c->plat->dma_write(0, CDEI, c->dma_ch);
-		c->plat->dma_write(0, CDFI, c->dma_ch);
+		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
+		c->plat->dma_write(0, CSEI, c->dma_ch);
+		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
 	} else {
 		if (dma_omap1()) {
 			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 2);
+			val &= ~(0x1f << 9 | 0x1f << 2);
+			val |= d->periph_port << 9;
 			val |= OMAP_DMA_PORT_EMIFF << 2;
 			c->plat->dma_write(val, CSDP, c->dma_ch);
 		}
 
 		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 12);
+		val &= ~(0x03 << 12 | 0x03 << 14);
+		val |= OMAP_DMA_AMODE_CONSTANT << 14;
 		val |= OMAP_DMA_AMODE_POST_INC << 12;
 		c->plat->dma_write(val, CCR, c->dma_ch);
 
-		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
-		c->plat->dma_write(0, CSEI, c->dma_ch);
-		c->plat->dma_write(0, CSFI, c->dma_ch);
+		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
+		c->plat->dma_write(0, CDEI, c->dma_ch);
+		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
 	}
 
 	val = c->plat->dma_read(CSDP, c->dma_ch);
@@ -158,91 +193,29 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 		val = c->plat->dma_read(CCR, c->dma_ch);
 
 		/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
-		val &= ~((1 << 23) | (3 << 19) | 0x1f);
+		val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
 		val |= (c->dma_sig & ~0x1f) << 14;
 		val |= c->dma_sig & 0x1f;
 
 		if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
 			val |= 1 << 5;
-		else
-			val &= ~(1 << 5);
 
 		if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
 			val |= 1 << 18;
-		else
-			val &= ~(1 << 18);
 
 		switch (d->sync_type) {
-		case OMAP_DMA_DST_SYNC_PREFETCH:
-			val &= ~(1 << 24);	/* dest synch */
+		case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
 			val |= 1 << 23;		/* Prefetch */
 			break;
 		case 0:
-			val &= ~(1 << 24);	/* dest synch */
 			break;
 		default:
-			val |= 1 << 24;		/* source synch */
+			val |= 1 << 24; 	/* source synch */
 			break;
 		}
 		c->plat->dma_write(val, CCR, c->dma_ch);
 	}
 
-	c->plat->dma_write(sg->en, CEN, c->dma_ch);
-	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
-
-	omap_start_dma(c->dma_ch);
-}
-
-static void omap_dma_start_desc(struct omap_chan *c)
-{
-	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
-	struct omap_desc *d;
-	uint32_t val;
-
-	if (!vd) {
-		c->desc = NULL;
-		return;
-	}
-
-	list_del(&vd->node);
-
-	c->desc = d = to_omap_dma_desc(&vd->tx);
-	c->sgidx = 0;
-
-	if (d->dir == DMA_DEV_TO_MEM) {
-		if (dma_omap1()) {
-			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 2);
-			val |= d->periph_port << 2;
-			c->plat->dma_write(val, CSDP, c->dma_ch);
-		}
-
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 12);
-		val |= OMAP_DMA_AMODE_CONSTANT << 12;
-		c->plat->dma_write(val, CCR, c->dma_ch);
-
-		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
-		c->plat->dma_write(0, CSEI, c->dma_ch);
-		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
-	} else {
-		if (dma_omap1()) {
-			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 9);
-			val |= d->periph_port << 9;
-			c->plat->dma_write(val, CSDP, c->dma_ch);
-		}
-
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 14);
-		val |= OMAP_DMA_AMODE_CONSTANT << 14;
-		c->plat->dma_write(val, CCR, c->dma_ch);
-
-		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
-		c->plat->dma_write(0, CDEI, c->dma_ch);
-		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
-	}
-
 	omap_dma_start_sg(c, d, 0);
 }
 
-- 
1.7.4.4

[PATCH RFC 04/26] dmaengine: omap-dma: consolidate writes to DMA registers

[Russell King]

There's no need to keep writing registers which don't change value in
omap_dma_start_sg().  Move this into omap_dma_start_desc() and merge
the register updates together.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  123 +++++++++++++++++++-----------------------------
 1 files changed, 48 insertions(+), 75 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index dd233ca2cf5a..602c98aebca8 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -99,40 +99,75 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	unsigned idx)
 {
 	struct omap_sg *sg = d->sg + idx;
+
+	if (d->dir == DMA_DEV_TO_MEM) {
+		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
+		c->plat->dma_write(0, CDEI, c->dma_ch);
+		c->plat->dma_write(0, CDFI, c->dma_ch);
+	} else {
+		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
+		c->plat->dma_write(0, CSEI, c->dma_ch);
+		c->plat->dma_write(0, CSFI, c->dma_ch);
+	}
+
+	c->plat->dma_write(sg->en, CEN, c->dma_ch);
+	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
+
+	omap_start_dma(c->dma_ch);
+}
+
+static void omap_dma_start_desc(struct omap_chan *c)
+{
+	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
+	struct omap_desc *d;
 	uint32_t val;
 
+	if (!vd) {
+		c->desc = NULL;
+		return;
+	}
+
+	list_del(&vd->node);
+
+	c->desc = d = to_omap_dma_desc(&vd->tx);
+	c->sgidx = 0;
+
 	if (d->dir == DMA_DEV_TO_MEM) {
 		if (dma_omap1()) {
 			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 9);
+			val &= ~(0x1f << 9 | 0x1f << 2);
 			val |= OMAP_DMA_PORT_EMIFF << 9;
+			val |= d->periph_port << 2;
 			c->plat->dma_write(val, CSDP, c->dma_ch);
 		}
 
 		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 14);
+		val &= ~(0x03 << 14 | 0x03 << 12);
 		val |= OMAP_DMA_AMODE_POST_INC << 14;
+		val |= OMAP_DMA_AMODE_CONSTANT << 12;
 		c->plat->dma_write(val, CCR, c->dma_ch);
 
-		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
-		c->plat->dma_write(0, CDEI, c->dma_ch);
-		c->plat->dma_write(0, CDFI, c->dma_ch);
+		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
+		c->plat->dma_write(0, CSEI, c->dma_ch);
+		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
 	} else {
 		if (dma_omap1()) {
 			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 2);
+			val &= ~(0x1f << 9 | 0x1f << 2);
+			val |= d->periph_port << 9;
 			val |= OMAP_DMA_PORT_EMIFF << 2;
 			c->plat->dma_write(val, CSDP, c->dma_ch);
 		}
 
 		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 12);
+		val &= ~(0x03 << 12 | 0x03 << 14);
+		val |= OMAP_DMA_AMODE_CONSTANT << 14;
 		val |= OMAP_DMA_AMODE_POST_INC << 12;
 		c->plat->dma_write(val, CCR, c->dma_ch);
 
-		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
-		c->plat->dma_write(0, CSEI, c->dma_ch);
-		c->plat->dma_write(0, CSFI, c->dma_ch);
+		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
+		c->plat->dma_write(0, CDEI, c->dma_ch);
+		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
 	}
 
 	val = c->plat->dma_read(CSDP, c->dma_ch);
@@ -158,91 +193,29 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 		val = c->plat->dma_read(CCR, c->dma_ch);
 
 		/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
-		val &= ~((1 << 23) | (3 << 19) | 0x1f);
+		val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
 		val |= (c->dma_sig & ~0x1f) << 14;
 		val |= c->dma_sig & 0x1f;
 
 		if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
 			val |= 1 << 5;
-		else
-			val &= ~(1 << 5);
 
 		if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
 			val |= 1 << 18;
-		else
-			val &= ~(1 << 18);
 
 		switch (d->sync_type) {
-		case OMAP_DMA_DST_SYNC_PREFETCH:
-			val &= ~(1 << 24);	/* dest synch */
+		case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
 			val |= 1 << 23;		/* Prefetch */
 			break;
 		case 0:
-			val &= ~(1 << 24);	/* dest synch */
 			break;
 		default:
-			val |= 1 << 24;		/* source synch */
+			val |= 1 << 24; 	/* source synch */
 			break;
 		}
 		c->plat->dma_write(val, CCR, c->dma_ch);
 	}
 
-	c->plat->dma_write(sg->en, CEN, c->dma_ch);
-	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
-
-	omap_start_dma(c->dma_ch);
-}
-
-static void omap_dma_start_desc(struct omap_chan *c)
-{
-	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
-	struct omap_desc *d;
-	uint32_t val;
-
-	if (!vd) {
-		c->desc = NULL;
-		return;
-	}
-
-	list_del(&vd->node);
-
-	c->desc = d = to_omap_dma_desc(&vd->tx);
-	c->sgidx = 0;
-
-	if (d->dir == DMA_DEV_TO_MEM) {
-		if (dma_omap1()) {
-			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 2);
-			val |= d->periph_port << 2;
-			c->plat->dma_write(val, CSDP, c->dma_ch);
-		}
-
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 12);
-		val |= OMAP_DMA_AMODE_CONSTANT << 12;
-		c->plat->dma_write(val, CCR, c->dma_ch);
-
-		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
-		c->plat->dma_write(0, CSEI, c->dma_ch);
-		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
-	} else {
-		if (dma_omap1()) {
-			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 9);
-			val |= d->periph_port << 9;
-			c->plat->dma_write(val, CSDP, c->dma_ch);
-		}
-
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 14);
-		val |= OMAP_DMA_AMODE_CONSTANT << 14;
-		c->plat->dma_write(val, CCR, c->dma_ch);
-
-		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
-		c->plat->dma_write(0, CDEI, c->dma_ch);
-		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
-	}
-
 	omap_dma_start_sg(c, d, 0);
 }
 
-- 
1.7.4.4

[PATCH RFC 05/26] dmaengine: omap-dma: control start/stop directly

[Russell King]

Program the non-cyclic mode DMA start/stop directly, rather than via
arch/arm/plat-omap/dma.c.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  152 ++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 142 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 602c98aebca8..8e2dd4f658d5 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -5,6 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/delay.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/err.h>
@@ -60,6 +61,7 @@ struct omap_desc {
 	uint8_t sync_mode;	/* OMAP_DMA_SYNC_xxx */
 	uint8_t sync_type;	/* OMAP_DMA_xxx_SYNC* */
 	uint8_t periph_port;	/* Peripheral port */
+	uint16_t cicr;		/* CICR value */
 
 	unsigned sglen;
 	struct omap_sg sg[0];
@@ -95,6 +97,112 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
 	kfree(container_of(vd, struct omap_desc, vd));
 }
 
+static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	uint32_t val;
+
+	if (__dma_omap15xx(od->plat->dma_attr))
+		c->plat->dma_write(0, CPC, c->dma_ch);
+	else
+		c->plat->dma_write(0, CDAC, c->dma_ch);
+
+	if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
+		val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
+
+		if (dma_omap1())
+			val &= ~(1 << 14);
+
+		val |= c->dma_ch | 1 << 15;
+
+		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
+	} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
+		c->plat->dma_write(c->dma_ch, CLNK_CTRL, c->dma_ch);
+
+	/* Clear CSR */
+	if (dma_omap1())
+		c->plat->dma_read(CSR, c->dma_ch);
+	else
+		c->plat->dma_write(~0, CSR, c->dma_ch);
+
+	/* Enable interrupts */
+	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
+
+	val = c->plat->dma_read(CCR, c->dma_ch);
+	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
+		val |= OMAP_DMA_CCR_BUFFERING_DISABLE;
+	val |= OMAP_DMA_CCR_EN;
+	mb();
+	c->plat->dma_write(val, CCR, c->dma_ch);
+}
+
+static void omap_dma_stop(struct omap_chan *c)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	uint32_t val;
+
+	/* disable irq */
+	c->plat->dma_write(0, CICR, c->dma_ch);
+
+	/* Clear CSR */
+	if (dma_omap1())
+		c->plat->dma_read(CSR, c->dma_ch);
+	else
+		c->plat->dma_write(~0, CSR, c->dma_ch);
+
+	val = c->plat->dma_read(CCR, c->dma_ch);
+	if (od->plat->errata & DMA_ERRATA_i541 &&
+	    val & OMAP_DMA_CCR_SEL_SRC_DST_SYNC) {
+		uint32_t sysconfig;
+		unsigned i;
+
+		sysconfig = c->plat->dma_read(OCP_SYSCONFIG, c->dma_ch);
+		val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
+		val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
+		c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch);
+
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~OMAP_DMA_CCR_EN;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		/* Wait for sDMA FIFO to drain */
+		for (i = 0; ; i++) {
+			val = c->plat->dma_read(CCR, c->dma_ch);
+			if (!(val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE)))
+				break;
+
+			if (i > 100)
+				break;
+
+			udelay(5);
+		}
+
+		if (val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE))
+			dev_err(c->vc.chan.device->dev,
+				"DMA drain did not complete on lch %d\n",
+			        c->dma_ch);
+
+		c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch);
+	} else {
+		val &= ~OMAP_DMA_CCR_EN;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+	}
+
+	mb();
+
+	if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
+		val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
+
+		if (dma_omap1())
+			val |= 1 << 14; /* set the STOP_LNK bit */
+
+		if (dma_omap2plus())
+			val &= ~(1 << 15); /* Clear the ENABLE_LNK bit */
+
+		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
+	}
+}
+
 static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	unsigned idx)
 {
@@ -113,7 +221,7 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	c->plat->dma_write(sg->en, CEN, c->dma_ch);
 	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
 
-	omap_start_dma(c->dma_ch);
+	omap_dma_start(c, d);
 }
 
 static void omap_dma_start_desc(struct omap_chan *c)
@@ -436,6 +544,12 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	d->sync_mode = OMAP_DMA_SYNC_FRAME;
 	d->sync_type = sync_type;
 	d->periph_port = OMAP_DMA_PORT_TIPB;
+	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
+
+	if (dma_omap1())
+		d->cicr |= OMAP1_DMA_TOUT_IRQ;
+	else if (dma_omap2plus())
+		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 
 	/*
 	 * Build our scatterlist entries: each contains the address,
@@ -465,6 +579,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	size_t period_len, enum dma_transfer_direction dir, unsigned long flags,
 	void *context)
 {
+	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
 	enum dma_slave_buswidth dev_width;
 	struct omap_desc *d;
@@ -521,15 +636,25 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	d->sg[0].en = period_len / es_bytes[es];
 	d->sg[0].fn = buf_len / period_len;
 	d->sglen = 1;
+	d->cicr = OMAP_DMA_DROP_IRQ;
+	if (flags & DMA_PREP_INTERRUPT)
+		d->cicr |= OMAP_DMA_FRAME_IRQ;
+
+	if (dma_omap1())
+		d->cicr |= OMAP1_DMA_TOUT_IRQ;
+	else if (dma_omap2plus())
+		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 
 	if (!c->cyclic) {
 		c->cyclic = true;
-		omap_dma_link_lch(c->dma_ch, c->dma_ch);
 
-		if (flags & DMA_PREP_INTERRUPT)
-			omap_enable_dma_irq(c->dma_ch, OMAP_DMA_FRAME_IRQ);
+		if (__dma_omap15xx(od->plat->dma_attr)) {
+			uint32_t val;
 
-		omap_disable_dma_irq(c->dma_ch, OMAP_DMA_BLOCK_IRQ);
+			val = c->plat->dma_read(CCR, c->dma_ch);
+			val |= 3 << 8;
+			c->plat->dma_write(val, CCR, c->dma_ch);
+		}
 	}
 
 	if (dma_omap2plus()) {
@@ -570,20 +695,27 @@ static int omap_dma_terminate_all(struct omap_chan *c)
 
 	/*
 	 * Stop DMA activity: we assume the callback will not be called
-	 * after omap_stop_dma() returns (even if it does, it will see
+	 * after omap_dma_stop() returns (even if it does, it will see
 	 * c->desc is NULL and exit.)
 	 */
 	if (c->desc) {
 		c->desc = NULL;
 		/* Avoid stopping the dma twice */
 		if (!c->paused)
-			omap_stop_dma(c->dma_ch);
+			omap_dma_stop(c);
 	}
 
 	if (c->cyclic) {
 		c->cyclic = false;
 		c->paused = false;
-		omap_dma_unlink_lch(c->dma_ch, c->dma_ch);
+
+		if (__dma_omap15xx(od->plat->dma_attr)) {
+			uint32_t val;
+
+			val = c->plat->dma_read(CCR, c->dma_ch);
+			val &= ~(3 << 8);
+			c->plat->dma_write(val, CCR, c->dma_ch);
+		}
 	}
 
 	vchan_get_all_descriptors(&c->vc, &head);
@@ -600,7 +732,7 @@ static int omap_dma_pause(struct omap_chan *c)
 		return -EINVAL;
 
 	if (!c->paused) {
-		omap_stop_dma(c->dma_ch);
+		omap_dma_stop(c);
 		c->paused = true;
 	}
 
@@ -614,7 +746,7 @@ static int omap_dma_resume(struct omap_chan *c)
 		return -EINVAL;
 
 	if (c->paused) {
-		omap_start_dma(c->dma_ch);
+		omap_dma_start(c, c->desc);
 		c->paused = false;
 	}
 
-- 
1.7.4.4

[PATCH RFC 05/26] dmaengine: omap-dma: control start/stop directly

[Russell King]

Program the non-cyclic mode DMA start/stop directly, rather than via
arch/arm/plat-omap/dma.c.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  152 ++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 142 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 602c98aebca8..8e2dd4f658d5 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -5,6 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/delay.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/err.h>
@@ -60,6 +61,7 @@ struct omap_desc {
 	uint8_t sync_mode;	/* OMAP_DMA_SYNC_xxx */
 	uint8_t sync_type;	/* OMAP_DMA_xxx_SYNC* */
 	uint8_t periph_port;	/* Peripheral port */
+	uint16_t cicr;		/* CICR value */
 
 	unsigned sglen;
 	struct omap_sg sg[0];
@@ -95,6 +97,112 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
 	kfree(container_of(vd, struct omap_desc, vd));
 }
 
+static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	uint32_t val;
+
+	if (__dma_omap15xx(od->plat->dma_attr))
+		c->plat->dma_write(0, CPC, c->dma_ch);
+	else
+		c->plat->dma_write(0, CDAC, c->dma_ch);
+
+	if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
+		val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
+
+		if (dma_omap1())
+			val &= ~(1 << 14);
+
+		val |= c->dma_ch | 1 << 15;
+
+		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
+	} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
+		c->plat->dma_write(c->dma_ch, CLNK_CTRL, c->dma_ch);
+
+	/* Clear CSR */
+	if (dma_omap1())
+		c->plat->dma_read(CSR, c->dma_ch);
+	else
+		c->plat->dma_write(~0, CSR, c->dma_ch);
+
+	/* Enable interrupts */
+	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
+
+	val = c->plat->dma_read(CCR, c->dma_ch);
+	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
+		val |= OMAP_DMA_CCR_BUFFERING_DISABLE;
+	val |= OMAP_DMA_CCR_EN;
+	mb();
+	c->plat->dma_write(val, CCR, c->dma_ch);
+}
+
+static void omap_dma_stop(struct omap_chan *c)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	uint32_t val;
+
+	/* disable irq */
+	c->plat->dma_write(0, CICR, c->dma_ch);
+
+	/* Clear CSR */
+	if (dma_omap1())
+		c->plat->dma_read(CSR, c->dma_ch);
+	else
+		c->plat->dma_write(~0, CSR, c->dma_ch);
+
+	val = c->plat->dma_read(CCR, c->dma_ch);
+	if (od->plat->errata & DMA_ERRATA_i541 &&
+	    val & OMAP_DMA_CCR_SEL_SRC_DST_SYNC) {
+		uint32_t sysconfig;
+		unsigned i;
+
+		sysconfig = c->plat->dma_read(OCP_SYSCONFIG, c->dma_ch);
+		val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
+		val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
+		c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch);
+
+		val = c->plat->dma_read(CCR, c->dma_ch);
+		val &= ~OMAP_DMA_CCR_EN;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+
+		/* Wait for sDMA FIFO to drain */
+		for (i = 0; ; i++) {
+			val = c->plat->dma_read(CCR, c->dma_ch);
+			if (!(val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE)))
+				break;
+
+			if (i > 100)
+				break;
+
+			udelay(5);
+		}
+
+		if (val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE))
+			dev_err(c->vc.chan.device->dev,
+				"DMA drain did not complete on lch %d\n",
+			        c->dma_ch);
+
+		c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch);
+	} else {
+		val &= ~OMAP_DMA_CCR_EN;
+		c->plat->dma_write(val, CCR, c->dma_ch);
+	}
+
+	mb();
+
+	if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
+		val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
+
+		if (dma_omap1())
+			val |= 1 << 14; /* set the STOP_LNK bit */
+
+		if (dma_omap2plus())
+			val &= ~(1 << 15); /* Clear the ENABLE_LNK bit */
+
+		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
+	}
+}
+
 static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	unsigned idx)
 {
@@ -113,7 +221,7 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	c->plat->dma_write(sg->en, CEN, c->dma_ch);
 	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
 
-	omap_start_dma(c->dma_ch);
+	omap_dma_start(c, d);
 }
 
 static void omap_dma_start_desc(struct omap_chan *c)
@@ -436,6 +544,12 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	d->sync_mode = OMAP_DMA_SYNC_FRAME;
 	d->sync_type = sync_type;
 	d->periph_port = OMAP_DMA_PORT_TIPB;
+	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
+
+	if (dma_omap1())
+		d->cicr |= OMAP1_DMA_TOUT_IRQ;
+	else if (dma_omap2plus())
+		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 
 	/*
 	 * Build our scatterlist entries: each contains the address,
@@ -465,6 +579,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	size_t period_len, enum dma_transfer_direction dir, unsigned long flags,
 	void *context)
 {
+	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
 	enum dma_slave_buswidth dev_width;
 	struct omap_desc *d;
@@ -521,15 +636,25 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	d->sg[0].en = period_len / es_bytes[es];
 	d->sg[0].fn = buf_len / period_len;
 	d->sglen = 1;
+	d->cicr = OMAP_DMA_DROP_IRQ;
+	if (flags & DMA_PREP_INTERRUPT)
+		d->cicr |= OMAP_DMA_FRAME_IRQ;
+
+	if (dma_omap1())
+		d->cicr |= OMAP1_DMA_TOUT_IRQ;
+	else if (dma_omap2plus())
+		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 
 	if (!c->cyclic) {
 		c->cyclic = true;
-		omap_dma_link_lch(c->dma_ch, c->dma_ch);
 
-		if (flags & DMA_PREP_INTERRUPT)
-			omap_enable_dma_irq(c->dma_ch, OMAP_DMA_FRAME_IRQ);
+		if (__dma_omap15xx(od->plat->dma_attr)) {
+			uint32_t val;
 
-		omap_disable_dma_irq(c->dma_ch, OMAP_DMA_BLOCK_IRQ);
+			val = c->plat->dma_read(CCR, c->dma_ch);
+			val |= 3 << 8;
+			c->plat->dma_write(val, CCR, c->dma_ch);
+		}
 	}
 
 	if (dma_omap2plus()) {
@@ -570,20 +695,27 @@ static int omap_dma_terminate_all(struct omap_chan *c)
 
 	/*
 	 * Stop DMA activity: we assume the callback will not be called
-	 * after omap_stop_dma() returns (even if it does, it will see
+	 * after omap_dma_stop() returns (even if it does, it will see
 	 * c->desc is NULL and exit.)
 	 */
 	if (c->desc) {
 		c->desc = NULL;
 		/* Avoid stopping the dma twice */
 		if (!c->paused)
-			omap_stop_dma(c->dma_ch);
+			omap_dma_stop(c);
 	}
 
 	if (c->cyclic) {
 		c->cyclic = false;
 		c->paused = false;
-		omap_dma_unlink_lch(c->dma_ch, c->dma_ch);
+
+		if (__dma_omap15xx(od->plat->dma_attr)) {
+			uint32_t val;
+
+			val = c->plat->dma_read(CCR, c->dma_ch);
+			val &= ~(3 << 8);
+			c->plat->dma_write(val, CCR, c->dma_ch);
+		}
 	}
 
 	vchan_get_all_descriptors(&c->vc, &head);
@@ -600,7 +732,7 @@ static int omap_dma_pause(struct omap_chan *c)
 		return -EINVAL;
 
 	if (!c->paused) {
-		omap_stop_dma(c->dma_ch);
+		omap_dma_stop(c);
 		c->paused = true;
 	}
 
@@ -614,7 +746,7 @@ static int omap_dma_resume(struct omap_chan *c)
 		return -EINVAL;
 
 	if (c->paused) {
-		omap_start_dma(c->dma_ch);
+		omap_dma_start(c, c->desc);
 		c->paused = false;
 	}
 
-- 
1.7.4.4

Re: [PATCH RFC 05/26] dmaengine: omap-dma: control start/stop directly

[Tony Lindgren]

* Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:14]:
> --- a/drivers/dma/omap-dma.c
> +++ b/drivers/dma/omap-dma.c
> @@ -570,20 +695,27 @@ static int omap_dma_terminate_all(struct omap_chan *c)
>  
>  	/*
>  	 * Stop DMA activity: we assume the callback will not be called
> -	 * after omap_stop_dma() returns (even if it does, it will see
> +	 * after omap_dma_stop() returns (even if it does, it will see
>  	 * c->desc is NULL and exit.)
>  	 */
>  	if (c->desc) {
>  		c->desc = NULL;
>  		/* Avoid stopping the dma twice */
>  		if (!c->paused)
> -			omap_stop_dma(c->dma_ch);
> +			omap_dma_stop(c);
>  	}
>  
>  	if (c->cyclic) {
>  		c->cyclic = false;
>  		c->paused = false;
> -		omap_dma_unlink_lch(c->dma_ch, c->dma_ch);
> +
> +		if (__dma_omap15xx(od->plat->dma_attr)) {
> +			uint32_t val;
> +
> +			val = c->plat->dma_read(CCR, c->dma_ch);
> +			val &= ~(3 << 8);
> +			c->plat->dma_write(val, CCR, c->dma_ch);
> +		}
>  	}
>  
>  	vchan_get_all_descriptors(&c->vc, &head);

This won't build for omap1 as od is just d in this function. Something
like the following needs to be folded in.

Tony

8< -----------------------
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -682,16 +682,16 @@ static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *c
 
 static int omap_dma_terminate_all(struct omap_chan *c)
 {
-	struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 	unsigned long flags;
 	LIST_HEAD(head);
 
 	spin_lock_irqsave(&c->vc.lock, flags);
 
 	/* Prevent this channel being scheduled */
-	spin_lock(&d->lock);
+	spin_lock(&od->lock);
 	list_del_init(&c->node);
-	spin_unlock(&d->lock);
+	spin_unlock(&od->lock);
 
 	/*
 	 * Stop DMA activity: we assume the callback will not be called

[PATCH RFC 05/26] dmaengine: omap-dma: control start/stop directly

[Tony Lindgren]

* Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:14]:
> --- a/drivers/dma/omap-dma.c
> +++ b/drivers/dma/omap-dma.c
> @@ -570,20 +695,27 @@ static int omap_dma_terminate_all(struct omap_chan *c)
>  
>  	/*
>  	 * Stop DMA activity: we assume the callback will not be called
> -	 * after omap_stop_dma() returns (even if it does, it will see
> +	 * after omap_dma_stop() returns (even if it does, it will see
>  	 * c->desc is NULL and exit.)
>  	 */
>  	if (c->desc) {
>  		c->desc = NULL;
>  		/* Avoid stopping the dma twice */
>  		if (!c->paused)
> -			omap_stop_dma(c->dma_ch);
> +			omap_dma_stop(c);
>  	}
>  
>  	if (c->cyclic) {
>  		c->cyclic = false;
>  		c->paused = false;
> -		omap_dma_unlink_lch(c->dma_ch, c->dma_ch);
> +
> +		if (__dma_omap15xx(od->plat->dma_attr)) {
> +			uint32_t val;
> +
> +			val = c->plat->dma_read(CCR, c->dma_ch);
> +			val &= ~(3 << 8);
> +			c->plat->dma_write(val, CCR, c->dma_ch);
> +		}
>  	}
>  
>  	vchan_get_all_descriptors(&c->vc, &head);

This won't build for omap1 as od is just d in this function. Something
like the following needs to be folded in.

Tony

8< -----------------------
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -682,16 +682,16 @@ static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *c
 
 static int omap_dma_terminate_all(struct omap_chan *c)
 {
-	struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 	unsigned long flags;
 	LIST_HEAD(head);
 
 	spin_lock_irqsave(&c->vc.lock, flags);
 
 	/* Prevent this channel being scheduled */
-	spin_lock(&d->lock);
+	spin_lock(&od->lock);
 	list_del_init(&c->node);
-	spin_unlock(&d->lock);
+	spin_unlock(&od->lock);
 
 	/*
 	 * Stop DMA activity: we assume the callback will not be called

[PATCH RFC 06/26] dmaengine: omap-dma: move reading of dma position to omap-dma.c

[Russell King]

Read the current DMA position from the hardware directly rather than via
arch/arm/plat-omap/dma.c.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   66 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 8e2dd4f658d5..7e6cdc39725c 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -430,6 +430,68 @@ static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
 	return size;
 }
 
+static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	dma_addr_t addr;
+
+	if (__dma_omap15xx(od->plat->dma_attr))
+		addr = c->plat->dma_read(CPC, c->dma_ch);
+	else
+		addr = c->plat->dma_read(CSAC, c->dma_ch);
+
+	if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0)
+		addr = c->plat->dma_read(CSAC, c->dma_ch);
+
+	if (!__dma_omap15xx(od->plat->dma_attr)) {
+		/*
+		 * CDAC == 0 indicates that the DMA transfer on the channel has
+		 * not been started (no data has been transferred so far).
+		 * Return the programmed source start address in this case.
+		 */
+		if (c->plat->dma_read(CDAC, c->dma_ch))
+			addr = c->plat->dma_read(CSAC, c->dma_ch);
+		else
+			addr = c->plat->dma_read(CSSA, c->dma_ch);
+	}
+
+	if (dma_omap1())
+		addr |= c->plat->dma_read(CSSA, c->dma_ch) & 0xffff0000;
+
+	return addr;
+}
+
+static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	dma_addr_t addr;
+
+	if (__dma_omap15xx(od->plat->dma_attr))
+		addr = c->plat->dma_read(CPC, c->dma_ch);
+	else
+		addr = c->plat->dma_read(CDAC, c->dma_ch);
+
+	/*
+	 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+	 * read before the DMA controller finished disabling the channel.
+	 */
+	if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) {
+		addr = c->plat->dma_read(CDAC, c->dma_ch);
+		/*
+		 * CDAC == 0 indicates that the DMA transfer on the channel has
+		 * not been started (no data has been transferred so far).
+		 * Return the programmed destination start address in this case.
+		 */
+		if (addr == 0)
+			addr = c->plat->dma_read(CDSA, c->dma_ch);
+	}
+
+	if (dma_omap1())
+		addr |= c->plat->dma_read(CDSA, c->dma_ch) & 0xffff0000;
+
+	return addr;
+}
+
 static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
 	dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
@@ -451,9 +513,9 @@ static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
 		dma_addr_t pos;
 
 		if (d->dir == DMA_MEM_TO_DEV)
-			pos = omap_get_dma_src_pos(c->dma_ch);
+			pos = omap_dma_get_src_pos(c);
 		else if (d->dir == DMA_DEV_TO_MEM)
-			pos = omap_get_dma_dst_pos(c->dma_ch);
+			pos = omap_dma_get_dst_pos(c);
 		else
 			pos = 0;
 
-- 
1.7.4.4

[PATCH RFC 06/26] dmaengine: omap-dma: move reading of dma position to omap-dma.c

[Russell King]

Read the current DMA position from the hardware directly rather than via
arch/arm/plat-omap/dma.c.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   66 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 8e2dd4f658d5..7e6cdc39725c 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -430,6 +430,68 @@ static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
 	return size;
 }
 
+static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	dma_addr_t addr;
+
+	if (__dma_omap15xx(od->plat->dma_attr))
+		addr = c->plat->dma_read(CPC, c->dma_ch);
+	else
+		addr = c->plat->dma_read(CSAC, c->dma_ch);
+
+	if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0)
+		addr = c->plat->dma_read(CSAC, c->dma_ch);
+
+	if (!__dma_omap15xx(od->plat->dma_attr)) {
+		/*
+		 * CDAC == 0 indicates that the DMA transfer on the channel has
+		 * not been started (no data has been transferred so far).
+		 * Return the programmed source start address in this case.
+		 */
+		if (c->plat->dma_read(CDAC, c->dma_ch))
+			addr = c->plat->dma_read(CSAC, c->dma_ch);
+		else
+			addr = c->plat->dma_read(CSSA, c->dma_ch);
+	}
+
+	if (dma_omap1())
+		addr |= c->plat->dma_read(CSSA, c->dma_ch) & 0xffff0000;
+
+	return addr;
+}
+
+static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	dma_addr_t addr;
+
+	if (__dma_omap15xx(od->plat->dma_attr))
+		addr = c->plat->dma_read(CPC, c->dma_ch);
+	else
+		addr = c->plat->dma_read(CDAC, c->dma_ch);
+
+	/*
+	 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+	 * read before the DMA controller finished disabling the channel.
+	 */
+	if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) {
+		addr = c->plat->dma_read(CDAC, c->dma_ch);
+		/*
+		 * CDAC == 0 indicates that the DMA transfer on the channel has
+		 * not been started (no data has been transferred so far).
+		 * Return the programmed destination start address in this case.
+		 */
+		if (addr == 0)
+			addr = c->plat->dma_read(CDSA, c->dma_ch);
+	}
+
+	if (dma_omap1())
+		addr |= c->plat->dma_read(CDSA, c->dma_ch) & 0xffff0000;
+
+	return addr;
+}
+
 static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
 	dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
@@ -451,9 +513,9 @@ static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
 		dma_addr_t pos;
 
 		if (d->dir == DMA_MEM_TO_DEV)
-			pos = omap_get_dma_src_pos(c->dma_ch);
+			pos = omap_dma_get_src_pos(c);
 		else if (d->dir == DMA_DEV_TO_MEM)
-			pos = omap_get_dma_dst_pos(c->dma_ch);
+			pos = omap_dma_get_dst_pos(c);
 		else
 			pos = 0;
 
-- 
1.7.4.4

[PATCH RFC 07/26] dmaengine: omap-dma: consolidate setup of CSDP

[Russell King]

Consolidate the setup of the channel source destination parameters
register.  This way, we calculate the required CSDP value when we setup
a transfer descriptor, and only write it to the device registers once
when we start the descriptor.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   64 +++++++++++++++++++++---------------------------
 1 files changed, 28 insertions(+), 36 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 7e6cdc39725c..98928f7209f6 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -60,8 +60,8 @@ struct omap_desc {
 	uint8_t es;		/* OMAP_DMA_DATA_TYPE_xxx */
 	uint8_t sync_mode;	/* OMAP_DMA_SYNC_xxx */
 	uint8_t sync_type;	/* OMAP_DMA_xxx_SYNC* */
-	uint8_t periph_port;	/* Peripheral port */
 	uint16_t cicr;		/* CICR value */
+	uint32_t csdp;		/* CSDP value */
 
 	unsigned sglen;
 	struct omap_sg sg[0];
@@ -241,14 +241,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->sgidx = 0;
 
 	if (d->dir == DMA_DEV_TO_MEM) {
-		if (dma_omap1()) {
-			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 9 | 0x1f << 2);
-			val |= OMAP_DMA_PORT_EMIFF << 9;
-			val |= d->periph_port << 2;
-			c->plat->dma_write(val, CSDP, c->dma_ch);
-		}
-
 		val = c->plat->dma_read(CCR, c->dma_ch);
 		val &= ~(0x03 << 14 | 0x03 << 12);
 		val |= OMAP_DMA_AMODE_POST_INC << 14;
@@ -259,14 +251,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
 		c->plat->dma_write(0, CSEI, c->dma_ch);
 		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
 	} else {
-		if (dma_omap1()) {
-			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 9 | 0x1f << 2);
-			val |= d->periph_port << 9;
-			val |= OMAP_DMA_PORT_EMIFF << 2;
-			c->plat->dma_write(val, CSDP, c->dma_ch);
-		}
-
 		val = c->plat->dma_read(CCR, c->dma_ch);
 		val &= ~(0x03 << 12 | 0x03 << 14);
 		val |= OMAP_DMA_AMODE_CONSTANT << 14;
@@ -278,10 +262,7 @@ static void omap_dma_start_desc(struct omap_chan *c)
 		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
 	}
 
-	val = c->plat->dma_read(CSDP, c->dma_ch);
-	val &= ~0x03;
-	val |= d->es;
-	c->plat->dma_write(val, CSDP, c->dma_ch);
+	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
 
 	if (dma_omap1()) {
 		val = c->plat->dma_read(CCR, c->dma_ch);
@@ -605,13 +586,21 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	d->es = es;
 	d->sync_mode = OMAP_DMA_SYNC_FRAME;
 	d->sync_type = sync_type;
-	d->periph_port = OMAP_DMA_PORT_TIPB;
 	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
+	d->csdp = es;
 
-	if (dma_omap1())
+	if (dma_omap1()) {
 		d->cicr |= OMAP1_DMA_TOUT_IRQ;
-	else if (dma_omap2plus())
+
+		if (dir == DMA_DEV_TO_MEM)
+			d->csdp |= OMAP_DMA_PORT_EMIFF << 9 |
+				   OMAP_DMA_PORT_TIPB << 2;
+		else
+			d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
+				   OMAP_DMA_PORT_EMIFF << 2;
+	} else if (dma_omap2plus()) {
 		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
+	}
 
 	/*
 	 * Build our scatterlist entries: each contains the address,
@@ -693,7 +682,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	else
 		d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
 	d->sync_type = sync_type;
-	d->periph_port = OMAP_DMA_PORT_MPUI;
 	d->sg[0].addr = buf_addr;
 	d->sg[0].en = period_len / es_bytes[es];
 	d->sg[0].fn = buf_len / period_len;
@@ -702,11 +690,24 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	if (flags & DMA_PREP_INTERRUPT)
 		d->cicr |= OMAP_DMA_FRAME_IRQ;
 
-	if (dma_omap1())
+	d->csdp = es;
+
+	if (dma_omap1()) {
 		d->cicr |= OMAP1_DMA_TOUT_IRQ;
-	else if (dma_omap2plus())
+
+		if (dir == DMA_DEV_TO_MEM)
+			d->csdp |= OMAP_DMA_PORT_EMIFF << 9 |
+				   OMAP_DMA_PORT_MPUI << 2;
+		else
+			d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
+				   OMAP_DMA_PORT_EMIFF << 2;
+	} else if (dma_omap2plus()) {
 		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 
+		/* src and dst burst mode 16 */
+		d->csdp |= 3 << 14 | 3 << 7;
+	}
+
 	if (!c->cyclic) {
 		c->cyclic = true;
 
@@ -719,15 +720,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 		}
 	}
 
-	if (dma_omap2plus()) {
-		uint32_t val;
-
-		val = c->plat->dma_read(CSDP, c->dma_ch);
-		val |= 0x03 << 7; /* src burst mode 16 */
-		val |= 0x03 << 14; /* dst burst mode 16 */
-		c->plat->dma_write(val, CSDP, c->dma_ch);
-	}
-
 	return vchan_tx_prep(&c->vc, &d->vd, flags);
 }
 
-- 
1.7.4.4

[PATCH RFC 07/26] dmaengine: omap-dma: consolidate setup of CSDP

[Russell King]

Consolidate the setup of the channel source destination parameters
register.  This way, we calculate the required CSDP value when we setup
a transfer descriptor, and only write it to the device registers once
when we start the descriptor.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   64 +++++++++++++++++++++---------------------------
 1 files changed, 28 insertions(+), 36 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 7e6cdc39725c..98928f7209f6 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -60,8 +60,8 @@ struct omap_desc {
 	uint8_t es;		/* OMAP_DMA_DATA_TYPE_xxx */
 	uint8_t sync_mode;	/* OMAP_DMA_SYNC_xxx */
 	uint8_t sync_type;	/* OMAP_DMA_xxx_SYNC* */
-	uint8_t periph_port;	/* Peripheral port */
 	uint16_t cicr;		/* CICR value */
+	uint32_t csdp;		/* CSDP value */
 
 	unsigned sglen;
 	struct omap_sg sg[0];
@@ -241,14 +241,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->sgidx = 0;
 
 	if (d->dir == DMA_DEV_TO_MEM) {
-		if (dma_omap1()) {
-			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 9 | 0x1f << 2);
-			val |= OMAP_DMA_PORT_EMIFF << 9;
-			val |= d->periph_port << 2;
-			c->plat->dma_write(val, CSDP, c->dma_ch);
-		}
-
 		val = c->plat->dma_read(CCR, c->dma_ch);
 		val &= ~(0x03 << 14 | 0x03 << 12);
 		val |= OMAP_DMA_AMODE_POST_INC << 14;
@@ -259,14 +251,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
 		c->plat->dma_write(0, CSEI, c->dma_ch);
 		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
 	} else {
-		if (dma_omap1()) {
-			val = c->plat->dma_read(CSDP, c->dma_ch);
-			val &= ~(0x1f << 9 | 0x1f << 2);
-			val |= d->periph_port << 9;
-			val |= OMAP_DMA_PORT_EMIFF << 2;
-			c->plat->dma_write(val, CSDP, c->dma_ch);
-		}
-
 		val = c->plat->dma_read(CCR, c->dma_ch);
 		val &= ~(0x03 << 12 | 0x03 << 14);
 		val |= OMAP_DMA_AMODE_CONSTANT << 14;
@@ -278,10 +262,7 @@ static void omap_dma_start_desc(struct omap_chan *c)
 		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
 	}
 
-	val = c->plat->dma_read(CSDP, c->dma_ch);
-	val &= ~0x03;
-	val |= d->es;
-	c->plat->dma_write(val, CSDP, c->dma_ch);
+	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
 
 	if (dma_omap1()) {
 		val = c->plat->dma_read(CCR, c->dma_ch);
@@ -605,13 +586,21 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	d->es = es;
 	d->sync_mode = OMAP_DMA_SYNC_FRAME;
 	d->sync_type = sync_type;
-	d->periph_port = OMAP_DMA_PORT_TIPB;
 	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
+	d->csdp = es;
 
-	if (dma_omap1())
+	if (dma_omap1()) {
 		d->cicr |= OMAP1_DMA_TOUT_IRQ;
-	else if (dma_omap2plus())
+
+		if (dir == DMA_DEV_TO_MEM)
+			d->csdp |= OMAP_DMA_PORT_EMIFF << 9 |
+				   OMAP_DMA_PORT_TIPB << 2;
+		else
+			d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
+				   OMAP_DMA_PORT_EMIFF << 2;
+	} else if (dma_omap2plus()) {
 		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
+	}
 
 	/*
 	 * Build our scatterlist entries: each contains the address,
@@ -693,7 +682,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	else
 		d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
 	d->sync_type = sync_type;
-	d->periph_port = OMAP_DMA_PORT_MPUI;
 	d->sg[0].addr = buf_addr;
 	d->sg[0].en = period_len / es_bytes[es];
 	d->sg[0].fn = buf_len / period_len;
@@ -702,11 +690,24 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	if (flags & DMA_PREP_INTERRUPT)
 		d->cicr |= OMAP_DMA_FRAME_IRQ;
 
-	if (dma_omap1())
+	d->csdp = es;
+
+	if (dma_omap1()) {
 		d->cicr |= OMAP1_DMA_TOUT_IRQ;
-	else if (dma_omap2plus())
+
+		if (dir == DMA_DEV_TO_MEM)
+			d->csdp |= OMAP_DMA_PORT_EMIFF << 9 |
+				   OMAP_DMA_PORT_MPUI << 2;
+		else
+			d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
+				   OMAP_DMA_PORT_EMIFF << 2;
+	} else if (dma_omap2plus()) {
 		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 
+		/* src and dst burst mode 16 */
+		d->csdp |= 3 << 14 | 3 << 7;
+	}
+
 	if (!c->cyclic) {
 		c->cyclic = true;
 
@@ -719,15 +720,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 		}
 	}
 
-	if (dma_omap2plus()) {
-		uint32_t val;
-
-		val = c->plat->dma_read(CSDP, c->dma_ch);
-		val |= 0x03 << 7; /* src burst mode 16 */
-		val |= 0x03 << 14; /* dst burst mode 16 */
-		c->plat->dma_write(val, CSDP, c->dma_ch);
-	}
-
 	return vchan_tx_prep(&c->vc, &d->vd, flags);
 }
 
-- 
1.7.4.4

[PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Russell King]

Consolidate the setup of the channel control register.  Prepare the
basic value in the preparation of the DMA descriptor, and write it into
the register upon descriptor execution.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  133 ++++++++++++++++-------------------------------
 1 files changed, 45 insertions(+), 88 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 98928f7209f6..796f882da03c 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -58,8 +58,7 @@ struct omap_desc {
 
 	int16_t fi;		/* for OMAP_DMA_SYNC_PACKET */
 	uint8_t es;		/* OMAP_DMA_DATA_TYPE_xxx */
-	uint8_t sync_mode;	/* OMAP_DMA_SYNC_xxx */
-	uint8_t sync_type;	/* OMAP_DMA_xxx_SYNC* */
+	uint32_t ccr;		/* CCR value */
 	uint16_t cicr;		/* CICR value */
 	uint32_t csdp;		/* CSDP value */
 
@@ -228,7 +227,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
 {
 	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 	struct omap_desc *d;
-	uint32_t val;
 
 	if (!vd) {
 		c->desc = NULL;
@@ -240,23 +238,15 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->desc = d = to_omap_dma_desc(&vd->tx);
 	c->sgidx = 0;
 
-	if (d->dir == DMA_DEV_TO_MEM) {
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 14 | 0x03 << 12);
-		val |= OMAP_DMA_AMODE_POST_INC << 14;
-		val |= OMAP_DMA_AMODE_CONSTANT << 12;
-		c->plat->dma_write(val, CCR, c->dma_ch);
+	c->plat->dma_write(d->ccr, CCR, c->dma_ch);
+	if (dma_omap1())
+		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
 
+	if (d->dir == DMA_DEV_TO_MEM) {
 		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
 		c->plat->dma_write(0, CSEI, c->dma_ch);
 		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
 	} else {
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 12 | 0x03 << 14);
-		val |= OMAP_DMA_AMODE_CONSTANT << 14;
-		val |= OMAP_DMA_AMODE_POST_INC << 12;
-		c->plat->dma_write(val, CCR, c->dma_ch);
-
 		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
 		c->plat->dma_write(0, CDEI, c->dma_ch);
 		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
@@ -264,47 +254,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
 
 	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
 
-	if (dma_omap1()) {
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(1 << 5);
-		if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
-			val |= 1 << 5;
-		c->plat->dma_write(val, CCR, c->dma_ch);
-
-		val = c->plat->dma_read(CCR2, c->dma_ch);
-		val &= ~(1 << 2);
-		if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
-			val |= 1 << 2;
-		c->plat->dma_write(val, CCR2, c->dma_ch);
-	}
-
-	if (dma_omap2plus() && c->dma_sig) {
-		val = c->plat->dma_read(CCR, c->dma_ch);
-
-		/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
-		val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
-		val |= (c->dma_sig & ~0x1f) << 14;
-		val |= c->dma_sig & 0x1f;
-
-		if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
-			val |= 1 << 5;
-
-		if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
-			val |= 1 << 18;
-
-		switch (d->sync_type) {
-		case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
-			val |= 1 << 23;		/* Prefetch */
-			break;
-		case 0:
-			break;
-		default:
-			val |= 1 << 24; 	/* source synch */
-			break;
-		}
-		c->plat->dma_write(val, CCR, c->dma_ch);
-	}
-
 	omap_dma_start_sg(c, d, 0);
 }
 
@@ -543,19 +492,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	struct scatterlist *sgent;
 	struct omap_desc *d;
 	dma_addr_t dev_addr;
-	unsigned i, j = 0, es, en, frame_bytes, sync_type;
+	unsigned i, j = 0, es, en, frame_bytes;
 	u32 burst;
 
 	if (dir == DMA_DEV_TO_MEM) {
 		dev_addr = c->cfg.src_addr;
 		dev_width = c->cfg.src_addr_width;
 		burst = c->cfg.src_maxburst;
-		sync_type = OMAP_DMA_SRC_SYNC;
 	} else if (dir == DMA_MEM_TO_DEV) {
 		dev_addr = c->cfg.dst_addr;
 		dev_width = c->cfg.dst_addr_width;
 		burst = c->cfg.dst_maxburst;
-		sync_type = OMAP_DMA_DST_SYNC;
 	} else {
 		dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 		return NULL;
@@ -584,12 +531,20 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	d->dir = dir;
 	d->dev_addr = dev_addr;
 	d->es = es;
-	d->sync_mode = OMAP_DMA_SYNC_FRAME;
-	d->sync_type = sync_type;
+
+	d->ccr = 0;
+	if (dir == DMA_DEV_TO_MEM)
+		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
+			  OMAP_DMA_AMODE_CONSTANT << 12;
+	else
+		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
+			  OMAP_DMA_AMODE_POST_INC << 12;
+
 	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 	d->csdp = es;
 
 	if (dma_omap1()) {
+		d->ccr |= 1 << 5; /* frame sync */
 		d->cicr |= OMAP1_DMA_TOUT_IRQ;
 
 		if (dir == DMA_DEV_TO_MEM)
@@ -599,6 +554,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 			d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
 				   OMAP_DMA_PORT_EMIFF << 2;
 	} else if (dma_omap2plus()) {
+		d->ccr |= (c->dma_sig & ~0x1f) << 14;
+		d->ccr |= c->dma_sig & 0x1f;
+		d->ccr |= 1 << 5; /* frame sync */
+
+		if (dir == DMA_DEV_TO_MEM)
+			d->ccr |= 1 << 24; /* source synch */
+
 		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 	}
 
@@ -635,19 +597,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	enum dma_slave_buswidth dev_width;
 	struct omap_desc *d;
 	dma_addr_t dev_addr;
-	unsigned es, sync_type;
+	unsigned es;
 	u32 burst;
 
 	if (dir == DMA_DEV_TO_MEM) {
 		dev_addr = c->cfg.src_addr;
 		dev_width = c->cfg.src_addr_width;
 		burst = c->cfg.src_maxburst;
-		sync_type = OMAP_DMA_SRC_SYNC;
 	} else if (dir == DMA_MEM_TO_DEV) {
 		dev_addr = c->cfg.dst_addr;
 		dev_width = c->cfg.dst_addr_width;
 		burst = c->cfg.dst_maxburst;
-		sync_type = OMAP_DMA_DST_SYNC;
 	} else {
 		dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 		return NULL;
@@ -677,15 +637,21 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	d->dev_addr = dev_addr;
 	d->fi = burst;
 	d->es = es;
-	if (burst)
-		d->sync_mode = OMAP_DMA_SYNC_PACKET;
-	else
-		d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
-	d->sync_type = sync_type;
 	d->sg[0].addr = buf_addr;
 	d->sg[0].en = period_len / es_bytes[es];
 	d->sg[0].fn = buf_len / period_len;
 	d->sglen = 1;
+
+	d->ccr = 0;
+	if (__dma_omap15xx(od->plat->dma_attr))
+		d->ccr = 3 << 8;
+	if (dir == DMA_DEV_TO_MEM)
+		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
+			  OMAP_DMA_AMODE_CONSTANT << 12;
+	else
+		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
+			  OMAP_DMA_AMODE_POST_INC << 12;
+
 	d->cicr = OMAP_DMA_DROP_IRQ;
 	if (flags & DMA_PREP_INTERRUPT)
 		d->cicr |= OMAP_DMA_FRAME_IRQ;
@@ -702,23 +668,22 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 			d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
 				   OMAP_DMA_PORT_EMIFF << 2;
 	} else if (dma_omap2plus()) {
+		d->ccr |= (c->dma_sig & ~0x1f) << 14;
+		d->ccr |= c->dma_sig & 0x1f;
+
+		if (burst)
+			d->ccr |= 1 << 18 | 1 << 5; /* packet */
+
+		if (dir == DMA_DEV_TO_MEM)
+			d->ccr |= 1 << 24; /* source synch */
+
 		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 
 		/* src and dst burst mode 16 */
 		d->csdp |= 3 << 14 | 3 << 7;
 	}
 
-	if (!c->cyclic) {
-		c->cyclic = true;
-
-		if (__dma_omap15xx(od->plat->dma_attr)) {
-			uint32_t val;
-
-			val = c->plat->dma_read(CCR, c->dma_ch);
-			val |= 3 << 8;
-			c->plat->dma_write(val, CCR, c->dma_ch);
-		}
-	}
+	c->cyclic = true;
 
 	return vchan_tx_prep(&c->vc, &d->vd, flags);
 }
@@ -762,14 +727,6 @@ static int omap_dma_terminate_all(struct omap_chan *c)
 	if (c->cyclic) {
 		c->cyclic = false;
 		c->paused = false;
-
-		if (__dma_omap15xx(od->plat->dma_attr)) {
-			uint32_t val;
-
-			val = c->plat->dma_read(CCR, c->dma_ch);
-			val &= ~(3 << 8);
-			c->plat->dma_write(val, CCR, c->dma_ch);
-		}
 	}
 
 	vchan_get_all_descriptors(&c->vc, &head);
-- 
1.7.4.4

[PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Russell King]

Consolidate the setup of the channel control register.  Prepare the
basic value in the preparation of the DMA descriptor, and write it into
the register upon descriptor execution.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  133 ++++++++++++++++-------------------------------
 1 files changed, 45 insertions(+), 88 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 98928f7209f6..796f882da03c 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -58,8 +58,7 @@ struct omap_desc {
 
 	int16_t fi;		/* for OMAP_DMA_SYNC_PACKET */
 	uint8_t es;		/* OMAP_DMA_DATA_TYPE_xxx */
-	uint8_t sync_mode;	/* OMAP_DMA_SYNC_xxx */
-	uint8_t sync_type;	/* OMAP_DMA_xxx_SYNC* */
+	uint32_t ccr;		/* CCR value */
 	uint16_t cicr;		/* CICR value */
 	uint32_t csdp;		/* CSDP value */
 
@@ -228,7 +227,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
 {
 	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 	struct omap_desc *d;
-	uint32_t val;
 
 	if (!vd) {
 		c->desc = NULL;
@@ -240,23 +238,15 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->desc = d = to_omap_dma_desc(&vd->tx);
 	c->sgidx = 0;
 
-	if (d->dir == DMA_DEV_TO_MEM) {
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 14 | 0x03 << 12);
-		val |= OMAP_DMA_AMODE_POST_INC << 14;
-		val |= OMAP_DMA_AMODE_CONSTANT << 12;
-		c->plat->dma_write(val, CCR, c->dma_ch);
+	c->plat->dma_write(d->ccr, CCR, c->dma_ch);
+	if (dma_omap1())
+		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
 
+	if (d->dir == DMA_DEV_TO_MEM) {
 		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
 		c->plat->dma_write(0, CSEI, c->dma_ch);
 		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
 	} else {
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(0x03 << 12 | 0x03 << 14);
-		val |= OMAP_DMA_AMODE_CONSTANT << 14;
-		val |= OMAP_DMA_AMODE_POST_INC << 12;
-		c->plat->dma_write(val, CCR, c->dma_ch);
-
 		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
 		c->plat->dma_write(0, CDEI, c->dma_ch);
 		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
@@ -264,47 +254,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
 
 	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
 
-	if (dma_omap1()) {
-		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~(1 << 5);
-		if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
-			val |= 1 << 5;
-		c->plat->dma_write(val, CCR, c->dma_ch);
-
-		val = c->plat->dma_read(CCR2, c->dma_ch);
-		val &= ~(1 << 2);
-		if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
-			val |= 1 << 2;
-		c->plat->dma_write(val, CCR2, c->dma_ch);
-	}
-
-	if (dma_omap2plus() && c->dma_sig) {
-		val = c->plat->dma_read(CCR, c->dma_ch);
-
-		/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
-		val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
-		val |= (c->dma_sig & ~0x1f) << 14;
-		val |= c->dma_sig & 0x1f;
-
-		if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
-			val |= 1 << 5;
-
-		if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
-			val |= 1 << 18;
-
-		switch (d->sync_type) {
-		case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
-			val |= 1 << 23;		/* Prefetch */
-			break;
-		case 0:
-			break;
-		default:
-			val |= 1 << 24; 	/* source synch */
-			break;
-		}
-		c->plat->dma_write(val, CCR, c->dma_ch);
-	}
-
 	omap_dma_start_sg(c, d, 0);
 }
 
@@ -543,19 +492,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	struct scatterlist *sgent;
 	struct omap_desc *d;
 	dma_addr_t dev_addr;
-	unsigned i, j = 0, es, en, frame_bytes, sync_type;
+	unsigned i, j = 0, es, en, frame_bytes;
 	u32 burst;
 
 	if (dir == DMA_DEV_TO_MEM) {
 		dev_addr = c->cfg.src_addr;
 		dev_width = c->cfg.src_addr_width;
 		burst = c->cfg.src_maxburst;
-		sync_type = OMAP_DMA_SRC_SYNC;
 	} else if (dir == DMA_MEM_TO_DEV) {
 		dev_addr = c->cfg.dst_addr;
 		dev_width = c->cfg.dst_addr_width;
 		burst = c->cfg.dst_maxburst;
-		sync_type = OMAP_DMA_DST_SYNC;
 	} else {
 		dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 		return NULL;
@@ -584,12 +531,20 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	d->dir = dir;
 	d->dev_addr = dev_addr;
 	d->es = es;
-	d->sync_mode = OMAP_DMA_SYNC_FRAME;
-	d->sync_type = sync_type;
+
+	d->ccr = 0;
+	if (dir == DMA_DEV_TO_MEM)
+		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
+			  OMAP_DMA_AMODE_CONSTANT << 12;
+	else
+		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
+			  OMAP_DMA_AMODE_POST_INC << 12;
+
 	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 	d->csdp = es;
 
 	if (dma_omap1()) {
+		d->ccr |= 1 << 5; /* frame sync */
 		d->cicr |= OMAP1_DMA_TOUT_IRQ;
 
 		if (dir == DMA_DEV_TO_MEM)
@@ -599,6 +554,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 			d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
 				   OMAP_DMA_PORT_EMIFF << 2;
 	} else if (dma_omap2plus()) {
+		d->ccr |= (c->dma_sig & ~0x1f) << 14;
+		d->ccr |= c->dma_sig & 0x1f;
+		d->ccr |= 1 << 5; /* frame sync */
+
+		if (dir == DMA_DEV_TO_MEM)
+			d->ccr |= 1 << 24; /* source synch */
+
 		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 	}
 
@@ -635,19 +597,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	enum dma_slave_buswidth dev_width;
 	struct omap_desc *d;
 	dma_addr_t dev_addr;
-	unsigned es, sync_type;
+	unsigned es;
 	u32 burst;
 
 	if (dir == DMA_DEV_TO_MEM) {
 		dev_addr = c->cfg.src_addr;
 		dev_width = c->cfg.src_addr_width;
 		burst = c->cfg.src_maxburst;
-		sync_type = OMAP_DMA_SRC_SYNC;
 	} else if (dir == DMA_MEM_TO_DEV) {
 		dev_addr = c->cfg.dst_addr;
 		dev_width = c->cfg.dst_addr_width;
 		burst = c->cfg.dst_maxburst;
-		sync_type = OMAP_DMA_DST_SYNC;
 	} else {
 		dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 		return NULL;
@@ -677,15 +637,21 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	d->dev_addr = dev_addr;
 	d->fi = burst;
 	d->es = es;
-	if (burst)
-		d->sync_mode = OMAP_DMA_SYNC_PACKET;
-	else
-		d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
-	d->sync_type = sync_type;
 	d->sg[0].addr = buf_addr;
 	d->sg[0].en = period_len / es_bytes[es];
 	d->sg[0].fn = buf_len / period_len;
 	d->sglen = 1;
+
+	d->ccr = 0;
+	if (__dma_omap15xx(od->plat->dma_attr))
+		d->ccr = 3 << 8;
+	if (dir == DMA_DEV_TO_MEM)
+		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
+			  OMAP_DMA_AMODE_CONSTANT << 12;
+	else
+		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
+			  OMAP_DMA_AMODE_POST_INC << 12;
+
 	d->cicr = OMAP_DMA_DROP_IRQ;
 	if (flags & DMA_PREP_INTERRUPT)
 		d->cicr |= OMAP_DMA_FRAME_IRQ;
@@ -702,23 +668,22 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 			d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
 				   OMAP_DMA_PORT_EMIFF << 2;
 	} else if (dma_omap2plus()) {
+		d->ccr |= (c->dma_sig & ~0x1f) << 14;
+		d->ccr |= c->dma_sig & 0x1f;
+
+		if (burst)
+			d->ccr |= 1 << 18 | 1 << 5; /* packet */
+
+		if (dir == DMA_DEV_TO_MEM)
+			d->ccr |= 1 << 24; /* source synch */
+
 		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
 
 		/* src and dst burst mode 16 */
 		d->csdp |= 3 << 14 | 3 << 7;
 	}
 
-	if (!c->cyclic) {
-		c->cyclic = true;
-
-		if (__dma_omap15xx(od->plat->dma_attr)) {
-			uint32_t val;
-
-			val = c->plat->dma_read(CCR, c->dma_ch);
-			val |= 3 << 8;
-			c->plat->dma_write(val, CCR, c->dma_ch);
-		}
-	}
+	c->cyclic = true;
 
 	return vchan_tx_prep(&c->vc, &d->vd, flags);
 }
@@ -762,14 +727,6 @@ static int omap_dma_terminate_all(struct omap_chan *c)
 	if (c->cyclic) {
 		c->cyclic = false;
 		c->paused = false;
-
-		if (__dma_omap15xx(od->plat->dma_attr)) {
-			uint32_t val;
-
-			val = c->plat->dma_read(CCR, c->dma_ch);
-			val &= ~(3 << 8);
-			c->plat->dma_write(val, CCR, c->dma_ch);
-		}
 	}
 
 	vchan_get_all_descriptors(&c->vc, &head);
-- 
1.7.4.4

Re: [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Tony Lindgren]

* Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:17]:
> Consolidate the setup of the channel control register.  Prepare the
> basic value in the preparation of the DMA descriptor, and write it into
> the register upon descriptor execution.

FYI, this patch seems to be the one that causes the
"DMA timeout with device 55" error for omap1.

Tony

[PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Tony Lindgren]

* Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:17]:
> Consolidate the setup of the channel control register.  Prepare the
> basic value in the preparation of the DMA descriptor, and write it into
> the register upon descriptor execution.

FYI, this patch seems to be the one that causes the
"DMA timeout with device 55" error for omap1.

Tony

Re: [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 02:14:26PM -0800, Tony Lindgren wrote:
> * Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:17]:
> > Consolidate the setup of the channel control register.  Prepare the
> > basic value in the preparation of the DMA descriptor, and write it into
> > the register upon descriptor execution.
> 
> FYI, this patch seems to be the one that causes the
> "DMA timeout with device 55" error for omap1.

Okay, looks like I've missed some bit of muxing for DMA signals or
something.  I've yet to find any information on this in the OMAP5912
docs, so I guess I'm going to have to do this not only blind, but also
without hardware.  GAH.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 02:14:26PM -0800, Tony Lindgren wrote:
> * Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:17]:
> > Consolidate the setup of the channel control register.  Prepare the
> > basic value in the preparation of the DMA descriptor, and write it into
> > the register upon descriptor execution.
> 
> FYI, this patch seems to be the one that causes the
> "DMA timeout with device 55" error for omap1.

Okay, looks like I've missed some bit of muxing for DMA signals or
something.  I've yet to find any information on this in the OMAP5912
docs, so I guess I'm going to have to do this not only blind, but also
without hardware.  GAH.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 11:12:27PM +0000, Russell King - ARM Linux wrote:
> On Mon, Jan 13, 2014 at 02:14:26PM -0800, Tony Lindgren wrote:
> > * Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:17]:
> > > Consolidate the setup of the channel control register.  Prepare the
> > > basic value in the preparation of the DMA descriptor, and write it into
> > > the register upon descriptor execution.
> > 
> > FYI, this patch seems to be the one that causes the
> > "DMA timeout with device 55" error for omap1.
> 
> Okay, looks like I've missed some bit of muxing for DMA signals or
> something.  I've yet to find any information on this in the OMAP5912
> docs, so I guess I'm going to have to do this not only blind, but also
> without hardware.  GAH.

Do you know which of the OMAP1 variants your device is?  Is it OMAP15xx
or OMAP16xx?  It looks like OMAP15xx is easy to fix for this as it hasn't
got the additional multiplexer on the DMA request signals.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 11:12:27PM +0000, Russell King - ARM Linux wrote:
> On Mon, Jan 13, 2014 at 02:14:26PM -0800, Tony Lindgren wrote:
> > * Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:17]:
> > > Consolidate the setup of the channel control register.  Prepare the
> > > basic value in the preparation of the DMA descriptor, and write it into
> > > the register upon descriptor execution.
> > 
> > FYI, this patch seems to be the one that causes the
> > "DMA timeout with device 55" error for omap1.
> 
> Okay, looks like I've missed some bit of muxing for DMA signals or
> something.  I've yet to find any information on this in the OMAP5912
> docs, so I guess I'm going to have to do this not only blind, but also
> without hardware.  GAH.

Do you know which of the OMAP1 variants your device is?  Is it OMAP15xx
or OMAP16xx?  It looks like OMAP15xx is easy to fix for this as it hasn't
got the additional multiplexer on the DMA request signals.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140114 05:41]:
> On Mon, Jan 13, 2014 at 11:12:27PM +0000, Russell King - ARM Linux wrote:
> > On Mon, Jan 13, 2014 at 02:14:26PM -0800, Tony Lindgren wrote:
> > > * Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:17]:
> > > > Consolidate the setup of the channel control register.  Prepare the
> > > > basic value in the preparation of the DMA descriptor, and write it into
> > > > the register upon descriptor execution.
> > > 
> > > FYI, this patch seems to be the one that causes the
> > > "DMA timeout with device 55" error for omap1.
> > 
> > Okay, looks like I've missed some bit of muxing for DMA signals or
> > something.  I've yet to find any information on this in the OMAP5912
> > docs, so I guess I'm going to have to do this not only blind, but also
> > without hardware.  GAH.
> 
> Do you know which of the OMAP1 variants your device is?  Is it OMAP15xx
> or OMAP16xx?  It looks like OMAP15xx is easy to fix for this as it hasn't
> got the additional multiplexer on the DMA request signals.

This was with Nokia 770, which is 1710. Should be pretty much the same
from SoC point of view as 5912 on OSK.

Tony

[PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140114 05:41]:
> On Mon, Jan 13, 2014 at 11:12:27PM +0000, Russell King - ARM Linux wrote:
> > On Mon, Jan 13, 2014 at 02:14:26PM -0800, Tony Lindgren wrote:
> > > * Russell King <rmk+kernel@arm.linux.org.uk> [140102 07:17]:
> > > > Consolidate the setup of the channel control register.  Prepare the
> > > > basic value in the preparation of the DMA descriptor, and write it into
> > > > the register upon descriptor execution.
> > > 
> > > FYI, this patch seems to be the one that causes the
> > > "DMA timeout with device 55" error for omap1.
> > 
> > Okay, looks like I've missed some bit of muxing for DMA signals or
> > something.  I've yet to find any information on this in the OMAP5912
> > docs, so I guess I'm going to have to do this not only blind, but also
> > without hardware.  GAH.
> 
> Do you know which of the OMAP1 variants your device is?  Is it OMAP15xx
> or OMAP16xx?  It looks like OMAP15xx is easy to fix for this as it hasn't
> got the additional multiplexer on the DMA request signals.

This was with Nokia 770, which is 1710. Should be pretty much the same
from SoC point of view as 5912 on OSK.

Tony

Re: [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Sricharan R]

Hi Russell,

On Thursday 02 January 2014 08:40 PM, Russell King wrote:
> Consolidate the setup of the channel control register.  Prepare the
> basic value in the preparation of the DMA descriptor, and write it into
> the register upon descriptor execution.
> 
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  drivers/dma/omap-dma.c |  133 ++++++++++++++++-------------------------------
>  1 files changed, 45 insertions(+), 88 deletions(-)
> 
> diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
> index 98928f7209f6..796f882da03c 100644
> --- a/drivers/dma/omap-dma.c
> +++ b/drivers/dma/omap-dma.c
> @@ -58,8 +58,7 @@ struct omap_desc {
>  
>  	int16_t fi;		/* for OMAP_DMA_SYNC_PACKET */
>  	uint8_t es;		/* OMAP_DMA_DATA_TYPE_xxx */
> -	uint8_t sync_mode;	/* OMAP_DMA_SYNC_xxx */
> -	uint8_t sync_type;	/* OMAP_DMA_xxx_SYNC* */
> +	uint32_t ccr;		/* CCR value */
>  	uint16_t cicr;		/* CICR value */
>  	uint32_t csdp;		/* CSDP value */
>  
> @@ -228,7 +227,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
>  {
>  	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
>  	struct omap_desc *d;
> -	uint32_t val;
>  
>  	if (!vd) {
>  		c->desc = NULL;
> @@ -240,23 +238,15 @@ static void omap_dma_start_desc(struct omap_chan *c)
>  	c->desc = d = to_omap_dma_desc(&vd->tx);
>  	c->sgidx = 0;
>  
> -	if (d->dir == DMA_DEV_TO_MEM) {
> -		val = c->plat->dma_read(CCR, c->dma_ch);
> -		val &= ~(0x03 << 14 | 0x03 << 12);
> -		val |= OMAP_DMA_AMODE_POST_INC << 14;
> -		val |= OMAP_DMA_AMODE_CONSTANT << 12;
> -		c->plat->dma_write(val, CCR, c->dma_ch);
> +	c->plat->dma_write(d->ccr, CCR, c->dma_ch);
> +	if (dma_omap1())
> +		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
>  
> +	if (d->dir == DMA_DEV_TO_MEM) {
>  		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
>  		c->plat->dma_write(0, CSEI, c->dma_ch);
>  		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
>  	} else {
> -		val = c->plat->dma_read(CCR, c->dma_ch);
> -		val &= ~(0x03 << 12 | 0x03 << 14);
> -		val |= OMAP_DMA_AMODE_CONSTANT << 14;
> -		val |= OMAP_DMA_AMODE_POST_INC << 12;
> -		c->plat->dma_write(val, CCR, c->dma_ch);
> -
>  		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
>  		c->plat->dma_write(0, CDEI, c->dma_ch);
>  		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
> @@ -264,47 +254,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
>  
>  	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
>  
> -	if (dma_omap1()) {
> -		val = c->plat->dma_read(CCR, c->dma_ch);
> -		val &= ~(1 << 5);
> -		if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
> -			val |= 1 << 5;
> -		c->plat->dma_write(val, CCR, c->dma_ch);
> -
> -		val = c->plat->dma_read(CCR2, c->dma_ch);
> -		val &= ~(1 << 2);
> -		if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
> -			val |= 1 << 2;
> -		c->plat->dma_write(val, CCR2, c->dma_ch);
> -	}
> -
> -	if (dma_omap2plus() && c->dma_sig) {
> -		val = c->plat->dma_read(CCR, c->dma_ch);
> -
> -		/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
> -		val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
> -		val |= (c->dma_sig & ~0x1f) << 14;
> -		val |= c->dma_sig & 0x1f;
> -
> -		if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
> -			val |= 1 << 5;
> -
> -		if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
> -			val |= 1 << 18;
> -
> -		switch (d->sync_type) {
> -		case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
> -			val |= 1 << 23;		/* Prefetch */
> -			break;
> -		case 0:
> -			break;
> -		default:
> -			val |= 1 << 24; 	/* source synch */
> -			break;
> -		}
> -		c->plat->dma_write(val, CCR, c->dma_ch);
> -	}
> -
>  	omap_dma_start_sg(c, d, 0);
>  }
>  
> @@ -543,19 +492,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
>  	struct scatterlist *sgent;
>  	struct omap_desc *d;
>  	dma_addr_t dev_addr;
> -	unsigned i, j = 0, es, en, frame_bytes, sync_type;
> +	unsigned i, j = 0, es, en, frame_bytes;
>  	u32 burst;
>  
>  	if (dir == DMA_DEV_TO_MEM) {
>  		dev_addr = c->cfg.src_addr;
>  		dev_width = c->cfg.src_addr_width;
>  		burst = c->cfg.src_maxburst;
> -		sync_type = OMAP_DMA_SRC_SYNC;
>  	} else if (dir == DMA_MEM_TO_DEV) {
>  		dev_addr = c->cfg.dst_addr;
>  		dev_width = c->cfg.dst_addr_width;
>  		burst = c->cfg.dst_maxburst;
> -		sync_type = OMAP_DMA_DST_SYNC;
>  	} else {
>  		dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
>  		return NULL;
> @@ -584,12 +531,20 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
>  	d->dir = dir;
>  	d->dev_addr = dev_addr;
>  	d->es = es;
> -	d->sync_mode = OMAP_DMA_SYNC_FRAME;
> -	d->sync_type = sync_type;
> +
> +	d->ccr = 0;
> +	if (dir == DMA_DEV_TO_MEM)
> +		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
> +			  OMAP_DMA_AMODE_CONSTANT << 12;
> +	else
> +		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
> +			  OMAP_DMA_AMODE_POST_INC << 12;
> +
>  	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
>  	d->csdp = es;
>  
>  	if (dma_omap1()) {
> +		d->ccr |= 1 << 5; /* frame sync */
>  		d->cicr |= OMAP1_DMA_TOUT_IRQ;
>  
>  		if (dir == DMA_DEV_TO_MEM)
> @@ -599,6 +554,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
>  			d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
>  				   OMAP_DMA_PORT_EMIFF << 2;
>  	} else if (dma_omap2plus()) {
> +		d->ccr |= (c->dma_sig & ~0x1f) << 14;
> +		d->ccr |= c->dma_sig & 0x1f;
> +		d->ccr |= 1 << 5; /* frame sync */
> +
> +		if (dir == DMA_DEV_TO_MEM)
> +			d->ccr |= 1 << 24; /* source synch */
> +
>  		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
>  	}
>  
> @@ -635,19 +597,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
>  	enum dma_slave_buswidth dev_width;
>  	struct omap_desc *d;
>  	dma_addr_t dev_addr;
> -	unsigned es, sync_type;
> +	unsigned es;
>  	u32 burst;
>  
>  	if (dir == DMA_DEV_TO_MEM) {
>  		dev_addr = c->cfg.src_addr;
>  		dev_width = c->cfg.src_addr_width;
>  		burst = c->cfg.src_maxburst;
> -		sync_type = OMAP_DMA_SRC_SYNC;
>  	} else if (dir == DMA_MEM_TO_DEV) {
>  		dev_addr = c->cfg.dst_addr;
>  		dev_width = c->cfg.dst_addr_width;
>  		burst = c->cfg.dst_maxburst;
> -		sync_type = OMAP_DMA_DST_SYNC;
>  	} else {
>  		dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
>  		return NULL;
> @@ -677,15 +637,21 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
>  	d->dev_addr = dev_addr;
>  	d->fi = burst;
>  	d->es = es;
> -	if (burst)
> -		d->sync_mode = OMAP_DMA_SYNC_PACKET;
> -	else
> -		d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
> -	d->sync_type = sync_type;
>  	d->sg[0].addr = buf_addr;
>  	d->sg[0].en = period_len / es_bytes[es];
>  	d->sg[0].fn = buf_len / period_len;
>  	d->sglen = 1;
> +
> +	d->ccr = 0;
> +	if (__dma_omap15xx(od->plat->dma_attr))
> +		d->ccr = 3 << 8;
> +	if (dir == DMA_DEV_TO_MEM)
> +		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
> +			  OMAP_DMA_AMODE_CONSTANT << 12;
> +	else
> +		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
> +			  OMAP_DMA_AMODE_POST_INC << 12;
> +
>  	d->cicr = OMAP_DMA_DROP_IRQ;
>  	if (flags & DMA_PREP_INTERRUPT)
>  		d->cicr |= OMAP_DMA_FRAME_IRQ;
> @@ -702,23 +668,22 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
>  			d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
>  				   OMAP_DMA_PORT_EMIFF << 2;
>  	} else if (dma_omap2plus()) {
> +		d->ccr |= (c->dma_sig & ~0x1f) << 14;
> +		d->ccr |= c->dma_sig & 0x1f;
> +
> +		if (burst)
> +			d->ccr |= 1 << 18 | 1 << 5; /* packet */
> +
> +		if (dir == DMA_DEV_TO_MEM)
> +			d->ccr |= 1 << 24; /* source synch */
> +
>  		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
>  
>  		/* src and dst burst mode 16 */
>  		d->csdp |= 3 << 14 | 3 << 7;
>  	}
>  
> -	if (!c->cyclic) {
> -		c->cyclic = true;
> -
> -		if (__dma_omap15xx(od->plat->dma_attr)) {
> -			uint32_t val;
> -
> -			val = c->plat->dma_read(CCR, c->dma_ch);
> -			val |= 3 << 8;
> -			c->plat->dma_write(val, CCR, c->dma_ch);
> -		}
> -	}
> +	c->cyclic = true;
>  
>  	return vchan_tx_prep(&c->vc, &d->vd, flags);
>  }
> @@ -762,14 +727,6 @@ static int omap_dma_terminate_all(struct omap_chan *c)
>  	if (c->cyclic) {
>  		c->cyclic = false;
>  		c->paused = false;
> -
> -		if (__dma_omap15xx(od->plat->dma_attr)) {
> -			uint32_t val;
> -
> -			val = c->plat->dma_read(CCR, c->dma_ch);
> -			val &= ~(3 << 8);
> -			c->plat->dma_write(val, CCR, c->dma_ch);
> -		}
>  	}
>  
>  	vchan_get_all_descriptors(&c->vc, &head);


Setting up of DMA_DST_SYNC_PREFETCH is missing after this ?

Regards,
 Sricharan

[PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Sricharan R]

Hi Russell,

On Thursday 02 January 2014 08:40 PM, Russell King wrote:
> Consolidate the setup of the channel control register.  Prepare the
> basic value in the preparation of the DMA descriptor, and write it into
> the register upon descriptor execution.
> 
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  drivers/dma/omap-dma.c |  133 ++++++++++++++++-------------------------------
>  1 files changed, 45 insertions(+), 88 deletions(-)
> 
> diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
> index 98928f7209f6..796f882da03c 100644
> --- a/drivers/dma/omap-dma.c
> +++ b/drivers/dma/omap-dma.c
> @@ -58,8 +58,7 @@ struct omap_desc {
>  
>  	int16_t fi;		/* for OMAP_DMA_SYNC_PACKET */
>  	uint8_t es;		/* OMAP_DMA_DATA_TYPE_xxx */
> -	uint8_t sync_mode;	/* OMAP_DMA_SYNC_xxx */
> -	uint8_t sync_type;	/* OMAP_DMA_xxx_SYNC* */
> +	uint32_t ccr;		/* CCR value */
>  	uint16_t cicr;		/* CICR value */
>  	uint32_t csdp;		/* CSDP value */
>  
> @@ -228,7 +227,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
>  {
>  	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
>  	struct omap_desc *d;
> -	uint32_t val;
>  
>  	if (!vd) {
>  		c->desc = NULL;
> @@ -240,23 +238,15 @@ static void omap_dma_start_desc(struct omap_chan *c)
>  	c->desc = d = to_omap_dma_desc(&vd->tx);
>  	c->sgidx = 0;
>  
> -	if (d->dir == DMA_DEV_TO_MEM) {
> -		val = c->plat->dma_read(CCR, c->dma_ch);
> -		val &= ~(0x03 << 14 | 0x03 << 12);
> -		val |= OMAP_DMA_AMODE_POST_INC << 14;
> -		val |= OMAP_DMA_AMODE_CONSTANT << 12;
> -		c->plat->dma_write(val, CCR, c->dma_ch);
> +	c->plat->dma_write(d->ccr, CCR, c->dma_ch);
> +	if (dma_omap1())
> +		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
>  
> +	if (d->dir == DMA_DEV_TO_MEM) {
>  		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
>  		c->plat->dma_write(0, CSEI, c->dma_ch);
>  		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
>  	} else {
> -		val = c->plat->dma_read(CCR, c->dma_ch);
> -		val &= ~(0x03 << 12 | 0x03 << 14);
> -		val |= OMAP_DMA_AMODE_CONSTANT << 14;
> -		val |= OMAP_DMA_AMODE_POST_INC << 12;
> -		c->plat->dma_write(val, CCR, c->dma_ch);
> -
>  		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
>  		c->plat->dma_write(0, CDEI, c->dma_ch);
>  		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
> @@ -264,47 +254,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
>  
>  	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
>  
> -	if (dma_omap1()) {
> -		val = c->plat->dma_read(CCR, c->dma_ch);
> -		val &= ~(1 << 5);
> -		if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
> -			val |= 1 << 5;
> -		c->plat->dma_write(val, CCR, c->dma_ch);
> -
> -		val = c->plat->dma_read(CCR2, c->dma_ch);
> -		val &= ~(1 << 2);
> -		if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
> -			val |= 1 << 2;
> -		c->plat->dma_write(val, CCR2, c->dma_ch);
> -	}
> -
> -	if (dma_omap2plus() && c->dma_sig) {
> -		val = c->plat->dma_read(CCR, c->dma_ch);
> -
> -		/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
> -		val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
> -		val |= (c->dma_sig & ~0x1f) << 14;
> -		val |= c->dma_sig & 0x1f;
> -
> -		if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
> -			val |= 1 << 5;
> -
> -		if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
> -			val |= 1 << 18;
> -
> -		switch (d->sync_type) {
> -		case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
> -			val |= 1 << 23;		/* Prefetch */
> -			break;
> -		case 0:
> -			break;
> -		default:
> -			val |= 1 << 24; 	/* source synch */
> -			break;
> -		}
> -		c->plat->dma_write(val, CCR, c->dma_ch);
> -	}
> -
>  	omap_dma_start_sg(c, d, 0);
>  }
>  
> @@ -543,19 +492,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
>  	struct scatterlist *sgent;
>  	struct omap_desc *d;
>  	dma_addr_t dev_addr;
> -	unsigned i, j = 0, es, en, frame_bytes, sync_type;
> +	unsigned i, j = 0, es, en, frame_bytes;
>  	u32 burst;
>  
>  	if (dir == DMA_DEV_TO_MEM) {
>  		dev_addr = c->cfg.src_addr;
>  		dev_width = c->cfg.src_addr_width;
>  		burst = c->cfg.src_maxburst;
> -		sync_type = OMAP_DMA_SRC_SYNC;
>  	} else if (dir == DMA_MEM_TO_DEV) {
>  		dev_addr = c->cfg.dst_addr;
>  		dev_width = c->cfg.dst_addr_width;
>  		burst = c->cfg.dst_maxburst;
> -		sync_type = OMAP_DMA_DST_SYNC;
>  	} else {
>  		dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
>  		return NULL;
> @@ -584,12 +531,20 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
>  	d->dir = dir;
>  	d->dev_addr = dev_addr;
>  	d->es = es;
> -	d->sync_mode = OMAP_DMA_SYNC_FRAME;
> -	d->sync_type = sync_type;
> +
> +	d->ccr = 0;
> +	if (dir == DMA_DEV_TO_MEM)
> +		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
> +			  OMAP_DMA_AMODE_CONSTANT << 12;
> +	else
> +		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
> +			  OMAP_DMA_AMODE_POST_INC << 12;
> +
>  	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
>  	d->csdp = es;
>  
>  	if (dma_omap1()) {
> +		d->ccr |= 1 << 5; /* frame sync */
>  		d->cicr |= OMAP1_DMA_TOUT_IRQ;
>  
>  		if (dir == DMA_DEV_TO_MEM)
> @@ -599,6 +554,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
>  			d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
>  				   OMAP_DMA_PORT_EMIFF << 2;
>  	} else if (dma_omap2plus()) {
> +		d->ccr |= (c->dma_sig & ~0x1f) << 14;
> +		d->ccr |= c->dma_sig & 0x1f;
> +		d->ccr |= 1 << 5; /* frame sync */
> +
> +		if (dir == DMA_DEV_TO_MEM)
> +			d->ccr |= 1 << 24; /* source synch */
> +
>  		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
>  	}
>  
> @@ -635,19 +597,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
>  	enum dma_slave_buswidth dev_width;
>  	struct omap_desc *d;
>  	dma_addr_t dev_addr;
> -	unsigned es, sync_type;
> +	unsigned es;
>  	u32 burst;
>  
>  	if (dir == DMA_DEV_TO_MEM) {
>  		dev_addr = c->cfg.src_addr;
>  		dev_width = c->cfg.src_addr_width;
>  		burst = c->cfg.src_maxburst;
> -		sync_type = OMAP_DMA_SRC_SYNC;
>  	} else if (dir == DMA_MEM_TO_DEV) {
>  		dev_addr = c->cfg.dst_addr;
>  		dev_width = c->cfg.dst_addr_width;
>  		burst = c->cfg.dst_maxburst;
> -		sync_type = OMAP_DMA_DST_SYNC;
>  	} else {
>  		dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
>  		return NULL;
> @@ -677,15 +637,21 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
>  	d->dev_addr = dev_addr;
>  	d->fi = burst;
>  	d->es = es;
> -	if (burst)
> -		d->sync_mode = OMAP_DMA_SYNC_PACKET;
> -	else
> -		d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
> -	d->sync_type = sync_type;
>  	d->sg[0].addr = buf_addr;
>  	d->sg[0].en = period_len / es_bytes[es];
>  	d->sg[0].fn = buf_len / period_len;
>  	d->sglen = 1;
> +
> +	d->ccr = 0;
> +	if (__dma_omap15xx(od->plat->dma_attr))
> +		d->ccr = 3 << 8;
> +	if (dir == DMA_DEV_TO_MEM)
> +		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
> +			  OMAP_DMA_AMODE_CONSTANT << 12;
> +	else
> +		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
> +			  OMAP_DMA_AMODE_POST_INC << 12;
> +
>  	d->cicr = OMAP_DMA_DROP_IRQ;
>  	if (flags & DMA_PREP_INTERRUPT)
>  		d->cicr |= OMAP_DMA_FRAME_IRQ;
> @@ -702,23 +668,22 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
>  			d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
>  				   OMAP_DMA_PORT_EMIFF << 2;
>  	} else if (dma_omap2plus()) {
> +		d->ccr |= (c->dma_sig & ~0x1f) << 14;
> +		d->ccr |= c->dma_sig & 0x1f;
> +
> +		if (burst)
> +			d->ccr |= 1 << 18 | 1 << 5; /* packet */
> +
> +		if (dir == DMA_DEV_TO_MEM)
> +			d->ccr |= 1 << 24; /* source synch */
> +
>  		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
>  
>  		/* src and dst burst mode 16 */
>  		d->csdp |= 3 << 14 | 3 << 7;
>  	}
>  
> -	if (!c->cyclic) {
> -		c->cyclic = true;
> -
> -		if (__dma_omap15xx(od->plat->dma_attr)) {
> -			uint32_t val;
> -
> -			val = c->plat->dma_read(CCR, c->dma_ch);
> -			val |= 3 << 8;
> -			c->plat->dma_write(val, CCR, c->dma_ch);
> -		}
> -	}
> +	c->cyclic = true;
>  
>  	return vchan_tx_prep(&c->vc, &d->vd, flags);
>  }
> @@ -762,14 +727,6 @@ static int omap_dma_terminate_all(struct omap_chan *c)
>  	if (c->cyclic) {
>  		c->cyclic = false;
>  		c->paused = false;
> -
> -		if (__dma_omap15xx(od->plat->dma_attr)) {
> -			uint32_t val;
> -
> -			val = c->plat->dma_read(CCR, c->dma_ch);
> -			val &= ~(3 << 8);
> -			c->plat->dma_write(val, CCR, c->dma_ch);
> -		}
>  	}
>  
>  	vchan_get_all_descriptors(&c->vc, &head);


Setting up of DMA_DST_SYNC_PREFETCH is missing after this ?

Regards,
 Sricharan

Re: [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Russell King - ARM Linux]

On Wed, Jan 22, 2014 at 06:25:57PM +0530, Sricharan R wrote:
> Setting up of DMA_DST_SYNC_PREFETCH is missing after this ?

I'm not looking for the DMA engine driver to be a 100% reimplementation
of the legacy driver.  Rather than supporting the entire set of features
which the legacy driver did, and have many of them simply not used, the
approach I'm taking here is to only support what is necessary for the
drivers we have in mainline - and what fits the DMA engine interfaces.

There is no point inventing new DMA engine interfaces for features for
which we have no users in mainline kernel - to try to do that will be
quite rightfully thrown out by the DMA engine maintainers.

Here's the total number of references/definitions of DMA_DST_SYNC_PREFETCH
in the mainline kernel:

arch/arm/plat-omap/dma.c:               if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
include/linux/omap-dma.h:#define OMAP_DMA_DST_SYNC_PREFETCH     0x02

Hence, this feature is unused at present.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Russell King - ARM Linux]

On Wed, Jan 22, 2014 at 06:25:57PM +0530, Sricharan R wrote:
> Setting up of DMA_DST_SYNC_PREFETCH is missing after this ?

I'm not looking for the DMA engine driver to be a 100% reimplementation
of the legacy driver.  Rather than supporting the entire set of features
which the legacy driver did, and have many of them simply not used, the
approach I'm taking here is to only support what is necessary for the
drivers we have in mainline - and what fits the DMA engine interfaces.

There is no point inventing new DMA engine interfaces for features for
which we have no users in mainline kernel - to try to do that will be
quite rightfully thrown out by the DMA engine maintainers.

Here's the total number of references/definitions of DMA_DST_SYNC_PREFETCH
in the mainline kernel:

arch/arm/plat-omap/dma.c:               if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
include/linux/omap-dma.h:#define OMAP_DMA_DST_SYNC_PREFETCH     0x02

Hence, this feature is unused at present.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Santosh Shilimkar]

On Wednesday 22 January 2014 09:19 AM, Russell King - ARM Linux wrote:
> On Wed, Jan 22, 2014 at 06:25:57PM +0530, Sricharan R wrote:
>> Setting up of DMA_DST_SYNC_PREFETCH is missing after this ?
> 
> I'm not looking for the DMA engine driver to be a 100% reimplementation
> of the legacy driver.  Rather than supporting the entire set of features
> which the legacy driver did, and have many of them simply not used, the
> approach I'm taking here is to only support what is necessary for the
> drivers we have in mainline - and what fits the DMA engine interfaces.
> 
+1 on the approach.

> There is no point inventing new DMA engine interfaces for features for
> which we have no users in mainline kernel - to try to do that will be
> quite rightfully thrown out by the DMA engine maintainers.
> 
> Here's the total number of references/definitions of DMA_DST_SYNC_PREFETCH
> in the mainline kernel:
> 
> arch/arm/plat-omap/dma.c:               if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
> include/linux/omap-dma.h:#define OMAP_DMA_DST_SYNC_PREFETCH     0x02
> 
> Hence, this feature is unused at present.
> 
I thought the crypto was using the prefetch feature but it isn't. 

Regards,
Santosh

[PATCH RFC 08/26] dmaengine: omap-dma: consolidate setup of CCR

[Santosh Shilimkar]

On Wednesday 22 January 2014 09:19 AM, Russell King - ARM Linux wrote:
> On Wed, Jan 22, 2014 at 06:25:57PM +0530, Sricharan R wrote:
>> Setting up of DMA_DST_SYNC_PREFETCH is missing after this ?
> 
> I'm not looking for the DMA engine driver to be a 100% reimplementation
> of the legacy driver.  Rather than supporting the entire set of features
> which the legacy driver did, and have many of them simply not used, the
> approach I'm taking here is to only support what is necessary for the
> drivers we have in mainline - and what fits the DMA engine interfaces.
> 
+1 on the approach.

> There is no point inventing new DMA engine interfaces for features for
> which we have no users in mainline kernel - to try to do that will be
> quite rightfully thrown out by the DMA engine maintainers.
> 
> Here's the total number of references/definitions of DMA_DST_SYNC_PREFETCH
> in the mainline kernel:
> 
> arch/arm/plat-omap/dma.c:               if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
> include/linux/omap-dma.h:#define OMAP_DMA_DST_SYNC_PREFETCH     0x02
> 
> Hence, this feature is unused at present.
> 
I thought the crypto was using the prefetch feature but it isn't. 

Regards,
Santosh

[PATCH RFC 09/26] dmaengine: omap-dma: provide register definitions

[Russell King]

Provide our own set of more complete register definitions; this allows
us to get rid of the meaningless 1 << n constants scattered throughout
this code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  166 +++++++++++++++++++++++++++++++++---------------
 1 files changed, 114 insertions(+), 52 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 796f882da03c..13dca8e0ef32 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -57,7 +57,7 @@ struct omap_desc {
 	dma_addr_t dev_addr;
 
 	int16_t fi;		/* for OMAP_DMA_SYNC_PACKET */
-	uint8_t es;		/* OMAP_DMA_DATA_TYPE_xxx */
+	uint8_t es;		/* CSDP_DATA_TYPE_xxx */
 	uint32_t ccr;		/* CCR value */
 	uint16_t cicr;		/* CICR value */
 	uint32_t csdp;		/* CSDP value */
@@ -66,10 +66,82 @@ struct omap_desc {
 	struct omap_sg sg[0];
 };
 
+enum {
+	CCR_FS			= BIT(5),
+	CCR_READ_PRIORITY	= BIT(6),
+	CCR_ENABLE		= BIT(7),
+	CCR_AUTO_INIT		= BIT(8),	/* OMAP1 only */
+	CCR_REPEAT		= BIT(9),	/* OMAP1 only */
+	CCR_SUSPEND_SENSITIVE	= BIT(8),	/* OMAP2+ only */
+	CCR_RD_ACTIVE		= BIT(9),	/* OMAP2+ only */
+	CCR_WR_ACTIVE		= BIT(10),	/* OMAP2+ only */
+	CCR_SRC_AMODE_CONSTANT	= 0 << 12,
+	CCR_SRC_AMODE_POSTINC	= 1 << 12,
+	CCR_SRC_AMODE_SGLIDX	= 2 << 12,
+	CCR_SRC_AMODE_DBLIDX	= 3 << 12,
+	CCR_DST_AMODE_CONSTANT	= 0 << 14,
+	CCR_DST_AMODE_POSTINC	= 1 << 14,
+	CCR_DST_AMODE_SGLIDX	= 2 << 14,
+	CCR_DST_AMODE_DBLIDX	= 3 << 14,
+	CCR_CONSTANT_FILL	= BIT(16),
+	CCR_TRANSPARENT_COPY	= BIT(17),
+	CCR_BS			= BIT(18),
+	CCR_SUPERVISOR		= BIT(22),
+	CCR_PREFETCH		= BIT(23),
+	CCR_TRIGGER_SRC		= BIT(24),
+	CCR_BUFFERING_DISABLE	= BIT(25),
+	CCR_WRITE_PRIORITY	= BIT(26),
+	CCR_SYNC_ELEMENT	= 0,
+	CCR_SYNC_FRAME		= CCR_FS,
+	CCR_SYNC_BLOCK		= CCR_BS,
+	CCR_SYNC_PACKET		= CCR_BS | CCR_FS,
+
+	CSDP_DATA_TYPE_8	= 0,
+	CSDP_DATA_TYPE_16	= 1,
+	CSDP_DATA_TYPE_32	= 2,
+	CSDP_SRC_PORT_EMIFF	= 0 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_EMIFS	= 1 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_OCP_T1	= 2 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_TIPB	= 3 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_OCP_T2	= 4 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_MPUI	= 5 << 2, /* OMAP1 only */
+	CSDP_SRC_PACKED		= BIT(6),
+	CSDP_SRC_BURST_1	= 0 << 7,
+	CSDP_SRC_BURST_16	= 1 << 7,
+	CSDP_SRC_BURST_32	= 2 << 7,
+	CSDP_SRC_BURST_64	= 3 << 7,
+	CSDP_DST_PORT_EMIFF	= 0 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_EMIFS	= 1 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_OCP_T1	= 2 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_TIPB	= 3 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_OCP_T2	= 4 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_MPUI	= 5 << 9, /* OMAP1 only */
+	CSDP_DST_PACKED		= BIT(13),
+	CSDP_DST_BURST_1	= 0 << 14,
+	CSDP_DST_BURST_16	= 1 << 14,
+	CSDP_DST_BURST_32	= 2 << 14,
+	CSDP_DST_BURST_64	= 3 << 14,
+
+	CICR_TOUT_IE		= BIT(0),	/* OMAP1 only */
+	CICR_DROP_IE		= BIT(1),
+	CICR_HALF_IE		= BIT(2),
+	CICR_FRAME_IE		= BIT(3),
+	CICR_LAST_IE		= BIT(4),
+	CICR_BLOCK_IE		= BIT(5),
+	CICR_PKT_IE		= BIT(7),	/* OMAP2+ only */
+	CICR_TRANS_ERR_IE	= BIT(8),	/* OMAP2+ only */
+	CICR_SUPERVISOR_ERR_IE	= BIT(10),	/* OMAP2+ only */
+	CICR_MISALIGNED_ERR_IE	= BIT(11),	/* OMAP2+ only */
+	CICR_DRAIN_IE		= BIT(12),	/* OMAP2+ only */
+	CICR_SUPER_BLOCK_IE	= BIT(14),	/* OMAP2+ only */
+
+	CLNK_CTRL_ENABLE_LNK	= BIT(15),
+};
+
 static const unsigned es_bytes[] = {
-	[OMAP_DMA_DATA_TYPE_S8] = 1,
-	[OMAP_DMA_DATA_TYPE_S16] = 2,
-	[OMAP_DMA_DATA_TYPE_S32] = 4,
+	[CSDP_DATA_TYPE_8] = 1,
+	[CSDP_DATA_TYPE_16] = 2,
+	[CSDP_DATA_TYPE_32] = 4,
 };
 
 static struct of_dma_filter_info omap_dma_info = {
@@ -112,7 +184,7 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 		if (dma_omap1())
 			val &= ~(1 << 14);
 
-		val |= c->dma_ch | 1 << 15;
+		val |= c->dma_ch | CLNK_CTRL_ENABLE_LNK;
 
 		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
 	} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
@@ -129,8 +201,8 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
 	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
-		val |= OMAP_DMA_CCR_BUFFERING_DISABLE;
-	val |= OMAP_DMA_CCR_EN;
+		val |= CCR_BUFFERING_DISABLE;
+	val |= CCR_ENABLE;
 	mb();
 	c->plat->dma_write(val, CCR, c->dma_ch);
 }
@@ -150,8 +222,7 @@ static void omap_dma_stop(struct omap_chan *c)
 		c->plat->dma_write(~0, CSR, c->dma_ch);
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
-	if (od->plat->errata & DMA_ERRATA_i541 &&
-	    val & OMAP_DMA_CCR_SEL_SRC_DST_SYNC) {
+	if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
 		uint32_t sysconfig;
 		unsigned i;
 
@@ -161,13 +232,13 @@ static void omap_dma_stop(struct omap_chan *c)
 		c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch);
 
 		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~OMAP_DMA_CCR_EN;
+		val &= ~CCR_ENABLE;
 		c->plat->dma_write(val, CCR, c->dma_ch);
 
 		/* Wait for sDMA FIFO to drain */
 		for (i = 0; ; i++) {
 			val = c->plat->dma_read(CCR, c->dma_ch);
-			if (!(val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE)))
+			if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
 				break;
 
 			if (i > 100)
@@ -176,14 +247,14 @@ static void omap_dma_stop(struct omap_chan *c)
 			udelay(5);
 		}
 
-		if (val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE))
+		if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))
 			dev_err(c->vc.chan.device->dev,
 				"DMA drain did not complete on lch %d\n",
 			        c->dma_ch);
 
 		c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch);
 	} else {
-		val &= ~OMAP_DMA_CCR_EN;
+		val &= ~CCR_ENABLE;
 		c->plat->dma_write(val, CCR, c->dma_ch);
 	}
 
@@ -196,7 +267,7 @@ static void omap_dma_stop(struct omap_chan *c)
 			val |= 1 << 14; /* set the STOP_LNK bit */
 
 		if (dma_omap2plus())
-			val &= ~(1 << 15); /* Clear the ENABLE_LNK bit */
+			val &= ~CLNK_CTRL_ENABLE_LNK;
 
 		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
 	}
@@ -511,13 +582,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	/* Bus width translates to the element size (ES) */
 	switch (dev_width) {
 	case DMA_SLAVE_BUSWIDTH_1_BYTE:
-		es = OMAP_DMA_DATA_TYPE_S8;
+		es = CSDP_DATA_TYPE_8;
 		break;
 	case DMA_SLAVE_BUSWIDTH_2_BYTES:
-		es = OMAP_DMA_DATA_TYPE_S16;
+		es = CSDP_DATA_TYPE_16;
 		break;
 	case DMA_SLAVE_BUSWIDTH_4_BYTES:
-		es = OMAP_DMA_DATA_TYPE_S32;
+		es = CSDP_DATA_TYPE_32;
 		break;
 	default: /* not reached */
 		return NULL;
@@ -532,36 +603,30 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	d->dev_addr = dev_addr;
 	d->es = es;
 
-	d->ccr = 0;
+	d->ccr = CCR_SYNC_FRAME;
 	if (dir == DMA_DEV_TO_MEM)
-		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
-			  OMAP_DMA_AMODE_CONSTANT << 12;
+		d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
 	else
-		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
-			  OMAP_DMA_AMODE_POST_INC << 12;
+		d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
 
-	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
+	d->cicr = CICR_DROP_IE | CICR_BLOCK_IE;
 	d->csdp = es;
 
 	if (dma_omap1()) {
-		d->ccr |= 1 << 5; /* frame sync */
-		d->cicr |= OMAP1_DMA_TOUT_IRQ;
+		d->cicr |= CICR_TOUT_IE;
 
 		if (dir == DMA_DEV_TO_MEM)
-			d->csdp |= OMAP_DMA_PORT_EMIFF << 9 |
-				   OMAP_DMA_PORT_TIPB << 2;
+			d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB;
 		else
-			d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
-				   OMAP_DMA_PORT_EMIFF << 2;
+			d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF;
 	} else if (dma_omap2plus()) {
 		d->ccr |= (c->dma_sig & ~0x1f) << 14;
 		d->ccr |= c->dma_sig & 0x1f;
-		d->ccr |= 1 << 5; /* frame sync */
 
 		if (dir == DMA_DEV_TO_MEM)
-			d->ccr |= 1 << 24; /* source synch */
+			d->ccr |= CCR_TRIGGER_SRC;
 
-		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
+		d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
 	}
 
 	/*
@@ -616,13 +681,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	/* Bus width translates to the element size (ES) */
 	switch (dev_width) {
 	case DMA_SLAVE_BUSWIDTH_1_BYTE:
-		es = OMAP_DMA_DATA_TYPE_S8;
+		es = CSDP_DATA_TYPE_8;
 		break;
 	case DMA_SLAVE_BUSWIDTH_2_BYTES:
-		es = OMAP_DMA_DATA_TYPE_S16;
+		es = CSDP_DATA_TYPE_16;
 		break;
 	case DMA_SLAVE_BUSWIDTH_4_BYTES:
-		es = OMAP_DMA_DATA_TYPE_S32;
+		es = CSDP_DATA_TYPE_32;
 		break;
 	default: /* not reached */
 		return NULL;
@@ -644,43 +709,40 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 
 	d->ccr = 0;
 	if (__dma_omap15xx(od->plat->dma_attr))
-		d->ccr = 3 << 8;
+		d->ccr = CCR_AUTO_INIT | CCR_REPEAT;
 	if (dir == DMA_DEV_TO_MEM)
-		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
-			  OMAP_DMA_AMODE_CONSTANT << 12;
+		d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
 	else
-		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
-			  OMAP_DMA_AMODE_POST_INC << 12;
+		d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
 
-	d->cicr = OMAP_DMA_DROP_IRQ;
+	d->cicr = CICR_DROP_IE;
 	if (flags & DMA_PREP_INTERRUPT)
-		d->cicr |= OMAP_DMA_FRAME_IRQ;
+		d->cicr |= CICR_FRAME_IE;
 
 	d->csdp = es;
 
 	if (dma_omap1()) {
-		d->cicr |= OMAP1_DMA_TOUT_IRQ;
+		d->cicr |= CICR_TOUT_IE;
 
 		if (dir == DMA_DEV_TO_MEM)
-			d->csdp |= OMAP_DMA_PORT_EMIFF << 9 |
-				   OMAP_DMA_PORT_MPUI << 2;
+			d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI;
 		else
-			d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
-				   OMAP_DMA_PORT_EMIFF << 2;
+			d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF;
 	} else if (dma_omap2plus()) {
 		d->ccr |= (c->dma_sig & ~0x1f) << 14;
 		d->ccr |= c->dma_sig & 0x1f;
 
 		if (burst)
-			d->ccr |= 1 << 18 | 1 << 5; /* packet */
+			d->ccr |= CCR_SYNC_PACKET;
+		else
+			d->ccr |= CCR_SYNC_ELEMENT;
 
 		if (dir == DMA_DEV_TO_MEM)
-			d->ccr |= 1 << 24; /* source synch */
+			d->ccr |= CCR_TRIGGER_SRC;
 
-		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
+		d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
 
-		/* src and dst burst mode 16 */
-		d->csdp |= 3 << 14 | 3 << 7;
+		d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
 	}
 
 	c->cyclic = true;
-- 
1.7.4.4

[PATCH RFC 09/26] dmaengine: omap-dma: provide register definitions

[Russell King]

Provide our own set of more complete register definitions; this allows
us to get rid of the meaningless 1 << n constants scattered throughout
this code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  166 +++++++++++++++++++++++++++++++++---------------
 1 files changed, 114 insertions(+), 52 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 796f882da03c..13dca8e0ef32 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -57,7 +57,7 @@ struct omap_desc {
 	dma_addr_t dev_addr;
 
 	int16_t fi;		/* for OMAP_DMA_SYNC_PACKET */
-	uint8_t es;		/* OMAP_DMA_DATA_TYPE_xxx */
+	uint8_t es;		/* CSDP_DATA_TYPE_xxx */
 	uint32_t ccr;		/* CCR value */
 	uint16_t cicr;		/* CICR value */
 	uint32_t csdp;		/* CSDP value */
@@ -66,10 +66,82 @@ struct omap_desc {
 	struct omap_sg sg[0];
 };
 
+enum {
+	CCR_FS			= BIT(5),
+	CCR_READ_PRIORITY	= BIT(6),
+	CCR_ENABLE		= BIT(7),
+	CCR_AUTO_INIT		= BIT(8),	/* OMAP1 only */
+	CCR_REPEAT		= BIT(9),	/* OMAP1 only */
+	CCR_SUSPEND_SENSITIVE	= BIT(8),	/* OMAP2+ only */
+	CCR_RD_ACTIVE		= BIT(9),	/* OMAP2+ only */
+	CCR_WR_ACTIVE		= BIT(10),	/* OMAP2+ only */
+	CCR_SRC_AMODE_CONSTANT	= 0 << 12,
+	CCR_SRC_AMODE_POSTINC	= 1 << 12,
+	CCR_SRC_AMODE_SGLIDX	= 2 << 12,
+	CCR_SRC_AMODE_DBLIDX	= 3 << 12,
+	CCR_DST_AMODE_CONSTANT	= 0 << 14,
+	CCR_DST_AMODE_POSTINC	= 1 << 14,
+	CCR_DST_AMODE_SGLIDX	= 2 << 14,
+	CCR_DST_AMODE_DBLIDX	= 3 << 14,
+	CCR_CONSTANT_FILL	= BIT(16),
+	CCR_TRANSPARENT_COPY	= BIT(17),
+	CCR_BS			= BIT(18),
+	CCR_SUPERVISOR		= BIT(22),
+	CCR_PREFETCH		= BIT(23),
+	CCR_TRIGGER_SRC		= BIT(24),
+	CCR_BUFFERING_DISABLE	= BIT(25),
+	CCR_WRITE_PRIORITY	= BIT(26),
+	CCR_SYNC_ELEMENT	= 0,
+	CCR_SYNC_FRAME		= CCR_FS,
+	CCR_SYNC_BLOCK		= CCR_BS,
+	CCR_SYNC_PACKET		= CCR_BS | CCR_FS,
+
+	CSDP_DATA_TYPE_8	= 0,
+	CSDP_DATA_TYPE_16	= 1,
+	CSDP_DATA_TYPE_32	= 2,
+	CSDP_SRC_PORT_EMIFF	= 0 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_EMIFS	= 1 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_OCP_T1	= 2 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_TIPB	= 3 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_OCP_T2	= 4 << 2, /* OMAP1 only */
+	CSDP_SRC_PORT_MPUI	= 5 << 2, /* OMAP1 only */
+	CSDP_SRC_PACKED		= BIT(6),
+	CSDP_SRC_BURST_1	= 0 << 7,
+	CSDP_SRC_BURST_16	= 1 << 7,
+	CSDP_SRC_BURST_32	= 2 << 7,
+	CSDP_SRC_BURST_64	= 3 << 7,
+	CSDP_DST_PORT_EMIFF	= 0 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_EMIFS	= 1 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_OCP_T1	= 2 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_TIPB	= 3 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_OCP_T2	= 4 << 9, /* OMAP1 only */
+	CSDP_DST_PORT_MPUI	= 5 << 9, /* OMAP1 only */
+	CSDP_DST_PACKED		= BIT(13),
+	CSDP_DST_BURST_1	= 0 << 14,
+	CSDP_DST_BURST_16	= 1 << 14,
+	CSDP_DST_BURST_32	= 2 << 14,
+	CSDP_DST_BURST_64	= 3 << 14,
+
+	CICR_TOUT_IE		= BIT(0),	/* OMAP1 only */
+	CICR_DROP_IE		= BIT(1),
+	CICR_HALF_IE		= BIT(2),
+	CICR_FRAME_IE		= BIT(3),
+	CICR_LAST_IE		= BIT(4),
+	CICR_BLOCK_IE		= BIT(5),
+	CICR_PKT_IE		= BIT(7),	/* OMAP2+ only */
+	CICR_TRANS_ERR_IE	= BIT(8),	/* OMAP2+ only */
+	CICR_SUPERVISOR_ERR_IE	= BIT(10),	/* OMAP2+ only */
+	CICR_MISALIGNED_ERR_IE	= BIT(11),	/* OMAP2+ only */
+	CICR_DRAIN_IE		= BIT(12),	/* OMAP2+ only */
+	CICR_SUPER_BLOCK_IE	= BIT(14),	/* OMAP2+ only */
+
+	CLNK_CTRL_ENABLE_LNK	= BIT(15),
+};
+
 static const unsigned es_bytes[] = {
-	[OMAP_DMA_DATA_TYPE_S8] = 1,
-	[OMAP_DMA_DATA_TYPE_S16] = 2,
-	[OMAP_DMA_DATA_TYPE_S32] = 4,
+	[CSDP_DATA_TYPE_8] = 1,
+	[CSDP_DATA_TYPE_16] = 2,
+	[CSDP_DATA_TYPE_32] = 4,
 };
 
 static struct of_dma_filter_info omap_dma_info = {
@@ -112,7 +184,7 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 		if (dma_omap1())
 			val &= ~(1 << 14);
 
-		val |= c->dma_ch | 1 << 15;
+		val |= c->dma_ch | CLNK_CTRL_ENABLE_LNK;
 
 		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
 	} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
@@ -129,8 +201,8 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
 	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
-		val |= OMAP_DMA_CCR_BUFFERING_DISABLE;
-	val |= OMAP_DMA_CCR_EN;
+		val |= CCR_BUFFERING_DISABLE;
+	val |= CCR_ENABLE;
 	mb();
 	c->plat->dma_write(val, CCR, c->dma_ch);
 }
@@ -150,8 +222,7 @@ static void omap_dma_stop(struct omap_chan *c)
 		c->plat->dma_write(~0, CSR, c->dma_ch);
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
-	if (od->plat->errata & DMA_ERRATA_i541 &&
-	    val & OMAP_DMA_CCR_SEL_SRC_DST_SYNC) {
+	if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
 		uint32_t sysconfig;
 		unsigned i;
 
@@ -161,13 +232,13 @@ static void omap_dma_stop(struct omap_chan *c)
 		c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch);
 
 		val = c->plat->dma_read(CCR, c->dma_ch);
-		val &= ~OMAP_DMA_CCR_EN;
+		val &= ~CCR_ENABLE;
 		c->plat->dma_write(val, CCR, c->dma_ch);
 
 		/* Wait for sDMA FIFO to drain */
 		for (i = 0; ; i++) {
 			val = c->plat->dma_read(CCR, c->dma_ch);
-			if (!(val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE)))
+			if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
 				break;
 
 			if (i > 100)
@@ -176,14 +247,14 @@ static void omap_dma_stop(struct omap_chan *c)
 			udelay(5);
 		}
 
-		if (val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE))
+		if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))
 			dev_err(c->vc.chan.device->dev,
 				"DMA drain did not complete on lch %d\n",
 			        c->dma_ch);
 
 		c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch);
 	} else {
-		val &= ~OMAP_DMA_CCR_EN;
+		val &= ~CCR_ENABLE;
 		c->plat->dma_write(val, CCR, c->dma_ch);
 	}
 
@@ -196,7 +267,7 @@ static void omap_dma_stop(struct omap_chan *c)
 			val |= 1 << 14; /* set the STOP_LNK bit */
 
 		if (dma_omap2plus())
-			val &= ~(1 << 15); /* Clear the ENABLE_LNK bit */
+			val &= ~CLNK_CTRL_ENABLE_LNK;
 
 		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
 	}
@@ -511,13 +582,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	/* Bus width translates to the element size (ES) */
 	switch (dev_width) {
 	case DMA_SLAVE_BUSWIDTH_1_BYTE:
-		es = OMAP_DMA_DATA_TYPE_S8;
+		es = CSDP_DATA_TYPE_8;
 		break;
 	case DMA_SLAVE_BUSWIDTH_2_BYTES:
-		es = OMAP_DMA_DATA_TYPE_S16;
+		es = CSDP_DATA_TYPE_16;
 		break;
 	case DMA_SLAVE_BUSWIDTH_4_BYTES:
-		es = OMAP_DMA_DATA_TYPE_S32;
+		es = CSDP_DATA_TYPE_32;
 		break;
 	default: /* not reached */
 		return NULL;
@@ -532,36 +603,30 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	d->dev_addr = dev_addr;
 	d->es = es;
 
-	d->ccr = 0;
+	d->ccr = CCR_SYNC_FRAME;
 	if (dir == DMA_DEV_TO_MEM)
-		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
-			  OMAP_DMA_AMODE_CONSTANT << 12;
+		d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
 	else
-		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
-			  OMAP_DMA_AMODE_POST_INC << 12;
+		d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
 
-	d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
+	d->cicr = CICR_DROP_IE | CICR_BLOCK_IE;
 	d->csdp = es;
 
 	if (dma_omap1()) {
-		d->ccr |= 1 << 5; /* frame sync */
-		d->cicr |= OMAP1_DMA_TOUT_IRQ;
+		d->cicr |= CICR_TOUT_IE;
 
 		if (dir == DMA_DEV_TO_MEM)
-			d->csdp |= OMAP_DMA_PORT_EMIFF << 9 |
-				   OMAP_DMA_PORT_TIPB << 2;
+			d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB;
 		else
-			d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
-				   OMAP_DMA_PORT_EMIFF << 2;
+			d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF;
 	} else if (dma_omap2plus()) {
 		d->ccr |= (c->dma_sig & ~0x1f) << 14;
 		d->ccr |= c->dma_sig & 0x1f;
-		d->ccr |= 1 << 5; /* frame sync */
 
 		if (dir == DMA_DEV_TO_MEM)
-			d->ccr |= 1 << 24; /* source synch */
+			d->ccr |= CCR_TRIGGER_SRC;
 
-		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
+		d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
 	}
 
 	/*
@@ -616,13 +681,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	/* Bus width translates to the element size (ES) */
 	switch (dev_width) {
 	case DMA_SLAVE_BUSWIDTH_1_BYTE:
-		es = OMAP_DMA_DATA_TYPE_S8;
+		es = CSDP_DATA_TYPE_8;
 		break;
 	case DMA_SLAVE_BUSWIDTH_2_BYTES:
-		es = OMAP_DMA_DATA_TYPE_S16;
+		es = CSDP_DATA_TYPE_16;
 		break;
 	case DMA_SLAVE_BUSWIDTH_4_BYTES:
-		es = OMAP_DMA_DATA_TYPE_S32;
+		es = CSDP_DATA_TYPE_32;
 		break;
 	default: /* not reached */
 		return NULL;
@@ -644,43 +709,40 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 
 	d->ccr = 0;
 	if (__dma_omap15xx(od->plat->dma_attr))
-		d->ccr = 3 << 8;
+		d->ccr = CCR_AUTO_INIT | CCR_REPEAT;
 	if (dir == DMA_DEV_TO_MEM)
-		d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
-			  OMAP_DMA_AMODE_CONSTANT << 12;
+		d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
 	else
-		d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
-			  OMAP_DMA_AMODE_POST_INC << 12;
+		d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
 
-	d->cicr = OMAP_DMA_DROP_IRQ;
+	d->cicr = CICR_DROP_IE;
 	if (flags & DMA_PREP_INTERRUPT)
-		d->cicr |= OMAP_DMA_FRAME_IRQ;
+		d->cicr |= CICR_FRAME_IE;
 
 	d->csdp = es;
 
 	if (dma_omap1()) {
-		d->cicr |= OMAP1_DMA_TOUT_IRQ;
+		d->cicr |= CICR_TOUT_IE;
 
 		if (dir == DMA_DEV_TO_MEM)
-			d->csdp |= OMAP_DMA_PORT_EMIFF << 9 |
-				   OMAP_DMA_PORT_MPUI << 2;
+			d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI;
 		else
-			d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
-				   OMAP_DMA_PORT_EMIFF << 2;
+			d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF;
 	} else if (dma_omap2plus()) {
 		d->ccr |= (c->dma_sig & ~0x1f) << 14;
 		d->ccr |= c->dma_sig & 0x1f;
 
 		if (burst)
-			d->ccr |= 1 << 18 | 1 << 5; /* packet */
+			d->ccr |= CCR_SYNC_PACKET;
+		else
+			d->ccr |= CCR_SYNC_ELEMENT;
 
 		if (dir == DMA_DEV_TO_MEM)
-			d->ccr |= 1 << 24; /* source synch */
+			d->ccr |= CCR_TRIGGER_SRC;
 
-		d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
+		d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
 
-		/* src and dst burst mode 16 */
-		d->csdp |= 3 << 14 | 3 << 7;
+		d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
 	}
 
 	c->cyclic = true;
-- 
1.7.4.4

[PATCH RFC 10/26] dmaengine: omap-dma: move CCR buffering disable errata out of the fast path

[Russell King]

Since we record the CCR register in the dma transaction, we can move the
processing of the iframe buffering errata out of the omap_dma_start().
Move it to the preparation functions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 13dca8e0ef32..ba0e10db5185 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -200,8 +200,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
-	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
-		val |= CCR_BUFFERING_DISABLE;
 	val |= CCR_ENABLE;
 	mb();
 	c->plat->dma_write(val, CCR, c->dma_ch);
@@ -558,6 +556,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
 	enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
 {
+	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
 	enum dma_slave_buswidth dev_width;
 	struct scatterlist *sgent;
@@ -628,6 +627,8 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 
 		d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
 	}
+	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
+		d->ccr |= CCR_BUFFERING_DISABLE;
 
 	/*
 	 * Build our scatterlist entries: each contains the address,
@@ -744,6 +745,8 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 
 		d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
 	}
+	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
+		d->ccr |= CCR_BUFFERING_DISABLE;
 
 	c->cyclic = true;
 
-- 
1.7.4.4

[PATCH RFC 10/26] dmaengine: omap-dma: move CCR buffering disable errata out of the fast path

[Russell King]

Since we record the CCR register in the dma transaction, we can move the
processing of the iframe buffering errata out of the omap_dma_start().
Move it to the preparation functions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 13dca8e0ef32..ba0e10db5185 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -200,8 +200,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
-	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
-		val |= CCR_BUFFERING_DISABLE;
 	val |= CCR_ENABLE;
 	mb();
 	c->plat->dma_write(val, CCR, c->dma_ch);
@@ -558,6 +556,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
 	enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
 {
+	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
 	enum dma_slave_buswidth dev_width;
 	struct scatterlist *sgent;
@@ -628,6 +627,8 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 
 		d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
 	}
+	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
+		d->ccr |= CCR_BUFFERING_DISABLE;
 
 	/*
 	 * Build our scatterlist entries: each contains the address,
@@ -744,6 +745,8 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 
 		d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
 	}
+	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
+		d->ccr |= CCR_BUFFERING_DISABLE;
 
 	c->cyclic = true;
 
-- 
1.7.4.4

[PATCH RFC 11/26] dmaengine: omap-dma: consolidate clearing channel status register

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index ba0e10db5185..574f38e3fead 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -168,6 +168,14 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
 	kfree(container_of(vd, struct omap_desc, vd));
 }
 
+static void omap_dma_clear_csr(struct omap_chan *c)
+{
+	if (dma_omap1())
+		c->plat->dma_read(CSR, c->dma_ch);
+	else
+		c->plat->dma_write(~0, CSR, c->dma_ch);
+}
+
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
@@ -190,11 +198,7 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
 		c->plat->dma_write(c->dma_ch, CLNK_CTRL, c->dma_ch);
 
-	/* Clear CSR */
-	if (dma_omap1())
-		c->plat->dma_read(CSR, c->dma_ch);
-	else
-		c->plat->dma_write(~0, CSR, c->dma_ch);
+	omap_dma_clear_csr(c);
 
 	/* Enable interrupts */
 	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
@@ -213,11 +217,7 @@ static void omap_dma_stop(struct omap_chan *c)
 	/* disable irq */
 	c->plat->dma_write(0, CICR, c->dma_ch);
 
-	/* Clear CSR */
-	if (dma_omap1())
-		c->plat->dma_read(CSR, c->dma_ch);
-	else
-		c->plat->dma_write(~0, CSR, c->dma_ch);
+	omap_dma_clear_csr(c);
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
 	if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
-- 
1.7.4.4

[PATCH RFC 11/26] dmaengine: omap-dma: consolidate clearing channel status register

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index ba0e10db5185..574f38e3fead 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -168,6 +168,14 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
 	kfree(container_of(vd, struct omap_desc, vd));
 }
 
+static void omap_dma_clear_csr(struct omap_chan *c)
+{
+	if (dma_omap1())
+		c->plat->dma_read(CSR, c->dma_ch);
+	else
+		c->plat->dma_write(~0, CSR, c->dma_ch);
+}
+
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
@@ -190,11 +198,7 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
 		c->plat->dma_write(c->dma_ch, CLNK_CTRL, c->dma_ch);
 
-	/* Clear CSR */
-	if (dma_omap1())
-		c->plat->dma_read(CSR, c->dma_ch);
-	else
-		c->plat->dma_write(~0, CSR, c->dma_ch);
+	omap_dma_clear_csr(c);
 
 	/* Enable interrupts */
 	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
@@ -213,11 +217,7 @@ static void omap_dma_stop(struct omap_chan *c)
 	/* disable irq */
 	c->plat->dma_write(0, CICR, c->dma_ch);
 
-	/* Clear CSR */
-	if (dma_omap1())
-		c->plat->dma_read(CSR, c->dma_ch);
-	else
-		c->plat->dma_write(~0, CSR, c->dma_ch);
+	omap_dma_clear_csr(c);
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
 	if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
-- 
1.7.4.4

[PATCH RFC 12/26] dmaengine: omap-dma: improve efficiency loading C.SA/C.EI/C.FI registers

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   32 ++++++++++++++++++++------------
 1 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 574f38e3fead..b4700e1f7c57 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -275,17 +275,21 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	unsigned idx)
 {
 	struct omap_sg *sg = d->sg + idx;
+	unsigned cxsa, cxei, cxfi;
 
 	if (d->dir == DMA_DEV_TO_MEM) {
-		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
-		c->plat->dma_write(0, CDEI, c->dma_ch);
-		c->plat->dma_write(0, CDFI, c->dma_ch);
+		cxsa = CDSA;
+		cxei = CDEI;
+		cxfi = CDFI;
 	} else {
-		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
-		c->plat->dma_write(0, CSEI, c->dma_ch);
-		c->plat->dma_write(0, CSFI, c->dma_ch);
+		cxsa = CSSA;
+		cxei = CSEI;
+		cxfi = CSFI;
 	}
 
+	c->plat->dma_write(sg->addr, cxsa, c->dma_ch);
+	c->plat->dma_write(0, cxei, c->dma_ch);
+	c->plat->dma_write(0, cxfi, c->dma_ch);
 	c->plat->dma_write(sg->en, CEN, c->dma_ch);
 	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
 
@@ -296,6 +300,7 @@ static void omap_dma_start_desc(struct omap_chan *c)
 {
 	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 	struct omap_desc *d;
+	unsigned cxsa, cxei, cxfi;
 
 	if (!vd) {
 		c->desc = NULL;
@@ -312,15 +317,18 @@ static void omap_dma_start_desc(struct omap_chan *c)
 		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
 
 	if (d->dir == DMA_DEV_TO_MEM) {
-		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
-		c->plat->dma_write(0, CSEI, c->dma_ch);
-		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
+		cxsa = CSSA;
+		cxei = CSEI;
+		cxfi = CSFI;
 	} else {
-		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
-		c->plat->dma_write(0, CDEI, c->dma_ch);
-		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
+		cxsa = CDSA;
+		cxei = CDEI;
+		cxfi = CDFI;
 	}
 
+	c->plat->dma_write(d->dev_addr, cxsa, c->dma_ch);
+	c->plat->dma_write(0, cxei, c->dma_ch);
+	c->plat->dma_write(d->fi, cxfi, c->dma_ch);
 	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
 
 	omap_dma_start_sg(c, d, 0);
-- 
1.7.4.4

[PATCH RFC 12/26] dmaengine: omap-dma: improve efficiency loading C.SA/C.EI/C.FI registers

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   32 ++++++++++++++++++++------------
 1 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 574f38e3fead..b4700e1f7c57 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -275,17 +275,21 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 	unsigned idx)
 {
 	struct omap_sg *sg = d->sg + idx;
+	unsigned cxsa, cxei, cxfi;
 
 	if (d->dir == DMA_DEV_TO_MEM) {
-		c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
-		c->plat->dma_write(0, CDEI, c->dma_ch);
-		c->plat->dma_write(0, CDFI, c->dma_ch);
+		cxsa = CDSA;
+		cxei = CDEI;
+		cxfi = CDFI;
 	} else {
-		c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
-		c->plat->dma_write(0, CSEI, c->dma_ch);
-		c->plat->dma_write(0, CSFI, c->dma_ch);
+		cxsa = CSSA;
+		cxei = CSEI;
+		cxfi = CSFI;
 	}
 
+	c->plat->dma_write(sg->addr, cxsa, c->dma_ch);
+	c->plat->dma_write(0, cxei, c->dma_ch);
+	c->plat->dma_write(0, cxfi, c->dma_ch);
 	c->plat->dma_write(sg->en, CEN, c->dma_ch);
 	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
 
@@ -296,6 +300,7 @@ static void omap_dma_start_desc(struct omap_chan *c)
 {
 	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 	struct omap_desc *d;
+	unsigned cxsa, cxei, cxfi;
 
 	if (!vd) {
 		c->desc = NULL;
@@ -312,15 +317,18 @@ static void omap_dma_start_desc(struct omap_chan *c)
 		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
 
 	if (d->dir == DMA_DEV_TO_MEM) {
-		c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
-		c->plat->dma_write(0, CSEI, c->dma_ch);
-		c->plat->dma_write(d->fi, CSFI, c->dma_ch);
+		cxsa = CSSA;
+		cxei = CSEI;
+		cxfi = CSFI;
 	} else {
-		c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
-		c->plat->dma_write(0, CDEI, c->dma_ch);
-		c->plat->dma_write(d->fi, CDFI, c->dma_ch);
+		cxsa = CDSA;
+		cxei = CDEI;
+		cxfi = CDFI;
 	}
 
+	c->plat->dma_write(d->dev_addr, cxsa, c->dma_ch);
+	c->plat->dma_write(0, cxei, c->dma_ch);
+	c->plat->dma_write(d->fi, cxfi, c->dma_ch);
 	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
 
 	omap_dma_start_sg(c, d, 0);
-- 
1.7.4.4

[PATCH RFC 13/26] dmaengine: omap-dma: move clnk_ctrl setting to preparation functions

[Russell King]

Move the clnk_ctrl setup to the preparation functions, saving its
value in the omap_desc.  This only needs to be set once per descriptor,
not for each segment, so set it in omap_dma_start_desc() rather than
omap_dma_start().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   23 +++++++++--------------
 1 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index b4700e1f7c57..bdea85802b5b 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -59,6 +59,7 @@ struct omap_desc {
 	int16_t fi;		/* for OMAP_DMA_SYNC_PACKET */
 	uint8_t es;		/* CSDP_DATA_TYPE_xxx */
 	uint32_t ccr;		/* CCR value */
+	uint16_t clnk_ctrl;	/* CLNK_CTRL value */
 	uint16_t cicr;		/* CICR value */
 	uint32_t csdp;		/* CSDP value */
 
@@ -186,18 +187,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	else
 		c->plat->dma_write(0, CDAC, c->dma_ch);
 
-	if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
-		val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
-
-		if (dma_omap1())
-			val &= ~(1 << 14);
-
-		val |= c->dma_ch | CLNK_CTRL_ENABLE_LNK;
-
-		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
-	} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
-		c->plat->dma_write(c->dma_ch, CLNK_CTRL, c->dma_ch);
-
 	omap_dma_clear_csr(c);
 
 	/* Enable interrupts */
@@ -330,6 +319,7 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->plat->dma_write(0, cxei, c->dma_ch);
 	c->plat->dma_write(d->fi, cxfi, c->dma_ch);
 	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
+	c->plat->dma_write(d->clnk_ctrl, CLNK_CTRL, c->dma_ch);
 
 	omap_dma_start_sg(c, d, 0);
 }
@@ -637,6 +627,8 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	}
 	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
 		d->ccr |= CCR_BUFFERING_DISABLE;
+	if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
+		d->clnk_ctrl = c->dma_ch;
 
 	/*
 	 * Build our scatterlist entries: each contains the address,
@@ -717,8 +709,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	d->sglen = 1;
 
 	d->ccr = 0;
-	if (__dma_omap15xx(od->plat->dma_attr))
-		d->ccr = CCR_AUTO_INIT | CCR_REPEAT;
 	if (dir == DMA_DEV_TO_MEM)
 		d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
 	else
@@ -756,6 +746,11 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
 		d->ccr |= CCR_BUFFERING_DISABLE;
 
+	if (__dma_omap15xx(od->plat->dma_attr))
+		d->ccr |= CCR_AUTO_INIT | CCR_REPEAT;
+	else
+		d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK;
+
 	c->cyclic = true;
 
 	return vchan_tx_prep(&c->vc, &d->vd, flags);
-- 
1.7.4.4

[PATCH RFC 13/26] dmaengine: omap-dma: move clnk_ctrl setting to preparation functions

[Russell King]

Move the clnk_ctrl setup to the preparation functions, saving its
value in the omap_desc.  This only needs to be set once per descriptor,
not for each segment, so set it in omap_dma_start_desc() rather than
omap_dma_start().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   23 +++++++++--------------
 1 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index b4700e1f7c57..bdea85802b5b 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -59,6 +59,7 @@ struct omap_desc {
 	int16_t fi;		/* for OMAP_DMA_SYNC_PACKET */
 	uint8_t es;		/* CSDP_DATA_TYPE_xxx */
 	uint32_t ccr;		/* CCR value */
+	uint16_t clnk_ctrl;	/* CLNK_CTRL value */
 	uint16_t cicr;		/* CICR value */
 	uint32_t csdp;		/* CSDP value */
 
@@ -186,18 +187,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	else
 		c->plat->dma_write(0, CDAC, c->dma_ch);
 
-	if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
-		val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
-
-		if (dma_omap1())
-			val &= ~(1 << 14);
-
-		val |= c->dma_ch | CLNK_CTRL_ENABLE_LNK;
-
-		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
-	} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
-		c->plat->dma_write(c->dma_ch, CLNK_CTRL, c->dma_ch);
-
 	omap_dma_clear_csr(c);
 
 	/* Enable interrupts */
@@ -330,6 +319,7 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->plat->dma_write(0, cxei, c->dma_ch);
 	c->plat->dma_write(d->fi, cxfi, c->dma_ch);
 	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
+	c->plat->dma_write(d->clnk_ctrl, CLNK_CTRL, c->dma_ch);
 
 	omap_dma_start_sg(c, d, 0);
 }
@@ -637,6 +627,8 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 	}
 	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
 		d->ccr |= CCR_BUFFERING_DISABLE;
+	if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
+		d->clnk_ctrl = c->dma_ch;
 
 	/*
 	 * Build our scatterlist entries: each contains the address,
@@ -717,8 +709,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	d->sglen = 1;
 
 	d->ccr = 0;
-	if (__dma_omap15xx(od->plat->dma_attr))
-		d->ccr = CCR_AUTO_INIT | CCR_REPEAT;
 	if (dir == DMA_DEV_TO_MEM)
 		d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
 	else
@@ -756,6 +746,11 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 	if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
 		d->ccr |= CCR_BUFFERING_DISABLE;
 
+	if (__dma_omap15xx(od->plat->dma_attr))
+		d->ccr |= CCR_AUTO_INIT | CCR_REPEAT;
+	else
+		d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK;
+
 	c->cyclic = true;
 
 	return vchan_tx_prep(&c->vc, &d->vd, flags);
-- 
1.7.4.4

[PATCH RFC 14/26] dmaengine: omap-dma: move barrier to omap_dma_start_desc()

[Russell King]

We don't need to issue a barrier for every segment of a DMA transfer;
doing this just once per descriptor will do.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index bdea85802b5b..e212e0df9b42 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -194,7 +194,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
 	val |= CCR_ENABLE;
-	mb();
 	c->plat->dma_write(val, CCR, c->dma_ch);
 }
 
@@ -301,6 +300,13 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->desc = d = to_omap_dma_desc(&vd->tx);
 	c->sgidx = 0;
 
+	/*
+	 * This provides the necessary barrier to ensure data held in
+	 * DMA coherent memory is visible to the DMA engine prior to
+	 * the transfer starting.
+	 */
+	mb();
+
 	c->plat->dma_write(d->ccr, CCR, c->dma_ch);
 	if (dma_omap1())
 		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
-- 
1.7.4.4

[PATCH RFC 14/26] dmaengine: omap-dma: move barrier to omap_dma_start_desc()

[Russell King]

We don't need to issue a barrier for every segment of a DMA transfer;
doing this just once per descriptor will do.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index bdea85802b5b..e212e0df9b42 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -194,7 +194,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 
 	val = c->plat->dma_read(CCR, c->dma_ch);
 	val |= CCR_ENABLE;
-	mb();
 	c->plat->dma_write(val, CCR, c->dma_ch);
 }
 
@@ -301,6 +300,13 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	c->desc = d = to_omap_dma_desc(&vd->tx);
 	c->sgidx = 0;
 
+	/*
+	 * This provides the necessary barrier to ensure data held in
+	 * DMA coherent memory is visible to the DMA engine prior to
+	 * the transfer starting.
+	 */
+	mb();
+
 	c->plat->dma_write(d->ccr, CCR, c->dma_ch);
 	if (dma_omap1())
 		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
-- 
1.7.4.4

[PATCH RFC 15/26] dmaengine: omap-dma: use cached CCR value when enabling DMA

[Russell King]

We don't need to read-modify-write the CCR register; we already know
what value it should contain at this point.  Use the cached CCR value
when setting the enable bit.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index e212e0df9b42..98e77adeaeb3 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -180,7 +180,6 @@ static void omap_dma_clear_csr(struct omap_chan *c)
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
-	uint32_t val;
 
 	if (__dma_omap15xx(od->plat->dma_attr))
 		c->plat->dma_write(0, CPC, c->dma_ch);
@@ -192,9 +191,8 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	/* Enable interrupts */
 	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
 
-	val = c->plat->dma_read(CCR, c->dma_ch);
-	val |= CCR_ENABLE;
-	c->plat->dma_write(val, CCR, c->dma_ch);
+	/* Enable channel */
+	c->plat->dma_write(d->ccr | CCR_ENABLE, CCR, c->dma_ch);
 }
 
 static void omap_dma_stop(struct omap_chan *c)
-- 
1.7.4.4

[PATCH RFC 15/26] dmaengine: omap-dma: use cached CCR value when enabling DMA

[Russell King]

We don't need to read-modify-write the CCR register; we already know
what value it should contain at this point.  Use the cached CCR value
when setting the enable bit.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index e212e0df9b42..98e77adeaeb3 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -180,7 +180,6 @@ static void omap_dma_clear_csr(struct omap_chan *c)
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
-	uint32_t val;
 
 	if (__dma_omap15xx(od->plat->dma_attr))
 		c->plat->dma_write(0, CPC, c->dma_ch);
@@ -192,9 +191,8 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	/* Enable interrupts */
 	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
 
-	val = c->plat->dma_read(CCR, c->dma_ch);
-	val |= CCR_ENABLE;
-	c->plat->dma_write(val, CCR, c->dma_ch);
+	/* Enable channel */
+	c->plat->dma_write(d->ccr | CCR_ENABLE, CCR, c->dma_ch);
 }
 
 static void omap_dma_stop(struct omap_chan *c)
-- 
1.7.4.4

[PATCH RFC 16/26] dmaengine: omap-dma: provide register read/write functions

[Russell King]

Provide a pair of channel register accessors, and a pair of global
accessors for non-channel specific registers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  102 ++++++++++++++++++++++++++++-------------------
 1 files changed, 61 insertions(+), 41 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 98e77adeaeb3..a1aefe9fe3fe 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -169,12 +169,32 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
 	kfree(container_of(vd, struct omap_desc, vd));
 }
 
+static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
+{
+	od->plat->dma_write(val, reg, 0);
+}
+
+static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
+{
+	return od->plat->dma_read(reg, 0);
+}
+
+static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
+{
+	c->plat->dma_write(val, reg, c->dma_ch);
+}
+
+static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
+{
+	return c->plat->dma_read(reg, c->dma_ch);
+}
+
 static void omap_dma_clear_csr(struct omap_chan *c)
 {
 	if (dma_omap1())
-		c->plat->dma_read(CSR, c->dma_ch);
+		omap_dma_chan_read(c, CSR);
 	else
-		c->plat->dma_write(~0, CSR, c->dma_ch);
+		omap_dma_chan_write(c, CSR, ~0);
 }
 
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
@@ -182,17 +202,17 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 
 	if (__dma_omap15xx(od->plat->dma_attr))
-		c->plat->dma_write(0, CPC, c->dma_ch);
+		omap_dma_chan_write(c, CPC, 0);
 	else
-		c->plat->dma_write(0, CDAC, c->dma_ch);
+		omap_dma_chan_write(c, CDAC, 0);
 
 	omap_dma_clear_csr(c);
 
 	/* Enable interrupts */
-	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
+	omap_dma_chan_write(c, CICR, d->cicr);
 
 	/* Enable channel */
-	c->plat->dma_write(d->ccr | CCR_ENABLE, CCR, c->dma_ch);
+	omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
 }
 
 static void omap_dma_stop(struct omap_chan *c)
@@ -201,27 +221,27 @@ static void omap_dma_stop(struct omap_chan *c)
 	uint32_t val;
 
 	/* disable irq */
-	c->plat->dma_write(0, CICR, c->dma_ch);
+	omap_dma_chan_write(c, CICR, 0);
 
 	omap_dma_clear_csr(c);
 
-	val = c->plat->dma_read(CCR, c->dma_ch);
+	val = omap_dma_chan_read(c, CCR);
 	if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
 		uint32_t sysconfig;
 		unsigned i;
 
-		sysconfig = c->plat->dma_read(OCP_SYSCONFIG, c->dma_ch);
+		sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
 		val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 		val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
-		c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch);
+		omap_dma_glbl_write(od, OCP_SYSCONFIG, val);
 
-		val = c->plat->dma_read(CCR, c->dma_ch);
+		val = omap_dma_chan_read(c, CCR);
 		val &= ~CCR_ENABLE;
-		c->plat->dma_write(val, CCR, c->dma_ch);
+		omap_dma_chan_write(c, CCR, val);
 
 		/* Wait for sDMA FIFO to drain */
 		for (i = 0; ; i++) {
-			val = c->plat->dma_read(CCR, c->dma_ch);
+			val = omap_dma_chan_read(c, CCR);
 			if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
 				break;
 
@@ -236,16 +256,16 @@ static void omap_dma_stop(struct omap_chan *c)
 				"DMA drain did not complete on lch %d\n",
 			        c->dma_ch);
 
-		c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch);
+		omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig);
 	} else {
 		val &= ~CCR_ENABLE;
-		c->plat->dma_write(val, CCR, c->dma_ch);
+		omap_dma_chan_write(c, CCR, val);
 	}
 
 	mb();
 
 	if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
-		val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
+		val = omap_dma_chan_read(c, CLNK_CTRL);
 
 		if (dma_omap1())
 			val |= 1 << 14; /* set the STOP_LNK bit */
@@ -253,7 +273,7 @@ static void omap_dma_stop(struct omap_chan *c)
 		if (dma_omap2plus())
 			val &= ~CLNK_CTRL_ENABLE_LNK;
 
-		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
+		omap_dma_chan_write(c, CLNK_CTRL, val);
 	}
 }
 
@@ -273,11 +293,11 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 		cxfi = CSFI;
 	}
 
-	c->plat->dma_write(sg->addr, cxsa, c->dma_ch);
-	c->plat->dma_write(0, cxei, c->dma_ch);
-	c->plat->dma_write(0, cxfi, c->dma_ch);
-	c->plat->dma_write(sg->en, CEN, c->dma_ch);
-	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
+	omap_dma_chan_write(c, cxsa, sg->addr);
+	omap_dma_chan_write(c, cxei, 0);
+	omap_dma_chan_write(c, cxfi, 0);
+	omap_dma_chan_write(c, CEN, sg->en);
+	omap_dma_chan_write(c, CFN, sg->fn);
 
 	omap_dma_start(c, d);
 }
@@ -305,9 +325,9 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	 */
 	mb();
 
-	c->plat->dma_write(d->ccr, CCR, c->dma_ch);
+	omap_dma_chan_write(c, CCR, d->ccr);
 	if (dma_omap1())
-		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
+		omap_dma_chan_write(c, CCR2, d->ccr >> 16);
 
 	if (d->dir == DMA_DEV_TO_MEM) {
 		cxsa = CSSA;
@@ -319,11 +339,11 @@ static void omap_dma_start_desc(struct omap_chan *c)
 		cxfi = CDFI;
 	}
 
-	c->plat->dma_write(d->dev_addr, cxsa, c->dma_ch);
-	c->plat->dma_write(0, cxei, c->dma_ch);
-	c->plat->dma_write(d->fi, cxfi, c->dma_ch);
-	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
-	c->plat->dma_write(d->clnk_ctrl, CLNK_CTRL, c->dma_ch);
+	omap_dma_chan_write(c, cxsa, d->dev_addr);
+	omap_dma_chan_write(c, cxei, 0);
+	omap_dma_chan_write(c, cxfi, d->fi);
+	omap_dma_chan_write(c, CSDP, d->csdp);
+	omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl);
 
 	omap_dma_start_sg(c, d, 0);
 }
@@ -437,12 +457,12 @@ static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
 	dma_addr_t addr;
 
 	if (__dma_omap15xx(od->plat->dma_attr))
-		addr = c->plat->dma_read(CPC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CPC);
 	else
-		addr = c->plat->dma_read(CSAC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CSAC);
 
 	if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0)
-		addr = c->plat->dma_read(CSAC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CSAC);
 
 	if (!__dma_omap15xx(od->plat->dma_attr)) {
 		/*
@@ -450,14 +470,14 @@ static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
 		 * not been started (no data has been transferred so far).
 		 * Return the programmed source start address in this case.
 		 */
-		if (c->plat->dma_read(CDAC, c->dma_ch))
-			addr = c->plat->dma_read(CSAC, c->dma_ch);
+		if (omap_dma_chan_read(c, CDAC))
+			addr = omap_dma_chan_read(c, CSAC);
 		else
-			addr = c->plat->dma_read(CSSA, c->dma_ch);
+			addr = omap_dma_chan_read(c, CSSA);
 	}
 
 	if (dma_omap1())
-		addr |= c->plat->dma_read(CSSA, c->dma_ch) & 0xffff0000;
+		addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000;
 
 	return addr;
 }
@@ -468,27 +488,27 @@ static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
 	dma_addr_t addr;
 
 	if (__dma_omap15xx(od->plat->dma_attr))
-		addr = c->plat->dma_read(CPC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CPC);
 	else
-		addr = c->plat->dma_read(CDAC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CDAC);
 
 	/*
 	 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 	 * read before the DMA controller finished disabling the channel.
 	 */
 	if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) {
-		addr = c->plat->dma_read(CDAC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CDAC);
 		/*
 		 * CDAC == 0 indicates that the DMA transfer on the channel has
 		 * not been started (no data has been transferred so far).
 		 * Return the programmed destination start address in this case.
 		 */
 		if (addr == 0)
-			addr = c->plat->dma_read(CDSA, c->dma_ch);
+			addr = omap_dma_chan_read(c, CDSA);
 	}
 
 	if (dma_omap1())
-		addr |= c->plat->dma_read(CDSA, c->dma_ch) & 0xffff0000;
+		addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000;
 
 	return addr;
 }
-- 
1.7.4.4

[PATCH RFC 16/26] dmaengine: omap-dma: provide register read/write functions

[Russell King]

Provide a pair of channel register accessors, and a pair of global
accessors for non-channel specific registers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  102 ++++++++++++++++++++++++++++-------------------
 1 files changed, 61 insertions(+), 41 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 98e77adeaeb3..a1aefe9fe3fe 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -169,12 +169,32 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
 	kfree(container_of(vd, struct omap_desc, vd));
 }
 
+static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
+{
+	od->plat->dma_write(val, reg, 0);
+}
+
+static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
+{
+	return od->plat->dma_read(reg, 0);
+}
+
+static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
+{
+	c->plat->dma_write(val, reg, c->dma_ch);
+}
+
+static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
+{
+	return c->plat->dma_read(reg, c->dma_ch);
+}
+
 static void omap_dma_clear_csr(struct omap_chan *c)
 {
 	if (dma_omap1())
-		c->plat->dma_read(CSR, c->dma_ch);
+		omap_dma_chan_read(c, CSR);
 	else
-		c->plat->dma_write(~0, CSR, c->dma_ch);
+		omap_dma_chan_write(c, CSR, ~0);
 }
 
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
@@ -182,17 +202,17 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 
 	if (__dma_omap15xx(od->plat->dma_attr))
-		c->plat->dma_write(0, CPC, c->dma_ch);
+		omap_dma_chan_write(c, CPC, 0);
 	else
-		c->plat->dma_write(0, CDAC, c->dma_ch);
+		omap_dma_chan_write(c, CDAC, 0);
 
 	omap_dma_clear_csr(c);
 
 	/* Enable interrupts */
-	c->plat->dma_write(d->cicr, CICR, c->dma_ch);
+	omap_dma_chan_write(c, CICR, d->cicr);
 
 	/* Enable channel */
-	c->plat->dma_write(d->ccr | CCR_ENABLE, CCR, c->dma_ch);
+	omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
 }
 
 static void omap_dma_stop(struct omap_chan *c)
@@ -201,27 +221,27 @@ static void omap_dma_stop(struct omap_chan *c)
 	uint32_t val;
 
 	/* disable irq */
-	c->plat->dma_write(0, CICR, c->dma_ch);
+	omap_dma_chan_write(c, CICR, 0);
 
 	omap_dma_clear_csr(c);
 
-	val = c->plat->dma_read(CCR, c->dma_ch);
+	val = omap_dma_chan_read(c, CCR);
 	if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
 		uint32_t sysconfig;
 		unsigned i;
 
-		sysconfig = c->plat->dma_read(OCP_SYSCONFIG, c->dma_ch);
+		sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
 		val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 		val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
-		c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch);
+		omap_dma_glbl_write(od, OCP_SYSCONFIG, val);
 
-		val = c->plat->dma_read(CCR, c->dma_ch);
+		val = omap_dma_chan_read(c, CCR);
 		val &= ~CCR_ENABLE;
-		c->plat->dma_write(val, CCR, c->dma_ch);
+		omap_dma_chan_write(c, CCR, val);
 
 		/* Wait for sDMA FIFO to drain */
 		for (i = 0; ; i++) {
-			val = c->plat->dma_read(CCR, c->dma_ch);
+			val = omap_dma_chan_read(c, CCR);
 			if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
 				break;
 
@@ -236,16 +256,16 @@ static void omap_dma_stop(struct omap_chan *c)
 				"DMA drain did not complete on lch %d\n",
 			        c->dma_ch);
 
-		c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch);
+		omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig);
 	} else {
 		val &= ~CCR_ENABLE;
-		c->plat->dma_write(val, CCR, c->dma_ch);
+		omap_dma_chan_write(c, CCR, val);
 	}
 
 	mb();
 
 	if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
-		val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
+		val = omap_dma_chan_read(c, CLNK_CTRL);
 
 		if (dma_omap1())
 			val |= 1 << 14; /* set the STOP_LNK bit */
@@ -253,7 +273,7 @@ static void omap_dma_stop(struct omap_chan *c)
 		if (dma_omap2plus())
 			val &= ~CLNK_CTRL_ENABLE_LNK;
 
-		c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
+		omap_dma_chan_write(c, CLNK_CTRL, val);
 	}
 }
 
@@ -273,11 +293,11 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 		cxfi = CSFI;
 	}
 
-	c->plat->dma_write(sg->addr, cxsa, c->dma_ch);
-	c->plat->dma_write(0, cxei, c->dma_ch);
-	c->plat->dma_write(0, cxfi, c->dma_ch);
-	c->plat->dma_write(sg->en, CEN, c->dma_ch);
-	c->plat->dma_write(sg->fn, CFN, c->dma_ch);
+	omap_dma_chan_write(c, cxsa, sg->addr);
+	omap_dma_chan_write(c, cxei, 0);
+	omap_dma_chan_write(c, cxfi, 0);
+	omap_dma_chan_write(c, CEN, sg->en);
+	omap_dma_chan_write(c, CFN, sg->fn);
 
 	omap_dma_start(c, d);
 }
@@ -305,9 +325,9 @@ static void omap_dma_start_desc(struct omap_chan *c)
 	 */
 	mb();
 
-	c->plat->dma_write(d->ccr, CCR, c->dma_ch);
+	omap_dma_chan_write(c, CCR, d->ccr);
 	if (dma_omap1())
-		c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
+		omap_dma_chan_write(c, CCR2, d->ccr >> 16);
 
 	if (d->dir == DMA_DEV_TO_MEM) {
 		cxsa = CSSA;
@@ -319,11 +339,11 @@ static void omap_dma_start_desc(struct omap_chan *c)
 		cxfi = CDFI;
 	}
 
-	c->plat->dma_write(d->dev_addr, cxsa, c->dma_ch);
-	c->plat->dma_write(0, cxei, c->dma_ch);
-	c->plat->dma_write(d->fi, cxfi, c->dma_ch);
-	c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
-	c->plat->dma_write(d->clnk_ctrl, CLNK_CTRL, c->dma_ch);
+	omap_dma_chan_write(c, cxsa, d->dev_addr);
+	omap_dma_chan_write(c, cxei, 0);
+	omap_dma_chan_write(c, cxfi, d->fi);
+	omap_dma_chan_write(c, CSDP, d->csdp);
+	omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl);
 
 	omap_dma_start_sg(c, d, 0);
 }
@@ -437,12 +457,12 @@ static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
 	dma_addr_t addr;
 
 	if (__dma_omap15xx(od->plat->dma_attr))
-		addr = c->plat->dma_read(CPC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CPC);
 	else
-		addr = c->plat->dma_read(CSAC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CSAC);
 
 	if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0)
-		addr = c->plat->dma_read(CSAC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CSAC);
 
 	if (!__dma_omap15xx(od->plat->dma_attr)) {
 		/*
@@ -450,14 +470,14 @@ static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
 		 * not been started (no data has been transferred so far).
 		 * Return the programmed source start address in this case.
 		 */
-		if (c->plat->dma_read(CDAC, c->dma_ch))
-			addr = c->plat->dma_read(CSAC, c->dma_ch);
+		if (omap_dma_chan_read(c, CDAC))
+			addr = omap_dma_chan_read(c, CSAC);
 		else
-			addr = c->plat->dma_read(CSSA, c->dma_ch);
+			addr = omap_dma_chan_read(c, CSSA);
 	}
 
 	if (dma_omap1())
-		addr |= c->plat->dma_read(CSSA, c->dma_ch) & 0xffff0000;
+		addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000;
 
 	return addr;
 }
@@ -468,27 +488,27 @@ static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
 	dma_addr_t addr;
 
 	if (__dma_omap15xx(od->plat->dma_attr))
-		addr = c->plat->dma_read(CPC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CPC);
 	else
-		addr = c->plat->dma_read(CDAC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CDAC);
 
 	/*
 	 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 	 * read before the DMA controller finished disabling the channel.
 	 */
 	if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) {
-		addr = c->plat->dma_read(CDAC, c->dma_ch);
+		addr = omap_dma_chan_read(c, CDAC);
 		/*
 		 * CDAC == 0 indicates that the DMA transfer on the channel has
 		 * not been started (no data has been transferred so far).
 		 * Return the programmed destination start address in this case.
 		 */
 		if (addr == 0)
-			addr = c->plat->dma_read(CDSA, c->dma_ch);
+			addr = omap_dma_chan_read(c, CDSA);
 	}
 
 	if (dma_omap1())
-		addr |= c->plat->dma_read(CDSA, c->dma_ch) & 0xffff0000;
+		addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000;
 
 	return addr;
 }
-- 
1.7.4.4

[PATCH RFC 17/26] dmaengine: omap-dma: cleanup errata 3.3 handling

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   52 ++++++++++++++++++++++++++---------------------
 1 files changed, 29 insertions(+), 23 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index a1aefe9fe3fe..04631e6732c4 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -451,28 +451,39 @@ static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
 	return size;
 }
 
+/*
+ * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+ * read before the DMA controller finished disabling the channel.
+ */
+static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	uint32_t val;
+
+	val = omap_dma_chan_read(c, reg);
+	if (val == 0 && od->plat->errata & DMA_ERRATA_3_3)
+		val = omap_dma_chan_read(c, reg);
+
+	return val;
+}
+
 static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
-	dma_addr_t addr;
+	dma_addr_t addr, cdac;
 
-	if (__dma_omap15xx(od->plat->dma_attr))
+	if (__dma_omap15xx(od->plat->dma_attr)) {
 		addr = omap_dma_chan_read(c, CPC);
-	else
-		addr = omap_dma_chan_read(c, CSAC);
-
-	if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0)
-		addr = omap_dma_chan_read(c, CSAC);
+	} else {
+		addr = omap_dma_chan_read_3_3(c, CSAC);
+		cdac = omap_dma_chan_read_3_3(c, CDAC);
 
-	if (!__dma_omap15xx(od->plat->dma_attr)) {
 		/*
 		 * CDAC == 0 indicates that the DMA transfer on the channel has
 		 * not been started (no data has been transferred so far).
 		 * Return the programmed source start address in this case.
 		 */
-		if (omap_dma_chan_read(c, CDAC))
-			addr = omap_dma_chan_read(c, CSAC);
-		else
+		if (cdac == 0)
 			addr = omap_dma_chan_read(c, CSSA);
 	}
 
@@ -487,21 +498,16 @@ static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 	dma_addr_t addr;
 
-	if (__dma_omap15xx(od->plat->dma_attr))
+	if (__dma_omap15xx(od->plat->dma_attr)) {
 		addr = omap_dma_chan_read(c, CPC);
-	else
-		addr = omap_dma_chan_read(c, CDAC);
+	} else {
+		addr = omap_dma_chan_read_3_3(c, CDAC);
 
-	/*
-	 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
-	 * read before the DMA controller finished disabling the channel.
-	 */
-	if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) {
-		addr = omap_dma_chan_read(c, CDAC);
 		/*
-		 * CDAC == 0 indicates that the DMA transfer on the channel has
-		 * not been started (no data has been transferred so far).
-		 * Return the programmed destination start address in this case.
+		 * CDAC == 0 indicates that the DMA transfer on the channel
+		 * has not been started (no data has been transferred so
+		 * far).  Return the programmed destination start address in
+		 * this case.
 		 */
 		if (addr == 0)
 			addr = omap_dma_chan_read(c, CDSA);
-- 
1.7.4.4

[PATCH RFC 17/26] dmaengine: omap-dma: cleanup errata 3.3 handling

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |   52 ++++++++++++++++++++++++++---------------------
 1 files changed, 29 insertions(+), 23 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index a1aefe9fe3fe..04631e6732c4 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -451,28 +451,39 @@ static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
 	return size;
 }
 
+/*
+ * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+ * read before the DMA controller finished disabling the channel.
+ */
+static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg)
+{
+	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
+	uint32_t val;
+
+	val = omap_dma_chan_read(c, reg);
+	if (val == 0 && od->plat->errata & DMA_ERRATA_3_3)
+		val = omap_dma_chan_read(c, reg);
+
+	return val;
+}
+
 static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
-	dma_addr_t addr;
+	dma_addr_t addr, cdac;
 
-	if (__dma_omap15xx(od->plat->dma_attr))
+	if (__dma_omap15xx(od->plat->dma_attr)) {
 		addr = omap_dma_chan_read(c, CPC);
-	else
-		addr = omap_dma_chan_read(c, CSAC);
-
-	if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0)
-		addr = omap_dma_chan_read(c, CSAC);
+	} else {
+		addr = omap_dma_chan_read_3_3(c, CSAC);
+		cdac = omap_dma_chan_read_3_3(c, CDAC);
 
-	if (!__dma_omap15xx(od->plat->dma_attr)) {
 		/*
 		 * CDAC == 0 indicates that the DMA transfer on the channel has
 		 * not been started (no data has been transferred so far).
 		 * Return the programmed source start address in this case.
 		 */
-		if (omap_dma_chan_read(c, CDAC))
-			addr = omap_dma_chan_read(c, CSAC);
-		else
+		if (cdac == 0)
 			addr = omap_dma_chan_read(c, CSSA);
 	}
 
@@ -487,21 +498,16 @@ static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 	dma_addr_t addr;
 
-	if (__dma_omap15xx(od->plat->dma_attr))
+	if (__dma_omap15xx(od->plat->dma_attr)) {
 		addr = omap_dma_chan_read(c, CPC);
-	else
-		addr = omap_dma_chan_read(c, CDAC);
+	} else {
+		addr = omap_dma_chan_read_3_3(c, CDAC);
 
-	/*
-	 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
-	 * read before the DMA controller finished disabling the channel.
-	 */
-	if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) {
-		addr = omap_dma_chan_read(c, CDAC);
 		/*
-		 * CDAC == 0 indicates that the DMA transfer on the channel has
-		 * not been started (no data has been transferred so far).
-		 * Return the programmed destination start address in this case.
+		 * CDAC == 0 indicates that the DMA transfer on the channel
+		 * has not been started (no data has been transferred so
+		 * far).  Return the programmed destination start address in
+		 * this case.
 		 */
 		if (addr == 0)
 			addr = omap_dma_chan_read(c, CDSA);
-- 
1.7.4.4

[PATCH RFC 18/26] ARM: omap: remove references to disable_irq_lch

[Russell King]

The disable_irq_lch method is never actually used, so there's not much
point it existing; remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |    1 -
 arch/arm/mach-omap2/dma.c |   10 ----------
 include/linux/omap-dma.h  |    1 -
 3 files changed, 0 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 5bb8ce86d54b..d292055d3117 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -363,7 +363,6 @@ static int __init omap1_system_dma_init(void)
 	p->clear_dma		= omap1_clear_dma;
 	p->dma_write		= dma_write;
 	p->dma_read		= dma_read;
-	p->disable_irq_lch	= NULL;
 
 	p->errata = configure_dma_errata();
 
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 49fd0d501c9b..81c2d3383bc5 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -112,15 +112,6 @@ static inline u32 dma_read(int reg, int lch)
 	return val;
 }
 
-static inline void omap2_disable_irq_lch(int lch)
-{
-	u32 val;
-
-	val = dma_read(IRQENABLE_L0, lch);
-	val &= ~(1 << lch);
-	dma_write(val, IRQENABLE_L0, lch);
-}
-
 static void omap2_clear_dma(int lch)
 {
 	int i = dma_common_ch_start;
@@ -239,7 +230,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 	}
 
 	p->dma_attr		= (struct omap_dma_dev_attr *)oh->dev_attr;
-	p->disable_irq_lch	= omap2_disable_irq_lch;
 	p->show_dma_caps	= omap2_show_dma_caps;
 	p->clear_dma		= omap2_clear_dma;
 	p->dma_write		= dma_write;
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index d631658e2237..0bb7de77d478 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -275,7 +275,6 @@ struct omap_dma_dev_attr {
 struct omap_system_dma_plat_info {
 	struct omap_dma_dev_attr *dma_attr;
 	u32 errata;
-	void (*disable_irq_lch)(int lch);
 	void (*show_dma_caps)(void);
 	void (*clear_lch_regs)(int lch);
 	void (*clear_dma)(int lch);
-- 
1.7.4.4

[PATCH RFC 18/26] ARM: omap: remove references to disable_irq_lch

[Russell King]

The disable_irq_lch method is never actually used, so there's not much
point it existing; remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |    1 -
 arch/arm/mach-omap2/dma.c |   10 ----------
 include/linux/omap-dma.h  |    1 -
 3 files changed, 0 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 5bb8ce86d54b..d292055d3117 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -363,7 +363,6 @@ static int __init omap1_system_dma_init(void)
 	p->clear_dma		= omap1_clear_dma;
 	p->dma_write		= dma_write;
 	p->dma_read		= dma_read;
-	p->disable_irq_lch	= NULL;
 
 	p->errata = configure_dma_errata();
 
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 49fd0d501c9b..81c2d3383bc5 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -112,15 +112,6 @@ static inline u32 dma_read(int reg, int lch)
 	return val;
 }
 
-static inline void omap2_disable_irq_lch(int lch)
-{
-	u32 val;
-
-	val = dma_read(IRQENABLE_L0, lch);
-	val &= ~(1 << lch);
-	dma_write(val, IRQENABLE_L0, lch);
-}
-
 static void omap2_clear_dma(int lch)
 {
 	int i = dma_common_ch_start;
@@ -239,7 +230,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 	}
 
 	p->dma_attr		= (struct omap_dma_dev_attr *)oh->dev_attr;
-	p->disable_irq_lch	= omap2_disable_irq_lch;
 	p->show_dma_caps	= omap2_show_dma_caps;
 	p->clear_dma		= omap2_clear_dma;
 	p->dma_write		= dma_write;
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index d631658e2237..0bb7de77d478 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -275,7 +275,6 @@ struct omap_dma_dev_attr {
 struct omap_system_dma_plat_info {
 	struct omap_dma_dev_attr *dma_attr;
 	u32 errata;
-	void (*disable_irq_lch)(int lch);
 	void (*show_dma_caps)(void);
 	void (*clear_lch_regs)(int lch);
 	void (*clear_dma)(int lch);
-- 
1.7.4.4

[PATCH RFC 19/26] ARM: omap: remove almost-const variables

[Russell King]

dma_stride and dma_common_ch_start are only ever initialised to one
known value at initialisation, and are private to each of these files.
There's no point these being variables at all.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |   14 ++++----------
 arch/arm/mach-omap2/dma.c |   14 +++++---------
 2 files changed, 9 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index d292055d3117..11f0b0ee67a3 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -36,8 +36,6 @@
 
 static u32 errata;
 static u32 enable_1510_mode;
-static u8 dma_stride;
-static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
 
 static u16 reg_map[] = {
 	[GCR]		= 0x400,
@@ -184,7 +182,7 @@ static inline void dma_write(u32 val, int reg, int lch)
 	u8  stride;
 	u32 offset;
 
-	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
 	offset = reg_map[reg] + (stride * lch);
 
 	__raw_writew(val, dma_base + offset);
@@ -200,7 +198,7 @@ static inline u32 dma_read(int reg, int lch)
 	u8 stride;
 	u32 offset, val;
 
-	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
 	offset = reg_map[reg] + (stride * lch);
 
 	val = __raw_readw(dma_base + offset);
@@ -216,9 +214,9 @@ static inline u32 dma_read(int reg, int lch)
 
 static void omap1_clear_lch_regs(int lch)
 {
-	int i = dma_common_ch_start;
+	int i;
 
-	for (; i <= dma_common_ch_end; i += 1)
+	for (i = CPC; i <= COLOR; i += 1)
 		dma_write(0, i, lch);
 }
 
@@ -380,10 +378,6 @@ static int __init omap1_system_dma_init(void)
 		goto exit_release_chan;
 	}
 
-	dma_stride		= OMAP1_DMA_STRIDE;
-	dma_common_ch_start	= CPC;
-	dma_common_ch_end	= COLOR;
-
 	dma_pdev = platform_device_register_full(&omap_dma_dev_info);
 	if (IS_ERR(dma_pdev)) {
 		ret = PTR_ERR(dma_pdev);
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 81c2d3383bc5..e4ac7ac9a228 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -38,11 +38,10 @@
 #define OMAP2_DMA_STRIDE	0x60
 
 static u32 errata;
-static u8 dma_stride;
 
 static struct omap_dma_dev_attr *d;
 
-static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+static enum omap_reg_offsets dma_common_ch_end;
 
 static u16 reg_map[] = {
 	[REVISION]		= 0x00,
@@ -96,7 +95,7 @@ static inline void dma_write(u32 val, int reg, int lch)
 	u8  stride;
 	u32 offset;
 
-	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
 	offset = reg_map[reg] + (stride * lch);
 	__raw_writel(val, dma_base + offset);
 }
@@ -106,7 +105,7 @@ static inline u32 dma_read(int reg, int lch)
 	u8 stride;
 	u32 offset, val;
 
-	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
 	offset = reg_map[reg] + (stride * lch);
 	val = __raw_readl(dma_base + offset);
 	return val;
@@ -114,9 +113,9 @@ static inline u32 dma_read(int reg, int lch)
 
 static void omap2_clear_dma(int lch)
 {
-	int i = dma_common_ch_start;
+	int i;
 
-	for (; i <= dma_common_ch_end; i += 1)
+	for (i = CSDP; i <= dma_common_ch_end; i += 1)
 		dma_write(0, i, lch);
 }
 
@@ -219,9 +218,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 	struct resource				*mem;
 	char					*name = "omap_dma_system";
 
-	dma_stride		= OMAP2_DMA_STRIDE;
-	dma_common_ch_start	= CSDP;
-
 	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
 	if (!p) {
 		pr_err("%s: Unable to allocate pdata for %s:%s\n",
-- 
1.7.4.4

[PATCH RFC 19/26] ARM: omap: remove almost-const variables

[Russell King]

dma_stride and dma_common_ch_start are only ever initialised to one
known value at initialisation, and are private to each of these files.
There's no point these being variables at all.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |   14 ++++----------
 arch/arm/mach-omap2/dma.c |   14 +++++---------
 2 files changed, 9 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index d292055d3117..11f0b0ee67a3 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -36,8 +36,6 @@
 
 static u32 errata;
 static u32 enable_1510_mode;
-static u8 dma_stride;
-static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
 
 static u16 reg_map[] = {
 	[GCR]		= 0x400,
@@ -184,7 +182,7 @@ static inline void dma_write(u32 val, int reg, int lch)
 	u8  stride;
 	u32 offset;
 
-	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
 	offset = reg_map[reg] + (stride * lch);
 
 	__raw_writew(val, dma_base + offset);
@@ -200,7 +198,7 @@ static inline u32 dma_read(int reg, int lch)
 	u8 stride;
 	u32 offset, val;
 
-	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
 	offset = reg_map[reg] + (stride * lch);
 
 	val = __raw_readw(dma_base + offset);
@@ -216,9 +214,9 @@ static inline u32 dma_read(int reg, int lch)
 
 static void omap1_clear_lch_regs(int lch)
 {
-	int i = dma_common_ch_start;
+	int i;
 
-	for (; i <= dma_common_ch_end; i += 1)
+	for (i = CPC; i <= COLOR; i += 1)
 		dma_write(0, i, lch);
 }
 
@@ -380,10 +378,6 @@ static int __init omap1_system_dma_init(void)
 		goto exit_release_chan;
 	}
 
-	dma_stride		= OMAP1_DMA_STRIDE;
-	dma_common_ch_start	= CPC;
-	dma_common_ch_end	= COLOR;
-
 	dma_pdev = platform_device_register_full(&omap_dma_dev_info);
 	if (IS_ERR(dma_pdev)) {
 		ret = PTR_ERR(dma_pdev);
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 81c2d3383bc5..e4ac7ac9a228 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -38,11 +38,10 @@
 #define OMAP2_DMA_STRIDE	0x60
 
 static u32 errata;
-static u8 dma_stride;
 
 static struct omap_dma_dev_attr *d;
 
-static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+static enum omap_reg_offsets dma_common_ch_end;
 
 static u16 reg_map[] = {
 	[REVISION]		= 0x00,
@@ -96,7 +95,7 @@ static inline void dma_write(u32 val, int reg, int lch)
 	u8  stride;
 	u32 offset;
 
-	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
 	offset = reg_map[reg] + (stride * lch);
 	__raw_writel(val, dma_base + offset);
 }
@@ -106,7 +105,7 @@ static inline u32 dma_read(int reg, int lch)
 	u8 stride;
 	u32 offset, val;
 
-	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
 	offset = reg_map[reg] + (stride * lch);
 	val = __raw_readl(dma_base + offset);
 	return val;
@@ -114,9 +113,9 @@ static inline u32 dma_read(int reg, int lch)
 
 static void omap2_clear_dma(int lch)
 {
-	int i = dma_common_ch_start;
+	int i;
 
-	for (; i <= dma_common_ch_end; i += 1)
+	for (i = CSDP; i <= dma_common_ch_end; i += 1)
 		dma_write(0, i, lch);
 }
 
@@ -219,9 +218,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 	struct resource				*mem;
 	char					*name = "omap_dma_system";
 
-	dma_stride		= OMAP2_DMA_STRIDE;
-	dma_common_ch_start	= CSDP;
-
 	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
 	if (!p) {
 		pr_err("%s: Unable to allocate pdata for %s:%s\n",
-- 
1.7.4.4

[PATCH RFC 20/26] ARM: omap: clean up DMA register accesses

[Russell King]

We can do much better with this by using a structure to describe each
register, rather than code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |  121 +++++++++++++++++++++------------------------
 arch/arm/mach-omap2/dma.c |   99 ++++++++++++++++++-------------------
 include/linux/omap-dma.h  |   13 +++++
 3 files changed, 117 insertions(+), 116 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 11f0b0ee67a3..de30e28ff487 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -32,53 +32,52 @@
 
 #define OMAP1_DMA_BASE			(0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT	17
-#define OMAP1_DMA_STRIDE		0x40
 
 static u32 errata;
 static u32 enable_1510_mode;
 
-static u16 reg_map[] = {
-	[GCR]		= 0x400,
-	[GSCR]		= 0x404,
-	[GRST1]		= 0x408,
-	[HW_ID]		= 0x442,
-	[PCH2_ID]	= 0x444,
-	[PCH0_ID]	= 0x446,
-	[PCH1_ID]	= 0x448,
-	[PCHG_ID]	= 0x44a,
-	[PCHD_ID]	= 0x44c,
-	[CAPS_0]	= 0x44e,
-	[CAPS_1]	= 0x452,
-	[CAPS_2]	= 0x456,
-	[CAPS_3]	= 0x458,
-	[CAPS_4]	= 0x45a,
-	[PCH2_SR]	= 0x460,
-	[PCH0_SR]	= 0x480,
-	[PCH1_SR]	= 0x482,
-	[PCHD_SR]	= 0x4c0,
+static const struct omap_dma_reg reg_map[] = {
+	[GCR]		= { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
+	[GSCR]		= { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
+	[GRST1]		= { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
+	[HW_ID]		= { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH2_ID]	= { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH0_ID]	= { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH1_ID]	= { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
+	[PCHG_ID]	= { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
+	[PCHD_ID]	= { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
+	[CAPS_0]	= { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
+	[CAPS_1]	= { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
+	[CAPS_2]	= { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
+	[CAPS_3]	= { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
+	[CAPS_4]	= { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH2_SR]	= { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH0_SR]	= { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH1_SR]	= { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
+	[PCHD_SR]	= { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
 
 	/* Common Registers */
-	[CSDP]		= 0x00,
-	[CCR]		= 0x02,
-	[CICR]		= 0x04,
-	[CSR]		= 0x06,
-	[CEN]		= 0x10,
-	[CFN]		= 0x12,
-	[CSFI]		= 0x14,
-	[CSEI]		= 0x16,
-	[CPC]		= 0x18,	/* 15xx only */
-	[CSAC]		= 0x18,
-	[CDAC]		= 0x1a,
-	[CDEI]		= 0x1c,
-	[CDFI]		= 0x1e,
-	[CLNK_CTRL]	= 0x28,
+	[CSDP]		= { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
+	[CCR]		= { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
+	[CICR]		= { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
+	[CSR]		= { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
+	[CEN]		= { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
+	[CFN]		= { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
+	[CSFI]		= { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
+	[CSEI]		= { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
+	[CPC]		= { 0x0018, 0x40, OMAP_DMA_REG_16BIT },	/* 15xx only */
+	[CSAC]		= { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
+	[CDAC]		= { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
+	[CDEI]		= { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
+	[CDFI]		= { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
+	[CLNK_CTRL]	= { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
 
 	/* Channel specific register offsets */
-	[CSSA]		= 0x08,
-	[CDSA]		= 0x0c,
-	[COLOR]		= 0x20,
-	[CCR2]		= 0x24,
-	[LCH_CTRL]	= 0x2a,
+	[CSSA]		= { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
+	[CDSA]		= { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
+	[COLOR]		= { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
+	[CCR2]		= { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
+	[LCH_CTRL]	= { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
 };
 
 static struct resource res[] __initdata = {
@@ -179,36 +178,28 @@ static struct resource res[] __initdata = {
 static void __iomem *dma_base;
 static inline void dma_write(u32 val, int reg, int lch)
 {
-	u8  stride;
-	u32 offset;
+	void __iomem *addr = dma_base;
 
-	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
-	offset = reg_map[reg] + (stride * lch);
+	addr += reg_map[reg].offset;
+	addr += reg_map[reg].stride * lch;
 
-	__raw_writew(val, dma_base + offset);
-	if ((reg > CLNK_CTRL && reg < CCEN) ||
-			(reg > PCHD_ID && reg < CAPS_2)) {
-		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
-		__raw_writew(val >> 16, dma_base + offset2);
-	}
+	__raw_writew(val, addr);
+	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+		__raw_writew(val >> 16, addr + 2);
 }
 
 static inline u32 dma_read(int reg, int lch)
 {
-	u8 stride;
-	u32 offset, val;
-
-	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
-	offset = reg_map[reg] + (stride * lch);
-
-	val = __raw_readw(dma_base + offset);
-	if ((reg > CLNK_CTRL && reg < CCEN) ||
-			(reg > PCHD_ID && reg < CAPS_2)) {
-		u16 upper;
-		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
-		upper = __raw_readw(dma_base + offset2);
-		val |= (upper << 16);
-	}
+	void __iomem *addr = dma_base;
+	uint32_t val;
+
+	addr += reg_map[reg].offset;
+	addr += reg_map[reg].stride * lch;
+
+	val = __raw_readw(addr);
+	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+		val |= __raw_readw(addr + 2) << 16;
+
 	return val;
 }
 
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index e4ac7ac9a228..e633b48a3fcb 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -35,80 +35,77 @@
 #include "omap_hwmod.h"
 #include "omap_device.h"
 
-#define OMAP2_DMA_STRIDE	0x60
-
 static u32 errata;
 
 static struct omap_dma_dev_attr *d;
 
 static enum omap_reg_offsets dma_common_ch_end;
 
-static u16 reg_map[] = {
-	[REVISION]		= 0x00,
-	[GCR]			= 0x78,
-	[IRQSTATUS_L0]		= 0x08,
-	[IRQSTATUS_L1]		= 0x0c,
-	[IRQSTATUS_L2]		= 0x10,
-	[IRQSTATUS_L3]		= 0x14,
-	[IRQENABLE_L0]		= 0x18,
-	[IRQENABLE_L1]		= 0x1c,
-	[IRQENABLE_L2]		= 0x20,
-	[IRQENABLE_L3]		= 0x24,
-	[SYSSTATUS]		= 0x28,
-	[OCP_SYSCONFIG]		= 0x2c,
-	[CAPS_0]		= 0x64,
-	[CAPS_2]		= 0x6c,
-	[CAPS_3]		= 0x70,
-	[CAPS_4]		= 0x74,
+static const struct omap_dma_reg reg_map[] = {
+	[REVISION]	= { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
+	[GCR]		= { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQSTATUS_L0]	= { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQSTATUS_L1]	= { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQSTATUS_L2]	= { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQSTATUS_L3]	= { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQENABLE_L0]	= { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQENABLE_L1]	= { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQENABLE_L2]	= { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQENABLE_L3]	= { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
+	[SYSSTATUS]	= { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
+	[OCP_SYSCONFIG]	= { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
+	[CAPS_0]	= { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
+	[CAPS_2]	= { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
+	[CAPS_3]	= { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
+	[CAPS_4]	= { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
 
 	/* Common register offsets */
-	[CCR]			= 0x80,
-	[CLNK_CTRL]		= 0x84,
-	[CICR]			= 0x88,
-	[CSR]			= 0x8c,
-	[CSDP]			= 0x90,
-	[CEN]			= 0x94,
-	[CFN]			= 0x98,
-	[CSEI]			= 0xa4,
-	[CSFI]			= 0xa8,
-	[CDEI]			= 0xac,
-	[CDFI]			= 0xb0,
-	[CSAC]			= 0xb4,
-	[CDAC]			= 0xb8,
+	[CCR]		= { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
+	[CLNK_CTRL]	= { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
+	[CICR]		= { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
+	[CSR]		= { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
+	[CSDP]		= { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
+	[CEN]		= { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
+	[CFN]		= { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
+	[CSEI]		= { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
+	[CSFI]		= { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
+	[CDEI]		= { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
+	[CDFI]		= { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
+	[CSAC]		= { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
+	[CDAC]		= { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
 
 	/* Channel specific register offsets */
-	[CSSA]			= 0x9c,
-	[CDSA]			= 0xa0,
-	[CCEN]			= 0xbc,
-	[CCFN]			= 0xc0,
-	[COLOR]			= 0xc4,
+	[CSSA]		= { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
+	[CDSA]		= { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
+	[CCEN]		= { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
+	[CCFN]		= { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
+	[COLOR]		= { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
 
 	/* OMAP4 specific registers */
-	[CDP]			= 0xd0,
-	[CNDP]			= 0xd4,
-	[CCDN]			= 0xd8,
+	[CDP]		= { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
+	[CNDP]		= { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
+	[CCDN]		= { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
 };
 
 static void __iomem *dma_base;
 static inline void dma_write(u32 val, int reg, int lch)
 {
-	u8  stride;
-	u32 offset;
+	void __iomem *addr = dma_base;
+
+	addr += reg_map[reg].offset;
+	addr += reg_map[reg].stride * lch;
 
-	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
-	offset = reg_map[reg] + (stride * lch);
-	__raw_writel(val, dma_base + offset);
+	__raw_writel(val, addr);
 }
 
 static inline u32 dma_read(int reg, int lch)
 {
-	u8 stride;
-	u32 offset, val;
+	void __iomem *addr = dma_base;
+
+	addr += reg_map[reg].offset;
+	addr += reg_map[reg].stride * lch;
 
-	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
-	offset = reg_map[reg] + (stride * lch);
-	val = __raw_readl(dma_base + offset);
-	return val;
+	return __raw_readl(addr);
 }
 
 static void omap2_clear_dma(int lch)
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 0bb7de77d478..41328725721a 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -271,6 +271,19 @@ struct omap_dma_dev_attr {
 	struct omap_dma_lch *chan;
 };
 
+enum {
+	OMAP_DMA_REG_NONE,
+	OMAP_DMA_REG_16BIT,
+	OMAP_DMA_REG_2X16BIT,
+	OMAP_DMA_REG_32BIT,
+};
+
+struct omap_dma_reg {
+	u16	offset;
+	u8	stride;
+	u8	type;
+};
+
 /* System DMA platform data structure */
 struct omap_system_dma_plat_info {
 	struct omap_dma_dev_attr *dma_attr;
-- 
1.7.4.4

[PATCH RFC 20/26] ARM: omap: clean up DMA register accesses

[Russell King]

We can do much better with this by using a structure to describe each
register, rather than code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |  121 +++++++++++++++++++++------------------------
 arch/arm/mach-omap2/dma.c |   99 ++++++++++++++++++-------------------
 include/linux/omap-dma.h  |   13 +++++
 3 files changed, 117 insertions(+), 116 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 11f0b0ee67a3..de30e28ff487 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -32,53 +32,52 @@
 
 #define OMAP1_DMA_BASE			(0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT	17
-#define OMAP1_DMA_STRIDE		0x40
 
 static u32 errata;
 static u32 enable_1510_mode;
 
-static u16 reg_map[] = {
-	[GCR]		= 0x400,
-	[GSCR]		= 0x404,
-	[GRST1]		= 0x408,
-	[HW_ID]		= 0x442,
-	[PCH2_ID]	= 0x444,
-	[PCH0_ID]	= 0x446,
-	[PCH1_ID]	= 0x448,
-	[PCHG_ID]	= 0x44a,
-	[PCHD_ID]	= 0x44c,
-	[CAPS_0]	= 0x44e,
-	[CAPS_1]	= 0x452,
-	[CAPS_2]	= 0x456,
-	[CAPS_3]	= 0x458,
-	[CAPS_4]	= 0x45a,
-	[PCH2_SR]	= 0x460,
-	[PCH0_SR]	= 0x480,
-	[PCH1_SR]	= 0x482,
-	[PCHD_SR]	= 0x4c0,
+static const struct omap_dma_reg reg_map[] = {
+	[GCR]		= { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
+	[GSCR]		= { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
+	[GRST1]		= { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
+	[HW_ID]		= { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH2_ID]	= { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH0_ID]	= { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH1_ID]	= { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
+	[PCHG_ID]	= { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
+	[PCHD_ID]	= { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
+	[CAPS_0]	= { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
+	[CAPS_1]	= { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
+	[CAPS_2]	= { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
+	[CAPS_3]	= { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
+	[CAPS_4]	= { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH2_SR]	= { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH0_SR]	= { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
+	[PCH1_SR]	= { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
+	[PCHD_SR]	= { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
 
 	/* Common Registers */
-	[CSDP]		= 0x00,
-	[CCR]		= 0x02,
-	[CICR]		= 0x04,
-	[CSR]		= 0x06,
-	[CEN]		= 0x10,
-	[CFN]		= 0x12,
-	[CSFI]		= 0x14,
-	[CSEI]		= 0x16,
-	[CPC]		= 0x18,	/* 15xx only */
-	[CSAC]		= 0x18,
-	[CDAC]		= 0x1a,
-	[CDEI]		= 0x1c,
-	[CDFI]		= 0x1e,
-	[CLNK_CTRL]	= 0x28,
+	[CSDP]		= { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
+	[CCR]		= { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
+	[CICR]		= { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
+	[CSR]		= { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
+	[CEN]		= { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
+	[CFN]		= { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
+	[CSFI]		= { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
+	[CSEI]		= { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
+	[CPC]		= { 0x0018, 0x40, OMAP_DMA_REG_16BIT },	/* 15xx only */
+	[CSAC]		= { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
+	[CDAC]		= { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
+	[CDEI]		= { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
+	[CDFI]		= { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
+	[CLNK_CTRL]	= { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
 
 	/* Channel specific register offsets */
-	[CSSA]		= 0x08,
-	[CDSA]		= 0x0c,
-	[COLOR]		= 0x20,
-	[CCR2]		= 0x24,
-	[LCH_CTRL]	= 0x2a,
+	[CSSA]		= { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
+	[CDSA]		= { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
+	[COLOR]		= { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
+	[CCR2]		= { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
+	[LCH_CTRL]	= { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
 };
 
 static struct resource res[] __initdata = {
@@ -179,36 +178,28 @@ static struct resource res[] __initdata = {
 static void __iomem *dma_base;
 static inline void dma_write(u32 val, int reg, int lch)
 {
-	u8  stride;
-	u32 offset;
+	void __iomem *addr = dma_base;
 
-	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
-	offset = reg_map[reg] + (stride * lch);
+	addr += reg_map[reg].offset;
+	addr += reg_map[reg].stride * lch;
 
-	__raw_writew(val, dma_base + offset);
-	if ((reg > CLNK_CTRL && reg < CCEN) ||
-			(reg > PCHD_ID && reg < CAPS_2)) {
-		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
-		__raw_writew(val >> 16, dma_base + offset2);
-	}
+	__raw_writew(val, addr);
+	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+		__raw_writew(val >> 16, addr + 2);
 }
 
 static inline u32 dma_read(int reg, int lch)
 {
-	u8 stride;
-	u32 offset, val;
-
-	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
-	offset = reg_map[reg] + (stride * lch);
-
-	val = __raw_readw(dma_base + offset);
-	if ((reg > CLNK_CTRL && reg < CCEN) ||
-			(reg > PCHD_ID && reg < CAPS_2)) {
-		u16 upper;
-		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
-		upper = __raw_readw(dma_base + offset2);
-		val |= (upper << 16);
-	}
+	void __iomem *addr = dma_base;
+	uint32_t val;
+
+	addr += reg_map[reg].offset;
+	addr += reg_map[reg].stride * lch;
+
+	val = __raw_readw(addr);
+	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+		val |= __raw_readw(addr + 2) << 16;
+
 	return val;
 }
 
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index e4ac7ac9a228..e633b48a3fcb 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -35,80 +35,77 @@
 #include "omap_hwmod.h"
 #include "omap_device.h"
 
-#define OMAP2_DMA_STRIDE	0x60
-
 static u32 errata;
 
 static struct omap_dma_dev_attr *d;
 
 static enum omap_reg_offsets dma_common_ch_end;
 
-static u16 reg_map[] = {
-	[REVISION]		= 0x00,
-	[GCR]			= 0x78,
-	[IRQSTATUS_L0]		= 0x08,
-	[IRQSTATUS_L1]		= 0x0c,
-	[IRQSTATUS_L2]		= 0x10,
-	[IRQSTATUS_L3]		= 0x14,
-	[IRQENABLE_L0]		= 0x18,
-	[IRQENABLE_L1]		= 0x1c,
-	[IRQENABLE_L2]		= 0x20,
-	[IRQENABLE_L3]		= 0x24,
-	[SYSSTATUS]		= 0x28,
-	[OCP_SYSCONFIG]		= 0x2c,
-	[CAPS_0]		= 0x64,
-	[CAPS_2]		= 0x6c,
-	[CAPS_3]		= 0x70,
-	[CAPS_4]		= 0x74,
+static const struct omap_dma_reg reg_map[] = {
+	[REVISION]	= { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
+	[GCR]		= { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQSTATUS_L0]	= { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQSTATUS_L1]	= { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQSTATUS_L2]	= { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQSTATUS_L3]	= { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQENABLE_L0]	= { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQENABLE_L1]	= { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQENABLE_L2]	= { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
+	[IRQENABLE_L3]	= { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
+	[SYSSTATUS]	= { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
+	[OCP_SYSCONFIG]	= { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
+	[CAPS_0]	= { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
+	[CAPS_2]	= { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
+	[CAPS_3]	= { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
+	[CAPS_4]	= { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
 
 	/* Common register offsets */
-	[CCR]			= 0x80,
-	[CLNK_CTRL]		= 0x84,
-	[CICR]			= 0x88,
-	[CSR]			= 0x8c,
-	[CSDP]			= 0x90,
-	[CEN]			= 0x94,
-	[CFN]			= 0x98,
-	[CSEI]			= 0xa4,
-	[CSFI]			= 0xa8,
-	[CDEI]			= 0xac,
-	[CDFI]			= 0xb0,
-	[CSAC]			= 0xb4,
-	[CDAC]			= 0xb8,
+	[CCR]		= { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
+	[CLNK_CTRL]	= { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
+	[CICR]		= { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
+	[CSR]		= { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
+	[CSDP]		= { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
+	[CEN]		= { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
+	[CFN]		= { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
+	[CSEI]		= { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
+	[CSFI]		= { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
+	[CDEI]		= { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
+	[CDFI]		= { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
+	[CSAC]		= { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
+	[CDAC]		= { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
 
 	/* Channel specific register offsets */
-	[CSSA]			= 0x9c,
-	[CDSA]			= 0xa0,
-	[CCEN]			= 0xbc,
-	[CCFN]			= 0xc0,
-	[COLOR]			= 0xc4,
+	[CSSA]		= { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
+	[CDSA]		= { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
+	[CCEN]		= { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
+	[CCFN]		= { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
+	[COLOR]		= { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
 
 	/* OMAP4 specific registers */
-	[CDP]			= 0xd0,
-	[CNDP]			= 0xd4,
-	[CCDN]			= 0xd8,
+	[CDP]		= { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
+	[CNDP]		= { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
+	[CCDN]		= { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
 };
 
 static void __iomem *dma_base;
 static inline void dma_write(u32 val, int reg, int lch)
 {
-	u8  stride;
-	u32 offset;
+	void __iomem *addr = dma_base;
+
+	addr += reg_map[reg].offset;
+	addr += reg_map[reg].stride * lch;
 
-	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
-	offset = reg_map[reg] + (stride * lch);
-	__raw_writel(val, dma_base + offset);
+	__raw_writel(val, addr);
 }
 
 static inline u32 dma_read(int reg, int lch)
 {
-	u8 stride;
-	u32 offset, val;
+	void __iomem *addr = dma_base;
+
+	addr += reg_map[reg].offset;
+	addr += reg_map[reg].stride * lch;
 
-	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
-	offset = reg_map[reg] + (stride * lch);
-	val = __raw_readl(dma_base + offset);
-	return val;
+	return __raw_readl(addr);
 }
 
 static void omap2_clear_dma(int lch)
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 0bb7de77d478..41328725721a 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -271,6 +271,19 @@ struct omap_dma_dev_attr {
 	struct omap_dma_lch *chan;
 };
 
+enum {
+	OMAP_DMA_REG_NONE,
+	OMAP_DMA_REG_16BIT,
+	OMAP_DMA_REG_2X16BIT,
+	OMAP_DMA_REG_32BIT,
+};
+
+struct omap_dma_reg {
+	u16	offset;
+	u8	stride;
+	u8	type;
+};
+
 /* System DMA platform data structure */
 struct omap_system_dma_plat_info {
 	struct omap_dma_dev_attr *dma_attr;
-- 
1.7.4.4

Re: [PATCH RFC 20/26] ARM: omap: clean up DMA register accesses

[Andy Shevchenko]

On Thu, 2014-01-02 at 15:12 +0000, Russell King wrote:
> We can do much better with this by using a structure to describe each
> register, rather than code.
> 

One comment bellow.


> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  arch/arm/mach-omap1/dma.c |  121 +++++++++++++++++++++------------------------
>  arch/arm/mach-omap2/dma.c |   99 ++++++++++++++++++-------------------
>  include/linux/omap-dma.h  |   13 +++++
>  3 files changed, 117 insertions(+), 116 deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> index 11f0b0ee67a3..de30e28ff487 100644
> --- a/arch/arm/mach-omap1/dma.c
> +++ b/arch/arm/mach-omap1/dma.c
> @@ -32,53 +32,52 @@
>  
>  #define OMAP1_DMA_BASE			(0xfffed800)
>  #define OMAP1_LOGICAL_DMA_CH_COUNT	17
> -#define OMAP1_DMA_STRIDE		0x40

Does this belong to patch 19/26 ?

>  
>  static u32 errata;
>  static u32 enable_1510_mode;
>  
> -static u16 reg_map[] = {
> -	[GCR]		= 0x400,
> -	[GSCR]		= 0x404,
> -	[GRST1]		= 0x408,
> -	[HW_ID]		= 0x442,
> -	[PCH2_ID]	= 0x444,
> -	[PCH0_ID]	= 0x446,
> -	[PCH1_ID]	= 0x448,
> -	[PCHG_ID]	= 0x44a,
> -	[PCHD_ID]	= 0x44c,
> -	[CAPS_0]	= 0x44e,
> -	[CAPS_1]	= 0x452,
> -	[CAPS_2]	= 0x456,
> -	[CAPS_3]	= 0x458,
> -	[CAPS_4]	= 0x45a,
> -	[PCH2_SR]	= 0x460,
> -	[PCH0_SR]	= 0x480,
> -	[PCH1_SR]	= 0x482,
> -	[PCHD_SR]	= 0x4c0,
> +static const struct omap_dma_reg reg_map[] = {
> +	[GCR]		= { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
> +	[GSCR]		= { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
> +	[GRST1]		= { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
> +	[HW_ID]		= { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH2_ID]	= { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH0_ID]	= { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH1_ID]	= { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCHG_ID]	= { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCHD_ID]	= { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
> +	[CAPS_0]	= { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
> +	[CAPS_1]	= { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
> +	[CAPS_2]	= { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
> +	[CAPS_3]	= { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
> +	[CAPS_4]	= { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH2_SR]	= { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH0_SR]	= { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH1_SR]	= { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCHD_SR]	= { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
>  
>  	/* Common Registers */
> -	[CSDP]		= 0x00,
> -	[CCR]		= 0x02,
> -	[CICR]		= 0x04,
> -	[CSR]		= 0x06,
> -	[CEN]		= 0x10,
> -	[CFN]		= 0x12,
> -	[CSFI]		= 0x14,
> -	[CSEI]		= 0x16,
> -	[CPC]		= 0x18,	/* 15xx only */
> -	[CSAC]		= 0x18,
> -	[CDAC]		= 0x1a,
> -	[CDEI]		= 0x1c,
> -	[CDFI]		= 0x1e,
> -	[CLNK_CTRL]	= 0x28,
> +	[CSDP]		= { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
> +	[CCR]		= { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
> +	[CICR]		= { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
> +	[CSR]		= { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
> +	[CEN]		= { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
> +	[CFN]		= { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
> +	[CSFI]		= { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
> +	[CSEI]		= { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
> +	[CPC]		= { 0x0018, 0x40, OMAP_DMA_REG_16BIT },	/* 15xx only */
> +	[CSAC]		= { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
> +	[CDAC]		= { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
> +	[CDEI]		= { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
> +	[CDFI]		= { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
> +	[CLNK_CTRL]	= { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
>  
>  	/* Channel specific register offsets */
> -	[CSSA]		= 0x08,
> -	[CDSA]		= 0x0c,
> -	[COLOR]		= 0x20,
> -	[CCR2]		= 0x24,
> -	[LCH_CTRL]	= 0x2a,
> +	[CSSA]		= { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
> +	[CDSA]		= { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
> +	[COLOR]		= { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
> +	[CCR2]		= { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
> +	[LCH_CTRL]	= { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
>  };
>  
>  static struct resource res[] __initdata = {
> @@ -179,36 +178,28 @@ static struct resource res[] __initdata = {
>  static void __iomem *dma_base;
>  static inline void dma_write(u32 val, int reg, int lch)
>  {
> -	u8  stride;
> -	u32 offset;
> +	void __iomem *addr = dma_base;
>  
> -	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
> -	offset = reg_map[reg] + (stride * lch);
> +	addr += reg_map[reg].offset;
> +	addr += reg_map[reg].stride * lch;
>  
> -	__raw_writew(val, dma_base + offset);
> -	if ((reg > CLNK_CTRL && reg < CCEN) ||
> -			(reg > PCHD_ID && reg < CAPS_2)) {
> -		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
> -		__raw_writew(val >> 16, dma_base + offset2);
> -	}
> +	__raw_writew(val, addr);
> +	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> +		__raw_writew(val >> 16, addr + 2);
>  }
>  
>  static inline u32 dma_read(int reg, int lch)
>  {
> -	u8 stride;
> -	u32 offset, val;
> -
> -	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
> -	offset = reg_map[reg] + (stride * lch);
> -
> -	val = __raw_readw(dma_base + offset);
> -	if ((reg > CLNK_CTRL && reg < CCEN) ||
> -			(reg > PCHD_ID && reg < CAPS_2)) {
> -		u16 upper;
> -		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
> -		upper = __raw_readw(dma_base + offset2);
> -		val |= (upper << 16);
> -	}
> +	void __iomem *addr = dma_base;
> +	uint32_t val;
> +
> +	addr += reg_map[reg].offset;
> +	addr += reg_map[reg].stride * lch;
> +
> +	val = __raw_readw(addr);
> +	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> +		val |= __raw_readw(addr + 2) << 16;
> +
>  	return val;
>  }
>  
> diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
> index e4ac7ac9a228..e633b48a3fcb 100644
> --- a/arch/arm/mach-omap2/dma.c
> +++ b/arch/arm/mach-omap2/dma.c
> @@ -35,80 +35,77 @@
>  #include "omap_hwmod.h"
>  #include "omap_device.h"
>  
> -#define OMAP2_DMA_STRIDE	0x60
> -
>  static u32 errata;
>  
>  static struct omap_dma_dev_attr *d;
>  
>  static enum omap_reg_offsets dma_common_ch_end;
>  
> -static u16 reg_map[] = {
> -	[REVISION]		= 0x00,
> -	[GCR]			= 0x78,
> -	[IRQSTATUS_L0]		= 0x08,
> -	[IRQSTATUS_L1]		= 0x0c,
> -	[IRQSTATUS_L2]		= 0x10,
> -	[IRQSTATUS_L3]		= 0x14,
> -	[IRQENABLE_L0]		= 0x18,
> -	[IRQENABLE_L1]		= 0x1c,
> -	[IRQENABLE_L2]		= 0x20,
> -	[IRQENABLE_L3]		= 0x24,
> -	[SYSSTATUS]		= 0x28,
> -	[OCP_SYSCONFIG]		= 0x2c,
> -	[CAPS_0]		= 0x64,
> -	[CAPS_2]		= 0x6c,
> -	[CAPS_3]		= 0x70,
> -	[CAPS_4]		= 0x74,
> +static const struct omap_dma_reg reg_map[] = {
> +	[REVISION]	= { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
> +	[GCR]		= { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQSTATUS_L0]	= { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQSTATUS_L1]	= { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQSTATUS_L2]	= { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQSTATUS_L3]	= { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQENABLE_L0]	= { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQENABLE_L1]	= { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQENABLE_L2]	= { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQENABLE_L3]	= { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
> +	[SYSSTATUS]	= { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
> +	[OCP_SYSCONFIG]	= { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
> +	[CAPS_0]	= { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
> +	[CAPS_2]	= { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
> +	[CAPS_3]	= { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
> +	[CAPS_4]	= { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
>  
>  	/* Common register offsets */
> -	[CCR]			= 0x80,
> -	[CLNK_CTRL]		= 0x84,
> -	[CICR]			= 0x88,
> -	[CSR]			= 0x8c,
> -	[CSDP]			= 0x90,
> -	[CEN]			= 0x94,
> -	[CFN]			= 0x98,
> -	[CSEI]			= 0xa4,
> -	[CSFI]			= 0xa8,
> -	[CDEI]			= 0xac,
> -	[CDFI]			= 0xb0,
> -	[CSAC]			= 0xb4,
> -	[CDAC]			= 0xb8,
> +	[CCR]		= { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
> +	[CLNK_CTRL]	= { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
> +	[CICR]		= { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSR]		= { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSDP]		= { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
> +	[CEN]		= { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
> +	[CFN]		= { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSEI]		= { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSFI]		= { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
> +	[CDEI]		= { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
> +	[CDFI]		= { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSAC]		= { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
> +	[CDAC]		= { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
>  
>  	/* Channel specific register offsets */
> -	[CSSA]			= 0x9c,
> -	[CDSA]			= 0xa0,
> -	[CCEN]			= 0xbc,
> -	[CCFN]			= 0xc0,
> -	[COLOR]			= 0xc4,
> +	[CSSA]		= { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
> +	[CDSA]		= { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
> +	[CCEN]		= { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
> +	[CCFN]		= { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
> +	[COLOR]		= { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
>  
>  	/* OMAP4 specific registers */
> -	[CDP]			= 0xd0,
> -	[CNDP]			= 0xd4,
> -	[CCDN]			= 0xd8,
> +	[CDP]		= { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
> +	[CNDP]		= { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
> +	[CCDN]		= { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
>  };
>  
>  static void __iomem *dma_base;
>  static inline void dma_write(u32 val, int reg, int lch)
>  {
> -	u8  stride;
> -	u32 offset;
> +	void __iomem *addr = dma_base;
> +
> +	addr += reg_map[reg].offset;
> +	addr += reg_map[reg].stride * lch;
>  
> -	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
> -	offset = reg_map[reg] + (stride * lch);
> -	__raw_writel(val, dma_base + offset);
> +	__raw_writel(val, addr);
>  }
>  
>  static inline u32 dma_read(int reg, int lch)
>  {
> -	u8 stride;
> -	u32 offset, val;
> +	void __iomem *addr = dma_base;
> +
> +	addr += reg_map[reg].offset;
> +	addr += reg_map[reg].stride * lch;
>  
> -	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
> -	offset = reg_map[reg] + (stride * lch);
> -	val = __raw_readl(dma_base + offset);
> -	return val;
> +	return __raw_readl(addr);
>  }
>  
>  static void omap2_clear_dma(int lch)
> diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
> index 0bb7de77d478..41328725721a 100644
> --- a/include/linux/omap-dma.h
> +++ b/include/linux/omap-dma.h
> @@ -271,6 +271,19 @@ struct omap_dma_dev_attr {
>  	struct omap_dma_lch *chan;
>  };
>  
> +enum {
> +	OMAP_DMA_REG_NONE,
> +	OMAP_DMA_REG_16BIT,
> +	OMAP_DMA_REG_2X16BIT,
> +	OMAP_DMA_REG_32BIT,
> +};
> +
> +struct omap_dma_reg {
> +	u16	offset;
> +	u8	stride;
> +	u8	type;
> +};
> +
>  /* System DMA platform data structure */
>  struct omap_system_dma_plat_info {
>  	struct omap_dma_dev_attr *dma_attr;

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

[PATCH RFC 20/26] ARM: omap: clean up DMA register accesses

[Andy Shevchenko]

On Thu, 2014-01-02 at 15:12 +0000, Russell King wrote:
> We can do much better with this by using a structure to describe each
> register, rather than code.
> 

One comment bellow.


> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  arch/arm/mach-omap1/dma.c |  121 +++++++++++++++++++++------------------------
>  arch/arm/mach-omap2/dma.c |   99 ++++++++++++++++++-------------------
>  include/linux/omap-dma.h  |   13 +++++
>  3 files changed, 117 insertions(+), 116 deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> index 11f0b0ee67a3..de30e28ff487 100644
> --- a/arch/arm/mach-omap1/dma.c
> +++ b/arch/arm/mach-omap1/dma.c
> @@ -32,53 +32,52 @@
>  
>  #define OMAP1_DMA_BASE			(0xfffed800)
>  #define OMAP1_LOGICAL_DMA_CH_COUNT	17
> -#define OMAP1_DMA_STRIDE		0x40

Does this belong to patch 19/26 ?

>  
>  static u32 errata;
>  static u32 enable_1510_mode;
>  
> -static u16 reg_map[] = {
> -	[GCR]		= 0x400,
> -	[GSCR]		= 0x404,
> -	[GRST1]		= 0x408,
> -	[HW_ID]		= 0x442,
> -	[PCH2_ID]	= 0x444,
> -	[PCH0_ID]	= 0x446,
> -	[PCH1_ID]	= 0x448,
> -	[PCHG_ID]	= 0x44a,
> -	[PCHD_ID]	= 0x44c,
> -	[CAPS_0]	= 0x44e,
> -	[CAPS_1]	= 0x452,
> -	[CAPS_2]	= 0x456,
> -	[CAPS_3]	= 0x458,
> -	[CAPS_4]	= 0x45a,
> -	[PCH2_SR]	= 0x460,
> -	[PCH0_SR]	= 0x480,
> -	[PCH1_SR]	= 0x482,
> -	[PCHD_SR]	= 0x4c0,
> +static const struct omap_dma_reg reg_map[] = {
> +	[GCR]		= { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
> +	[GSCR]		= { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
> +	[GRST1]		= { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
> +	[HW_ID]		= { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH2_ID]	= { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH0_ID]	= { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH1_ID]	= { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCHG_ID]	= { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCHD_ID]	= { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
> +	[CAPS_0]	= { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
> +	[CAPS_1]	= { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
> +	[CAPS_2]	= { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
> +	[CAPS_3]	= { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
> +	[CAPS_4]	= { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH2_SR]	= { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH0_SR]	= { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCH1_SR]	= { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
> +	[PCHD_SR]	= { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
>  
>  	/* Common Registers */
> -	[CSDP]		= 0x00,
> -	[CCR]		= 0x02,
> -	[CICR]		= 0x04,
> -	[CSR]		= 0x06,
> -	[CEN]		= 0x10,
> -	[CFN]		= 0x12,
> -	[CSFI]		= 0x14,
> -	[CSEI]		= 0x16,
> -	[CPC]		= 0x18,	/* 15xx only */
> -	[CSAC]		= 0x18,
> -	[CDAC]		= 0x1a,
> -	[CDEI]		= 0x1c,
> -	[CDFI]		= 0x1e,
> -	[CLNK_CTRL]	= 0x28,
> +	[CSDP]		= { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
> +	[CCR]		= { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
> +	[CICR]		= { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
> +	[CSR]		= { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
> +	[CEN]		= { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
> +	[CFN]		= { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
> +	[CSFI]		= { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
> +	[CSEI]		= { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
> +	[CPC]		= { 0x0018, 0x40, OMAP_DMA_REG_16BIT },	/* 15xx only */
> +	[CSAC]		= { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
> +	[CDAC]		= { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
> +	[CDEI]		= { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
> +	[CDFI]		= { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
> +	[CLNK_CTRL]	= { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
>  
>  	/* Channel specific register offsets */
> -	[CSSA]		= 0x08,
> -	[CDSA]		= 0x0c,
> -	[COLOR]		= 0x20,
> -	[CCR2]		= 0x24,
> -	[LCH_CTRL]	= 0x2a,
> +	[CSSA]		= { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
> +	[CDSA]		= { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
> +	[COLOR]		= { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
> +	[CCR2]		= { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
> +	[LCH_CTRL]	= { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
>  };
>  
>  static struct resource res[] __initdata = {
> @@ -179,36 +178,28 @@ static struct resource res[] __initdata = {
>  static void __iomem *dma_base;
>  static inline void dma_write(u32 val, int reg, int lch)
>  {
> -	u8  stride;
> -	u32 offset;
> +	void __iomem *addr = dma_base;
>  
> -	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
> -	offset = reg_map[reg] + (stride * lch);
> +	addr += reg_map[reg].offset;
> +	addr += reg_map[reg].stride * lch;
>  
> -	__raw_writew(val, dma_base + offset);
> -	if ((reg > CLNK_CTRL && reg < CCEN) ||
> -			(reg > PCHD_ID && reg < CAPS_2)) {
> -		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
> -		__raw_writew(val >> 16, dma_base + offset2);
> -	}
> +	__raw_writew(val, addr);
> +	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> +		__raw_writew(val >> 16, addr + 2);
>  }
>  
>  static inline u32 dma_read(int reg, int lch)
>  {
> -	u8 stride;
> -	u32 offset, val;
> -
> -	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
> -	offset = reg_map[reg] + (stride * lch);
> -
> -	val = __raw_readw(dma_base + offset);
> -	if ((reg > CLNK_CTRL && reg < CCEN) ||
> -			(reg > PCHD_ID && reg < CAPS_2)) {
> -		u16 upper;
> -		u32 offset2 = reg_map[reg] + 2 + (stride * lch);
> -		upper = __raw_readw(dma_base + offset2);
> -		val |= (upper << 16);
> -	}
> +	void __iomem *addr = dma_base;
> +	uint32_t val;
> +
> +	addr += reg_map[reg].offset;
> +	addr += reg_map[reg].stride * lch;
> +
> +	val = __raw_readw(addr);
> +	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> +		val |= __raw_readw(addr + 2) << 16;
> +
>  	return val;
>  }
>  
> diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
> index e4ac7ac9a228..e633b48a3fcb 100644
> --- a/arch/arm/mach-omap2/dma.c
> +++ b/arch/arm/mach-omap2/dma.c
> @@ -35,80 +35,77 @@
>  #include "omap_hwmod.h"
>  #include "omap_device.h"
>  
> -#define OMAP2_DMA_STRIDE	0x60
> -
>  static u32 errata;
>  
>  static struct omap_dma_dev_attr *d;
>  
>  static enum omap_reg_offsets dma_common_ch_end;
>  
> -static u16 reg_map[] = {
> -	[REVISION]		= 0x00,
> -	[GCR]			= 0x78,
> -	[IRQSTATUS_L0]		= 0x08,
> -	[IRQSTATUS_L1]		= 0x0c,
> -	[IRQSTATUS_L2]		= 0x10,
> -	[IRQSTATUS_L3]		= 0x14,
> -	[IRQENABLE_L0]		= 0x18,
> -	[IRQENABLE_L1]		= 0x1c,
> -	[IRQENABLE_L2]		= 0x20,
> -	[IRQENABLE_L3]		= 0x24,
> -	[SYSSTATUS]		= 0x28,
> -	[OCP_SYSCONFIG]		= 0x2c,
> -	[CAPS_0]		= 0x64,
> -	[CAPS_2]		= 0x6c,
> -	[CAPS_3]		= 0x70,
> -	[CAPS_4]		= 0x74,
> +static const struct omap_dma_reg reg_map[] = {
> +	[REVISION]	= { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
> +	[GCR]		= { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQSTATUS_L0]	= { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQSTATUS_L1]	= { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQSTATUS_L2]	= { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQSTATUS_L3]	= { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQENABLE_L0]	= { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQENABLE_L1]	= { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQENABLE_L2]	= { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
> +	[IRQENABLE_L3]	= { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
> +	[SYSSTATUS]	= { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
> +	[OCP_SYSCONFIG]	= { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
> +	[CAPS_0]	= { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
> +	[CAPS_2]	= { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
> +	[CAPS_3]	= { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
> +	[CAPS_4]	= { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
>  
>  	/* Common register offsets */
> -	[CCR]			= 0x80,
> -	[CLNK_CTRL]		= 0x84,
> -	[CICR]			= 0x88,
> -	[CSR]			= 0x8c,
> -	[CSDP]			= 0x90,
> -	[CEN]			= 0x94,
> -	[CFN]			= 0x98,
> -	[CSEI]			= 0xa4,
> -	[CSFI]			= 0xa8,
> -	[CDEI]			= 0xac,
> -	[CDFI]			= 0xb0,
> -	[CSAC]			= 0xb4,
> -	[CDAC]			= 0xb8,
> +	[CCR]		= { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
> +	[CLNK_CTRL]	= { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
> +	[CICR]		= { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSR]		= { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSDP]		= { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
> +	[CEN]		= { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
> +	[CFN]		= { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSEI]		= { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSFI]		= { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
> +	[CDEI]		= { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
> +	[CDFI]		= { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
> +	[CSAC]		= { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
> +	[CDAC]		= { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
>  
>  	/* Channel specific register offsets */
> -	[CSSA]			= 0x9c,
> -	[CDSA]			= 0xa0,
> -	[CCEN]			= 0xbc,
> -	[CCFN]			= 0xc0,
> -	[COLOR]			= 0xc4,
> +	[CSSA]		= { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
> +	[CDSA]		= { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
> +	[CCEN]		= { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
> +	[CCFN]		= { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
> +	[COLOR]		= { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
>  
>  	/* OMAP4 specific registers */
> -	[CDP]			= 0xd0,
> -	[CNDP]			= 0xd4,
> -	[CCDN]			= 0xd8,
> +	[CDP]		= { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
> +	[CNDP]		= { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
> +	[CCDN]		= { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
>  };
>  
>  static void __iomem *dma_base;
>  static inline void dma_write(u32 val, int reg, int lch)
>  {
> -	u8  stride;
> -	u32 offset;
> +	void __iomem *addr = dma_base;
> +
> +	addr += reg_map[reg].offset;
> +	addr += reg_map[reg].stride * lch;
>  
> -	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
> -	offset = reg_map[reg] + (stride * lch);
> -	__raw_writel(val, dma_base + offset);
> +	__raw_writel(val, addr);
>  }
>  
>  static inline u32 dma_read(int reg, int lch)
>  {
> -	u8 stride;
> -	u32 offset, val;
> +	void __iomem *addr = dma_base;
> +
> +	addr += reg_map[reg].offset;
> +	addr += reg_map[reg].stride * lch;
>  
> -	stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0;
> -	offset = reg_map[reg] + (stride * lch);
> -	val = __raw_readl(dma_base + offset);
> -	return val;
> +	return __raw_readl(addr);
>  }
>  
>  static void omap2_clear_dma(int lch)
> diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
> index 0bb7de77d478..41328725721a 100644
> --- a/include/linux/omap-dma.h
> +++ b/include/linux/omap-dma.h
> @@ -271,6 +271,19 @@ struct omap_dma_dev_attr {
>  	struct omap_dma_lch *chan;
>  };
>  
> +enum {
> +	OMAP_DMA_REG_NONE,
> +	OMAP_DMA_REG_16BIT,
> +	OMAP_DMA_REG_2X16BIT,
> +	OMAP_DMA_REG_32BIT,
> +};
> +
> +struct omap_dma_reg {
> +	u16	offset;
> +	u8	stride;
> +	u8	type;
> +};
> +
>  /* System DMA platform data structure */
>  struct omap_system_dma_plat_info {
>  	struct omap_dma_dev_attr *dma_attr;

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH RFC 20/26] ARM: omap: clean up DMA register accesses

[Russell King - ARM Linux]

On Thu, Jan 02, 2014 at 05:49:38PM +0200, Andy Shevchenko wrote:
> On Thu, 2014-01-02 at 15:12 +0000, Russell King wrote:
> > We can do much better with this by using a structure to describe each
> > register, rather than code.
> > 
> 
> One comment bellow.
> 
> 
> > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> > ---
> >  arch/arm/mach-omap1/dma.c |  121 +++++++++++++++++++++------------------------
> >  arch/arm/mach-omap2/dma.c |   99 ++++++++++++++++++-------------------
> >  include/linux/omap-dma.h  |   13 +++++
> >  3 files changed, 117 insertions(+), 116 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> > index 11f0b0ee67a3..de30e28ff487 100644
> > --- a/arch/arm/mach-omap1/dma.c
> > +++ b/arch/arm/mach-omap1/dma.c
> > @@ -32,53 +32,52 @@
> >  
> >  #define OMAP1_DMA_BASE			(0xfffed800)
> >  #define OMAP1_LOGICAL_DMA_CH_COUNT	17
> > -#define OMAP1_DMA_STRIDE		0x40
> 
> Does this belong to patch 19/26 ?

Why?

> >  static void __iomem *dma_base;
> >  static inline void dma_write(u32 val, int reg, int lch)
> >  {
> > -	u8  stride;
> > -	u32 offset;
> > +	void __iomem *addr = dma_base;
> >  
> > -	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
                                ^^^^^^^^^^^^^^^^
The code here still uses it prior to this patch.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 20/26] ARM: omap: clean up DMA register accesses

[Russell King - ARM Linux]

On Thu, Jan 02, 2014 at 05:49:38PM +0200, Andy Shevchenko wrote:
> On Thu, 2014-01-02 at 15:12 +0000, Russell King wrote:
> > We can do much better with this by using a structure to describe each
> > register, rather than code.
> > 
> 
> One comment bellow.
> 
> 
> > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> > ---
> >  arch/arm/mach-omap1/dma.c |  121 +++++++++++++++++++++------------------------
> >  arch/arm/mach-omap2/dma.c |   99 ++++++++++++++++++-------------------
> >  include/linux/omap-dma.h  |   13 +++++
> >  3 files changed, 117 insertions(+), 116 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> > index 11f0b0ee67a3..de30e28ff487 100644
> > --- a/arch/arm/mach-omap1/dma.c
> > +++ b/arch/arm/mach-omap1/dma.c
> > @@ -32,53 +32,52 @@
> >  
> >  #define OMAP1_DMA_BASE			(0xfffed800)
> >  #define OMAP1_LOGICAL_DMA_CH_COUNT	17
> > -#define OMAP1_DMA_STRIDE		0x40
> 
> Does this belong to patch 19/26 ?

Why?

> >  static void __iomem *dma_base;
> >  static inline void dma_write(u32 val, int reg, int lch)
> >  {
> > -	u8  stride;
> > -	u32 offset;
> > +	void __iomem *addr = dma_base;
> >  
> > -	stride = (reg >= CPC) ? OMAP1_DMA_STRIDE : 0;
                                ^^^^^^^^^^^^^^^^
The code here still uses it prior to this patch.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 21/26] ARM: omap: dma: get rid of errata global

[Russell King]

There's no need for this to be a global variable; move it into the
errata configuration function instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |    4 ++--
 arch/arm/mach-omap2/dma.c |    5 ++---
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index de30e28ff487..4aae75d40bdd 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -33,7 +33,6 @@
 #define OMAP1_DMA_BASE			(0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT	17
 
-static u32 errata;
 static u32 enable_1510_mode;
 
 static const struct omap_dma_reg reg_map[] = {
@@ -244,8 +243,9 @@ static void omap1_show_dma_caps(void)
 	return;
 }
 
-static u32 configure_dma_errata(void)
+static unsigned configure_dma_errata(void)
 {
+	unsigned errata = 0;
 
 	/*
 	 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index e633b48a3fcb..244ff5012aed 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -35,8 +35,6 @@
 #include "omap_hwmod.h"
 #include "omap_device.h"
 
-static u32 errata;
-
 static struct omap_dma_dev_attr *d;
 
 static enum omap_reg_offsets dma_common_ch_end;
@@ -124,8 +122,9 @@ static void omap2_show_dma_caps(void)
 	return;
 }
 
-static u32 configure_dma_errata(void)
+static unsigned configure_dma_errata(void)
 {
+	unsigned errata = 0;
 
 	/*
 	 * Errata applicable for OMAP2430ES1.0 and all omap2420
-- 
1.7.4.4

[PATCH RFC 21/26] ARM: omap: dma: get rid of errata global

[Russell King]

There's no need for this to be a global variable; move it into the
errata configuration function instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |    4 ++--
 arch/arm/mach-omap2/dma.c |    5 ++---
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index de30e28ff487..4aae75d40bdd 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -33,7 +33,6 @@
 #define OMAP1_DMA_BASE			(0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT	17
 
-static u32 errata;
 static u32 enable_1510_mode;
 
 static const struct omap_dma_reg reg_map[] = {
@@ -244,8 +243,9 @@ static void omap1_show_dma_caps(void)
 	return;
 }
 
-static u32 configure_dma_errata(void)
+static unsigned configure_dma_errata(void)
 {
+	unsigned errata = 0;
 
 	/*
 	 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index e633b48a3fcb..244ff5012aed 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -35,8 +35,6 @@
 #include "omap_hwmod.h"
 #include "omap_device.h"
 
-static u32 errata;
-
 static struct omap_dma_dev_attr *d;
 
 static enum omap_reg_offsets dma_common_ch_end;
@@ -124,8 +122,9 @@ static void omap2_show_dma_caps(void)
 	return;
 }
 
-static u32 configure_dma_errata(void)
+static unsigned configure_dma_errata(void)
 {
+	unsigned errata = 0;
 
 	/*
 	 * Errata applicable for OMAP2430ES1.0 and all omap2420
-- 
1.7.4.4

[PATCH RFC 22/26] ARM: omap: move dma channel allocation into plat-omap code

[Russell King]

This really needs to be there, because otherwise the plat-omap code can
kfree() this data structure, and then re-use the pointer later.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |   11 -----------
 arch/arm/mach-omap2/dma.c |    7 -------
 arch/arm/plat-omap/dma.c  |   11 ++++++++---
 include/linux/omap-dma.h  |    1 -
 4 files changed, 8 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 4aae75d40bdd..3e93d0a323a4 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -325,17 +325,6 @@ static int __init omap1_system_dma_init(void)
 	d->dev_caps		|= CLEAR_CSR_ON_READ;
 	d->dev_caps		|= IS_WORD_16;
 
-
-	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
-					(d->lch_count), GFP_KERNEL);
-	if (!d->chan) {
-		dev_err(&pdev->dev,
-			"%s: Memory allocation failed for d->chan!\n",
-			__func__);
-		ret = -ENOMEM;
-		goto exit_release_d;
-	}
-
 	if (cpu_is_omap15xx())
 		d->chan_count = 9;
 	else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 244ff5012aed..9f210d637354 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -251,13 +251,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 	}
 
 	d = oh->dev_attr;
-	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
-					(d->lch_count), GFP_KERNEL);
-
-	if (!d->chan) {
-		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
-		return -ENOMEM;
-	}
 
 	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
 		d->dev_caps |= HS_CHANNELS_RESERVED;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index d4d9a5e62152..377c3d7dc4ce 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2030,9 +2030,16 @@ static int omap_system_dma_probe(struct platform_device *pdev)
 
 	dma_lch_count		= d->lch_count;
 	dma_chan_count		= dma_lch_count;
-	dma_chan		= d->chan;
 	enable_1510_mode	= d->dev_caps & ENABLE_1510_MODE;
 
+	dma_chan = devm_kzalloc(&pdev->dev, sizeof(struct omap_dma_lch) *
+				dma_lch_count, GFP_KERNEL);
+	if (!dma_chan) {
+		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
+		return -ENOMEM;
+	}
+
+
 	if (dma_omap2plus()) {
 		dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
 						dma_lch_count, GFP_KERNEL);
@@ -2117,7 +2124,6 @@ static int omap_system_dma_probe(struct platform_device *pdev)
 	}
 
 exit_dma_lch_fail:
-	kfree(dma_chan);
 	return ret;
 }
 
@@ -2137,7 +2143,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
 			free_irq(dma_irq, (void *)(irq_rel + 1));
 		}
 	}
-	kfree(dma_chan);
 	return 0;
 }
 
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 41328725721a..7813636a193d 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -268,7 +268,6 @@ struct omap_dma_dev_attr {
 	u32 dev_caps;
 	u16 lch_count;
 	u16 chan_count;
-	struct omap_dma_lch *chan;
 };
 
 enum {
-- 
1.7.4.4

[PATCH RFC 22/26] ARM: omap: move dma channel allocation into plat-omap code

[Russell King]

This really needs to be there, because otherwise the plat-omap code can
kfree() this data structure, and then re-use the pointer later.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |   11 -----------
 arch/arm/mach-omap2/dma.c |    7 -------
 arch/arm/plat-omap/dma.c  |   11 ++++++++---
 include/linux/omap-dma.h  |    1 -
 4 files changed, 8 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 4aae75d40bdd..3e93d0a323a4 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -325,17 +325,6 @@ static int __init omap1_system_dma_init(void)
 	d->dev_caps		|= CLEAR_CSR_ON_READ;
 	d->dev_caps		|= IS_WORD_16;
 
-
-	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
-					(d->lch_count), GFP_KERNEL);
-	if (!d->chan) {
-		dev_err(&pdev->dev,
-			"%s: Memory allocation failed for d->chan!\n",
-			__func__);
-		ret = -ENOMEM;
-		goto exit_release_d;
-	}
-
 	if (cpu_is_omap15xx())
 		d->chan_count = 9;
 	else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 244ff5012aed..9f210d637354 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -251,13 +251,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 	}
 
 	d = oh->dev_attr;
-	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
-					(d->lch_count), GFP_KERNEL);
-
-	if (!d->chan) {
-		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
-		return -ENOMEM;
-	}
 
 	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
 		d->dev_caps |= HS_CHANNELS_RESERVED;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index d4d9a5e62152..377c3d7dc4ce 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2030,9 +2030,16 @@ static int omap_system_dma_probe(struct platform_device *pdev)
 
 	dma_lch_count		= d->lch_count;
 	dma_chan_count		= dma_lch_count;
-	dma_chan		= d->chan;
 	enable_1510_mode	= d->dev_caps & ENABLE_1510_MODE;
 
+	dma_chan = devm_kzalloc(&pdev->dev, sizeof(struct omap_dma_lch) *
+				dma_lch_count, GFP_KERNEL);
+	if (!dma_chan) {
+		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
+		return -ENOMEM;
+	}
+
+
 	if (dma_omap2plus()) {
 		dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
 						dma_lch_count, GFP_KERNEL);
@@ -2117,7 +2124,6 @@ static int omap_system_dma_probe(struct platform_device *pdev)
 	}
 
 exit_dma_lch_fail:
-	kfree(dma_chan);
 	return ret;
 }
 
@@ -2137,7 +2143,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
 			free_irq(dma_irq, (void *)(irq_rel + 1));
 		}
 	}
-	kfree(dma_chan);
 	return 0;
 }
 
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 41328725721a..7813636a193d 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -268,7 +268,6 @@ struct omap_dma_dev_attr {
 	u32 dev_caps;
 	u16 lch_count;
 	u16 chan_count;
-	struct omap_dma_lch *chan;
 };
 
 enum {
-- 
1.7.4.4

Re: [PATCH RFC 22/26] ARM: omap: move dma channel allocation into plat-omap code

[Andy Shevchenko]

On Thu, 2014-01-02 at 15:12 +0000, Russell King wrote:
> This really needs to be there, because otherwise the plat-omap code can
> kfree() this data structure, and then re-use the pointer later.

One comment bellow.

> 
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  arch/arm/mach-omap1/dma.c |   11 -----------
>  arch/arm/mach-omap2/dma.c |    7 -------
>  arch/arm/plat-omap/dma.c  |   11 ++++++++---
>  include/linux/omap-dma.h  |    1 -
>  4 files changed, 8 insertions(+), 22 deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> index 4aae75d40bdd..3e93d0a323a4 100644
> --- a/arch/arm/mach-omap1/dma.c
> +++ b/arch/arm/mach-omap1/dma.c
> @@ -325,17 +325,6 @@ static int __init omap1_system_dma_init(void)
>  	d->dev_caps		|= CLEAR_CSR_ON_READ;
>  	d->dev_caps		|= IS_WORD_16;
>  
> -
> -	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
> -					(d->lch_count), GFP_KERNEL);
> -	if (!d->chan) {
> -		dev_err(&pdev->dev,
> -			"%s: Memory allocation failed for d->chan!\n",
> -			__func__);
> -		ret = -ENOMEM;
> -		goto exit_release_d;
> -	}
> -
>  	if (cpu_is_omap15xx())
>  		d->chan_count = 9;
>  	else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
> diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
> index 244ff5012aed..9f210d637354 100644
> --- a/arch/arm/mach-omap2/dma.c
> +++ b/arch/arm/mach-omap2/dma.c
> @@ -251,13 +251,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
>  	}
>  
>  	d = oh->dev_attr;
> -	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
> -					(d->lch_count), GFP_KERNEL);
> -
> -	if (!d->chan) {
> -		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
> -		return -ENOMEM;
> -	}
>  
>  	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
>  		d->dev_caps |= HS_CHANNELS_RESERVED;
> diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
> index d4d9a5e62152..377c3d7dc4ce 100644
> --- a/arch/arm/plat-omap/dma.c
> +++ b/arch/arm/plat-omap/dma.c
> @@ -2030,9 +2030,16 @@ static int omap_system_dma_probe(struct platform_device *pdev)
>  
>  	dma_lch_count		= d->lch_count;
>  	dma_chan_count		= dma_lch_count;
> -	dma_chan		= d->chan;
>  	enable_1510_mode	= d->dev_caps & ENABLE_1510_MODE;
>  
> +	dma_chan = devm_kzalloc(&pdev->dev, sizeof(struct omap_dma_lch) *
> +				dma_lch_count, GFP_KERNEL);

devm_kcalloc ?

> +	if (!dma_chan) {
> +		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
> +		return -ENOMEM;
> +	}
> +
> +
>  	if (dma_omap2plus()) {
>  		dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
>  						dma_lch_count, GFP_KERNEL);
> @@ -2117,7 +2124,6 @@ static int omap_system_dma_probe(struct platform_device *pdev)
>  	}
>  
>  exit_dma_lch_fail:
> -	kfree(dma_chan);
>  	return ret;
>  }
>  
> @@ -2137,7 +2143,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
>  			free_irq(dma_irq, (void *)(irq_rel + 1));
>  		}
>  	}
> -	kfree(dma_chan);
>  	return 0;
>  }
>  
> diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
> index 41328725721a..7813636a193d 100644
> --- a/include/linux/omap-dma.h
> +++ b/include/linux/omap-dma.h
> @@ -268,7 +268,6 @@ struct omap_dma_dev_attr {
>  	u32 dev_caps;
>  	u16 lch_count;
>  	u16 chan_count;
> -	struct omap_dma_lch *chan;
>  };
>  
>  enum {

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

[PATCH RFC 22/26] ARM: omap: move dma channel allocation into plat-omap code

[Andy Shevchenko]

On Thu, 2014-01-02 at 15:12 +0000, Russell King wrote:
> This really needs to be there, because otherwise the plat-omap code can
> kfree() this data structure, and then re-use the pointer later.

One comment bellow.

> 
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  arch/arm/mach-omap1/dma.c |   11 -----------
>  arch/arm/mach-omap2/dma.c |    7 -------
>  arch/arm/plat-omap/dma.c  |   11 ++++++++---
>  include/linux/omap-dma.h  |    1 -
>  4 files changed, 8 insertions(+), 22 deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> index 4aae75d40bdd..3e93d0a323a4 100644
> --- a/arch/arm/mach-omap1/dma.c
> +++ b/arch/arm/mach-omap1/dma.c
> @@ -325,17 +325,6 @@ static int __init omap1_system_dma_init(void)
>  	d->dev_caps		|= CLEAR_CSR_ON_READ;
>  	d->dev_caps		|= IS_WORD_16;
>  
> -
> -	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
> -					(d->lch_count), GFP_KERNEL);
> -	if (!d->chan) {
> -		dev_err(&pdev->dev,
> -			"%s: Memory allocation failed for d->chan!\n",
> -			__func__);
> -		ret = -ENOMEM;
> -		goto exit_release_d;
> -	}
> -
>  	if (cpu_is_omap15xx())
>  		d->chan_count = 9;
>  	else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
> diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
> index 244ff5012aed..9f210d637354 100644
> --- a/arch/arm/mach-omap2/dma.c
> +++ b/arch/arm/mach-omap2/dma.c
> @@ -251,13 +251,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
>  	}
>  
>  	d = oh->dev_attr;
> -	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
> -					(d->lch_count), GFP_KERNEL);
> -
> -	if (!d->chan) {
> -		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
> -		return -ENOMEM;
> -	}
>  
>  	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
>  		d->dev_caps |= HS_CHANNELS_RESERVED;
> diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
> index d4d9a5e62152..377c3d7dc4ce 100644
> --- a/arch/arm/plat-omap/dma.c
> +++ b/arch/arm/plat-omap/dma.c
> @@ -2030,9 +2030,16 @@ static int omap_system_dma_probe(struct platform_device *pdev)
>  
>  	dma_lch_count		= d->lch_count;
>  	dma_chan_count		= dma_lch_count;
> -	dma_chan		= d->chan;
>  	enable_1510_mode	= d->dev_caps & ENABLE_1510_MODE;
>  
> +	dma_chan = devm_kzalloc(&pdev->dev, sizeof(struct omap_dma_lch) *
> +				dma_lch_count, GFP_KERNEL);

devm_kcalloc ?

> +	if (!dma_chan) {
> +		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
> +		return -ENOMEM;
> +	}
> +
> +
>  	if (dma_omap2plus()) {
>  		dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
>  						dma_lch_count, GFP_KERNEL);
> @@ -2117,7 +2124,6 @@ static int omap_system_dma_probe(struct platform_device *pdev)
>  	}
>  
>  exit_dma_lch_fail:
> -	kfree(dma_chan);
>  	return ret;
>  }
>  
> @@ -2137,7 +2143,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
>  			free_irq(dma_irq, (void *)(irq_rel + 1));
>  		}
>  	}
> -	kfree(dma_chan);
>  	return 0;
>  }
>  
> diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
> index 41328725721a..7813636a193d 100644
> --- a/include/linux/omap-dma.h
> +++ b/include/linux/omap-dma.h
> @@ -268,7 +268,6 @@ struct omap_dma_dev_attr {
>  	u32 dev_caps;
>  	u16 lch_count;
>  	u16 chan_count;
> -	struct omap_dma_lch *chan;
>  };
>  
>  enum {

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

[PATCH RFC 23/26] ARM: omap: dma: get rid of 'p' allocation and clean up

[Russell King]

The omap_system_dma_plat_info structure is only seven words, it's not
worth the expense of kmalloc()'ing backing store for this only to
release it later.  Note that platform_device_add_data() copies the
data anyway.  Clean up the initialisation of this structure - we don't
even need code to initialise most of this structure.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |   36 ++++++++++++++----------------------
 arch/arm/mach-omap2/dma.c |   34 +++++++++++++---------------------
 2 files changed, 27 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 3e93d0a323a4..8b1b914d0a6f 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -263,9 +263,17 @@ static const struct platform_device_info omap_dma_dev_info = {
 	.dma_mask = DMA_BIT_MASK(32),
 };
 
+static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+	.show_dma_caps	= omap1_show_dma_caps,
+	.clear_lch_regs	= omap1_clear_lch_regs,
+	.clear_dma	= omap1_clear_dma,
+	.dma_write	= dma_write,
+	.dma_read	= dma_read,
+};
+
 static int __init omap1_system_dma_init(void)
 {
-	struct omap_system_dma_plat_info	*p;
+	struct omap_system_dma_plat_info	p;
 	struct omap_dma_dev_attr		*d;
 	struct platform_device			*pdev, *dma_pdev;
 	int ret;
@@ -291,20 +299,12 @@ static int __init omap1_system_dma_init(void)
 		goto exit_iounmap;
 	}
 
-	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
-	if (!p) {
-		dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
-			__func__, pdev->name);
-		ret = -ENOMEM;
-		goto exit_iounmap;
-	}
-
 	d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
 	if (!d) {
 		dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
 			__func__, pdev->name);
 		ret = -ENOMEM;
-		goto exit_release_p;
+		goto exit_iounmap;
 	}
 
 	d->lch_count		= OMAP1_LOGICAL_DMA_CH_COUNT;
@@ -334,17 +334,11 @@ static int __init omap1_system_dma_init(void)
 			d->chan_count = 9;
 	}
 
-	p->dma_attr = d;
-
-	p->show_dma_caps	= omap1_show_dma_caps;
-	p->clear_lch_regs	= omap1_clear_lch_regs;
-	p->clear_dma		= omap1_clear_dma;
-	p->dma_write		= dma_write;
-	p->dma_read		= dma_read;
-
-	p->errata = configure_dma_errata();
+	p = dma_plat_info;
+	p.dma_attr = d;
+	p.errata = configure_dma_errata();
 
-	ret = platform_device_add_data(pdev, p, sizeof(*p));
+	ret = platform_device_add_data(pdev, &p, sizeof(p));
 	if (ret) {
 		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
 			__func__, pdev->name, pdev->id);
@@ -372,8 +366,6 @@ static int __init omap1_system_dma_init(void)
 	kfree(d->chan);
 exit_release_d:
 	kfree(d);
-exit_release_p:
-	kfree(p);
 exit_iounmap:
 	iounmap(dma_base);
 exit_device_put:
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 9f210d637354..6331fc4b4054 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -35,8 +35,6 @@
 #include "omap_hwmod.h"
 #include "omap_device.h"
 
-static struct omap_dma_dev_attr *d;
-
 static enum omap_reg_offsets dma_common_ch_end;
 
 static const struct omap_dma_reg reg_map[] = {
@@ -206,33 +204,27 @@ static unsigned configure_dma_errata(void)
 	return errata;
 }
 
+static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+	.show_dma_caps	= omap2_show_dma_caps,
+	.clear_dma	= omap2_clear_dma,
+	.dma_write	= dma_write,
+	.dma_read	= dma_read,
+};
+
 /* One time initializations */
 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 {
 	struct platform_device			*pdev;
-	struct omap_system_dma_plat_info	*p;
+	struct omap_system_dma_plat_info	p;
+	struct omap_dma_dev_attr		*d;
 	struct resource				*mem;
 	char					*name = "omap_dma_system";
 
-	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
-	if (!p) {
-		pr_err("%s: Unable to allocate pdata for %s:%s\n",
-			__func__, name, oh->name);
-		return -ENOMEM;
-	}
-
-	p->dma_attr		= (struct omap_dma_dev_attr *)oh->dev_attr;
-	p->show_dma_caps	= omap2_show_dma_caps;
-	p->clear_dma		= omap2_clear_dma;
-	p->dma_write		= dma_write;
-	p->dma_read		= dma_read;
-
-	p->clear_lch_regs	= NULL;
-
-	p->errata		= configure_dma_errata();
+	p = dma_plat_info;
+	p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
+	p.errata = configure_dma_errata();
 
-	pdev = omap_device_build(name, 0, oh, p, sizeof(*p));
-	kfree(p);
+	pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
 	if (IS_ERR(pdev)) {
 		pr_err("%s: Can't build omap_device for %s:%s.\n",
 			__func__, name, oh->name);
-- 
1.7.4.4

[PATCH RFC 23/26] ARM: omap: dma: get rid of 'p' allocation and clean up

[Russell King]

The omap_system_dma_plat_info structure is only seven words, it's not
worth the expense of kmalloc()'ing backing store for this only to
release it later.  Note that platform_device_add_data() copies the
data anyway.  Clean up the initialisation of this structure - we don't
even need code to initialise most of this structure.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |   36 ++++++++++++++----------------------
 arch/arm/mach-omap2/dma.c |   34 +++++++++++++---------------------
 2 files changed, 27 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 3e93d0a323a4..8b1b914d0a6f 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -263,9 +263,17 @@ static const struct platform_device_info omap_dma_dev_info = {
 	.dma_mask = DMA_BIT_MASK(32),
 };
 
+static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+	.show_dma_caps	= omap1_show_dma_caps,
+	.clear_lch_regs	= omap1_clear_lch_regs,
+	.clear_dma	= omap1_clear_dma,
+	.dma_write	= dma_write,
+	.dma_read	= dma_read,
+};
+
 static int __init omap1_system_dma_init(void)
 {
-	struct omap_system_dma_plat_info	*p;
+	struct omap_system_dma_plat_info	p;
 	struct omap_dma_dev_attr		*d;
 	struct platform_device			*pdev, *dma_pdev;
 	int ret;
@@ -291,20 +299,12 @@ static int __init omap1_system_dma_init(void)
 		goto exit_iounmap;
 	}
 
-	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
-	if (!p) {
-		dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
-			__func__, pdev->name);
-		ret = -ENOMEM;
-		goto exit_iounmap;
-	}
-
 	d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
 	if (!d) {
 		dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
 			__func__, pdev->name);
 		ret = -ENOMEM;
-		goto exit_release_p;
+		goto exit_iounmap;
 	}
 
 	d->lch_count		= OMAP1_LOGICAL_DMA_CH_COUNT;
@@ -334,17 +334,11 @@ static int __init omap1_system_dma_init(void)
 			d->chan_count = 9;
 	}
 
-	p->dma_attr = d;
-
-	p->show_dma_caps	= omap1_show_dma_caps;
-	p->clear_lch_regs	= omap1_clear_lch_regs;
-	p->clear_dma		= omap1_clear_dma;
-	p->dma_write		= dma_write;
-	p->dma_read		= dma_read;
-
-	p->errata = configure_dma_errata();
+	p = dma_plat_info;
+	p.dma_attr = d;
+	p.errata = configure_dma_errata();
 
-	ret = platform_device_add_data(pdev, p, sizeof(*p));
+	ret = platform_device_add_data(pdev, &p, sizeof(p));
 	if (ret) {
 		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
 			__func__, pdev->name, pdev->id);
@@ -372,8 +366,6 @@ static int __init omap1_system_dma_init(void)
 	kfree(d->chan);
 exit_release_d:
 	kfree(d);
-exit_release_p:
-	kfree(p);
 exit_iounmap:
 	iounmap(dma_base);
 exit_device_put:
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 9f210d637354..6331fc4b4054 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -35,8 +35,6 @@
 #include "omap_hwmod.h"
 #include "omap_device.h"
 
-static struct omap_dma_dev_attr *d;
-
 static enum omap_reg_offsets dma_common_ch_end;
 
 static const struct omap_dma_reg reg_map[] = {
@@ -206,33 +204,27 @@ static unsigned configure_dma_errata(void)
 	return errata;
 }
 
+static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+	.show_dma_caps	= omap2_show_dma_caps,
+	.clear_dma	= omap2_clear_dma,
+	.dma_write	= dma_write,
+	.dma_read	= dma_read,
+};
+
 /* One time initializations */
 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 {
 	struct platform_device			*pdev;
-	struct omap_system_dma_plat_info	*p;
+	struct omap_system_dma_plat_info	p;
+	struct omap_dma_dev_attr		*d;
 	struct resource				*mem;
 	char					*name = "omap_dma_system";
 
-	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
-	if (!p) {
-		pr_err("%s: Unable to allocate pdata for %s:%s\n",
-			__func__, name, oh->name);
-		return -ENOMEM;
-	}
-
-	p->dma_attr		= (struct omap_dma_dev_attr *)oh->dev_attr;
-	p->show_dma_caps	= omap2_show_dma_caps;
-	p->clear_dma		= omap2_clear_dma;
-	p->dma_write		= dma_write;
-	p->dma_read		= dma_read;
-
-	p->clear_lch_regs	= NULL;
-
-	p->errata		= configure_dma_errata();
+	p = dma_plat_info;
+	p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
+	p.errata = configure_dma_errata();
 
-	pdev = omap_device_build(name, 0, oh, p, sizeof(*p));
-	kfree(p);
+	pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
 	if (IS_ERR(pdev)) {
 		pr_err("%s: Can't build omap_device for %s:%s.\n",
 			__func__, name, oh->name);
-- 
1.7.4.4

[PATCH RFC 24/26] dmaengine: omap-dma: move register read/writes into omap-dma.c

[Russell King]

Export the DMA register information from the SoC specific data, such
that we can access the registers directly in omap-dma.c, mapping the
register region ourselves as well.

Rather than calculating the DMA channel register in its entirety for
each access, we pre-calculate an offset base address for the allocated
DMA channel and then just use the appropriate register offset.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |    2 +
 arch/arm/mach-omap2/dma.c |    2 +
 drivers/dma/omap-dma.c    |   96 ++++++++++++++++++++++++++++++++++++++++----
 include/linux/omap-dma.h  |    2 +
 4 files changed, 93 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 8b1b914d0a6f..3afde9628839 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -264,6 +264,8 @@ static const struct platform_device_info omap_dma_dev_info = {
 };
 
 static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+	.reg_map	= reg_map,
+	.channel_stride	= 0x40,
 	.show_dma_caps	= omap1_show_dma_caps,
 	.clear_lch_regs	= omap1_clear_lch_regs,
 	.clear_dma	= omap1_clear_dma,
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 6331fc4b4054..e08e55a173b6 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -205,6 +205,8 @@ static unsigned configure_dma_errata(void)
 }
 
 static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+	.reg_map	= reg_map,
+	.channel_stride	= 0x60,
 	.show_dma_caps	= omap2_show_dma_caps,
 	.clear_dma	= omap2_clear_dma,
 	.dma_write	= dma_write,
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 04631e6732c4..611963e82623 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -27,13 +27,16 @@ struct omap_dmadev {
 	spinlock_t lock;
 	struct tasklet_struct task;
 	struct list_head pending;
+	void __iomem *base;
+	const struct omap_dma_reg *reg_map;
 	struct omap_system_dma_plat_info *plat;
 };
 
 struct omap_chan {
 	struct virt_dma_chan vc;
 	struct list_head node;
-	struct omap_system_dma_plat_info *plat;
+	void __iomem *channel_base;
+	const struct omap_dma_reg *reg_map;
 
 	struct dma_slave_config	cfg;
 	unsigned dma_sig;
@@ -169,24 +172,77 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
 	kfree(container_of(vd, struct omap_desc, vd));
 }
 
+static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
+{
+	switch (type) {
+	case OMAP_DMA_REG_16BIT:
+		writew_relaxed(val, addr);
+		break;
+	case OMAP_DMA_REG_2X16BIT:
+		writew_relaxed(val, addr);
+		writew_relaxed(val >> 16, addr + 2);
+		break;
+	case OMAP_DMA_REG_32BIT:
+		writel_relaxed(val, addr);
+		break;
+	default:
+		WARN_ON(1);
+	}
+}
+
+static unsigned omap_dma_read(unsigned type, void __iomem *addr)
+{
+	unsigned val;
+
+	switch (type) {
+	case OMAP_DMA_REG_16BIT:
+		val = readw_relaxed(addr);
+		break;
+	case OMAP_DMA_REG_2X16BIT:
+		val = readw_relaxed(addr);
+		val |= readw_relaxed(addr + 2) << 16;
+		break;
+	case OMAP_DMA_REG_32BIT:
+		val = readl_relaxed(addr);
+		break;
+	default:
+		WARN_ON(1);
+		val = 0;
+	}
+
+	return val;
+}
+
 static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
 {
-	od->plat->dma_write(val, reg, 0);
+	const struct omap_dma_reg *r = od->reg_map + reg;
+
+	WARN_ON(r->stride);
+
+	omap_dma_write(val, r->type, od->base + r->offset);
 }
 
 static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
 {
-	return od->plat->dma_read(reg, 0);
+	const struct omap_dma_reg *r = od->reg_map + reg;
+
+	WARN_ON(r->stride);
+
+	return omap_dma_read(r->type, od->base + r->offset);
 }
 
 static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
 {
-	c->plat->dma_write(val, reg, c->dma_ch);
+	const struct omap_dma_reg *r = c->reg_map + reg;
+
+	omap_dma_write(val, r->type, c->channel_base + r->offset);
 }
 
 static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
 {
-	return c->plat->dma_read(reg, c->dma_ch);
+	const struct omap_dma_reg *r = c->reg_map + reg;
+
+	return omap_dma_read(r->type, c->channel_base + r->offset);
 }
 
 static void omap_dma_clear_csr(struct omap_chan *c)
@@ -197,6 +253,12 @@ static void omap_dma_clear_csr(struct omap_chan *c)
 		omap_dma_chan_write(c, CSR, ~0);
 }
 
+static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
+	unsigned lch)
+{
+	c->channel_base = od->base + od->plat->channel_stride * lch;
+}
+
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
@@ -400,18 +462,26 @@ static void omap_dma_sched(unsigned long data)
 
 static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
 {
+	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
+	int ret;
+
+	dev_info(od->ddev.dev, "allocating channel for %u\n", c->dma_sig);
 
-	dev_info(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig);
+	ret = omap_request_dma(c->dma_sig, "DMA engine", omap_dma_callback,
+			       c, &c->dma_ch);
 
-	return omap_request_dma(c->dma_sig, "DMA engine",
-		omap_dma_callback, c, &c->dma_ch);
+	if (ret >= 0)
+		omap_dma_assign(od, c, c->dma_ch);
+
+	return ret;
 }
 
 static void omap_dma_free_chan_resources(struct dma_chan *chan)
 {
 	struct omap_chan *c = to_omap_dma_chan(chan);
 
+	c->channel_base = NULL;
 	vchan_free_chan_resources(&c->vc);
 	omap_free_dma(c->dma_ch);
 
@@ -901,7 +971,7 @@ static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
 	if (!c)
 		return -ENOMEM;
 
-	c->plat = od->plat;
+	c->reg_map = od->reg_map;
 	c->dma_sig = dma_sig;
 	c->vc.desc_free = omap_dma_desc_free;
 	vchan_init(&c->vc, &od->ddev);
@@ -928,16 +998,24 @@ static void omap_dma_free(struct omap_dmadev *od)
 static int omap_dma_probe(struct platform_device *pdev)
 {
 	struct omap_dmadev *od;
+	struct resource *res;
 	int rc, i;
 
 	od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 	if (!od)
 		return -ENOMEM;
 
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	od->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(od->base))
+		return PTR_ERR(od->base);
+
 	od->plat = omap_get_plat_info();
 	if (!od->plat)
 		return -EPROBE_DEFER;
 
+	od->reg_map = od->plat->reg_map;
+
 	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 	dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 	od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 7813636a193d..41a13e70f41f 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -285,6 +285,8 @@ struct omap_dma_reg {
 
 /* System DMA platform data structure */
 struct omap_system_dma_plat_info {
+	const struct omap_dma_reg *reg_map;
+	unsigned channel_stride;
 	struct omap_dma_dev_attr *dma_attr;
 	u32 errata;
 	void (*show_dma_caps)(void);
-- 
1.7.4.4

[PATCH RFC 24/26] dmaengine: omap-dma: move register read/writes into omap-dma.c

[Russell King]

Export the DMA register information from the SoC specific data, such
that we can access the registers directly in omap-dma.c, mapping the
register region ourselves as well.

Rather than calculating the DMA channel register in its entirety for
each access, we pre-calculate an offset base address for the allocated
DMA channel and then just use the appropriate register offset.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap1/dma.c |    2 +
 arch/arm/mach-omap2/dma.c |    2 +
 drivers/dma/omap-dma.c    |   96 ++++++++++++++++++++++++++++++++++++++++----
 include/linux/omap-dma.h  |    2 +
 4 files changed, 93 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 8b1b914d0a6f..3afde9628839 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -264,6 +264,8 @@ static const struct platform_device_info omap_dma_dev_info = {
 };
 
 static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+	.reg_map	= reg_map,
+	.channel_stride	= 0x40,
 	.show_dma_caps	= omap1_show_dma_caps,
 	.clear_lch_regs	= omap1_clear_lch_regs,
 	.clear_dma	= omap1_clear_dma,
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 6331fc4b4054..e08e55a173b6 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -205,6 +205,8 @@ static unsigned configure_dma_errata(void)
 }
 
 static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+	.reg_map	= reg_map,
+	.channel_stride	= 0x60,
 	.show_dma_caps	= omap2_show_dma_caps,
 	.clear_dma	= omap2_clear_dma,
 	.dma_write	= dma_write,
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 04631e6732c4..611963e82623 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -27,13 +27,16 @@ struct omap_dmadev {
 	spinlock_t lock;
 	struct tasklet_struct task;
 	struct list_head pending;
+	void __iomem *base;
+	const struct omap_dma_reg *reg_map;
 	struct omap_system_dma_plat_info *plat;
 };
 
 struct omap_chan {
 	struct virt_dma_chan vc;
 	struct list_head node;
-	struct omap_system_dma_plat_info *plat;
+	void __iomem *channel_base;
+	const struct omap_dma_reg *reg_map;
 
 	struct dma_slave_config	cfg;
 	unsigned dma_sig;
@@ -169,24 +172,77 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
 	kfree(container_of(vd, struct omap_desc, vd));
 }
 
+static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
+{
+	switch (type) {
+	case OMAP_DMA_REG_16BIT:
+		writew_relaxed(val, addr);
+		break;
+	case OMAP_DMA_REG_2X16BIT:
+		writew_relaxed(val, addr);
+		writew_relaxed(val >> 16, addr + 2);
+		break;
+	case OMAP_DMA_REG_32BIT:
+		writel_relaxed(val, addr);
+		break;
+	default:
+		WARN_ON(1);
+	}
+}
+
+static unsigned omap_dma_read(unsigned type, void __iomem *addr)
+{
+	unsigned val;
+
+	switch (type) {
+	case OMAP_DMA_REG_16BIT:
+		val = readw_relaxed(addr);
+		break;
+	case OMAP_DMA_REG_2X16BIT:
+		val = readw_relaxed(addr);
+		val |= readw_relaxed(addr + 2) << 16;
+		break;
+	case OMAP_DMA_REG_32BIT:
+		val = readl_relaxed(addr);
+		break;
+	default:
+		WARN_ON(1);
+		val = 0;
+	}
+
+	return val;
+}
+
 static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
 {
-	od->plat->dma_write(val, reg, 0);
+	const struct omap_dma_reg *r = od->reg_map + reg;
+
+	WARN_ON(r->stride);
+
+	omap_dma_write(val, r->type, od->base + r->offset);
 }
 
 static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
 {
-	return od->plat->dma_read(reg, 0);
+	const struct omap_dma_reg *r = od->reg_map + reg;
+
+	WARN_ON(r->stride);
+
+	return omap_dma_read(r->type, od->base + r->offset);
 }
 
 static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
 {
-	c->plat->dma_write(val, reg, c->dma_ch);
+	const struct omap_dma_reg *r = c->reg_map + reg;
+
+	omap_dma_write(val, r->type, c->channel_base + r->offset);
 }
 
 static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
 {
-	return c->plat->dma_read(reg, c->dma_ch);
+	const struct omap_dma_reg *r = c->reg_map + reg;
+
+	return omap_dma_read(r->type, c->channel_base + r->offset);
 }
 
 static void omap_dma_clear_csr(struct omap_chan *c)
@@ -197,6 +253,12 @@ static void omap_dma_clear_csr(struct omap_chan *c)
 		omap_dma_chan_write(c, CSR, ~0);
 }
 
+static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
+	unsigned lch)
+{
+	c->channel_base = od->base + od->plat->channel_stride * lch;
+}
+
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
@@ -400,18 +462,26 @@ static void omap_dma_sched(unsigned long data)
 
 static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
 {
+	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
+	int ret;
+
+	dev_info(od->ddev.dev, "allocating channel for %u\n", c->dma_sig);
 
-	dev_info(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig);
+	ret = omap_request_dma(c->dma_sig, "DMA engine", omap_dma_callback,
+			       c, &c->dma_ch);
 
-	return omap_request_dma(c->dma_sig, "DMA engine",
-		omap_dma_callback, c, &c->dma_ch);
+	if (ret >= 0)
+		omap_dma_assign(od, c, c->dma_ch);
+
+	return ret;
 }
 
 static void omap_dma_free_chan_resources(struct dma_chan *chan)
 {
 	struct omap_chan *c = to_omap_dma_chan(chan);
 
+	c->channel_base = NULL;
 	vchan_free_chan_resources(&c->vc);
 	omap_free_dma(c->dma_ch);
 
@@ -901,7 +971,7 @@ static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
 	if (!c)
 		return -ENOMEM;
 
-	c->plat = od->plat;
+	c->reg_map = od->reg_map;
 	c->dma_sig = dma_sig;
 	c->vc.desc_free = omap_dma_desc_free;
 	vchan_init(&c->vc, &od->ddev);
@@ -928,16 +998,24 @@ static void omap_dma_free(struct omap_dmadev *od)
 static int omap_dma_probe(struct platform_device *pdev)
 {
 	struct omap_dmadev *od;
+	struct resource *res;
 	int rc, i;
 
 	od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 	if (!od)
 		return -ENOMEM;
 
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	od->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(od->base))
+		return PTR_ERR(od->base);
+
 	od->plat = omap_get_plat_info();
 	if (!od->plat)
 		return -EPROBE_DEFER;
 
+	od->reg_map = od->plat->reg_map;
+
 	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 	dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 	od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 7813636a193d..41a13e70f41f 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -285,6 +285,8 @@ struct omap_dma_reg {
 
 /* System DMA platform data structure */
 struct omap_system_dma_plat_info {
+	const struct omap_dma_reg *reg_map;
+	unsigned channel_stride;
 	struct omap_dma_dev_attr *dma_attr;
 	u32 errata;
 	void (*show_dma_caps)(void);
-- 
1.7.4.4

[PATCH RFC 25/26] dmaengine: omap-dma: move IRQ handling to omap-dma

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  121 +++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 115 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 611963e82623..f219c9a4dab7 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -30,6 +30,10 @@ struct omap_dmadev {
 	void __iomem *base;
 	const struct omap_dma_reg *reg_map;
 	struct omap_system_dma_plat_info *plat;
+	bool legacy;
+	spinlock_t irq_lock;
+	uint32_t irq_enable_mask;
+	struct omap_chan *lch_map[32];
 };
 
 struct omap_chan {
@@ -253,10 +257,22 @@ static void omap_dma_clear_csr(struct omap_chan *c)
 		omap_dma_chan_write(c, CSR, ~0);
 }
 
+static unsigned omap_dma_get_csr(struct omap_chan *c)
+{
+	unsigned val = omap_dma_chan_read(c, CSR);
+
+	if (!dma_omap1())
+		omap_dma_chan_write(c, CSR, val);
+
+	return val;
+}
+
 static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
 	unsigned lch)
 {
 	c->channel_base = od->base + od->plat->channel_stride * lch;
+
+	od->lch_map[lch] = c;
 }
 
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
@@ -460,32 +476,103 @@ static void omap_dma_sched(unsigned long data)
 	}
 }
 
+static irqreturn_t omap_dma_irq(int irq, void *devid)
+{
+	struct omap_dmadev *od = devid;
+	unsigned status, channel;
+
+	spin_lock(&od->irq_lock);
+
+	status = omap_dma_glbl_read(od, IRQSTATUS_L1);
+	status &= od->irq_enable_mask;
+	if (status == 0) {
+		spin_unlock(&od->irq_lock);
+		return IRQ_NONE;
+	}
+
+	while ((channel = ffs(status)) != 0) {
+		unsigned mask, csr;
+		struct omap_chan *c;
+
+		channel -= 1;
+		mask = BIT(channel);
+		status &= ~mask;
+
+		c = od->lch_map[channel];
+		if (c == NULL) {
+			/* This should never happen */
+			dev_err(od->ddev.dev, "invalid channel %u\n", channel);
+			continue;
+		}
+
+		csr = omap_dma_get_csr(c);
+		omap_dma_glbl_write(od, IRQSTATUS_L1, mask);
+
+		omap_dma_callback(channel, csr, c);
+	}
+
+	spin_unlock(&od->irq_lock);
+
+	return IRQ_HANDLED;
+}
+
 static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
 	int ret;
 
-	dev_info(od->ddev.dev, "allocating channel for %u\n", c->dma_sig);
+	if (od->legacy) {
+		ret = omap_request_dma(c->dma_sig, "DMA engine",
+				       omap_dma_callback, c, &c->dma_ch);
+	} else {
+		ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL,
+				       &c->dma_ch);
+	}
 
-	ret = omap_request_dma(c->dma_sig, "DMA engine", omap_dma_callback,
-			       c, &c->dma_ch);
+	dev_info(od->ddev.dev, "allocating channel %u for %u\n",
+		 c->dma_ch, c->dma_sig);
 
-	if (ret >= 0)
+	if (ret >= 0) {
 		omap_dma_assign(od, c, c->dma_ch);
 
+		if (!od->legacy) {
+			unsigned val;
+
+			spin_lock_irq(&od->irq_lock);
+			val = BIT(c->dma_ch);
+			omap_dma_glbl_write(od, IRQSTATUS_L1, val);
+			od->irq_enable_mask |= val;
+			omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
+
+			val = omap_dma_glbl_read(od, IRQENABLE_L0);
+			val &= ~BIT(c->dma_ch);
+			omap_dma_glbl_write(od, IRQENABLE_L0, val);
+			spin_unlock_irq(&od->irq_lock);
+		}
+	}
+
 	return ret;
 }
 
 static void omap_dma_free_chan_resources(struct dma_chan *chan)
 {
+	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
 
+	if (!od->legacy) {
+		spin_lock_irq(&od->irq_lock);
+		od->irq_enable_mask &= ~BIT(c->dma_ch);
+		omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
+		spin_unlock_irq(&od->irq_lock);
+	}
+
 	c->channel_base = NULL;
+	od->lch_map[c->dma_ch] = NULL;
 	vchan_free_chan_resources(&c->vc);
 	omap_free_dma(c->dma_ch);
 
-	dev_info(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig);
+	dev_info(od->ddev.dev, "freeing channel for %u\n", c->dma_sig);
 }
 
 static size_t omap_dma_sg_size(struct omap_sg *sg)
@@ -999,7 +1086,7 @@ static int omap_dma_probe(struct platform_device *pdev)
 {
 	struct omap_dmadev *od;
 	struct resource *res;
-	int rc, i;
+	int rc, i, irq;
 
 	od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 	if (!od)
@@ -1029,6 +1116,7 @@ static int omap_dma_probe(struct platform_device *pdev)
 	INIT_LIST_HEAD(&od->ddev.channels);
 	INIT_LIST_HEAD(&od->pending);
 	spin_lock_init(&od->lock);
+	spin_lock_init(&od->irq_lock);
 
 	tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
 
@@ -1040,6 +1128,21 @@ static int omap_dma_probe(struct platform_device *pdev)
 		}
 	}
 
+	irq = platform_get_irq(pdev, 1);
+	if (irq <= 0) {
+		dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq);
+		od->legacy = true;
+	} else {
+		/* Disable all interrupts */
+		od->irq_enable_mask = 0;
+		omap_dma_glbl_write(od, IRQENABLE_L1, 0);
+
+		rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq,
+				      IRQF_SHARED, "omap-dma-engine", od);
+		if (rc)
+			return rc;
+	}
+
 	rc = dma_async_device_register(&od->ddev);
 	if (rc) {
 		pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
@@ -1076,6 +1179,12 @@ static int omap_dma_remove(struct platform_device *pdev)
 		of_dma_controller_free(pdev->dev.of_node);
 
 	dma_async_device_unregister(&od->ddev);
+
+	if (!od->legacy) {
+		/* Disable all interrupts */
+		omap_dma_glbl_write(od, IRQENABLE_L0, 0);
+	}
+
 	omap_dma_free(od);
 
 	return 0;
-- 
1.7.4.4

[PATCH RFC 25/26] dmaengine: omap-dma: move IRQ handling to omap-dma

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/dma/omap-dma.c |  121 +++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 115 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 611963e82623..f219c9a4dab7 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -30,6 +30,10 @@ struct omap_dmadev {
 	void __iomem *base;
 	const struct omap_dma_reg *reg_map;
 	struct omap_system_dma_plat_info *plat;
+	bool legacy;
+	spinlock_t irq_lock;
+	uint32_t irq_enable_mask;
+	struct omap_chan *lch_map[32];
 };
 
 struct omap_chan {
@@ -253,10 +257,22 @@ static void omap_dma_clear_csr(struct omap_chan *c)
 		omap_dma_chan_write(c, CSR, ~0);
 }
 
+static unsigned omap_dma_get_csr(struct omap_chan *c)
+{
+	unsigned val = omap_dma_chan_read(c, CSR);
+
+	if (!dma_omap1())
+		omap_dma_chan_write(c, CSR, val);
+
+	return val;
+}
+
 static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
 	unsigned lch)
 {
 	c->channel_base = od->base + od->plat->channel_stride * lch;
+
+	od->lch_map[lch] = c;
 }
 
 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
@@ -460,32 +476,103 @@ static void omap_dma_sched(unsigned long data)
 	}
 }
 
+static irqreturn_t omap_dma_irq(int irq, void *devid)
+{
+	struct omap_dmadev *od = devid;
+	unsigned status, channel;
+
+	spin_lock(&od->irq_lock);
+
+	status = omap_dma_glbl_read(od, IRQSTATUS_L1);
+	status &= od->irq_enable_mask;
+	if (status == 0) {
+		spin_unlock(&od->irq_lock);
+		return IRQ_NONE;
+	}
+
+	while ((channel = ffs(status)) != 0) {
+		unsigned mask, csr;
+		struct omap_chan *c;
+
+		channel -= 1;
+		mask = BIT(channel);
+		status &= ~mask;
+
+		c = od->lch_map[channel];
+		if (c == NULL) {
+			/* This should never happen */
+			dev_err(od->ddev.dev, "invalid channel %u\n", channel);
+			continue;
+		}
+
+		csr = omap_dma_get_csr(c);
+		omap_dma_glbl_write(od, IRQSTATUS_L1, mask);
+
+		omap_dma_callback(channel, csr, c);
+	}
+
+	spin_unlock(&od->irq_lock);
+
+	return IRQ_HANDLED;
+}
+
 static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
 {
 	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
 	int ret;
 
-	dev_info(od->ddev.dev, "allocating channel for %u\n", c->dma_sig);
+	if (od->legacy) {
+		ret = omap_request_dma(c->dma_sig, "DMA engine",
+				       omap_dma_callback, c, &c->dma_ch);
+	} else {
+		ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL,
+				       &c->dma_ch);
+	}
 
-	ret = omap_request_dma(c->dma_sig, "DMA engine", omap_dma_callback,
-			       c, &c->dma_ch);
+	dev_info(od->ddev.dev, "allocating channel %u for %u\n",
+		 c->dma_ch, c->dma_sig);
 
-	if (ret >= 0)
+	if (ret >= 0) {
 		omap_dma_assign(od, c, c->dma_ch);
 
+		if (!od->legacy) {
+			unsigned val;
+
+			spin_lock_irq(&od->irq_lock);
+			val = BIT(c->dma_ch);
+			omap_dma_glbl_write(od, IRQSTATUS_L1, val);
+			od->irq_enable_mask |= val;
+			omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
+
+			val = omap_dma_glbl_read(od, IRQENABLE_L0);
+			val &= ~BIT(c->dma_ch);
+			omap_dma_glbl_write(od, IRQENABLE_L0, val);
+			spin_unlock_irq(&od->irq_lock);
+		}
+	}
+
 	return ret;
 }
 
 static void omap_dma_free_chan_resources(struct dma_chan *chan)
 {
+	struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 	struct omap_chan *c = to_omap_dma_chan(chan);
 
+	if (!od->legacy) {
+		spin_lock_irq(&od->irq_lock);
+		od->irq_enable_mask &= ~BIT(c->dma_ch);
+		omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
+		spin_unlock_irq(&od->irq_lock);
+	}
+
 	c->channel_base = NULL;
+	od->lch_map[c->dma_ch] = NULL;
 	vchan_free_chan_resources(&c->vc);
 	omap_free_dma(c->dma_ch);
 
-	dev_info(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig);
+	dev_info(od->ddev.dev, "freeing channel for %u\n", c->dma_sig);
 }
 
 static size_t omap_dma_sg_size(struct omap_sg *sg)
@@ -999,7 +1086,7 @@ static int omap_dma_probe(struct platform_device *pdev)
 {
 	struct omap_dmadev *od;
 	struct resource *res;
-	int rc, i;
+	int rc, i, irq;
 
 	od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 	if (!od)
@@ -1029,6 +1116,7 @@ static int omap_dma_probe(struct platform_device *pdev)
 	INIT_LIST_HEAD(&od->ddev.channels);
 	INIT_LIST_HEAD(&od->pending);
 	spin_lock_init(&od->lock);
+	spin_lock_init(&od->irq_lock);
 
 	tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
 
@@ -1040,6 +1128,21 @@ static int omap_dma_probe(struct platform_device *pdev)
 		}
 	}
 
+	irq = platform_get_irq(pdev, 1);
+	if (irq <= 0) {
+		dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq);
+		od->legacy = true;
+	} else {
+		/* Disable all interrupts */
+		od->irq_enable_mask = 0;
+		omap_dma_glbl_write(od, IRQENABLE_L1, 0);
+
+		rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq,
+				      IRQF_SHARED, "omap-dma-engine", od);
+		if (rc)
+			return rc;
+	}
+
 	rc = dma_async_device_register(&od->ddev);
 	if (rc) {
 		pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
@@ -1076,6 +1179,12 @@ static int omap_dma_remove(struct platform_device *pdev)
 		of_dma_controller_free(pdev->dev.of_node);
 
 	dma_async_device_unregister(&od->ddev);
+
+	if (!od->legacy) {
+		/* Disable all interrupts */
+		omap_dma_glbl_write(od, IRQENABLE_L0, 0);
+	}
+
 	omap_dma_free(od);
 
 	return 0;
-- 
1.7.4.4

[PATCH RFC 26/26] ARM: omap2: ensure dma platform device has resources

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap2/dma.c |   16 ++++++++++------
 1 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index e08e55a173b6..5689c88d986d 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -213,6 +213,12 @@ static struct omap_system_dma_plat_info dma_plat_info __initdata = {
 	.dma_read	= dma_read,
 };
 
+static struct platform_device_info omap_dma_dev_info = {
+	.name = "omap-dma-engine",
+	.id = -1,
+	.dma_mask = DMA_BIT_MASK(32),
+};
+
 /* One time initializations */
 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 {
@@ -233,11 +239,15 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 		return PTR_ERR(pdev);
 	}
 
+	omap_dma_dev_info.res = pdev->resource;
+	omap_dma_dev_info.num_res = pdev->num_resources;
+
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!mem) {
 		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
 		return -EINVAL;
 	}
+
 	dma_base = ioremap(mem->start, resource_size(mem));
 	if (!dma_base) {
 		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
@@ -258,12 +268,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 	return 0;
 }
 
-static const struct platform_device_info omap_dma_dev_info = {
-	.name = "omap-dma-engine",
-	.id = -1,
-	.dma_mask = DMA_BIT_MASK(32),
-};
-
 static int __init omap2_system_dma_init(void)
 {
 	struct platform_device *pdev;
-- 
1.7.4.4

[PATCH RFC 26/26] ARM: omap2: ensure dma platform device has resources

[Russell King]

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap2/dma.c |   16 ++++++++++------
 1 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index e08e55a173b6..5689c88d986d 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -213,6 +213,12 @@ static struct omap_system_dma_plat_info dma_plat_info __initdata = {
 	.dma_read	= dma_read,
 };
 
+static struct platform_device_info omap_dma_dev_info = {
+	.name = "omap-dma-engine",
+	.id = -1,
+	.dma_mask = DMA_BIT_MASK(32),
+};
+
 /* One time initializations */
 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 {
@@ -233,11 +239,15 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 		return PTR_ERR(pdev);
 	}
 
+	omap_dma_dev_info.res = pdev->resource;
+	omap_dma_dev_info.num_res = pdev->num_resources;
+
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!mem) {
 		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
 		return -EINVAL;
 	}
+
 	dma_base = ioremap(mem->start, resource_size(mem));
 	if (!dma_base) {
 		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
@@ -258,12 +268,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 	return 0;
 }
 
-static const struct platform_device_info omap_dma_dev_info = {
-	.name = "omap-dma-engine",
-	.id = -1,
-	.dma_mask = DMA_BIT_MASK(32),
-};
-
 static int __init omap2_system_dma_init(void)
 {
 	struct platform_device *pdev;
-- 
1.7.4.4

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140102 07:11]:
> The following patch series moves code to setup the DMA hardware and
> service interrupts from the hardware to the DMA engine driver.  This
> reduces the dependency on the legacy DMA implementation.
> 
> This series does not remove the channel allocation/freeing hooks which
> are used to manage the allocation of physical channels - this is the
> next step in the evolution.
> 
> The patches which move the interrupt handling are currently less than
> perfect since they're writing to ENABLE_L0 under a different spinlock,
> and hence RFC only at the moment.

Nice to see this happening. These seem to work for me based on a quick
try on omap2+, but on omap1 the build fails:

arch/arm/mach-omap1/dma.c: In function ‘dma_write’:
arch/arm/mach-omap1/dma.c:186: error: ‘const struct omap_dma_reg’ has no member named ‘size’

Regards,

Tony
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[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140102 07:11]:
> The following patch series moves code to setup the DMA hardware and
> service interrupts from the hardware to the DMA engine driver.  This
> reduces the dependency on the legacy DMA implementation.
> 
> This series does not remove the channel allocation/freeing hooks which
> are used to manage the allocation of physical channels - this is the
> next step in the evolution.
> 
> The patches which move the interrupt handling are currently less than
> perfect since they're writing to ENABLE_L0 under a different spinlock,
> and hence RFC only at the moment.

Nice to see this happening. These seem to work for me based on a quick
try on omap2+, but on omap1 the build fails:

arch/arm/mach-omap1/dma.c: In function ?dma_write?:
arch/arm/mach-omap1/dma.c:186: error: ?const struct omap_dma_reg? has no member named ?size?

Regards,

Tony

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Tue, Jan 07, 2014 at 05:21:11PM -0800, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [140102 07:11]:
> > The following patch series moves code to setup the DMA hardware and
> > service interrupts from the hardware to the DMA engine driver.  This
> > reduces the dependency on the legacy DMA implementation.
> > 
> > This series does not remove the channel allocation/freeing hooks which
> > are used to manage the allocation of physical channels - this is the
> > next step in the evolution.
> > 
> > The patches which move the interrupt handling are currently less than
> > perfect since they're writing to ENABLE_L0 under a different spinlock,
> > and hence RFC only at the moment.
> 
> Nice to see this happening. These seem to work for me based on a quick
> try on omap2+, but on omap1 the build fails:
> 
> arch/arm/mach-omap1/dma.c: In function ‘dma_write’:
> arch/arm/mach-omap1/dma.c:186: error: ‘const struct omap_dma_reg’ has no member named ‘size’

Right, needs this incremental patch:

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 3afde9628839..404f89e3eeb8 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -183,7 +183,7 @@ static inline void dma_write(u32 val, int reg, int lch)
 	addr += reg_map[reg].stride * lch;
 
 	__raw_writew(val, addr);
-	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
 		__raw_writew(val >> 16, addr + 2);
 }
 
@@ -196,7 +196,7 @@ static inline u32 dma_read(int reg, int lch)
 	addr += reg_map[reg].stride * lch;
 
 	val = __raw_readw(addr);
-	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
 		val |= __raw_readw(addr + 2) << 16;
 
 	return val;


-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Tue, Jan 07, 2014 at 05:21:11PM -0800, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [140102 07:11]:
> > The following patch series moves code to setup the DMA hardware and
> > service interrupts from the hardware to the DMA engine driver.  This
> > reduces the dependency on the legacy DMA implementation.
> > 
> > This series does not remove the channel allocation/freeing hooks which
> > are used to manage the allocation of physical channels - this is the
> > next step in the evolution.
> > 
> > The patches which move the interrupt handling are currently less than
> > perfect since they're writing to ENABLE_L0 under a different spinlock,
> > and hence RFC only at the moment.
> 
> Nice to see this happening. These seem to work for me based on a quick
> try on omap2+, but on omap1 the build fails:
> 
> arch/arm/mach-omap1/dma.c: In function ?dma_write?:
> arch/arm/mach-omap1/dma.c:186: error: ?const struct omap_dma_reg? has no member named ?size?

Right, needs this incremental patch:

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 3afde9628839..404f89e3eeb8 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -183,7 +183,7 @@ static inline void dma_write(u32 val, int reg, int lch)
 	addr += reg_map[reg].stride * lch;
 
 	__raw_writew(val, addr);
-	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
 		__raw_writew(val >> 16, addr + 2);
 }
 
@@ -196,7 +196,7 @@ static inline u32 dma_read(int reg, int lch)
 	addr += reg_map[reg].stride * lch;
 
 	val = __raw_readw(addr);
-	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
 		val |= __raw_readw(addr + 2) << 16;
 
 	return val;


-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Thu, Jan 09, 2014 at 03:24:37PM +0000, Russell King - ARM Linux wrote:
> On Tue, Jan 07, 2014 at 05:21:11PM -0800, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140102 07:11]:
> > > The following patch series moves code to setup the DMA hardware and
> > > service interrupts from the hardware to the DMA engine driver.  This
> > > reduces the dependency on the legacy DMA implementation.
> > > 
> > > This series does not remove the channel allocation/freeing hooks which
> > > are used to manage the allocation of physical channels - this is the
> > > next step in the evolution.
> > > 
> > > The patches which move the interrupt handling are currently less than
> > > perfect since they're writing to ENABLE_L0 under a different spinlock,
> > > and hence RFC only at the moment.
> > 
> > Nice to see this happening. These seem to work for me based on a quick
> > try on omap2+, but on omap1 the build fails:
> > 
> > arch/arm/mach-omap1/dma.c: In function ‘dma_write’:
> > arch/arm/mach-omap1/dma.c:186: error: ‘const struct omap_dma_reg’ has no member named ‘size’
> 
> Right, needs this incremental patch:
> 
> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> index 3afde9628839..404f89e3eeb8 100644
> --- a/arch/arm/mach-omap1/dma.c
> +++ b/arch/arm/mach-omap1/dma.c
> @@ -183,7 +183,7 @@ static inline void dma_write(u32 val, int reg, int lch)
>  	addr += reg_map[reg].stride * lch;
>  
>  	__raw_writew(val, addr);
> -	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> +	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
>  		__raw_writew(val >> 16, addr + 2);
>  }
>  
> @@ -196,7 +196,7 @@ static inline u32 dma_read(int reg, int lch)
>  	addr += reg_map[reg].stride * lch;
>  
>  	val = __raw_readw(addr);
> -	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> +	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
>  		val |= __raw_readw(addr + 2) << 16;
>  
>  	return val;
> 

Any news on this?

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Thu, Jan 09, 2014 at 03:24:37PM +0000, Russell King - ARM Linux wrote:
> On Tue, Jan 07, 2014 at 05:21:11PM -0800, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140102 07:11]:
> > > The following patch series moves code to setup the DMA hardware and
> > > service interrupts from the hardware to the DMA engine driver.  This
> > > reduces the dependency on the legacy DMA implementation.
> > > 
> > > This series does not remove the channel allocation/freeing hooks which
> > > are used to manage the allocation of physical channels - this is the
> > > next step in the evolution.
> > > 
> > > The patches which move the interrupt handling are currently less than
> > > perfect since they're writing to ENABLE_L0 under a different spinlock,
> > > and hence RFC only at the moment.
> > 
> > Nice to see this happening. These seem to work for me based on a quick
> > try on omap2+, but on omap1 the build fails:
> > 
> > arch/arm/mach-omap1/dma.c: In function ?dma_write?:
> > arch/arm/mach-omap1/dma.c:186: error: ?const struct omap_dma_reg? has no member named ?size?
> 
> Right, needs this incremental patch:
> 
> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> index 3afde9628839..404f89e3eeb8 100644
> --- a/arch/arm/mach-omap1/dma.c
> +++ b/arch/arm/mach-omap1/dma.c
> @@ -183,7 +183,7 @@ static inline void dma_write(u32 val, int reg, int lch)
>  	addr += reg_map[reg].stride * lch;
>  
>  	__raw_writew(val, addr);
> -	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> +	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
>  		__raw_writew(val >> 16, addr + 2);
>  }
>  
> @@ -196,7 +196,7 @@ static inline u32 dma_read(int reg, int lch)
>  	addr += reg_map[reg].stride * lch;
>  
>  	val = __raw_readw(addr);
> -	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> +	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
>  		val |= __raw_readw(addr + 2) << 16;
>  
>  	return val;
> 

Any news on this?

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> On Thu, Jan 09, 2014 at 03:24:37PM +0000, Russell King - ARM Linux wrote:
> > On Tue, Jan 07, 2014 at 05:21:11PM -0800, Tony Lindgren wrote:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140102 07:11]:
> > > > The following patch series moves code to setup the DMA hardware and
> > > > service interrupts from the hardware to the DMA engine driver.  This
> > > > reduces the dependency on the legacy DMA implementation.
> > > > 
> > > > This series does not remove the channel allocation/freeing hooks which
> > > > are used to manage the allocation of physical channels - this is the
> > > > next step in the evolution.
> > > > 
> > > > The patches which move the interrupt handling are currently less than
> > > > perfect since they're writing to ENABLE_L0 under a different spinlock,
> > > > and hence RFC only at the moment.
> > > 
> > > Nice to see this happening. These seem to work for me based on a quick
> > > try on omap2+, but on omap1 the build fails:
> > > 
> > > arch/arm/mach-omap1/dma.c: In function ‘dma_write’:
> > > arch/arm/mach-omap1/dma.c:186: error: ‘const struct omap_dma_reg’ has no member named ‘size’
> > 
> > Right, needs this incremental patch:
> > 
> > diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> > index 3afde9628839..404f89e3eeb8 100644
> > --- a/arch/arm/mach-omap1/dma.c
> > +++ b/arch/arm/mach-omap1/dma.c
> > @@ -183,7 +183,7 @@ static inline void dma_write(u32 val, int reg, int lch)
> >  	addr += reg_map[reg].stride * lch;
> >  
> >  	__raw_writew(val, addr);
> > -	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> > +	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
> >  		__raw_writew(val >> 16, addr + 2);
> >  }
> >  
> > @@ -196,7 +196,7 @@ static inline u32 dma_read(int reg, int lch)
> >  	addr += reg_map[reg].stride * lch;
> >  
> >  	val = __raw_readw(addr);
> > -	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> > +	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
> >  		val |= __raw_readw(addr + 2) << 16;
> >  
> >  	return val;
> > 
> 
> Any news on this?

Sorry for the delay, now getting this:

arch/arm/mach-omap1/dma.c: In function ‘omap1_system_dma_init’:
arch/arm/mach-omap1/dma.c:368: error: ‘struct omap_dma_dev_attr’ has no member named ‘chan’

Regards,

Tony
--
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[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> On Thu, Jan 09, 2014 at 03:24:37PM +0000, Russell King - ARM Linux wrote:
> > On Tue, Jan 07, 2014 at 05:21:11PM -0800, Tony Lindgren wrote:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140102 07:11]:
> > > > The following patch series moves code to setup the DMA hardware and
> > > > service interrupts from the hardware to the DMA engine driver.  This
> > > > reduces the dependency on the legacy DMA implementation.
> > > > 
> > > > This series does not remove the channel allocation/freeing hooks which
> > > > are used to manage the allocation of physical channels - this is the
> > > > next step in the evolution.
> > > > 
> > > > The patches which move the interrupt handling are currently less than
> > > > perfect since they're writing to ENABLE_L0 under a different spinlock,
> > > > and hence RFC only at the moment.
> > > 
> > > Nice to see this happening. These seem to work for me based on a quick
> > > try on omap2+, but on omap1 the build fails:
> > > 
> > > arch/arm/mach-omap1/dma.c: In function ?dma_write?:
> > > arch/arm/mach-omap1/dma.c:186: error: ?const struct omap_dma_reg? has no member named ?size?
> > 
> > Right, needs this incremental patch:
> > 
> > diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> > index 3afde9628839..404f89e3eeb8 100644
> > --- a/arch/arm/mach-omap1/dma.c
> > +++ b/arch/arm/mach-omap1/dma.c
> > @@ -183,7 +183,7 @@ static inline void dma_write(u32 val, int reg, int lch)
> >  	addr += reg_map[reg].stride * lch;
> >  
> >  	__raw_writew(val, addr);
> > -	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> > +	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
> >  		__raw_writew(val >> 16, addr + 2);
> >  }
> >  
> > @@ -196,7 +196,7 @@ static inline u32 dma_read(int reg, int lch)
> >  	addr += reg_map[reg].stride * lch;
> >  
> >  	val = __raw_readw(addr);
> > -	if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
> > +	if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
> >  		val |= __raw_readw(addr + 2) << 16;
> >  
> >  	return val;
> > 
> 
> Any news on this?

Sorry for the delay, now getting this:

arch/arm/mach-omap1/dma.c: In function ?omap1_system_dma_init?:
arch/arm/mach-omap1/dma.c:368: error: ?struct omap_dma_dev_attr? has no member named ?chan?

Regards,

Tony

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > Any news on this?
> 
> Sorry for the delay, now getting this:
> 
> arch/arm/mach-omap1/dma.c: In function ‘omap1_system_dma_init’:
> arch/arm/mach-omap1/dma.c:368: error: ‘struct omap_dma_dev_attr’ has no member named ‘chan’

Gah.  Next incremental patch:

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 404f89e3eeb8..1b1b64647def 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -344,14 +344,14 @@ static int __init omap1_system_dma_init(void)
 	if (ret) {
 		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
 			__func__, pdev->name, pdev->id);
-		goto exit_release_chan;
+		goto exit_release_d;
 	}
 
 	ret = platform_device_add(pdev);
 	if (ret) {
 		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
 			__func__, pdev->name, pdev->id);
-		goto exit_release_chan;
+		goto exit_release_d;
 	}
 
 	dma_pdev = platform_device_register_full(&omap_dma_dev_info);
@@ -364,8 +364,6 @@ static int __init omap1_system_dma_init(void)
 
 exit_release_pdev:
 	platform_device_del(pdev);
-exit_release_chan:
-	kfree(d->chan);
 exit_release_d:
 	kfree(d);
 exit_iounmap:


-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > Any news on this?
> 
> Sorry for the delay, now getting this:
> 
> arch/arm/mach-omap1/dma.c: In function ?omap1_system_dma_init?:
> arch/arm/mach-omap1/dma.c:368: error: ?struct omap_dma_dev_attr? has no member named ?chan?

Gah.  Next incremental patch:

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 404f89e3eeb8..1b1b64647def 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -344,14 +344,14 @@ static int __init omap1_system_dma_init(void)
 	if (ret) {
 		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
 			__func__, pdev->name, pdev->id);
-		goto exit_release_chan;
+		goto exit_release_d;
 	}
 
 	ret = platform_device_add(pdev);
 	if (ret) {
 		dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
 			__func__, pdev->name, pdev->id);
-		goto exit_release_chan;
+		goto exit_release_d;
 	}
 
 	dma_pdev = platform_device_register_full(&omap_dma_dev_info);
@@ -364,8 +364,6 @@ static int __init omap1_system_dma_init(void)
 
 exit_release_pdev:
 	platform_device_del(pdev);
-exit_release_chan:
-	kfree(d->chan);
 exit_release_d:
 	kfree(d);
 exit_iounmap:


-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > Any news on this?
> > 
> > Sorry for the delay, now getting this:
> > 
> > arch/arm/mach-omap1/dma.c: In function ‘omap1_system_dma_init’:
> > arch/arm/mach-omap1/dma.c:368: error: ‘struct omap_dma_dev_attr’ has no member named ‘chan’
> 
> Gah.  Next incremental patch:

Thanks, now getting this on omap1:

# dmesg | grep -i dma
DMA: preallocated 256 KiB pool for atomic coherent allocations
OMAP DMA hardware version 1
DMA capabilities: 0000000c:00000000:01ff:003f:007f
omap-dma-engine omap-dma-engine: invalid resource
omap-dma-engine: probe of omap-dma-engine failed with error -22
mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55

Regards,

Tony
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > Any news on this?
> > 
> > Sorry for the delay, now getting this:
> > 
> > arch/arm/mach-omap1/dma.c: In function ?omap1_system_dma_init?:
> > arch/arm/mach-omap1/dma.c:368: error: ?struct omap_dma_dev_attr? has no member named ?chan?
> 
> Gah.  Next incremental patch:

Thanks, now getting this on omap1:

# dmesg | grep -i dma
DMA: preallocated 256 KiB pool for atomic coherent allocations
OMAP DMA hardware version 1
DMA capabilities: 0000000c:00000000:01ff:003f:007f
omap-dma-engine omap-dma-engine: invalid resource
omap-dma-engine: probe of omap-dma-engine failed with error -22
mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55

Regards,

Tony

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 11:26:31AM -0800, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> > On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > > Any news on this?
> > > 
> > > Sorry for the delay, now getting this:
> > > 
> > > arch/arm/mach-omap1/dma.c: In function ‘omap1_system_dma_init’:
> > > arch/arm/mach-omap1/dma.c:368: error: ‘struct omap_dma_dev_attr’ has no member named ‘chan’
> > 
> > Gah.  Next incremental patch:
> 
> Thanks, now getting this on omap1:
> 
> # dmesg | grep -i dma
> DMA: preallocated 256 KiB pool for atomic coherent allocations
> OMAP DMA hardware version 1
> DMA capabilities: 0000000c:00000000:01ff:003f:007f
> omap-dma-engine omap-dma-engine: invalid resource
> omap-dma-engine: probe of omap-dma-engine failed with error -22
> mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
> mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55

Sigh... let's give it the iomem resource then:

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 1b1b64647def..4be601b638d7 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -261,6 +261,8 @@ static const struct platform_device_info omap_dma_dev_info = {
 	.name = "omap-dma-engine",
 	.id = -1,
 	.dma_mask = DMA_BIT_MASK(32),
+	.res = res,
+	.num_res = 1,
 };
 
 static struct omap_system_dma_plat_info dma_plat_info __initdata = {


-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 11:26:31AM -0800, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> > On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > > Any news on this?
> > > 
> > > Sorry for the delay, now getting this:
> > > 
> > > arch/arm/mach-omap1/dma.c: In function ?omap1_system_dma_init?:
> > > arch/arm/mach-omap1/dma.c:368: error: ?struct omap_dma_dev_attr? has no member named ?chan?
> > 
> > Gah.  Next incremental patch:
> 
> Thanks, now getting this on omap1:
> 
> # dmesg | grep -i dma
> DMA: preallocated 256 KiB pool for atomic coherent allocations
> OMAP DMA hardware version 1
> DMA capabilities: 0000000c:00000000:01ff:003f:007f
> omap-dma-engine omap-dma-engine: invalid resource
> omap-dma-engine: probe of omap-dma-engine failed with error -22
> mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
> mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55

Sigh... let's give it the iomem resource then:

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 1b1b64647def..4be601b638d7 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -261,6 +261,8 @@ static const struct platform_device_info omap_dma_dev_info = {
 	.name = "omap-dma-engine",
 	.id = -1,
 	.dma_mask = DMA_BIT_MASK(32),
+	.res = res,
+	.num_res = 1,
 };
 
 static struct omap_system_dma_plat_info dma_plat_info __initdata = {


-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 12:36]:
> On Mon, Jan 13, 2014 at 11:26:31AM -0800, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> > > On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > > > Any news on this?
> > > > 
> > > > Sorry for the delay, now getting this:
> > > > 
> > > > arch/arm/mach-omap1/dma.c: In function ‘omap1_system_dma_init’:
> > > > arch/arm/mach-omap1/dma.c:368: error: ‘struct omap_dma_dev_attr’ has no member named ‘chan’
> > > 
> > > Gah.  Next incremental patch:
> > 
> > Thanks, now getting this on omap1:
> > 
> > # dmesg | grep -i dma
> > DMA: preallocated 256 KiB pool for atomic coherent allocations
> > OMAP DMA hardware version 1
> > DMA capabilities: 0000000c:00000000:01ff:003f:007f
> > omap-dma-engine omap-dma-engine: invalid resource
> > omap-dma-engine: probe of omap-dma-engine failed with error -22
> > mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
> > mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55
> 
> Sigh... let's give it the iomem resource then:

OK, looks like adding that makes MMC card detection to fail with:

DMA timeout with device 55

Regards,

Tony
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[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 12:36]:
> On Mon, Jan 13, 2014 at 11:26:31AM -0800, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> > > On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > > > Any news on this?
> > > > 
> > > > Sorry for the delay, now getting this:
> > > > 
> > > > arch/arm/mach-omap1/dma.c: In function ?omap1_system_dma_init?:
> > > > arch/arm/mach-omap1/dma.c:368: error: ?struct omap_dma_dev_attr? has no member named ?chan?
> > > 
> > > Gah.  Next incremental patch:
> > 
> > Thanks, now getting this on omap1:
> > 
> > # dmesg | grep -i dma
> > DMA: preallocated 256 KiB pool for atomic coherent allocations
> > OMAP DMA hardware version 1
> > DMA capabilities: 0000000c:00000000:01ff:003f:007f
> > omap-dma-engine omap-dma-engine: invalid resource
> > omap-dma-engine: probe of omap-dma-engine failed with error -22
> > mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
> > mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55
> 
> Sigh... let's give it the iomem resource then:

OK, looks like adding that makes MMC card detection to fail with:

DMA timeout with device 55

Regards,

Tony

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 01:02:42PM -0800, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 12:36]:
> > On Mon, Jan 13, 2014 at 11:26:31AM -0800, Tony Lindgren wrote:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> > > > On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > > > > Any news on this?
> > > > > 
> > > > > Sorry for the delay, now getting this:
> > > > > 
> > > > > arch/arm/mach-omap1/dma.c: In function ‘omap1_system_dma_init’:
> > > > > arch/arm/mach-omap1/dma.c:368: error: ‘struct omap_dma_dev_attr’ has no member named ‘chan’
> > > > 
> > > > Gah.  Next incremental patch:
> > > 
> > > Thanks, now getting this on omap1:
> > > 
> > > # dmesg | grep -i dma
> > > DMA: preallocated 256 KiB pool for atomic coherent allocations
> > > OMAP DMA hardware version 1
> > > DMA capabilities: 0000000c:00000000:01ff:003f:007f
> > > omap-dma-engine omap-dma-engine: invalid resource
> > > omap-dma-engine: probe of omap-dma-engine failed with error -22
> > > mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
> > > mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55
> > 
> > Sigh... let's give it the iomem resource then:
> 
> OK, looks like adding that makes MMC card detection to fail with:
> 
> DMA timeout with device 55

You should also see a message:

oma-dma-engine omap-dma-engine: failed to get L1 IRQ: ..

which indicates that it's falling back to the old driver for IRQ
servicing.  Can you confirm that please?

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 01:02:42PM -0800, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 12:36]:
> > On Mon, Jan 13, 2014 at 11:26:31AM -0800, Tony Lindgren wrote:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> > > > On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > > > > Any news on this?
> > > > > 
> > > > > Sorry for the delay, now getting this:
> > > > > 
> > > > > arch/arm/mach-omap1/dma.c: In function ?omap1_system_dma_init?:
> > > > > arch/arm/mach-omap1/dma.c:368: error: ?struct omap_dma_dev_attr? has no member named ?chan?
> > > > 
> > > > Gah.  Next incremental patch:
> > > 
> > > Thanks, now getting this on omap1:
> > > 
> > > # dmesg | grep -i dma
> > > DMA: preallocated 256 KiB pool for atomic coherent allocations
> > > OMAP DMA hardware version 1
> > > DMA capabilities: 0000000c:00000000:01ff:003f:007f
> > > omap-dma-engine omap-dma-engine: invalid resource
> > > omap-dma-engine: probe of omap-dma-engine failed with error -22
> > > mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
> > > mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55
> > 
> > Sigh... let's give it the iomem resource then:
> 
> OK, looks like adding that makes MMC card detection to fail with:
> 
> DMA timeout with device 55

You should also see a message:

oma-dma-engine omap-dma-engine: failed to get L1 IRQ: ..

which indicates that it's falling back to the old driver for IRQ
servicing.  Can you confirm that please?

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 13:13]:
> On Mon, Jan 13, 2014 at 01:02:42PM -0800, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 12:36]:
> > > On Mon, Jan 13, 2014 at 11:26:31AM -0800, Tony Lindgren wrote:
> > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> > > > > On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > > > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > > > > > Any news on this?
> > > > > > 
> > > > > > Sorry for the delay, now getting this:
> > > > > > 
> > > > > > arch/arm/mach-omap1/dma.c: In function ‘omap1_system_dma_init’:
> > > > > > arch/arm/mach-omap1/dma.c:368: error: ‘struct omap_dma_dev_attr’ has no member named ‘chan’
> > > > > 
> > > > > Gah.  Next incremental patch:
> > > > 
> > > > Thanks, now getting this on omap1:
> > > > 
> > > > # dmesg | grep -i dma
> > > > DMA: preallocated 256 KiB pool for atomic coherent allocations
> > > > OMAP DMA hardware version 1
> > > > DMA capabilities: 0000000c:00000000:01ff:003f:007f
> > > > omap-dma-engine omap-dma-engine: invalid resource
> > > > omap-dma-engine: probe of omap-dma-engine failed with error -22
> > > > mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
> > > > mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55
> > > 
> > > Sigh... let's give it the iomem resource then:
> > 
> > OK, looks like adding that makes MMC card detection to fail with:
> > 
> > DMA timeout with device 55
> 
> You should also see a message:
> 
> oma-dma-engine omap-dma-engine: failed to get L1 IRQ: ..
> 
> which indicates that it's falling back to the old driver for IRQ
> servicing.  Can you confirm that please?

Yes that's correct, here are all the DMA related lines:

DMA: preallocated 256 KiB pool for atomic coherent allocations
OMAP DMA hardware version 1
DMA capabilities: 0000000c:00000000:01ff:003f:007f
omap-dma-engine omap-dma-engine: failed to get L1 IRQ: -6
omap-dma-engine omap-dma-engine: OMAP DMA engine driver
omap-dma-engine omap-dma-engine: allocating channel 0 for 54
omap-dma-engine omap-dma-engine: allocating channel 1 for 55
DMA timeout with device 55

Regards,

Tony
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 13:13]:
> On Mon, Jan 13, 2014 at 01:02:42PM -0800, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 12:36]:
> > > On Mon, Jan 13, 2014 at 11:26:31AM -0800, Tony Lindgren wrote:
> > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 10:57]:
> > > > > On Mon, Jan 13, 2014 at 09:37:45AM -0800, Tony Lindgren wrote:
> > > > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 08:48]:
> > > > > > > Any news on this?
> > > > > > 
> > > > > > Sorry for the delay, now getting this:
> > > > > > 
> > > > > > arch/arm/mach-omap1/dma.c: In function ?omap1_system_dma_init?:
> > > > > > arch/arm/mach-omap1/dma.c:368: error: ?struct omap_dma_dev_attr? has no member named ?chan?
> > > > > 
> > > > > Gah.  Next incremental patch:
> > > > 
> > > > Thanks, now getting this on omap1:
> > > > 
> > > > # dmesg | grep -i dma
> > > > DMA: preallocated 256 KiB pool for atomic coherent allocations
> > > > OMAP DMA hardware version 1
> > > > DMA capabilities: 0000000c:00000000:01ff:003f:007f
> > > > omap-dma-engine omap-dma-engine: invalid resource
> > > > omap-dma-engine: probe of omap-dma-engine failed with error -22
> > > > mmci-omap mmci-omap.1: unable to obtain TX DMA engine channel 54
> > > > mmci-omap mmci-omap.1: unable to obtain RX DMA engine channel 55
> > > 
> > > Sigh... let's give it the iomem resource then:
> > 
> > OK, looks like adding that makes MMC card detection to fail with:
> > 
> > DMA timeout with device 55
> 
> You should also see a message:
> 
> oma-dma-engine omap-dma-engine: failed to get L1 IRQ: ..
> 
> which indicates that it's falling back to the old driver for IRQ
> servicing.  Can you confirm that please?

Yes that's correct, here are all the DMA related lines:

DMA: preallocated 256 KiB pool for atomic coherent allocations
OMAP DMA hardware version 1
DMA capabilities: 0000000c:00000000:01ff:003f:007f
omap-dma-engine omap-dma-engine: failed to get L1 IRQ: -6
omap-dma-engine omap-dma-engine: OMAP DMA engine driver
omap-dma-engine omap-dma-engine: allocating channel 0 for 54
omap-dma-engine omap-dma-engine: allocating channel 1 for 55
DMA timeout with device 55

Regards,

Tony

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 01:21:18PM -0800, Tony Lindgren wrote:
> Yes that's correct, here are all the DMA related lines:
> 
> DMA: preallocated 256 KiB pool for atomic coherent allocations
> OMAP DMA hardware version 1
> DMA capabilities: 0000000c:00000000:01ff:003f:007f
> omap-dma-engine omap-dma-engine: failed to get L1 IRQ: -6
> omap-dma-engine omap-dma-engine: OMAP DMA engine driver
> omap-dma-engine omap-dma-engine: allocating channel 0 for 54
> omap-dma-engine omap-dma-engine: allocating channel 1 for 55
> DMA timeout with device 55

Hmm, that's annoying, and will be annoying to debug remotely.  Would
you like a new set of patches to try bisecting to find the culpret?

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Mon, Jan 13, 2014 at 01:21:18PM -0800, Tony Lindgren wrote:
> Yes that's correct, here are all the DMA related lines:
> 
> DMA: preallocated 256 KiB pool for atomic coherent allocations
> OMAP DMA hardware version 1
> DMA capabilities: 0000000c:00000000:01ff:003f:007f
> omap-dma-engine omap-dma-engine: failed to get L1 IRQ: -6
> omap-dma-engine omap-dma-engine: OMAP DMA engine driver
> omap-dma-engine omap-dma-engine: allocating channel 0 for 54
> omap-dma-engine omap-dma-engine: allocating channel 1 for 55
> DMA timeout with device 55

Hmm, that's annoying, and will be annoying to debug remotely.  Would
you like a new set of patches to try bisecting to find the culpret?

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 13:30]:
> On Mon, Jan 13, 2014 at 01:21:18PM -0800, Tony Lindgren wrote:
> > Yes that's correct, here are all the DMA related lines:
> > 
> > DMA: preallocated 256 KiB pool for atomic coherent allocations
> > OMAP DMA hardware version 1
> > DMA capabilities: 0000000c:00000000:01ff:003f:007f
> > omap-dma-engine omap-dma-engine: failed to get L1 IRQ: -6
> > omap-dma-engine omap-dma-engine: OMAP DMA engine driver
> > omap-dma-engine omap-dma-engine: allocating channel 0 for 54
> > omap-dma-engine omap-dma-engine: allocating channel 1 for 55
> > DMA timeout with device 55
> 
> Hmm, that's annoying, and will be annoying to debug remotely.  Would
> you like a new set of patches to try bisecting to find the culpret?

Sure that would help.

Regards,

Tony

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [140113 13:30]:
> On Mon, Jan 13, 2014 at 01:21:18PM -0800, Tony Lindgren wrote:
> > Yes that's correct, here are all the DMA related lines:
> > 
> > DMA: preallocated 256 KiB pool for atomic coherent allocations
> > OMAP DMA hardware version 1
> > DMA capabilities: 0000000c:00000000:01ff:003f:007f
> > omap-dma-engine omap-dma-engine: failed to get L1 IRQ: -6
> > omap-dma-engine omap-dma-engine: OMAP DMA engine driver
> > omap-dma-engine omap-dma-engine: allocating channel 0 for 54
> > omap-dma-engine omap-dma-engine: allocating channel 1 for 55
> > DMA timeout with device 55
> 
> Hmm, that's annoying, and will be annoying to debug remotely.  Would
> you like a new set of patches to try bisecting to find the culpret?

Sure that would help.

Regards,

Tony

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Vinod Koul]

On Thu, Jan 02, 2014 at 03:08:36PM +0000, Russell King - ARM Linux wrote:
> The following patch series moves code to setup the DMA hardware and
> service interrupts from the hardware to the DMA engine driver.  This
> reduces the dependency on the legacy DMA implementation.
Didnt the code getting removed from legacy, are there any users still of
the legacy driver in mainline?

--
~Vinod
> 
> This series does not remove the channel allocation/freeing hooks which
> are used to manage the allocation of physical channels - this is the
> next step in the evolution.
> 
> The patches which move the interrupt handling are currently less than
> perfect since they're writing to ENABLE_L0 under a different spinlock,
> and hence RFC only at the moment.
> 
>  arch/arm/mach-omap1/dma.c |  183 +++++--------
>  arch/arm/mach-omap2/dma.c |  183 ++++++--------
>  arch/arm/plat-omap/dma.c  |   17 +-
>  drivers/dma/omap-dma.c    |  653 ++++++++++++++++++++++++++++++++++++++++-----
>  include/linux/omap-dma.h  |   25 ++-
>  5 files changed, 774 insertions(+), 287 deletions(-)
> 
> -- 
> FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
> in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
> Estimate before purchase was "up to 13.2Mbit".

-- 

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Vinod Koul]

On Thu, Jan 02, 2014 at 03:08:36PM +0000, Russell King - ARM Linux wrote:
> The following patch series moves code to setup the DMA hardware and
> service interrupts from the hardware to the DMA engine driver.  This
> reduces the dependency on the legacy DMA implementation.
Didnt the code getting removed from legacy, are there any users still of
the legacy driver in mainline?

--
~Vinod
> 
> This series does not remove the channel allocation/freeing hooks which
> are used to manage the allocation of physical channels - this is the
> next step in the evolution.
> 
> The patches which move the interrupt handling are currently less than
> perfect since they're writing to ENABLE_L0 under a different spinlock,
> and hence RFC only at the moment.
> 
>  arch/arm/mach-omap1/dma.c |  183 +++++--------
>  arch/arm/mach-omap2/dma.c |  183 ++++++--------
>  arch/arm/plat-omap/dma.c  |   17 +-
>  drivers/dma/omap-dma.c    |  653 ++++++++++++++++++++++++++++++++++++++++-----
>  include/linux/omap-dma.h  |   25 ++-
>  5 files changed, 774 insertions(+), 287 deletions(-)
> 
> -- 
> FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
> in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
> Estimate before purchase was "up to 13.2Mbit".

-- 

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

The following patch series moves code to setup the DMA hardware and
service interrupts from the hardware to the DMA engine driver.  This
reduces the dependency on the legacy DMA implementation.

This series does not remove the channel allocation/freeing hooks which
are used to manage the allocation of physical channels - this is the
next step in the evolution.

The patches which move the interrupt handling are currently less than
perfect since they're writing to ENABLE_L0 under a different spinlock,
and hence RFC only at the moment.

 arch/arm/mach-omap1/dma.c |  183 +++++--------
 arch/arm/mach-omap2/dma.c |  183 ++++++--------
 arch/arm/plat-omap/dma.c  |   17 +-
 drivers/dma/omap-dma.c    |  653 ++++++++++++++++++++++++++++++++++++++++-----
 include/linux/omap-dma.h  |   25 ++-
 5 files changed, 774 insertions(+), 287 deletions(-)

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Sricharan R]

On Thursday 02 January 2014 08:36 PM, Russell King - ARM Linux wrote:
> The following patch series moves code to setup the DMA hardware and
> service interrupts from the hardware to the DMA engine driver.  This
> reduces the dependency on the legacy DMA implementation.
> 
> This series does not remove the channel allocation/freeing hooks which
> are used to manage the allocation of physical channels - this is the
> next step in the evolution.
> 
> The patches which move the interrupt handling are currently less than
> perfect since they're writing to ENABLE_L0 under a different spinlock,
> and hence RFC only at the moment.
> 
>  arch/arm/mach-omap1/dma.c |  183 +++++--------
>  arch/arm/mach-omap2/dma.c |  183 ++++++--------
>  arch/arm/plat-omap/dma.c  |   17 +-
>  drivers/dma/omap-dma.c    |  653 ++++++++++++++++++++++++++++++++++++++++-----
>  include/linux/omap-dma.h  |   25 ++-
>  5 files changed, 774 insertions(+), 287 deletions(-)
> 

I tested this series on DRA7 with mmc peripheral dma and it looked
fine. Some how dmaengine test cases were not fine. But that may not
have anything to do with this series. I will check more on that and
will come back with that results as well.

Regards,
 Sricharan

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Fri, Jan 10, 2014 at 05:46:20PM +0530, Sricharan R wrote:
> I tested this series on DRA7 with mmc peripheral dma and it looked
> fine. Some how dmaengine test cases were not fine. But that may not
> have anything to do with this series. I will check more on that and
> will come back with that results as well.

Not fine in what sense?

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Fri, Jan 10, 2014 at 05:46:20PM +0530, Sricharan R wrote:
> I tested this series on DRA7 with mmc peripheral dma and it looked
> fine. Some how dmaengine test cases were not fine. But that may not
> have anything to do with this series. I will check more on that and
> will come back with that results as well.

Not fine in what sense?

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Sricharan R]

On Monday 13 January 2014 07:47 PM, Russell King - ARM Linux wrote:
> On Fri, Jan 10, 2014 at 05:46:20PM +0530, Sricharan R wrote:
>> I tested this series on DRA7 with mmc peripheral dma and it looked
>> fine. Some how dmaengine test cases were not fine. But that may not
>> have anything to do with this series. I will check more on that and
>> will come back with that results as well.
> 
> Not fine in what sense?
> 
Sorry for delayed response.

So in the case of dmaengine test case, it looks for channels
with DMA_MEMCPY, DMA_XOR, DMA_PQ capabilities. But the omap-dma
 device is not registered with MEMCPY capabilities, hence the
testcase fails as no channels are available.

Regards,
 Sricharan

[PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Sricharan R]

On Monday 13 January 2014 07:47 PM, Russell King - ARM Linux wrote:
> On Fri, Jan 10, 2014 at 05:46:20PM +0530, Sricharan R wrote:
>> I tested this series on DRA7 with mmc peripheral dma and it looked
>> fine. Some how dmaengine test cases were not fine. But that may not
>> have anything to do with this series. I will check more on that and
>> will come back with that results as well.
> 
> Not fine in what sense?
> 
Sorry for delayed response.

So in the case of dmaengine test case, it looks for channels
with DMA_MEMCPY, DMA_XOR, DMA_PQ capabilities. But the omap-dma
 device is not registered with MEMCPY capabilities, hence the
testcase fails as no channels are available.

Regards,
 Sricharan