* [PATCH V3 0/8] PCI:Add SPEAr13xx PCie support
@ 2014-01-30 10:48 ` Mohit Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: arnd
Cc: Mohit Kumar, linux-arm-kernel, devicetree, linux-ide, linux-pci,
spear-devel, Tejun Heo
First three patches are improvement and fixes for SPEAr13xx support.
Next patch modify phy-core driver for its initialization during
subsys_initcall(). Platform ahci driver is modified for phy hooks.
Patch#6 and 7 modify/add support for SPEAr13xx SATA and PCIe.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall()
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
pcie designware driver improvements,fixes for IO translation bug, PCIe dw
driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.
PCIe driver support for SPEAr1310/40 platform board is added.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Mohit Kumar (2):
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
Pratyush Anand (6):
clk: SPEAr13xx: Fix pcie clock name
SPEAr13xx: Fix static mapping table
phy: Initialize phy core with subsys_initcall
ata: ahci platform: Add phy hooks to make it more generic
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
pcie: SPEAr13xx: Add designware pcie support
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ide@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: Tejun Heo <tj@kernel.org>
.../devicetree/bindings/ata/ahci-platform.txt | 2 +
.../devicetree/bindings/pci/spear13xx-pcie.txt | 7 +
.../devicetree/bindings/phy/spear13xx-miphy.txt | 8 +
MAINTAINERS | 6 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 87 ++++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 29 ++-
arch/arm/boot/dts/spear13xx.dtsi | 10 +-
arch/arm/configs/spear13xx_defconfig | 16 +
arch/arm/mach-spear/Kconfig | 3 +
arch/arm/mach-spear/include/mach/spear.h | 4 +-
arch/arm/mach-spear/spear1340.c | 127 +-----
arch/arm/mach-spear/spear13xx.c | 2 +-
drivers/ata/ahci.h | 2 +
drivers/ata/ahci_platform.c | 20 +
drivers/clk/spear/spear1310_clock.c | 6 +-
drivers/clk/spear/spear1340_clock.c | 2 +-
drivers/pci/host/Kconfig | 5 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 407 +++++++++++++++++
drivers/phy/Kconfig | 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-core.c | 2 +-
drivers/phy/phy-spear13xx-sata-pcie.c | 481 ++++++++++++++++++++
25 files changed, 1102 insertions(+), 140 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
create mode 100644 drivers/pci/host/pcie-spear13xx.c
create mode 100644 drivers/phy/phy-spear13xx-sata-pcie.c
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V3 0/8] PCI:Add SPEAr13xx PCie support
@ 2014-01-30 10:48 ` Mohit Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: arnd
Cc: Mohit Kumar, linux-arm-kernel, devicetree, linux-ide, linux-pci,
spear-devel, Tejun Heo
First three patches are improvement and fixes for SPEAr13xx support.
Next patch modify phy-core driver for its initialization during
subsys_initcall(). Platform ahci driver is modified for phy hooks.
Patch#6 and 7 modify/add support for SPEAr13xx SATA and PCIe.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall()
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
pcie designware driver improvements,fixes for IO translation bug, PCIe dw
driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.
PCIe driver support for SPEAr1310/40 platform board is added.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Mohit Kumar (2):
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
Pratyush Anand (6):
clk: SPEAr13xx: Fix pcie clock name
SPEAr13xx: Fix static mapping table
phy: Initialize phy core with subsys_initcall
ata: ahci platform: Add phy hooks to make it more generic
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
pcie: SPEAr13xx: Add designware pcie support
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ide@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: Tejun Heo <tj@kernel.org>
.../devicetree/bindings/ata/ahci-platform.txt | 2 +
.../devicetree/bindings/pci/spear13xx-pcie.txt | 7 +
.../devicetree/bindings/phy/spear13xx-miphy.txt | 8 +
MAINTAINERS | 6 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 87 ++++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 29 ++-
arch/arm/boot/dts/spear13xx.dtsi | 10 +-
arch/arm/configs/spear13xx_defconfig | 16 +
arch/arm/mach-spear/Kconfig | 3 +
arch/arm/mach-spear/include/mach/spear.h | 4 +-
arch/arm/mach-spear/spear1340.c | 127 +-----
arch/arm/mach-spear/spear13xx.c | 2 +-
drivers/ata/ahci.h | 2 +
drivers/ata/ahci_platform.c | 20 +
drivers/clk/spear/spear1310_clock.c | 6 +-
drivers/clk/spear/spear1340_clock.c | 2 +-
drivers/pci/host/Kconfig | 5 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 407 +++++++++++++++++
drivers/phy/Kconfig | 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-core.c | 2 +-
drivers/phy/phy-spear13xx-sata-pcie.c | 481 ++++++++++++++++++++
25 files changed, 1102 insertions(+), 140 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
create mode 100644 drivers/pci/host/pcie-spear13xx.c
create mode 100644 drivers/phy/phy-spear13xx-sata-pcie.c
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V3 0/8] PCI:Add SPEAr13xx PCie support
@ 2014-01-30 10:48 ` Mohit Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: linux-arm-kernel
First three patches are improvement and fixes for SPEAr13xx support.
Next patch modify phy-core driver for its initialization during
subsys_initcall(). Platform ahci driver is modified for phy hooks.
Patch#6 and 7 modify/add support for SPEAr13xx SATA and PCIe.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall()
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
pcie designware driver improvements,fixes for IO translation bug, PCIe dw
driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.
PCIe driver support for SPEAr1310/40 platform board is added.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Mohit Kumar (2):
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
Pratyush Anand (6):
clk: SPEAr13xx: Fix pcie clock name
SPEAr13xx: Fix static mapping table
phy: Initialize phy core with subsys_initcall
ata: ahci platform: Add phy hooks to make it more generic
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
pcie: SPEAr13xx: Add designware pcie support
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-ide at vger.kernel.org
Cc: linux-pci at vger.kernel.org
Cc: spear-devel at list.st.com
Cc: Tejun Heo <tj@kernel.org>
.../devicetree/bindings/ata/ahci-platform.txt | 2 +
.../devicetree/bindings/pci/spear13xx-pcie.txt | 7 +
.../devicetree/bindings/phy/spear13xx-miphy.txt | 8 +
MAINTAINERS | 6 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 87 ++++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 29 ++-
arch/arm/boot/dts/spear13xx.dtsi | 10 +-
arch/arm/configs/spear13xx_defconfig | 16 +
arch/arm/mach-spear/Kconfig | 3 +
arch/arm/mach-spear/include/mach/spear.h | 4 +-
arch/arm/mach-spear/spear1340.c | 127 +-----
arch/arm/mach-spear/spear13xx.c | 2 +-
drivers/ata/ahci.h | 2 +
drivers/ata/ahci_platform.c | 20 +
drivers/clk/spear/spear1310_clock.c | 6 +-
drivers/clk/spear/spear1340_clock.c | 2 +-
drivers/pci/host/Kconfig | 5 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 407 +++++++++++++++++
drivers/phy/Kconfig | 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-core.c | 2 +-
drivers/phy/phy-spear13xx-sata-pcie.c | 481 ++++++++++++++++++++
25 files changed, 1102 insertions(+), 140 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
create mode 100644 drivers/pci/host/pcie-spear13xx.c
create mode 100644 drivers/phy/phy-spear13xx-sata-pcie.c
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V3 1/8] clk: SPEAr13xx: Fix pcie clock name
2014-01-30 10:48 ` Mohit Kumar
(?)
(?)
@ 2014-01-30 10:48 ` Mohit Kumar
-1 siblings, 0 replies; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
Follow dt clock naming convention for PCIe clocks.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
drivers/clk/spear/spear1310_clock.c | 6 +++---
drivers/clk/spear/spear1340_clock.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7..4daa597 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.0");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.1");
+ clk_register_clkdev(clk, NULL, "b1800000.pcie");
clk_register_clkdev(clk, NULL, "b1800000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.2");
+ clk_register_clkdev(clk, NULL, "b4000000.pcie");
clk_register_clkdev(clk, NULL, "b4000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index fe835c1..5a5c664 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
--
1.7.0.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH V3 2/8] SPEAr13xx: Fix static mapping table
2014-01-30 10:48 ` Mohit Kumar
` (2 preceding siblings ...)
(?)
@ 2014-01-30 10:48 ` Mohit Kumar
-1 siblings, 0 replies; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr13xx was using virtual address space 0xFE000000 to map physical address
space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So
change 0xFE000000 to 0xF9000000.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: stable at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm/mach-spear/include/mach/spear.h | 4 ++--
arch/arm/mach-spear/spear13xx.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 5cdc53d..f2d6a01 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -52,10 +52,10 @@
#ifdef CONFIG_ARCH_SPEAR13XX
#define PERIP_GRP2_BASE UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000)
+#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)
#define MCIF_SDHCI_BASE UL(0xB3000000)
#define SYSRAM0_BASE UL(0xB3800000)
-#define VA_SYSRAM0_BASE IOMEM(0xFE800000)
+#define VA_SYSRAM0_BASE IOMEM(0xF9800000)
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
#define PERIP_GRP1_BASE UL(0xE0000000)
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 7aa6e8c..89212ff 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)
/*
* Following will create 16MB static virtual/physical mappings
* PHYSICAL VIRTUAL
- * 0xB3000000 0xFE000000
+ * 0xB3000000 0xF9000000
* 0xE0000000 0xFD000000
* 0xEC000000 0xFC000000
* 0xED000000 0xFB000000
--
1.7.0.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH V3 3/8] SPEAr13xx: defconfig: Update
2014-01-30 10:48 ` Mohit Kumar
` (3 preceding siblings ...)
(?)
@ 2014-01-30 10:48 ` Mohit Kumar
2014-01-30 13:02 ` Arnd Bergmann
-1 siblings, 1 reply; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: linux-arm-kernel
Enable EABI, OEABI, VFP and NFS configs in default configuration file for
SPEAr13xx.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm/configs/spear13xx_defconfig | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 82eaa55..0cf87d0 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -14,10 +14,19 @@ CONFIG_MACH_SPEAR1340=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
@@ -27,6 +36,7 @@ CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
# CONFIG_SATA_PMP is not set
CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +76,7 @@ CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +90,14 @@ CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
--
1.7.0.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall
2014-01-30 10:48 ` Mohit Kumar
` (4 preceding siblings ...)
(?)
@ 2014-01-30 10:48 ` Mohit Kumar
2014-01-30 11:43 ` Kishon Vijay Abraham I
-1 siblings, 1 reply; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: arnd
Cc: Pratyush Anand, Mohit Kumar, Kishon Vijay Abraham I, spear-devel,
linux-kernel
From: Pratyush Anand <pratyush.anand@st.com>
PCIe RC drivers are initialized with subsys_initcall. Few PCIe drivers
like SPEAr13xx needs phy drivers to be initialized.
Therefore initialize phy core driver with subsys_initcall to avoid
calling of phy_get before phy_class is created.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: spear-devel@list.st.com
Cc: linux-kernel@vger.kernel.org
---
drivers/phy/phy-core.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 03cf8fb..fa73101 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -685,7 +685,7 @@ static int __init phy_core_init(void)
return 0;
}
-module_init(phy_core_init);
+subsys_initcall(phy_core_init);
static void __exit phy_core_exit(void)
{
--
1.7.0.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH V3 5/8] ata: ahci platform: Add phy hooks to make it more generic
2014-01-30 10:48 ` Mohit Kumar
` (5 preceding siblings ...)
(?)
@ 2014-01-30 10:48 ` Mohit Kumar
2014-01-30 13:06 ` Arnd Bergmann
-1 siblings, 1 reply; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: arnd; +Cc: Pratyush Anand, Mohit Kumar, Tejun Heo, spear-devel, linux-ide
From: Pratyush Anand <pratyush.anand@st.com>
Few platform does only phy specific work in platform callbacks. It is
better to use standard phy callbacks for such platform in stead of
platform callbacks.
This patch does not break any platform callbacks. It adds phy plugins
on top of that.
It has been assumed that no platform will need both phy plugins as well
as platform callbacks.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: spear-devel@list.st.com
Cc: linux-ide@vger.kernel.org
---
.../devicetree/bindings/ata/ahci-platform.txt | 2 ++
drivers/ata/ahci.h | 2 ++
drivers/ata/ahci_platform.c | 20 ++++++++++++++++++++
3 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 89de156..73dff5a 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -10,6 +10,8 @@ Required properties:
Optional properties:
- dma-coherent : Present if dma operations are coherent
+- phys : phandle to phy node associated with ahci controller
+- phy-names : must be "ahci-phy"
Example:
sata@ffe08000 {
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 2289efd..77d1412 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -37,6 +37,7 @@
#include <linux/clk.h>
#include <linux/libata.h>
+#include <linux/phy/phy.h>
/* Enclosure Management Control */
#define EM_CTRL_MSG_TYPE 0x000f0000
@@ -322,6 +323,7 @@ struct ahci_host_priv {
u32 em_buf_sz; /* EM buffer size in byte */
u32 em_msg_type; /* EM message type */
struct clk *clk; /* Only for platforms supporting clk */
+ struct phy *phy; /* associated phy struct */
void *plat_data; /* Other platform data */
};
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index f955431..4253c03 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -123,6 +123,12 @@ static int ahci_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ /*
+ * all ahci platform may not have phy node. So no need to
+ * check return value of devm_phy_get.
+ */
+ hpriv->phy = devm_phy_get(dev, "ahci-phy");
+
hpriv->flags |= (unsigned long)pi.private_data;
hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
@@ -152,6 +158,10 @@ static int ahci_probe(struct platform_device *pdev)
rc = pdata->init(dev, hpriv->mmio);
if (rc)
goto disable_unprepare_clk;
+ } else if (hpriv->phy && hpriv->phy->ops->init) {
+ rc = hpriv->phy->ops->init(hpriv->phy);
+ if (rc)
+ goto disable_unprepare_clk;
}
ahci_save_initial_config(dev, hpriv,
@@ -221,6 +231,8 @@ static int ahci_probe(struct platform_device *pdev)
pdata_exit:
if (pdata && pdata->exit)
pdata->exit(dev);
+ else if (hpriv->phy && hpriv->phy->ops->exit)
+ hpriv->phy->ops->exit(hpriv->phy);
disable_unprepare_clk:
if (!IS_ERR(hpriv->clk))
clk_disable_unprepare(hpriv->clk);
@@ -238,6 +250,8 @@ static void ahci_host_stop(struct ata_host *host)
if (pdata && pdata->exit)
pdata->exit(dev);
+ else if (hpriv->phy && hpriv->phy->ops->exit)
+ hpriv->phy->ops->exit(hpriv->phy);
if (!IS_ERR(hpriv->clk)) {
clk_disable_unprepare(hpriv->clk);
@@ -276,6 +290,8 @@ static int ahci_suspend(struct device *dev)
if (pdata && pdata->suspend)
return pdata->suspend(dev);
+ else if (hpriv->phy && hpriv->phy->ops->power_off)
+ return hpriv->phy->ops->power_off(hpriv->phy);
if (!IS_ERR(hpriv->clk))
clk_disable_unprepare(hpriv->clk);
@@ -302,6 +318,10 @@ static int ahci_resume(struct device *dev)
rc = pdata->resume(dev);
if (rc)
goto disable_unprepare_clk;
+ } else if (hpriv->phy && hpriv->phy->ops->power_on) {
+ rc = hpriv->phy->ops->power_on(hpriv->phy);
+ if (rc)
+ goto disable_unprepare_clk;
}
if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
--
1.7.0.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH V3 6/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
2014-01-30 10:48 ` Mohit Kumar
@ 2014-01-30 10:48 ` Mohit Kumar
-1 siblings, 0 replies; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: arnd-r2nGTMty4D4
Cc: Pratyush Anand, Viresh Kumar, Tejun Heo, Kishon Vijay Abraham I,
spear-devel-nkJGhpqTU55BDgjK7y7TUQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-ide-u79uwXL29TY76Z2rM5mHXA
From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
ahci driver needs some platform specific functions which are called at
init, exit, suspend and resume conditions. Till now these functions were
present in a platform driver with a fixme notes.
Similar functions modifying same set of registers will also be needed in
case of PCIe phy init/exit.
So move all these SATA platform code to a proper phy driver.
Same phy driver will be used to add PCIe init/exit routine.
Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Tested-by: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Tejun Heo <tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
.../devicetree/bindings/phy/spear13xx-miphy.txt | 8 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 36 +++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 12 +-
arch/arm/boot/dts/spear13xx.dtsi | 5 +
arch/arm/mach-spear/Kconfig | 2 +
arch/arm/mach-spear/spear1340.c | 127 +--------
drivers/phy/Kconfig | 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-spear13xx-sata-pcie.c | 305 ++++++++++++++++++++
11 files changed, 380 insertions(+), 130 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
create mode 100644 drivers/phy/phy-spear13xx-sata-pcie.c
diff --git a/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
new file mode 100644
index 0000000..208b37d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
@@ -0,0 +1,8 @@
+Required properties:
+- compatible : should be "st,spear1340-sata-pcie-phy".
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- #phy-cells : from the generic PHY bindings, must be 2.
+ - 1st arg: phandle to the phy node.
+ - 2nd arg: 0 if phy (in 1st arg) is to be used for sata else 1.
+ - 3rd arg: Instance id of the phy (in 1st arg).
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
status = "okay";
};
+ miphy@eb800000 {
+ status = "okay";
+ };
+
cf@b2800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..0d62418 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,54 @@
#gpio-cells = <2>;
};
- ahci@b1000000 {
+ miphy0: miphy@eb800000 {
+ compatible = "st,spear1340-sata-pcie-phy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <2>;
+ status = "disabled";
+ };
+
+ miphy1: miphy@eb804000 {
+ compatible = "st,spear1340-sata-pcie-phy";
+ reg = <0xeb804000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <2>;
+ status = "disabled";
+ };
+
+ miphy2: miphy@eb808000 {
+ compatible = "st,spear1340-sata-pcie-phy";
+ reg = <0xeb808000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <2>;
+ status = "disabled";
+ };
+
+ ahci0: ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
+ phys = <&miphy0 0 0>;
+ phy-names = "ahci-phy";
status = "disabled";
};
- ahci@b1800000 {
+ ahci1: ahci@b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
+ phys = <&miphy1 0 1>;
+ phy-names = "ahci-phy";
status = "disabled";
};
- ahci@b4000000 {
+ ahci2: ahci@b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
+ phys = <&miphy2 0 2>;
+ phy-names = "ahci-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
status = "okay";
};
+ miphy@eb800000 {
+ status = "okay";
+ };
+
dma@ea800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..c6b0e34 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,20 @@
status = "disabled";
};
- ahci@b1000000 {
+ miphy0: miphy@eb800000 {
+ compatible = "st,spear1340-sata-pcie-phy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <2>;
+ status = "disabled";
+ };
+
+ ahci0: ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
+ phys = <&miphy0 0 0>;
+ phy-names = "ahci-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
+ misc: syscon@e0700000 {
+ compatible = "st,spear1340-misc", "syscon";
+ reg = <0xe0700000 0x1000>;
+ };
+
gpio0: gpio@e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e..44d8543 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select USE_OF
+ select MFD_SYSCON
+ select PHY_SPEAR13XX_SATA_PCIE
help
Supports for ARM's SPEAR13XX family
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..8e27093 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -11,138 +11,13 @@
* warranty of any kind, whether express or implied.
*/
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
- /* PCIE CFG MASks */
- #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
- #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
- #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
- #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
- #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
- #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
- #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
- #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
- #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
- #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
- #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
- #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
- SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
- SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
- SPEAR1340_PCIE_CFG_POWERUP_RESET | \
- SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
- #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
- SPEAR1340_SATA_CFG_PM_CLK_EN | \
- SPEAR1340_SATA_CFG_POWERUP_RESET | \
- SPEAR1340_SATA_CFG_RX_CLK_EN | \
- SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
- #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
- #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
- #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_CLK_REF_DIV2 | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
- (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
- writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
- writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
- SPEAR1340_PCIE_MIPHY_CFG);
- /* Switch on sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
- /* Disable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
-
- return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
- writel(0, SPEAR1340_PCIE_SATA_CFG);
- writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
- /* Enable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
- /* Switch off sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_FREEZE)
- return 0;
-
- sata_miphy_exit(dev);
-
- return 0;
-}
-
-int sata_resume(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_THAW)
- return 0;
-
- return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
- .init = sata_miphy_init,
- .exit = sata_miphy_exit,
- .suspend = sata_suspend,
- .resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
- &sata_pdata),
- {}
-};
static void __init spear1340_dt_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- spear1340_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const spear1340_dt_board_compat[] = {
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a344f3d..ae34fb8 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -51,4 +51,10 @@ config PHY_EXYNOS_DP_VIDEO
help
Support for Display Port PHY found on Samsung EXYNOS SoCs.
+config PHY_SPEAR13XX_SATA_PCIE
+ tristate "SPEAr13xx SoC SATA PCIe PHY driver"
+ help
+ Support for SATA and PCIe PHY for SPEAr13xx SoC
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9..8941283 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_PHY_SPEAR13XX_SATA_PCIE) += phy-spear13xx-sata-pcie.o
diff --git a/drivers/phy/phy-spear13xx-sata-pcie.c b/drivers/phy/phy-spear13xx-sata-pcie.c
new file mode 100644
index 0000000..6adfa64
--- /dev/null
+++ b/drivers/phy/phy-spear13xx-sata-pcie.c
@@ -0,0 +1,305 @@
+/*
+ * ST SPEAr13xx SATA PCIe PHY driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG 0x100
+ #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
+#define SPEAR1340_PCM_WKUP_CFG 0x104
+#define SPEAR1340_SWITCH_CTR 0x108
+
+#define SPEAR1340_PERIP1_SW_RST 0x318
+ #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
+#define SPEAR1340_PERIP2_SW_RST 0x31C
+#define SPEAR1340_PERIP3_SW_RST 0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG 0x424
+ /* PCIE CFG MASks */
+ #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
+ #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
+ #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
+ #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
+ #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
+ #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
+ #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
+ #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
+ #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
+ #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
+ #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
+ #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
+ SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+ SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+ SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+ SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+ #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
+ SPEAR1340_SATA_CFG_PM_CLK_EN | \
+ SPEAR1340_SATA_CFG_POWERUP_RESET | \
+ SPEAR1340_SATA_CFG_RX_CLK_EN | \
+ SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG 0x428
+ #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
+ #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
+enum phy_mode {
+ SATA,
+ PCIE
+};
+
+struct spear13xx_phy_priv {
+ /* regmap for SPEAr13xx misc registers */
+ struct regmap *misc;
+ /* phy struct pointer */
+ struct phy *phy;
+ /* phy mode: 0 for SATA and 1 for PCIe */
+ enum phy_mode mode;
+ /* instance id of this phy */
+ u32 id;
+};
+
+static int spear1340_sata_miphy_init(struct spear13xx_phy_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+ /* Switch on sata power domain */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN);
+ msleep(20);
+ /* Disable PCIE SATA Controller reset */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RST_SATA, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int spear1340_sata_miphy_exit(struct spear13xx_phy_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+ /* Enable PCIE SATA Controller reset */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RST_SATA,
+ SPEAR1340_PERIP1_SW_RST_SATA);
+ msleep(20);
+ /* Switch off sata power domain */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int sata_miphy_init(struct spear13xx_phy_priv *phypriv)
+{
+ if (of_machine_is_compatible("st,spear1340"))
+ return spear1340_sata_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_exit(struct spear13xx_phy_priv *phypriv)
+{
+ if (of_machine_is_compatible("st,spear1340"))
+ return spear1340_sata_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_suspend(struct spear13xx_phy_priv *phypriv)
+{
+ return sata_miphy_exit(phypriv);
+}
+
+static int sata_miphy_resume(struct spear13xx_phy_priv *phypriv)
+{
+ return sata_miphy_init(phypriv);
+}
+
+static int miphy_init(struct phy *phy)
+{
+ struct spear13xx_phy_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_init(phypriv);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int miphy_exit(struct phy *phy)
+{
+ struct spear13xx_phy_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_exit(phypriv);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int miphy_power_off(struct phy *phy)
+{
+ struct spear13xx_phy_priv *phypriv = phy_get_drvdata(phy);
+ struct device *dev = &phy->dev;
+
+ if (dev->power.power_state.event == PM_EVENT_FREEZE)
+ return 0;
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_suspend(phypriv);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int miphy_power_on(struct phy *phy)
+{
+ struct spear13xx_phy_priv *phypriv = phy_get_drvdata(phy);
+ struct device *dev = &phy->dev;
+
+ if (dev->power.power_state.event == PM_EVENT_THAW)
+ return 0;
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_resume(phypriv);
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct of_device_id spear13xx_phy_of_match[] = {
+ { .compatible = "st,spear1340-sata-pcie-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, spear13xx_phy_of_match);
+
+static struct phy_ops spear13xx_sata_pcie_phy_ops = {
+ .init = miphy_init,
+ .exit = miphy_exit,
+ .power_off = miphy_power_off,
+ .power_on = miphy_power_on,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *spear13xx_sata_pcie_phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct spear13xx_phy_priv *phypriv = dev_get_drvdata(dev);
+
+ if (args->args_count < 2) {
+ dev_err(dev, "DT did not pass correct no of args\n");
+ return NULL;
+ }
+
+ phypriv->mode = args->args[0];
+ phypriv->id = args->args[1];
+
+ return phypriv->phy;
+}
+
+static int __init spear13xx_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct spear13xx_phy_priv *phypriv;
+ struct phy_provider *phy_provider;
+
+ phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
+ if (!phypriv) {
+ dev_err(dev, "can't alloc sata pcie private date memory\n");
+ return -ENOMEM;
+ }
+
+ phypriv->misc =
+ syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+ if (IS_ERR(phypriv->misc)) {
+ dev_err(dev, "failed to find SPEAr13xx misc regmap\n");
+ return PTR_ERR(phypriv->misc);
+ }
+
+ phy_provider = devm_of_phy_provider_register(dev,
+ spear13xx_sata_pcie_phy_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ phypriv->phy = devm_phy_create(dev, &spear13xx_sata_pcie_phy_ops, NULL);
+ if (IS_ERR(phypriv->phy)) {
+ dev_err(dev, "failed to create SATA PCIe PHY\n");
+ return PTR_ERR(phypriv->phy);
+ }
+
+ dev_set_drvdata(dev, phypriv);
+ phy_set_drvdata(phypriv->phy, phypriv);
+
+ return 0;
+}
+
+static int __exit spear13xx_phy_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver spear13xx_phy_driver = {
+ .remove = __exit_p(spear13xx_phy_remove),
+ .driver = {
+ .name = "spear13xx-sata_pcie-phy",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(spear13xx_phy_of_match),
+ },
+};
+
+static int __init spear13xx_phy_init(void)
+{
+
+ return platform_driver_probe(&spear13xx_phy_driver,
+ spear13xx_phy_probe);
+}
+subsys_initcall(spear13xx_phy_init);
+
+MODULE_DESCRIPTION("ST SPEAr13xx SATA PCIe PHY driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
--
1.7.0.1
--
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH V3 6/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-01-30 10:48 ` Mohit Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
ahci driver needs some platform specific functions which are called at
init, exit, suspend and resume conditions. Till now these functions were
present in a platform driver with a fixme notes.
Similar functions modifying same set of registers will also be needed in
case of PCIe phy init/exit.
So move all these SATA platform code to a proper phy driver.
Same phy driver will be used to add PCIe init/exit routine.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-ide at vger.kernel.org
---
.../devicetree/bindings/phy/spear13xx-miphy.txt | 8 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 36 +++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 12 +-
arch/arm/boot/dts/spear13xx.dtsi | 5 +
arch/arm/mach-spear/Kconfig | 2 +
arch/arm/mach-spear/spear1340.c | 127 +--------
drivers/phy/Kconfig | 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-spear13xx-sata-pcie.c | 305 ++++++++++++++++++++
11 files changed, 380 insertions(+), 130 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
create mode 100644 drivers/phy/phy-spear13xx-sata-pcie.c
diff --git a/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
new file mode 100644
index 0000000..208b37d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
@@ -0,0 +1,8 @@
+Required properties:
+- compatible : should be "st,spear1340-sata-pcie-phy".
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- #phy-cells : from the generic PHY bindings, must be 2.
+ - 1st arg: phandle to the phy node.
+ - 2nd arg: 0 if phy (in 1st arg) is to be used for sata else 1.
+ - 3rd arg: Instance id of the phy (in 1st arg).
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
status = "okay";
};
+ miphy at eb800000 {
+ status = "okay";
+ };
+
cf at b2800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..0d62418 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,54 @@
#gpio-cells = <2>;
};
- ahci at b1000000 {
+ miphy0: miphy at eb800000 {
+ compatible = "st,spear1340-sata-pcie-phy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <2>;
+ status = "disabled";
+ };
+
+ miphy1: miphy at eb804000 {
+ compatible = "st,spear1340-sata-pcie-phy";
+ reg = <0xeb804000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <2>;
+ status = "disabled";
+ };
+
+ miphy2: miphy at eb808000 {
+ compatible = "st,spear1340-sata-pcie-phy";
+ reg = <0xeb808000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <2>;
+ status = "disabled";
+ };
+
+ ahci0: ahci at b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
+ phys = <&miphy0 0 0>;
+ phy-names = "ahci-phy";
status = "disabled";
};
- ahci at b1800000 {
+ ahci1: ahci at b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
+ phys = <&miphy1 0 1>;
+ phy-names = "ahci-phy";
status = "disabled";
};
- ahci at b4000000 {
+ ahci2: ahci at b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
+ phys = <&miphy2 0 2>;
+ phy-names = "ahci-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
status = "okay";
};
+ miphy at eb800000 {
+ status = "okay";
+ };
+
dma at ea800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..c6b0e34 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,20 @@
status = "disabled";
};
- ahci at b1000000 {
+ miphy0: miphy at eb800000 {
+ compatible = "st,spear1340-sata-pcie-phy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <2>;
+ status = "disabled";
+ };
+
+ ahci0: ahci at b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
+ phys = <&miphy0 0 0>;
+ phy-names = "ahci-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
+ misc: syscon at e0700000 {
+ compatible = "st,spear1340-misc", "syscon";
+ reg = <0xe0700000 0x1000>;
+ };
+
gpio0: gpio at e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e..44d8543 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select USE_OF
+ select MFD_SYSCON
+ select PHY_SPEAR13XX_SATA_PCIE
help
Supports for ARM's SPEAR13XX family
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..8e27093 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -11,138 +11,13 @@
* warranty of any kind, whether express or implied.
*/
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
- /* PCIE CFG MASks */
- #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
- #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
- #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
- #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
- #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
- #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
- #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
- #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
- #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
- #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
- #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
- #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
- SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
- SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
- SPEAR1340_PCIE_CFG_POWERUP_RESET | \
- SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
- #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
- SPEAR1340_SATA_CFG_PM_CLK_EN | \
- SPEAR1340_SATA_CFG_POWERUP_RESET | \
- SPEAR1340_SATA_CFG_RX_CLK_EN | \
- SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
- #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
- #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
- #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_CLK_REF_DIV2 | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
- (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
- writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
- writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
- SPEAR1340_PCIE_MIPHY_CFG);
- /* Switch on sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
- /* Disable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
-
- return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
- writel(0, SPEAR1340_PCIE_SATA_CFG);
- writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
- /* Enable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
- /* Switch off sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_FREEZE)
- return 0;
-
- sata_miphy_exit(dev);
-
- return 0;
-}
-
-int sata_resume(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_THAW)
- return 0;
-
- return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
- .init = sata_miphy_init,
- .exit = sata_miphy_exit,
- .suspend = sata_suspend,
- .resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
- &sata_pdata),
- {}
-};
static void __init spear1340_dt_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- spear1340_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const spear1340_dt_board_compat[] = {
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a344f3d..ae34fb8 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -51,4 +51,10 @@ config PHY_EXYNOS_DP_VIDEO
help
Support for Display Port PHY found on Samsung EXYNOS SoCs.
+config PHY_SPEAR13XX_SATA_PCIE
+ tristate "SPEAr13xx SoC SATA PCIe PHY driver"
+ help
+ Support for SATA and PCIe PHY for SPEAr13xx SoC
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9..8941283 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_PHY_SPEAR13XX_SATA_PCIE) += phy-spear13xx-sata-pcie.o
diff --git a/drivers/phy/phy-spear13xx-sata-pcie.c b/drivers/phy/phy-spear13xx-sata-pcie.c
new file mode 100644
index 0000000..6adfa64
--- /dev/null
+++ b/drivers/phy/phy-spear13xx-sata-pcie.c
@@ -0,0 +1,305 @@
+/*
+ * ST SPEAr13xx SATA PCIe PHY driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG 0x100
+ #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
+#define SPEAR1340_PCM_WKUP_CFG 0x104
+#define SPEAR1340_SWITCH_CTR 0x108
+
+#define SPEAR1340_PERIP1_SW_RST 0x318
+ #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
+#define SPEAR1340_PERIP2_SW_RST 0x31C
+#define SPEAR1340_PERIP3_SW_RST 0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG 0x424
+ /* PCIE CFG MASks */
+ #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
+ #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
+ #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
+ #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
+ #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
+ #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
+ #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
+ #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
+ #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
+ #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
+ #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
+ #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
+ SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+ SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+ SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+ SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+ #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
+ SPEAR1340_SATA_CFG_PM_CLK_EN | \
+ SPEAR1340_SATA_CFG_POWERUP_RESET | \
+ SPEAR1340_SATA_CFG_RX_CLK_EN | \
+ SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG 0x428
+ #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
+ #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
+enum phy_mode {
+ SATA,
+ PCIE
+};
+
+struct spear13xx_phy_priv {
+ /* regmap for SPEAr13xx misc registers */
+ struct regmap *misc;
+ /* phy struct pointer */
+ struct phy *phy;
+ /* phy mode: 0 for SATA and 1 for PCIe */
+ enum phy_mode mode;
+ /* instance id of this phy */
+ u32 id;
+};
+
+static int spear1340_sata_miphy_init(struct spear13xx_phy_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+ /* Switch on sata power domain */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN);
+ msleep(20);
+ /* Disable PCIE SATA Controller reset */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RST_SATA, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int spear1340_sata_miphy_exit(struct spear13xx_phy_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+ /* Enable PCIE SATA Controller reset */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RST_SATA,
+ SPEAR1340_PERIP1_SW_RST_SATA);
+ msleep(20);
+ /* Switch off sata power domain */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int sata_miphy_init(struct spear13xx_phy_priv *phypriv)
+{
+ if (of_machine_is_compatible("st,spear1340"))
+ return spear1340_sata_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_exit(struct spear13xx_phy_priv *phypriv)
+{
+ if (of_machine_is_compatible("st,spear1340"))
+ return spear1340_sata_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_suspend(struct spear13xx_phy_priv *phypriv)
+{
+ return sata_miphy_exit(phypriv);
+}
+
+static int sata_miphy_resume(struct spear13xx_phy_priv *phypriv)
+{
+ return sata_miphy_init(phypriv);
+}
+
+static int miphy_init(struct phy *phy)
+{
+ struct spear13xx_phy_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_init(phypriv);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int miphy_exit(struct phy *phy)
+{
+ struct spear13xx_phy_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_exit(phypriv);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int miphy_power_off(struct phy *phy)
+{
+ struct spear13xx_phy_priv *phypriv = phy_get_drvdata(phy);
+ struct device *dev = &phy->dev;
+
+ if (dev->power.power_state.event == PM_EVENT_FREEZE)
+ return 0;
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_suspend(phypriv);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int miphy_power_on(struct phy *phy)
+{
+ struct spear13xx_phy_priv *phypriv = phy_get_drvdata(phy);
+ struct device *dev = &phy->dev;
+
+ if (dev->power.power_state.event == PM_EVENT_THAW)
+ return 0;
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_resume(phypriv);
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct of_device_id spear13xx_phy_of_match[] = {
+ { .compatible = "st,spear1340-sata-pcie-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, spear13xx_phy_of_match);
+
+static struct phy_ops spear13xx_sata_pcie_phy_ops = {
+ .init = miphy_init,
+ .exit = miphy_exit,
+ .power_off = miphy_power_off,
+ .power_on = miphy_power_on,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *spear13xx_sata_pcie_phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct spear13xx_phy_priv *phypriv = dev_get_drvdata(dev);
+
+ if (args->args_count < 2) {
+ dev_err(dev, "DT did not pass correct no of args\n");
+ return NULL;
+ }
+
+ phypriv->mode = args->args[0];
+ phypriv->id = args->args[1];
+
+ return phypriv->phy;
+}
+
+static int __init spear13xx_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct spear13xx_phy_priv *phypriv;
+ struct phy_provider *phy_provider;
+
+ phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
+ if (!phypriv) {
+ dev_err(dev, "can't alloc sata pcie private date memory\n");
+ return -ENOMEM;
+ }
+
+ phypriv->misc =
+ syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+ if (IS_ERR(phypriv->misc)) {
+ dev_err(dev, "failed to find SPEAr13xx misc regmap\n");
+ return PTR_ERR(phypriv->misc);
+ }
+
+ phy_provider = devm_of_phy_provider_register(dev,
+ spear13xx_sata_pcie_phy_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ phypriv->phy = devm_phy_create(dev, &spear13xx_sata_pcie_phy_ops, NULL);
+ if (IS_ERR(phypriv->phy)) {
+ dev_err(dev, "failed to create SATA PCIe PHY\n");
+ return PTR_ERR(phypriv->phy);
+ }
+
+ dev_set_drvdata(dev, phypriv);
+ phy_set_drvdata(phypriv->phy, phypriv);
+
+ return 0;
+}
+
+static int __exit spear13xx_phy_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver spear13xx_phy_driver = {
+ .remove = __exit_p(spear13xx_phy_remove),
+ .driver = {
+ .name = "spear13xx-sata_pcie-phy",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(spear13xx_phy_of_match),
+ },
+};
+
+static int __init spear13xx_phy_init(void)
+{
+
+ return platform_driver_probe(&spear13xx_phy_driver,
+ spear13xx_phy_probe);
+}
+subsys_initcall(spear13xx_phy_init);
+
+MODULE_DESCRIPTION("ST SPEAr13xx SATA PCIe PHY driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
--
1.7.0.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support
2014-01-30 10:48 ` Mohit Kumar
` (7 preceding siblings ...)
(?)
@ 2014-01-30 10:48 ` Mohit Kumar
2014-01-30 13:34 ` Arnd Bergmann
-1 siblings, 1 reply; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: arnd
Cc: Pratyush Anand, Mohit Kumar, Jingoo Han, Viresh Kumar,
spear-devel, linux-pci
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
with ahci/sata pins. By default evaluation board of both controller
works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the
necessary modifications on board and enable (okay) pcie and miphy
from respective evb dtsi file.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
Cc: Arnd Bergmann <arnd@arndb.de>
---
.../devicetree/bindings/pci/spear13xx-pcie.txt | 7 +
arch/arm/boot/dts/spear1310.dtsi | 51 +++
arch/arm/boot/dts/spear1340.dtsi | 17 +
arch/arm/boot/dts/spear13xx.dtsi | 5 +-
arch/arm/configs/spear13xx_defconfig | 2 +
arch/arm/mach-spear/Kconfig | 1 +
drivers/pci/host/Kconfig | 5 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 407 ++++++++++++++++++++
drivers/phy/phy-spear13xx-sata-pcie.c | 176 +++++++++
10 files changed, 670 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
create mode 100644 drivers/pci/host/pcie-spear13xx.c
diff --git a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
new file mode 100644
index 0000000..dc8ae44
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
@@ -0,0 +1,7 @@
+Required properties:
+- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
+- pcie_is_gen1: pass <1> if forced gen1 initialization is needed to work with
+ some buggy cards else pass <0>.
+- phys : phandle to phy node associated with pcie controller
+- phy-names : must be "pcie-phy"
+- All other definitions as per generic PCI bindings
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 0d62418..5a9bc58 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -80,6 +80,57 @@
status = "disabled";
};
+ pcie0: pcie@b1000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1000000 0x4000>;
+ interrupts = <0 68 0x4>;
+ pcie_is_gen1 = <0>;
+ num-lanes = <1>;
+ phys = <&miphy0 1 0>;
+ phy-names = "pcie-phy";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
+ pcie1: pcie@b1800000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1800000 0x4000>;
+ interrupts = <0 69 0x4>;
+ pcie_is_gen1 = <0>;
+ num-lanes = <1>;
+ phys = <&miphy1 1 1>;
+ phy-names = "pcie-phy";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
+ pcie2: pcie@b4000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb4000000 0x4000>;
+ interrupts = <0 70 0x4>;
+ pcie_is_gen1 = <0>;
+ num-lanes = <1>;
+ phys = <&miphy2 1 2>;
+ phy-names = "pcie-phy";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
gmac1: eth@5c400000 {
compatible = "st,spear600-gmac";
reg = <0x5c400000 0x8000>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index c6b0e34..32fb001 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -48,6 +48,23 @@
status = "disabled";
};
+ pcie0: pcie@b1000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1000000 0x4000>;
+ interrupts = <0 68 0x4>;
+ pcie_is_gen1 = <0>;
+ num-lanes = <1>;
+ phys = <&miphy0 1 0>;
+ phy-names = "pcie-phy";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
i2s-play@b2400000 {
compatible = "snps,designware-i2s";
reg = <0xb2400000 0x10000>;
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 3a72508..ec7feaf 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -83,8 +83,8 @@
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
- 0xb0000000 0xb0000000 0x10000000
- 0xd0000000 0xd0000000 0x02000000
+ 0x80000000 0x80000000 0x20000000
+ 0xb0000000 0xb0000000 0x22000000
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
@@ -338,6 +338,7 @@
reg = <0xe07008c4 0x4>;
thermal_flags = <0x7000>;
};
+
};
};
};
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 0cf87d0..41cfb4f 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -11,6 +11,8 @@ CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
# CONFIG_SWP_EMULATE is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_SPEAR13XX=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 44d8543..6dddca7 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -28,6 +28,7 @@ config ARCH_SPEAR13XX
select USE_OF
select MFD_SYSCON
select PHY_SPEAR13XX_SATA_PCIE
+ select PCI
help
Supports for ARM's SPEAR13XX family
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6..df52fad 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,9 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
+config PCIE_SPEAR13XX
+ bool "STMicroelectronics SPEAr PCIe controller"
+ depends on ARCH_SPEAR13XX
+ select PCIEPORTBUS
+ select PCIE_DW
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..42a491d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
new file mode 100644
index 0000000..f2bcf0b
--- /dev/null
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -0,0 +1,407 @@
+/*
+ * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
+ *
+ * SPEAr13xx PCIe Glue Layer Source Code
+ *
+ * Copyright (C) 2010-2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include "pcie-designware.h"
+
+struct spear13xx_pcie {
+ void __iomem *app_base;
+ struct phy *phy;
+ struct clk *clk;
+ struct pcie_port pp;
+ int is_gen1;
+};
+
+struct pcie_app_reg {
+ u32 app_ctrl_0; /*cr0*/
+ u32 app_ctrl_1; /*cr1*/
+ u32 app_status_0; /*cr2*/
+ u32 app_status_1; /*cr3*/
+ u32 msg_status; /*cr4*/
+ u32 msg_payload; /*cr5*/
+ u32 int_sts; /*cr6*/
+ u32 int_clr; /*cr7*/
+ u32 int_mask; /*cr8*/
+ u32 mst_bmisc; /*cr9*/
+ u32 phy_ctrl; /*cr10*/
+ u32 phy_status; /*cr11*/
+ u32 cxpl_debug_info_0; /*cr12*/
+ u32 cxpl_debug_info_1; /*cr13*/
+ u32 ven_msg_ctrl_0; /*cr14*/
+ u32 ven_msg_ctrl_1; /*cr15*/
+ u32 ven_msg_data_0; /*cr16*/
+ u32 ven_msg_data_1; /*cr17*/
+ u32 ven_msi_0; /*cr18*/
+ u32 ven_msi_1; /*cr19*/
+ u32 mst_rmisc; /*cr 20*/
+};
+
+/*CR0 ID*/
+#define RX_LANE_FLIP_EN_ID 0
+#define TX_LANE_FLIP_EN_ID 1
+#define SYS_AUX_PWR_DET_ID 2
+#define APP_LTSSM_ENABLE_ID 3
+#define SYS_ATTEN_BUTTON_PRESSED_ID 4
+#define SYS_MRL_SENSOR_STATE_ID 5
+#define SYS_PWR_FAULT_DET_ID 6
+#define SYS_MRL_SENSOR_CHGED_ID 7
+#define SYS_PRE_DET_CHGED_ID 8
+#define SYS_CMD_CPLED_INT_ID 9
+#define APP_INIT_RST_0_ID 11
+#define APP_REQ_ENTR_L1_ID 12
+#define APP_READY_ENTR_L23_ID 13
+#define APP_REQ_EXIT_L1_ID 14
+#define DEVICE_TYPE_EP (0 << 25)
+#define DEVICE_TYPE_LEP (1 << 25)
+#define DEVICE_TYPE_RC (4 << 25)
+#define SYS_INT_ID 29
+#define MISCTRL_EN_ID 30
+#define REG_TRANSLATION_ENABLE 31
+
+/*CR1 ID*/
+#define APPS_PM_XMT_TURNOFF_ID 2
+#define APPS_PM_XMT_PME_ID 5
+
+/*CR3 ID*/
+#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
+#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
+#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
+#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
+#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
+#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
+#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
+#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
+#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
+#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
+#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
+#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
+#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
+#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
+#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
+#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
+#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
+#define XMLH_LTSSM_STATE_L0 0x11
+#define XMLH_LTSSM_STATE_L0S 0x12
+#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
+#define XMLH_LTSSM_STATE_L1_IDLE 0x14
+#define XMLH_LTSSM_STATE_L2_IDLE 0x15
+#define XMLH_LTSSM_STATE_L2_WAKE 0x16
+#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
+#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
+#define XMLH_LTSSM_STATE_DISABLED 0x19
+#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
+#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
+#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
+#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
+#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
+#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
+#define XMLH_LTSSM_STATE_MASK 0x3F
+#define XMLH_LINK_UP (1 << 6)
+
+/*CR4 ID*/
+#define CFG_MSI_EN_ID 18
+
+/*CR6*/
+#define INTA_CTRL_INT (1 << 7)
+#define INTB_CTRL_INT (1 << 8)
+#define INTC_CTRL_INT (1 << 9)
+#define INTD_CTRL_INT (1 << 10)
+#define MSI_CTRL_INT (1 << 26)
+
+/*CR19 ID*/
+#define VEN_MSI_REQ_ID 11
+#define VEN_MSI_FUN_NUM_ID 8
+#define VEN_MSI_TC_ID 5
+#define VEN_MSI_VECTOR_ID 0
+#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
+#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
+#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
+#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
+
+#define PCI_CAP_ID_EXP_OFFSET 0x70
+
+#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
+
+static int spear13xx_pcie_establish_link(struct pcie_port *pp)
+{
+ u32 val;
+ int count = 0;
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+ u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
+
+ if (dw_pcie_link_up(pp)) {
+ dev_err(pp->dev, "Link already up\n");
+ return 0;
+ }
+
+ /* setup root complex */
+ dw_pcie_setup_rc(pp);
+
+ /*
+ * this controller support only 128 bytes read size, however its
+ * default value in capability register is 512 bytes. So force
+ * it to 128 here.
+ */
+ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
+ val &= ~PCI_EXP_DEVCTL_READRQ;
+ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
+
+ /* program vid and did for RC */
+ dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
+ dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
+
+ /*
+ * if is_gen1 is set then handle it, so that some buggy card
+ * also works
+ */
+ if (spear13xx_pcie->is_gen1) {
+ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
+ &val);
+ if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+ val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+ val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+ PCI_EXP_LNKCAP, 4, val);
+ }
+
+ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
+ &val);
+ if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+ val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+ val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+ PCI_EXP_LNKCTL2, 4, val);
+ }
+ }
+
+ /* enable ltssm */
+ writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
+ | (1 << APP_LTSSM_ENABLE_ID)
+ | ((u32)1 << REG_TRANSLATION_ENABLE),
+ &app_reg->app_ctrl_0);
+
+ /* check if the link is up or not */
+ while (!dw_pcie_link_up(pp)) {
+ mdelay(100);
+ count++;
+ if (count == 10) {
+ dev_err(pp->dev, "Link Fail\n");
+ return -EINVAL;
+ }
+ }
+ dev_info(pp->dev, "Link up\n");
+
+ return 0;
+}
+
+static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
+{
+ struct pcie_port *pp = arg;
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+ unsigned int status;
+
+ status = readl(&app_reg->int_sts);
+
+ if (status & MSI_CTRL_INT) {
+ if (!IS_ENABLED(CONFIG_PCI_MSI))
+ BUG();
+ dw_handle_msi_irq(pp);
+ }
+
+ writel(status, &app_reg->int_clr);
+
+ return IRQ_HANDLED;
+}
+
+static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
+{
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+ /* Enable MSI interrupt */
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ dw_pcie_msi_init(pp);
+ writel(readl(&app_reg->int_mask) |
+ MSI_CTRL_INT, &app_reg->int_mask);
+ }
+
+ return;
+}
+
+static int spear13xx_pcie_link_up(struct pcie_port *pp)
+{
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+ if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
+ return 1;
+
+ return 0;
+}
+
+static void spear13xx_pcie_host_init(struct pcie_port *pp)
+{
+ spear13xx_pcie_establish_link(pp);
+ spear13xx_pcie_enable_interrupts(pp);
+}
+
+static struct pcie_host_ops spear13xx_pcie_host_ops = {
+ .link_up = spear13xx_pcie_link_up,
+ .host_init = spear13xx_pcie_host_init,
+};
+
+static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pp->irq = platform_get_irq(pdev, 0);
+ if (!pp->irq) {
+ dev_err(dev, "failed to get irq\n");
+ return -ENODEV;
+ }
+ ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
+ IRQF_SHARED, "spear1340-pcie", pp);
+ if (ret) {
+ dev_err(dev, "failed to request irq\n");
+ return ret;
+ }
+
+ pp->root_bus_nr = -1;
+ pp->ops = &spear13xx_pcie_host_ops;
+
+ spin_lock_init(&pp->conf_lock);
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "failed to initialize host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __init spear13xx_pcie_probe(struct platform_device *pdev)
+{
+ struct spear13xx_pcie *spear13xx_pcie;
+ struct pcie_port *pp;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
+ struct resource *dbi_base;
+ int ret;
+
+ spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie),
+ GFP_KERNEL);
+ if (!spear13xx_pcie) {
+ dev_err(dev, "no memory for SPEAr13xx pcie\n");
+ return -ENOMEM;
+ }
+
+ spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
+ if (IS_ERR(spear13xx_pcie->phy)) {
+ dev_err(dev, "Could not get PHY\n");
+ return -EPROBE_DEFER;
+ }
+
+ phy_init(spear13xx_pcie->phy);
+
+ spear13xx_pcie->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(spear13xx_pcie->clk)) {
+ dev_err(dev, "couldn't get clk for pcie\n");
+ return PTR_ERR(spear13xx_pcie->clk);
+ }
+ ret = clk_prepare_enable(spear13xx_pcie->clk);
+ if (ret) {
+ dev_err(dev, "couldn't enable clk for pcie\n");
+ return ret;
+ }
+
+ pp = &spear13xx_pcie->pp;
+
+ pp->dev = dev;
+
+ dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
+ if (IS_ERR(pp->dbi_base)) {
+ dev_err(dev, "couldn't remap dbi base\n");
+ ret = PTR_ERR(pp->dbi_base);
+ goto fail_clk;
+ }
+ spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
+
+ of_property_read_u32(np, "pcie_is_gen1", &spear13xx_pcie->is_gen1);
+
+ ret = add_pcie_port(pp, pdev);
+ if (ret < 0)
+ goto fail_clk;
+
+ platform_set_drvdata(pdev, spear13xx_pcie);
+ return 0;
+
+fail_clk:
+ clk_disable_unprepare(spear13xx_pcie->clk);
+
+ return ret;
+}
+
+static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
+{
+ struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(spear13xx_pcie->clk);
+
+ phy_exit(spear13xx_pcie->phy);
+
+ return 0;
+}
+
+static const struct of_device_id spear13xx_pcie_of_match[] = {
+ { .compatible = "st,spear1340-pcie", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
+
+static struct platform_driver spear13xx_pcie_driver = {
+ .remove = __exit_p(spear13xx_pcie_remove),
+ .driver = {
+ .name = "spear-pcie",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
+ },
+};
+
+/* SPEAr13xx PCIe driver does not allow module unload */
+
+static int __init pcie_init(void)
+{
+
+ return platform_driver_probe(&spear13xx_pcie_driver,
+ spear13xx_pcie_probe);
+}
+subsys_initcall(pcie_init);
+
+MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-spear13xx-sata-pcie.c b/drivers/phy/phy-spear13xx-sata-pcie.c
index 6adfa64..5eabf51 100644
--- a/drivers/phy/phy-spear13xx-sata-pcie.c
+++ b/drivers/phy/phy-spear13xx-sata-pcie.c
@@ -71,6 +71,80 @@
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG 0x3A4
+ #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
+ #define SPEAR1310_PCIE_SATA2_SEL_SATA (1 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_SATA (1 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_SATA (1 << 29)
+ #define SPEAR1310_SATA2_CFG_TX_CLK_EN (1 << 27)
+ #define SPEAR1310_SATA2_CFG_RX_CLK_EN (1 << 26)
+ #define SPEAR1310_SATA2_CFG_POWERUP_RESET (1 << 25)
+ #define SPEAR1310_SATA2_CFG_PM_CLK_EN (1 << 24)
+ #define SPEAR1310_SATA1_CFG_TX_CLK_EN (1 << 23)
+ #define SPEAR1310_SATA1_CFG_RX_CLK_EN (1 << 22)
+ #define SPEAR1310_SATA1_CFG_POWERUP_RESET (1 << 21)
+ #define SPEAR1310_SATA1_CFG_PM_CLK_EN (1 << 20)
+ #define SPEAR1310_SATA0_CFG_TX_CLK_EN (1 << 19)
+ #define SPEAR1310_SATA0_CFG_RX_CLK_EN (1 << 18)
+ #define SPEAR1310_SATA0_CFG_POWERUP_RESET (1 << 17)
+ #define SPEAR1310_SATA0_CFG_PM_CLK_EN (1 << 16)
+ #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT (1 << 11)
+ #define SPEAR1310_PCIE2_CFG_POWERUP_RESET (1 << 10)
+ #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN (1 << 9)
+ #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN (1 << 8)
+ #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT (1 << 7)
+ #define SPEAR1310_PCIE1_CFG_POWERUP_RESET (1 << 6)
+ #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN (1 << 5)
+ #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN (1 << 4)
+ #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT (1 << 3)
+ #define SPEAR1310_PCIE0_CFG_POWERUP_RESET (1 << 2)
+ #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN (1 << 1)
+ #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN (1 << 0)
+
+ #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | (1 << (x + 29)))
+ #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+ (1 << (x + 29)))
+ #define SPEAR1310_PCIE_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+ SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+ #define SPEAR1310_SATA_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+ SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
+ #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT (1 << 31)
+ #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 (1 << 28)
+ #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
+ #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT (1 << 15)
+ #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 (1 << 12)
+ #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
enum phy_mode {
SATA,
@@ -154,6 +228,104 @@ static int sata_miphy_resume(struct spear13xx_phy_priv *phypriv)
return sata_miphy_init(phypriv);
}
+static int spear1340_pcie_miphy_init(struct spear13xx_phy_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
+
+ return 0;
+}
+
+static int spear1340_pcie_miphy_exit(struct spear13xx_phy_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+ return 0;
+}
+
+static int spear1310_pcie_miphy_init(struct spear13xx_phy_priv *phypriv)
+{
+ u32 mask, val;
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+ switch (phypriv->id) {
+ case 0:
+ mask = SPEAR1310_PCIE_CFG_MASK(0);
+ val = SPEAR1310_PCIE_CFG_VAL(0);
+ break;
+ case 1:
+ mask = SPEAR1310_PCIE_CFG_MASK(1);
+ val = SPEAR1310_PCIE_CFG_VAL(1);
+ break;
+ case 2:
+ mask = SPEAR1310_PCIE_CFG_MASK(2);
+ val = SPEAR1310_PCIE_CFG_VAL(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG, mask, val);
+
+ return 0;
+}
+
+static int spear1310_pcie_miphy_exit(struct spear13xx_phy_priv *phypriv)
+{
+ u32 mask;
+
+ switch (phypriv->id) {
+ case 0:
+ mask = SPEAR1310_PCIE_CFG_MASK(0);
+ break;
+ case 1:
+ mask = SPEAR1310_PCIE_CFG_MASK(1);
+ break;
+ case 2:
+ mask = SPEAR1310_PCIE_CFG_MASK(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
+
+ return 0;
+}
+
+static int pcie_miphy_init(struct spear13xx_phy_priv *phypriv)
+{
+ if (of_machine_is_compatible("st,spear1340"))
+ return spear1340_pcie_miphy_init(phypriv);
+ else if (of_machine_is_compatible("st,spear1310"))
+ return spear1310_pcie_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int pcie_miphy_exit(struct spear13xx_phy_priv *phypriv)
+{
+ if (of_machine_is_compatible("st,spear1340"))
+ return spear1340_pcie_miphy_exit(phypriv);
+ else if (of_machine_is_compatible("st,spear1310"))
+ return spear1310_pcie_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
static int miphy_init(struct phy *phy)
{
struct spear13xx_phy_priv *phypriv = phy_get_drvdata(phy);
@@ -161,6 +333,8 @@ static int miphy_init(struct phy *phy)
switch (phypriv->mode) {
case SATA:
return sata_miphy_init(phypriv);
+ case PCIE:
+ return pcie_miphy_init(phypriv);
default:
return -EINVAL;
}
@@ -173,6 +347,8 @@ static int miphy_exit(struct phy *phy)
switch (phypriv->mode) {
case SATA:
return sata_miphy_exit(phypriv);
+ case PCIE:
+ return pcie_miphy_exit(phypriv);
default:
return -EINVAL;
}
--
1.7.0.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH V3 8/8] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
2014-01-30 10:48 ` Mohit Kumar
` (8 preceding siblings ...)
(?)
@ 2014-01-30 10:48 ` Mohit Kumar
2014-02-03 0:08 ` Jingoo Han
-1 siblings, 1 reply; 39+ messages in thread
From: Mohit Kumar @ 2014-01-30 10:48 UTC (permalink / raw)
To: arnd; +Cc: Mohit Kumar, Pratyush Anand, Jingoo Han, linux-pci
Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: linux-pci@vger.kernel.org
---
MAINTAINERS | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8285ed4..fd03da6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6462,6 +6462,12 @@ L: linux-pci@vger.kernel.org
S: Maintained
F: drivers/pci/host/pci-exynos.c
+PCIE DRIVER FOR ST SPEAR13XX
+M: Mohit Kumar <mohit.kumar@st.com>
+L: linux-pci@vger.kernel.org
+S: Maintained
+F: drivers/pci/host/pcie-spear13xx.c
+
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
L: linux-pcmcia@lists.infradead.org
--
1.7.0.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall
2014-01-30 10:48 ` [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall Mohit Kumar
@ 2014-01-30 11:43 ` Kishon Vijay Abraham I
2014-01-30 11:52 ` Pratyush Anand
0 siblings, 1 reply; 39+ messages in thread
From: Kishon Vijay Abraham I @ 2014-01-30 11:43 UTC (permalink / raw)
To: Mohit Kumar, arnd; +Cc: Pratyush Anand, spear-devel, linux-kernel
Hi,
On Thursday 30 January 2014 04:18 PM, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> PCIe RC drivers are initialized with subsys_initcall. Few PCIe drivers
> like SPEAr13xx needs phy drivers to be initialized.
Instead change PCIe RC drivers to module init. Phy drivers should be loaded
very early otherwise. (Hint: drivers/Makefile).
Thanks
Kishon
>
> Therefore initialize phy core driver with subsys_initcall to avoid
> calling of phy_get before phy_class is created.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: spear-devel@list.st.com
> Cc: linux-kernel@vger.kernel.org
> ---
> drivers/phy/phy-core.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> index 03cf8fb..fa73101 100644
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -685,7 +685,7 @@ static int __init phy_core_init(void)
>
> return 0;
> }
> -module_init(phy_core_init);
> +subsys_initcall(phy_core_init);
>
> static void __exit phy_core_exit(void)
> {
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall
2014-01-30 11:43 ` Kishon Vijay Abraham I
@ 2014-01-30 11:52 ` Pratyush Anand
2014-01-30 12:10 ` Kishon Vijay Abraham I
` (2 more replies)
0 siblings, 3 replies; 39+ messages in thread
From: Pratyush Anand @ 2014-01-30 11:52 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mohit KUMAR DCG, arnd, spear-devel, linux-kernel, Bjorn Helgaas
On Thu, Jan 30, 2014 at 07:43:37PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 30 January 2014 04:18 PM, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > PCIe RC drivers are initialized with subsys_initcall. Few PCIe drivers
> > like SPEAr13xx needs phy drivers to be initialized.
>
> Instead change PCIe RC drivers to module init. Phy drivers should be loaded
> very early otherwise. (Hint: drivers/Makefile).
I think PCIe RC driver can not be made module init. Bjorn can comment
better.
All PCIe card drivers are initialized with module init. RC driver must
have been initialized before any card driver initialization.
Currently, card drivers does not have deferred probe concept, so I am
not sure if keeping RC driver as module init will work always.
By the way, is there any side effect of loading phy driver very early?
Regards
Pratyush
>
> Thanks
> Kishon
> >
> > Therefore initialize phy core driver with subsys_initcall to avoid
> > calling of phy_get before phy_class is created.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Cc: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: spear-devel@list.st.com
> > Cc: linux-kernel@vger.kernel.org
> > ---
> > drivers/phy/phy-core.c | 2 +-
> > 1 files changed, 1 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> > index 03cf8fb..fa73101 100644
> > --- a/drivers/phy/phy-core.c
> > +++ b/drivers/phy/phy-core.c
> > @@ -685,7 +685,7 @@ static int __init phy_core_init(void)
> >
> > return 0;
> > }
> > -module_init(phy_core_init);
> > +subsys_initcall(phy_core_init);
> >
> > static void __exit phy_core_exit(void)
> > {
> >
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall
2014-01-30 11:52 ` Pratyush Anand
@ 2014-01-30 12:10 ` Kishon Vijay Abraham I
2014-01-30 12:15 ` Pratyush Anand
2014-01-30 12:44 ` Arnd Bergmann
2 siblings, 0 replies; 39+ messages in thread
From: Kishon Vijay Abraham I @ 2014-01-30 12:10 UTC (permalink / raw)
To: Pratyush Anand
Cc: Mohit KUMAR DCG, arnd, spear-devel, linux-kernel, Bjorn Helgaas
Hi,
On Thursday 30 January 2014 05:22 PM, Pratyush Anand wrote:
> On Thu, Jan 30, 2014 at 07:43:37PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 30 January 2014 04:18 PM, Mohit Kumar wrote:
>>> From: Pratyush Anand <pratyush.anand@st.com>
>>>
>>> PCIe RC drivers are initialized with subsys_initcall. Few PCIe drivers
>>> like SPEAr13xx needs phy drivers to be initialized.
>>
>> Instead change PCIe RC drivers to module init. Phy drivers should be loaded
>> very early otherwise. (Hint: drivers/Makefile).
>
> I think PCIe RC driver can not be made module init. Bjorn can comment
> better.
Why not? I have used it for DRA7xx without any issues (I'll send that one
upstream once the PIPE3 phy part gets clear).
>
> All PCIe card drivers are initialized with module init. RC driver must
> have been initialized before any card driver initialization.
> Currently, card drivers does not have deferred probe concept, so I am
> not sure if keeping RC driver as module init will work always.
the card drivers will anyway be probed only after RC driver comes up no?
>
> By the way, is there any side effect of loading phy driver very early?
I assume you meant 'is there any side effect of using subsys_initcall?', since
phy driver is loaded early anyway.
The answer is no just that module_init is common one and more people prefer to
use module_init. (btw initial versions of phy-core had susbsys_initcall before
it got changed to use module_init)
Thanks
Kishon
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall
2014-01-30 11:52 ` Pratyush Anand
2014-01-30 12:10 ` Kishon Vijay Abraham I
@ 2014-01-30 12:15 ` Pratyush Anand
2014-01-30 12:25 ` Kishon Vijay Abraham I
2014-01-30 12:44 ` Arnd Bergmann
2 siblings, 1 reply; 39+ messages in thread
From: Pratyush Anand @ 2014-01-30 12:15 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mohit KUMAR DCG, arnd, spear-devel, linux-kernel, Bjorn Helgaas
On Thu, Jan 30, 2014 at 07:52:12PM +0800, Pratyush ANAND wrote:
> On Thu, Jan 30, 2014 at 07:43:37PM +0800, Kishon Vijay Abraham I wrote:
> > Hi,
> >
> > On Thursday 30 January 2014 04:18 PM, Mohit Kumar wrote:
> > > From: Pratyush Anand <pratyush.anand@st.com>
> > >
> > > PCIe RC drivers are initialized with subsys_initcall. Few PCIe drivers
> > > like SPEAr13xx needs phy drivers to be initialized.
> >
> > Instead change PCIe RC drivers to module init. Phy drivers should be loaded
> > very early otherwise. (Hint: drivers/Makefile).
>From hint, you mean that if makefile has pci entry (and hence RC
driver entry) before card drivers entry, then it insures that rc
driver's probe is called before card driver's probe?
I think, yes.
And if yes, then what you say is acceptable :)
Regards
Pratyush
>
> I think PCIe RC driver can not be made module init. Bjorn can comment
> better.
>
> All PCIe card drivers are initialized with module init. RC driver must
> have been initialized before any card driver initialization.
> Currently, card drivers does not have deferred probe concept, so I am
> not sure if keeping RC driver as module init will work always.
>
> By the way, is there any side effect of loading phy driver very early?
>
> Regards
> Pratyush
> >
> > Thanks
> > Kishon
> > >
> > > Therefore initialize phy core driver with subsys_initcall to avoid
> > > calling of phy_get before phy_class is created.
> > >
> > > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > > Cc: Mohit Kumar <mohit.kumar@st.com>
> > > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > > Cc: Arnd Bergmann <arnd@arndb.de>
> > > Cc: spear-devel@list.st.com
> > > Cc: linux-kernel@vger.kernel.org
> > > ---
> > > drivers/phy/phy-core.c | 2 +-
> > > 1 files changed, 1 insertions(+), 1 deletions(-)
> > >
> > > diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> > > index 03cf8fb..fa73101 100644
> > > --- a/drivers/phy/phy-core.c
> > > +++ b/drivers/phy/phy-core.c
> > > @@ -685,7 +685,7 @@ static int __init phy_core_init(void)
> > >
> > > return 0;
> > > }
> > > -module_init(phy_core_init);
> > > +subsys_initcall(phy_core_init);
> > >
> > > static void __exit phy_core_exit(void)
> > > {
> > >
> >
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall
2014-01-30 12:15 ` Pratyush Anand
@ 2014-01-30 12:25 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 39+ messages in thread
From: Kishon Vijay Abraham I @ 2014-01-30 12:25 UTC (permalink / raw)
To: Pratyush Anand
Cc: Mohit KUMAR DCG, arnd, spear-devel, linux-kernel, Bjorn Helgaas
On Thursday 30 January 2014 05:45 PM, Pratyush Anand wrote:
> On Thu, Jan 30, 2014 at 07:52:12PM +0800, Pratyush ANAND wrote:
>> On Thu, Jan 30, 2014 at 07:43:37PM +0800, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Thursday 30 January 2014 04:18 PM, Mohit Kumar wrote:
>>>> From: Pratyush Anand <pratyush.anand@st.com>
>>>>
>>>> PCIe RC drivers are initialized with subsys_initcall. Few PCIe drivers
>>>> like SPEAr13xx needs phy drivers to be initialized.
>>>
>>> Instead change PCIe RC drivers to module init. Phy drivers should be loaded
>>> very early otherwise. (Hint: drivers/Makefile).
>
> From hint, you mean that if makefile has pci entry (and hence RC
> driver entry) before card drivers entry, then it insures that rc
> driver's probe is called before card driver's probe?
That's right but here I was referring to PHY and PCI.
Thanks
Kishon
> I think, yes.
> And if yes, then what you say is acceptable :)
>
> Regards
> Pratyush
>>
>> I think PCIe RC driver can not be made module init. Bjorn can comment
>> better.
>>
>> All PCIe card drivers are initialized with module init. RC driver must
>> have been initialized before any card driver initialization.
>> Currently, card drivers does not have deferred probe concept, so I am
>> not sure if keeping RC driver as module init will work always.
>>
>> By the way, is there any side effect of loading phy driver very early?
>>
>> Regards
>> Pratyush
>>>
>>> Thanks
>>> Kishon
>>>>
>>>> Therefore initialize phy core driver with subsys_initcall to avoid
>>>> calling of phy_get before phy_class is created.
>>>>
>>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>>> Cc: Mohit Kumar <mohit.kumar@st.com>
>>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>>> Cc: spear-devel@list.st.com
>>>> Cc: linux-kernel@vger.kernel.org
>>>> ---
>>>> drivers/phy/phy-core.c | 2 +-
>>>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>>>
>>>> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
>>>> index 03cf8fb..fa73101 100644
>>>> --- a/drivers/phy/phy-core.c
>>>> +++ b/drivers/phy/phy-core.c
>>>> @@ -685,7 +685,7 @@ static int __init phy_core_init(void)
>>>>
>>>> return 0;
>>>> }
>>>> -module_init(phy_core_init);
>>>> +subsys_initcall(phy_core_init);
>>>>
>>>> static void __exit phy_core_exit(void)
>>>> {
>>>>
>>>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall
2014-01-30 11:52 ` Pratyush Anand
2014-01-30 12:10 ` Kishon Vijay Abraham I
2014-01-30 12:15 ` Pratyush Anand
@ 2014-01-30 12:44 ` Arnd Bergmann
2014-01-31 3:48 ` Pratyush Anand
2 siblings, 1 reply; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-30 12:44 UTC (permalink / raw)
To: Pratyush Anand
Cc: Kishon Vijay Abraham I, Mohit KUMAR DCG, spear-devel,
linux-kernel, Bjorn Helgaas
On Thursday 30 January 2014, Pratyush Anand wrote:
> On Thu, Jan 30, 2014 at 07:43:37PM +0800, Kishon Vijay Abraham I wrote:
> > Hi,
> >
> > On Thursday 30 January 2014 04:18 PM, Mohit Kumar wrote:
> > > From: Pratyush Anand <pratyush.anand@st.com>
> > >
> > > PCIe RC drivers are initialized with subsys_initcall. Few PCIe drivers
> > > like SPEAr13xx needs phy drivers to be initialized.
> >
> > Instead change PCIe RC drivers to module init. Phy drivers should be loaded
> > very early otherwise. (Hint: drivers/Makefile).
>
> I think PCIe RC driver can not be made module init. Bjorn can comment
> better.
I don't think there is any problem here: the PCI devices will only appear
after the PCIe root bus has been probed. All drivers using the regular
pci_driver framework should work fine even if they are loaded before the
device is found. There are a handful of drivers using 'pci_get_device'
rather than pci_register_driver, and those will break. As far as I can
tell, those drivers are all x86 specific, and you should not worry about
them.
Having the PHY driver get initialized after the PCI root driver should
also work, but it requires correct handling of -EPROBE_DEFER: if phy_get
returns this error, the PCI driver must silently return the same error
from its probe() function so it will get called again at a later time
(after some other devices have been probed successfully).
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V3 3/8] SPEAr13xx: defconfig: Update
2014-01-30 10:48 ` [PATCH V3 3/8] SPEAr13xx: defconfig: Update Mohit Kumar
@ 2014-01-30 13:02 ` Arnd Bergmann
2014-01-31 8:50 ` Mohit KUMAR DCG
0 siblings, 1 reply; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-30 13:02 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 30 January 2014, Mohit Kumar wrote:
> Enable EABI, OEABI, VFP and NFS configs in default configuration file for
> SPEAr13xx.
Are you sure about OABI_COMPAT? That seems unusual.
Also, please add all the options you need to multi_v7_defconfig
and ensure that this configuration works with your hardware as well.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 5/8] ata: ahci platform: Add phy hooks to make it more generic
2014-01-30 10:48 ` [PATCH V3 5/8] ata: ahci platform: Add phy hooks to make it more generic Mohit Kumar
@ 2014-01-30 13:06 ` Arnd Bergmann
2014-01-31 3:52 ` Pratyush Anand
0 siblings, 1 reply; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-30 13:06 UTC (permalink / raw)
To: Mohit Kumar
Cc: Pratyush Anand, Tejun Heo, spear-devel, linux-ide, Roger Quadros
On Thursday 30 January 2014, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> Few platform does only phy specific work in platform callbacks. It is
> better to use standard phy callbacks for such platform in stead of
> platform callbacks.
>
> This patch does not break any platform callbacks. It adds phy plugins
> on top of that.
>
> It has been assumed that no platform will need both phy plugins as well
> as platform callbacks.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: spear-devel@list.st.com
> Cc: linux-ide@vger.kernel.org
This patch looks good to me, but as I mentioned, there has
been some related work recently. Please see the patch from
Roger Quadros posted at http://lkml.org/lkml/2014/1/8/142
One of the two should be enough.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 6/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
2014-01-30 10:48 ` Mohit Kumar
@ 2014-01-30 13:21 ` Arnd Bergmann
-1 siblings, 0 replies; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-30 13:21 UTC (permalink / raw)
To: Mohit Kumar
Cc: Pratyush Anand, Viresh Kumar, Tejun Heo, Kishon Vijay Abraham I,
spear-devel, linux-arm-kernel, devicetree, linux-ide
On Thursday 30 January 2014, Mohit Kumar wrote:
>
> diff --git a/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> new file mode 100644
> index 0000000..208b37d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> @@ -0,0 +1,8 @@
> +Required properties:
> +- compatible : should be "st,spear1340-sata-pcie-phy".
Just for confirmation: This phy is by design only capable of driving
sata or pcie, but nothing else if reused in a different SoC, right?
If the phy is actually more generic than that, I'd suggest changing
the name, otherwise it's ok.
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- #phy-cells : from the generic PHY bindings, must be 2.
> + - 1st arg: phandle to the phy node.
> + - 2nd arg: 0 if phy (in 1st arg) is to be used for sata else 1.
> + - 3rd arg: Instance id of the phy (in 1st arg).
I would count "arg" differently: There are three cells, and the first
cell is the phandle, while the second and third cells contain the first
and second argument.
The third cell seems redundant, more on that below.
> + ahci0: ahci@b1000000 {
> compatible = "snps,spear-ahci";
> reg = <0xb1000000 0x10000>;
> interrupts = <0 68 0x4>;
> + phys = <&miphy0 0 0>;
> + phy-names = "ahci-phy";
> status = "disabled";
> };
>
> - ahci@b1800000 {
> + ahci1: ahci@b1800000 {
> compatible = "snps,spear-ahci";
> reg = <0xb1800000 0x10000>;
> interrupts = <0 69 0x4>;
> + phys = <&miphy1 0 1>;
> + phy-names = "ahci-phy";
> status = "disabled";
> };
>
> - ahci@b4000000 {
> + ahci2: ahci@b4000000 {
> compatible = "snps,spear-ahci";
> reg = <0xb4000000 0x10000>;
> interrupts = <0 70 0x4>;
> + phys = <&miphy2 0 2>;
> + phy-names = "ahci-phy";
> status = "disabled";
> };
In each case, the number of the phy 'miphyX' is identical to the
third cell, and I suspect this is by design. In the driver, the
'id' field is set in the xlate function, but I could not find any
place where it actually gets used, so unless you know that it's
needed, I'd suggest simply removing it.
Even if you need it, it may be better to have the instance encoded
in the phy node itself, since it's a property of the phy hardware
(e.g. if you have to pass the number into a generic register that
is global to all phys.
Alternatively, you could have a different representation, where you
have a single DT device node representing all three PHYs, with
"reg = <0xeb800000 0xc000>;" In that case, all sata devices would
point to the same phy node and pass the instance id so the phy
driver can operated the correct register set.
> +static int spear1340_sata_miphy_init(struct spear13xx_phy_priv *phypriv)
> +{
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> + /* Switch on sata power domain */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> + msleep(20);
> + /* Disable PCIE SATA Controller reset */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> + msleep(20);
> +
> + return 0;
> +}
I guess some of the parts above can eventually get moved into other
drivers (reset controller, power domains) that get called directly
by the SATA driver (e.g. though reset_device()). Since that won't
impact the PHY binding, it seems fine to leave it here for now.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V3 6/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-01-30 13:21 ` Arnd Bergmann
0 siblings, 0 replies; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-30 13:21 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 30 January 2014, Mohit Kumar wrote:
>
> diff --git a/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> new file mode 100644
> index 0000000..208b37d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> @@ -0,0 +1,8 @@
> +Required properties:
> +- compatible : should be "st,spear1340-sata-pcie-phy".
Just for confirmation: This phy is by design only capable of driving
sata or pcie, but nothing else if reused in a different SoC, right?
If the phy is actually more generic than that, I'd suggest changing
the name, otherwise it's ok.
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- #phy-cells : from the generic PHY bindings, must be 2.
> + - 1st arg: phandle to the phy node.
> + - 2nd arg: 0 if phy (in 1st arg) is to be used for sata else 1.
> + - 3rd arg: Instance id of the phy (in 1st arg).
I would count "arg" differently: There are three cells, and the first
cell is the phandle, while the second and third cells contain the first
and second argument.
The third cell seems redundant, more on that below.
> + ahci0: ahci at b1000000 {
> compatible = "snps,spear-ahci";
> reg = <0xb1000000 0x10000>;
> interrupts = <0 68 0x4>;
> + phys = <&miphy0 0 0>;
> + phy-names = "ahci-phy";
> status = "disabled";
> };
>
> - ahci at b1800000 {
> + ahci1: ahci at b1800000 {
> compatible = "snps,spear-ahci";
> reg = <0xb1800000 0x10000>;
> interrupts = <0 69 0x4>;
> + phys = <&miphy1 0 1>;
> + phy-names = "ahci-phy";
> status = "disabled";
> };
>
> - ahci at b4000000 {
> + ahci2: ahci at b4000000 {
> compatible = "snps,spear-ahci";
> reg = <0xb4000000 0x10000>;
> interrupts = <0 70 0x4>;
> + phys = <&miphy2 0 2>;
> + phy-names = "ahci-phy";
> status = "disabled";
> };
In each case, the number of the phy 'miphyX' is identical to the
third cell, and I suspect this is by design. In the driver, the
'id' field is set in the xlate function, but I could not find any
place where it actually gets used, so unless you know that it's
needed, I'd suggest simply removing it.
Even if you need it, it may be better to have the instance encoded
in the phy node itself, since it's a property of the phy hardware
(e.g. if you have to pass the number into a generic register that
is global to all phys.
Alternatively, you could have a different representation, where you
have a single DT device node representing all three PHYs, with
"reg = <0xeb800000 0xc000>;" In that case, all sata devices would
point to the same phy node and pass the instance id so the phy
driver can operated the correct register set.
> +static int spear1340_sata_miphy_init(struct spear13xx_phy_priv *phypriv)
> +{
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> + /* Switch on sata power domain */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> + msleep(20);
> + /* Disable PCIE SATA Controller reset */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> + msleep(20);
> +
> + return 0;
> +}
I guess some of the parts above can eventually get moved into other
drivers (reset controller, power domains) that get called directly
by the SATA driver (e.g. though reset_device()). Since that won't
impact the PHY binding, it seems fine to leave it here for now.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support
2014-01-30 10:48 ` [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support Mohit Kumar
@ 2014-01-30 13:34 ` Arnd Bergmann
2014-01-30 13:44 ` Arnd Bergmann
2014-01-31 4:24 ` Pratyush Anand
0 siblings, 2 replies; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-30 13:34 UTC (permalink / raw)
To: Mohit Kumar
Cc: Pratyush Anand, Jingoo Han, Viresh Kumar, spear-devel, linux-pci
On Thursday 30 January 2014, Mohit Kumar wrote:
> @@ -80,6 +80,57 @@
> status = "disabled";
> };
>
> + pcie0: pcie@b1000000 {
> + compatible = "st,spear1340-pcie", "snps,dw-pcie";
> + reg = <0xb1000000 0x4000>;
> + interrupts = <0 68 0x4>;
> + pcie_is_gen1 = <0>;
> + num-lanes = <1>;
> + phys = <&miphy0 1 0>;
> + phy-names = "pcie-phy";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
> + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
> + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
> + status = "disabled";
> + };
Shouldn't there be more than one interrupt? Normally each root port has
four legacy IRQs, in order to support bridge devices.
> + spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
> + if (IS_ERR(spear13xx_pcie->phy)) {
> + dev_err(dev, "Could not get PHY\n");
> + return -EPROBE_DEFER;
> + }
I think you should only return -EPROBE_DEFER if you got that
error from the PHY layer. If there is some other problem
with getting the PHY, you want that returned as a fatal
error here and not retry the PCIe probe function.
> diff --git a/drivers/phy/phy-spear13xx-sata-pcie.c b/drivers/phy/phy-spear13xx-sata-pcie.c
> index 6adfa64..5eabf51 100644
> --- a/drivers/phy/phy-spear13xx-sata-pcie.c
> +++ b/drivers/phy/phy-spear13xx-sata-pcie.c
> @@ -71,6 +71,80 @@
> #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
Please split this out into a separate patch.
> +static int spear1310_pcie_miphy_init(struct spear13xx_phy_priv *phypriv)
> +{
> + u32 mask, val;
> +
> + regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
> + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
> +
> + switch (phypriv->id) {
> + case 0:
> + mask = SPEAR1310_PCIE_CFG_MASK(0);
> + val = SPEAR1310_PCIE_CFG_VAL(0);
> + break;
> + case 1:
> + mask = SPEAR1310_PCIE_CFG_MASK(1);
> + val = SPEAR1310_PCIE_CFG_VAL(1);
> + break;
> + case 2:
> + mask = SPEAR1310_PCIE_CFG_MASK(2);
> + val = SPEAR1310_PCIE_CFG_VAL(2);
> + break;
Ah, so this is what the ID gets used for. I would indeed encode this in the
phy node, unlike the configuration of whether it's used for PCIe or SATA.
> +static int pcie_miphy_init(struct spear13xx_phy_priv *phypriv)
> +{
> + if (of_machine_is_compatible("st,spear1340"))
> + return spear1340_pcie_miphy_init(phypriv);
> + else if (of_machine_is_compatible("st,spear1310"))
> + return spear1310_pcie_miphy_init(phypriv);
> + else
> + return -EINVAL;
> +}
You should never check global properties such as the machine compatible
value to make local decisions. You have two options here: Either use
two different compatible strings for the phy node, or encode the
difference in another property. If the only difference between spear1310
and spear1340 is the location of the register within the "misc" syscon
space, a good represenation would be to put the register offset next
to the syscon phandle in the same property. That way it could transparently
work for future SoCs.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support
2014-01-30 13:34 ` Arnd Bergmann
@ 2014-01-30 13:44 ` Arnd Bergmann
2014-01-31 4:44 ` Pratyush Anand
2014-01-31 4:24 ` Pratyush Anand
1 sibling, 1 reply; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-30 13:44 UTC (permalink / raw)
To: Mohit Kumar
Cc: Pratyush Anand, Jingoo Han, Viresh Kumar, spear-devel, linux-pci
On Thursday 30 January 2014, Arnd Bergmann wrote:
> > + pcie0: pcie@b1000000 {
> > + compatible = "st,spear1340-pcie", "snps,dw-pcie";
> > + reg = <0xb1000000 0x4000>;
> > + interrupts = <0 68 0x4>;
> > + pcie_is_gen1 = <0>;
> > + num-lanes = <1>;
> > + phys = <&miphy0 1 0>;
> > + phy-names = "pcie-phy";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
> > + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
> > + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
> > + status = "disabled";
> > + };
>
> Shouldn't there be more than one interrupt? Normally each root port has
> four legacy IRQs, in order to support bridge devices.
>
Sorry, my mistake: I was thinking of the interrupt map for legacy IRQs.
The interrupt here is used only for the integrated MSI controller, right?
That seems fine from the DT bindings perspective but raises two other
questions:
1. Are you not lacking an interrupt-map property to enable legacy IntA
IRQs?
2. If the MSI controller is integrated in the pcie host controller,
does that maintain the PCIe ordering guarantees between inbound
DMA and MSI, or is it possible that the <0 68 0x4> IRQ gets
raised at the CPU before the the DMA transfer becomes visible to
the CPU in main memory?
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall
2014-01-30 12:44 ` Arnd Bergmann
@ 2014-01-31 3:48 ` Pratyush Anand
2014-01-31 15:25 ` Arnd Bergmann
0 siblings, 1 reply; 39+ messages in thread
From: Pratyush Anand @ 2014-01-31 3:48 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Kishon Vijay Abraham I, Mohit KUMAR DCG, spear-devel,
linux-kernel, Bjorn Helgaas
On Thu, Jan 30, 2014 at 08:44:58PM +0800, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Pratyush Anand wrote:
> > On Thu, Jan 30, 2014 at 07:43:37PM +0800, Kishon Vijay Abraham I wrote:
> > > Hi,
> > >
> > > On Thursday 30 January 2014 04:18 PM, Mohit Kumar wrote:
> > > > From: Pratyush Anand <pratyush.anand@st.com>
> > > >
> > > > PCIe RC drivers are initialized with subsys_initcall. Few PCIe drivers
> > > > like SPEAr13xx needs phy drivers to be initialized.
> > >
> > > Instead change PCIe RC drivers to module init. Phy drivers should be loaded
> > > very early otherwise. (Hint: drivers/Makefile).
> >
> > I think PCIe RC driver can not be made module init. Bjorn can comment
> > better.
>
> I don't think there is any problem here: the PCI devices will only appear
> after the PCIe root bus has been probed. All drivers using the regular
> pci_driver framework should work fine even if they are loaded before the
> device is found. There are a handful of drivers using 'pci_get_device'
> rather than pci_register_driver, and those will break. As far as I can
> tell, those drivers are all x86 specific, and you should not worry about
> them.
>
> Having the PHY driver get initialized after the PCI root driver should
> also work, but it requires correct handling of -EPROBE_DEFER: if phy_get
I had issue with phy-core driver getting initialized after pcie rc
driver. I found a kernel crash, as devm_phy_get was called before
phy_class was created. I think this too need to be fixed, we should
not see a crash.
Anyway, I will keep spear phy and rc driver both with module_init and
-EPROBE_DEFER implementation.
Regards
Pratyush
> returns this error, the PCI driver must silently return the same error
> from its probe() function so it will get called again at a later time
> (after some other devices have been probed successfully).
>
> Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 5/8] ata: ahci platform: Add phy hooks to make it more generic
2014-01-30 13:06 ` Arnd Bergmann
@ 2014-01-31 3:52 ` Pratyush Anand
0 siblings, 0 replies; 39+ messages in thread
From: Pratyush Anand @ 2014-01-31 3:52 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mohit KUMAR DCG, Tejun Heo, spear-devel, linux-ide, Roger Quadros
On Thu, Jan 30, 2014 at 09:06:14PM +0800, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > Few platform does only phy specific work in platform callbacks. It is
> > better to use standard phy callbacks for such platform in stead of
> > platform callbacks.
> >
> > This patch does not break any platform callbacks. It adds phy plugins
> > on top of that.
> >
> > It has been assumed that no platform will need both phy plugins as well
> > as platform callbacks.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Cc: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Tejun Heo <tj@kernel.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: spear-devel@list.st.com
> > Cc: linux-ide@vger.kernel.org
>
> This patch looks good to me, but as I mentioned, there has
> been some related work recently. Please see the patch from
> Roger Quadros posted at http://lkml.org/lkml/2014/1/8/142
I am not subscribed to ide list and I did not see that patch :(.
Will test our platform with above patch.
Regards
Pratyush
>
> One of the two should be enough.
>
> Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 6/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
2014-01-30 13:21 ` Arnd Bergmann
@ 2014-01-31 4:12 ` Pratyush Anand
-1 siblings, 0 replies; 39+ messages in thread
From: Pratyush Anand @ 2014-01-31 4:12 UTC (permalink / raw)
To: Arnd Bergmann
Cc: devicetree, Mohit KUMAR DCG, spear-devel, Kishon Vijay Abraham I,
linux-ide, Viresh Kumar, Tejun Heo, linux-arm-kernel
On Thu, Jan 30, 2014 at 09:21:00PM +0800, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Mohit Kumar wrote:
> >
> > diff --git a/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > new file mode 100644
> > index 0000000..208b37d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > @@ -0,0 +1,8 @@
> > +Required properties:
> > +- compatible : should be "st,spear1340-sata-pcie-phy".
>
> Just for confirmation: This phy is by design only capable of driving
> sata or pcie, but nothing else if reused in a different SoC, right?
>
> If the phy is actually more generic than that, I'd suggest changing
> the name, otherwise it's ok.
OK, we will give a generic name as it can be used for sata/pcie/usb3.0.
Although, phy register definition may vary from version to version,
but that can be managed,as and when support of new soc is added.
>
> > +- reg : offset and length of the PHY register set.
> > +- misc: phandle for the syscon node to access misc registers
> > +- #phy-cells : from the generic PHY bindings, must be 2.
> > + - 1st arg: phandle to the phy node.
> > + - 2nd arg: 0 if phy (in 1st arg) is to be used for sata else 1.
> > + - 3rd arg: Instance id of the phy (in 1st arg).
>
> I would count "arg" differently: There are three cells, and the first
> cell is the phandle, while the second and third cells contain the first
> and second argument.
Ok..will modify accordingly.
>
> The third cell seems redundant, more on that below.
>
> > + ahci0: ahci@b1000000 {
> > compatible = "snps,spear-ahci";
> > reg = <0xb1000000 0x10000>;
> > interrupts = <0 68 0x4>;
> > + phys = <&miphy0 0 0>;
> > + phy-names = "ahci-phy";
> > status = "disabled";
> > };
> >
> > - ahci@b1800000 {
> > + ahci1: ahci@b1800000 {
> > compatible = "snps,spear-ahci";
> > reg = <0xb1800000 0x10000>;
> > interrupts = <0 69 0x4>;
> > + phys = <&miphy1 0 1>;
> > + phy-names = "ahci-phy";
> > status = "disabled";
> > };
> >
> > - ahci@b4000000 {
> > + ahci2: ahci@b4000000 {
> > compatible = "snps,spear-ahci";
> > reg = <0xb4000000 0x10000>;
> > interrupts = <0 70 0x4>;
> > + phys = <&miphy2 0 2>;
> > + phy-names = "ahci-phy";
> > status = "disabled";
> > };
>
> In each case, the number of the phy 'miphyX' is identical to the
> third cell, and I suspect this is by design. In the driver, the
> 'id' field is set in the xlate function, but I could not find any
> place where it actually gets used, so unless you know that it's
> needed, I'd suggest simply removing it.
It has not been used in this patch, as SATA support is currently only
for SPEAr1340, where we have only one instance.
Will be using it in PCIe for SPEAr1310 where 3 instances are present.
>
> Even if you need it, it may be better to have the instance encoded
> in the phy node itself, since it's a property of the phy hardware
> (e.g. if you have to pass the number into a generic register that
> is global to all phys.
Ok..ll do that.
>
> Alternatively, you could have a different representation, where you
> have a single DT device node representing all three PHYs, with
> "reg = <0xeb800000 0xc000>;" In that case, all sata devices would
> point to the same phy node and pass the instance id so the phy
> driver can operated the correct register set.
Instance ID is mainly needed to manipulate wrapper register present
within SPEAr13xx misc space. We have a single register in misc space
having bit fields controlling all 3 phys, and there we need this id.
>
> > +static int spear1340_sata_miphy_init(struct spear13xx_phy_priv *phypriv)
> > +{
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> > + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> > + /* Switch on sata power domain */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> > + msleep(20);
> > + /* Disable PCIE SATA Controller reset */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> > + msleep(20);
> > +
> > + return 0;
> > +}
>
> I guess some of the parts above can eventually get moved into other
> drivers (reset controller, power domains) that get called directly
> by the SATA driver (e.g. though reset_device()). Since that won't
> impact the PHY binding, it seems fine to leave it here for now.
thanks :)
Regards
Pratyush
>
> Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V3 6/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-01-31 4:12 ` Pratyush Anand
0 siblings, 0 replies; 39+ messages in thread
From: Pratyush Anand @ 2014-01-31 4:12 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jan 30, 2014 at 09:21:00PM +0800, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Mohit Kumar wrote:
> >
> > diff --git a/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > new file mode 100644
> > index 0000000..208b37d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > @@ -0,0 +1,8 @@
> > +Required properties:
> > +- compatible : should be "st,spear1340-sata-pcie-phy".
>
> Just for confirmation: This phy is by design only capable of driving
> sata or pcie, but nothing else if reused in a different SoC, right?
>
> If the phy is actually more generic than that, I'd suggest changing
> the name, otherwise it's ok.
OK, we will give a generic name as it can be used for sata/pcie/usb3.0.
Although, phy register definition may vary from version to version,
but that can be managed,as and when support of new soc is added.
>
> > +- reg : offset and length of the PHY register set.
> > +- misc: phandle for the syscon node to access misc registers
> > +- #phy-cells : from the generic PHY bindings, must be 2.
> > + - 1st arg: phandle to the phy node.
> > + - 2nd arg: 0 if phy (in 1st arg) is to be used for sata else 1.
> > + - 3rd arg: Instance id of the phy (in 1st arg).
>
> I would count "arg" differently: There are three cells, and the first
> cell is the phandle, while the second and third cells contain the first
> and second argument.
Ok..will modify accordingly.
>
> The third cell seems redundant, more on that below.
>
> > + ahci0: ahci at b1000000 {
> > compatible = "snps,spear-ahci";
> > reg = <0xb1000000 0x10000>;
> > interrupts = <0 68 0x4>;
> > + phys = <&miphy0 0 0>;
> > + phy-names = "ahci-phy";
> > status = "disabled";
> > };
> >
> > - ahci at b1800000 {
> > + ahci1: ahci at b1800000 {
> > compatible = "snps,spear-ahci";
> > reg = <0xb1800000 0x10000>;
> > interrupts = <0 69 0x4>;
> > + phys = <&miphy1 0 1>;
> > + phy-names = "ahci-phy";
> > status = "disabled";
> > };
> >
> > - ahci at b4000000 {
> > + ahci2: ahci at b4000000 {
> > compatible = "snps,spear-ahci";
> > reg = <0xb4000000 0x10000>;
> > interrupts = <0 70 0x4>;
> > + phys = <&miphy2 0 2>;
> > + phy-names = "ahci-phy";
> > status = "disabled";
> > };
>
> In each case, the number of the phy 'miphyX' is identical to the
> third cell, and I suspect this is by design. In the driver, the
> 'id' field is set in the xlate function, but I could not find any
> place where it actually gets used, so unless you know that it's
> needed, I'd suggest simply removing it.
It has not been used in this patch, as SATA support is currently only
for SPEAr1340, where we have only one instance.
Will be using it in PCIe for SPEAr1310 where 3 instances are present.
>
> Even if you need it, it may be better to have the instance encoded
> in the phy node itself, since it's a property of the phy hardware
> (e.g. if you have to pass the number into a generic register that
> is global to all phys.
Ok..ll do that.
>
> Alternatively, you could have a different representation, where you
> have a single DT device node representing all three PHYs, with
> "reg = <0xeb800000 0xc000>;" In that case, all sata devices would
> point to the same phy node and pass the instance id so the phy
> driver can operated the correct register set.
Instance ID is mainly needed to manipulate wrapper register present
within SPEAr13xx misc space. We have a single register in misc space
having bit fields controlling all 3 phys, and there we need this id.
>
> > +static int spear1340_sata_miphy_init(struct spear13xx_phy_priv *phypriv)
> > +{
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> > + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> > + /* Switch on sata power domain */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> > + msleep(20);
> > + /* Disable PCIE SATA Controller reset */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> > + msleep(20);
> > +
> > + return 0;
> > +}
>
> I guess some of the parts above can eventually get moved into other
> drivers (reset controller, power domains) that get called directly
> by the SATA driver (e.g. though reset_device()). Since that won't
> impact the PHY binding, it seems fine to leave it here for now.
thanks :)
Regards
Pratyush
>
> Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support
2014-01-30 13:34 ` Arnd Bergmann
2014-01-30 13:44 ` Arnd Bergmann
@ 2014-01-31 4:24 ` Pratyush Anand
2014-01-31 15:29 ` Arnd Bergmann
1 sibling, 1 reply; 39+ messages in thread
From: Pratyush Anand @ 2014-01-31 4:24 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mohit KUMAR DCG, Jingoo Han, Viresh Kumar, spear-devel, linux-pci
On Thu, Jan 30, 2014 at 09:34:19PM +0800, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Mohit Kumar wrote:
>
> > @@ -80,6 +80,57 @@
> > status = "disabled";
> > };
> >
> > + pcie0: pcie@b1000000 {
> > + compatible = "st,spear1340-pcie", "snps,dw-pcie";
> > + reg = <0xb1000000 0x4000>;
> > + interrupts = <0 68 0x4>;
> > + pcie_is_gen1 = <0>;
> > + num-lanes = <1>;
> > + phys = <&miphy0 1 0>;
> > + phy-names = "pcie-phy";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
> > + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
> > + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
> > + status = "disabled";
> > + };
>
> Shouldn't there be more than one interrupt? Normally each root port has
> four legacy IRQs, in order to support bridge devices.
>
> > + spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
> > + if (IS_ERR(spear13xx_pcie->phy)) {
> > + dev_err(dev, "Could not get PHY\n");
> > + return -EPROBE_DEFER;
> > + }
>
> I think you should only return -EPROBE_DEFER if you got that
> error from the PHY layer. If there is some other problem
> with getting the PHY, you want that returned as a fatal
> error here and not retry the PCIe probe function.
OK.
>
> > diff --git a/drivers/phy/phy-spear13xx-sata-pcie.c b/drivers/phy/phy-spear13xx-sata-pcie.c
> > index 6adfa64..5eabf51 100644
> > --- a/drivers/phy/phy-spear13xx-sata-pcie.c
> > +++ b/drivers/phy/phy-spear13xx-sata-pcie.c
> > @@ -71,6 +71,80 @@
> > #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> > (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
>
> Please split this out into a separate patch.
ok.
>
> > +static int spear1310_pcie_miphy_init(struct spear13xx_phy_priv *phypriv)
> > +{
> > + u32 mask, val;
> > +
> > + regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> > + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
> > + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
> > +
> > + switch (phypriv->id) {
> > + case 0:
> > + mask = SPEAR1310_PCIE_CFG_MASK(0);
> > + val = SPEAR1310_PCIE_CFG_VAL(0);
> > + break;
> > + case 1:
> > + mask = SPEAR1310_PCIE_CFG_MASK(1);
> > + val = SPEAR1310_PCIE_CFG_VAL(1);
> > + break;
> > + case 2:
> > + mask = SPEAR1310_PCIE_CFG_MASK(2);
> > + val = SPEAR1310_PCIE_CFG_VAL(2);
> > + break;
>
> Ah, so this is what the ID gets used for. I would indeed encode this in the
> phy node, unlike the configuration of whether it's used for PCIe or SATA.
ok.. ll use "phy_id = <n>;" in phy node.
>
> > +static int pcie_miphy_init(struct spear13xx_phy_priv *phypriv)
> > +{
> > + if (of_machine_is_compatible("st,spear1340"))
> > + return spear1340_pcie_miphy_init(phypriv);
> > + else if (of_machine_is_compatible("st,spear1310"))
> > + return spear1310_pcie_miphy_init(phypriv);
> > + else
> > + return -EINVAL;
> > +}
>
> You should never check global properties such as the machine compatible
> value to make local decisions. You have two options here: Either use
> two different compatible strings for the phy node, or encode the
> difference in another property. If the only difference between spear1310
> and spear1340 is the location of the register within the "misc" syscon
> space, a good represenation would be to put the register offset next
> to the syscon phandle in the same property. That way it could transparently
> work for future SoCs.
Currently, there is only difference in misc syscon space. But, as I
said few phy register definition might also change in different soc.
Ok.. I ll go with first option, ie different compatible string for
different socs. It seems most logical also.
Regards
Pratyush
>
> Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support
2014-01-30 13:44 ` Arnd Bergmann
@ 2014-01-31 4:44 ` Pratyush Anand
2014-01-31 19:01 ` Arnd Bergmann
0 siblings, 1 reply; 39+ messages in thread
From: Pratyush Anand @ 2014-01-31 4:44 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mohit KUMAR DCG, Jingoo Han, Viresh Kumar, spear-devel, linux-pci
On Thu, Jan 30, 2014 at 09:44:57PM +0800, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Arnd Bergmann wrote:
> > > + pcie0: pcie@b1000000 {
> > > + compatible = "st,spear1340-pcie", "snps,dw-pcie";
> > > + reg = <0xb1000000 0x4000>;
> > > + interrupts = <0 68 0x4>;
> > > + pcie_is_gen1 = <0>;
> > > + num-lanes = <1>;
> > > + phys = <&miphy0 1 0>;
> > > + phy-names = "pcie-phy";
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > + device_type = "pci";
> > > + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
> > > + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
> > > + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
> > > + status = "disabled";
> > > + };
> >
> > Shouldn't there be more than one interrupt? Normally each root port has
> > four legacy IRQs, in order to support bridge devices.
> >
>
> Sorry, my mistake: I was thinking of the interrupt map for legacy IRQs.
> The interrupt here is used only for the integrated MSI controller, right?
yes.
> That seems fine from the DT bindings perspective but raises two other
> questions:
>
> 1. Are you not lacking an interrupt-map property to enable legacy IntA
> IRQs?
As current pcie-designeware driver is not supporting legacy IntA IRQs,
so we left it.
>
> 2. If the MSI controller is integrated in the pcie host controller,
> does that maintain the PCIe ordering guarantees between inbound
> DMA and MSI, or is it possible that the <0 68 0x4> IRQ gets
> raised at the CPU before the the DMA transfer becomes visible to
> the CPU in main memory?
If the system does not guarantee it, then won't be it a bug in the
hardware?
In our case, there is no separate interrupt for DMA completion. (I do
not know if other system does have DMA interrupt). We have only one
interrupt and when it is received SW will look into main memory (MSI
address) for MSI data. If DMA transfer is yet not complete, then SW ll
read junk data and which will be a bug.
We have never seen any erroneous behaviour with MSI interrupt.
Regards
Pratyush
>
> Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V3 3/8] SPEAr13xx: defconfig: Update
2014-01-30 13:02 ` Arnd Bergmann
@ 2014-01-31 8:50 ` Mohit KUMAR DCG
0 siblings, 0 replies; 39+ messages in thread
From: Mohit KUMAR DCG @ 2014-01-31 8:50 UTC (permalink / raw)
To: linux-arm-kernel
Hello Arnd,
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Thursday, January 30, 2014 6:32 PM
> To: Mohit KUMAR DCG
> Cc: Pratyush ANAND; spear-devel; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH V3 3/8] SPEAr13xx: defconfig: Update
>
> On Thursday 30 January 2014, Mohit Kumar wrote:
> > Enable EABI, OEABI, VFP and NFS configs in default configuration file
> > for SPEAr13xx.
>
> Are you sure about OABI_COMPAT? That seems unusual.
- yes, this option is not required
>
> Also, please add all the options you need to multi_v7_defconfig and ensure
> that this configuration works with your hardware as well.
- OK, will do this and test with SPEAr1310.
Thanks
Mohit
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall
2014-01-31 3:48 ` Pratyush Anand
@ 2014-01-31 15:25 ` Arnd Bergmann
0 siblings, 0 replies; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-31 15:25 UTC (permalink / raw)
To: Pratyush Anand
Cc: Kishon Vijay Abraham I, Mohit KUMAR DCG, spear-devel,
linux-kernel, Bjorn Helgaas
On Friday 31 January 2014, Pratyush Anand wrote:
> > Having the PHY driver get initialized after the PCI root driver should
> > also work, but it requires correct handling of -EPROBE_DEFER: if phy_get
>
> I had issue with phy-core driver getting initialized after pcie rc
> driver. I found a kernel crash, as devm_phy_get was called before
> phy_class was created. I think this too need to be fixed, we should
> not see a crash.
Yes, agreed. This should be trivial to do though.
> Anyway, I will keep spear phy and rc driver both with module_init and
> -EPROBE_DEFER implementation.
Ok.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 6/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
2014-01-31 4:12 ` Pratyush Anand
@ 2014-01-31 15:27 ` Arnd Bergmann
-1 siblings, 0 replies; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-31 15:27 UTC (permalink / raw)
To: Pratyush Anand
Cc: Mohit KUMAR DCG, Viresh Kumar, Tejun Heo, Kishon Vijay Abraham I,
spear-devel, linux-arm-kernel, devicetree, linux-ide
On Friday 31 January 2014, Pratyush Anand wrote:
> On Thu, Jan 30, 2014 at 09:21:00PM +0800, Arnd Bergmann wrote:
> > On Thursday 30 January 2014, Mohit Kumar wrote:
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > > new file mode 100644
> > > index 0000000..208b37d
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > > @@ -0,0 +1,8 @@
> > > +Required properties:
> > > +- compatible : should be "st,spear1340-sata-pcie-phy".
> >
> > Just for confirmation: This phy is by design only capable of driving
> > sata or pcie, but nothing else if reused in a different SoC, right?
> >
> > If the phy is actually more generic than that, I'd suggest changing
> > the name, otherwise it's ok.
>
> OK, we will give a generic name as it can be used for sata/pcie/usb3.0.
> Although, phy register definition may vary from version to version,
> but that can be managed,as and when support of new soc is added.
It probably doesn't hurt to already define a list of possible
modes in the binding that you already know about. That way, you
don't have to update the binding in sync with the driver if you
add another mode, such as USB.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V3 6/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-01-31 15:27 ` Arnd Bergmann
0 siblings, 0 replies; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-31 15:27 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 31 January 2014, Pratyush Anand wrote:
> On Thu, Jan 30, 2014 at 09:21:00PM +0800, Arnd Bergmann wrote:
> > On Thursday 30 January 2014, Mohit Kumar wrote:
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > > new file mode 100644
> > > index 0000000..208b37d
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > > @@ -0,0 +1,8 @@
> > > +Required properties:
> > > +- compatible : should be "st,spear1340-sata-pcie-phy".
> >
> > Just for confirmation: This phy is by design only capable of driving
> > sata or pcie, but nothing else if reused in a different SoC, right?
> >
> > If the phy is actually more generic than that, I'd suggest changing
> > the name, otherwise it's ok.
>
> OK, we will give a generic name as it can be used for sata/pcie/usb3.0.
> Although, phy register definition may vary from version to version,
> but that can be managed,as and when support of new soc is added.
It probably doesn't hurt to already define a list of possible
modes in the binding that you already know about. That way, you
don't have to update the binding in sync with the driver if you
add another mode, such as USB.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support
2014-01-31 4:24 ` Pratyush Anand
@ 2014-01-31 15:29 ` Arnd Bergmann
0 siblings, 0 replies; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-31 15:29 UTC (permalink / raw)
To: Pratyush Anand
Cc: Mohit KUMAR DCG, Jingoo Han, Viresh Kumar, spear-devel, linux-pci
On Friday 31 January 2014, Pratyush Anand wrote:
> On Thu, Jan 30, 2014 at 09:34:19PM +0800, Arnd Bergmann wrote:
> > On Thursday 30 January 2014, Mohit Kumar wrote:
> >
> > Ah, so this is what the ID gets used for. I would indeed encode this in the
> > phy node, unlike the configuration of whether it's used for PCIe or SATA.
>
> ok.. ll use "phy_id = <n>;" in phy node.
Ok. Minor comment: the preferred style would be 'phy-id' rather than 'phy_id'
in DT,
> > > +static int pcie_miphy_init(struct spear13xx_phy_priv *phypriv)
> > > +{
> > > + if (of_machine_is_compatible("st,spear1340"))
> > > + return spear1340_pcie_miphy_init(phypriv);
> > > + else if (of_machine_is_compatible("st,spear1310"))
> > > + return spear1310_pcie_miphy_init(phypriv);
> > > + else
> > > + return -EINVAL;
> > > +}
> >
> > You should never check global properties such as the machine compatible
> > value to make local decisions. You have two options here: Either use
> > two different compatible strings for the phy node, or encode the
> > difference in another property. If the only difference between spear1310
> > and spear1340 is the location of the register within the "misc" syscon
> > space, a good represenation would be to put the register offset next
> > to the syscon phandle in the same property. That way it could transparently
> > work for future SoCs.
>
> Currently, there is only difference in misc syscon space. But, as I
> said few phy register definition might also change in different soc.
>
> Ok.. I ll go with first option, ie different compatible string for
> different socs. It seems most logical also.
Ok.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support
2014-01-31 4:44 ` Pratyush Anand
@ 2014-01-31 19:01 ` Arnd Bergmann
2014-02-01 6:32 ` Pratyush Anand
0 siblings, 1 reply; 39+ messages in thread
From: Arnd Bergmann @ 2014-01-31 19:01 UTC (permalink / raw)
To: Pratyush Anand
Cc: Mohit KUMAR DCG, Jingoo Han, Viresh Kumar, spear-devel, linux-pci
On Friday 31 January 2014, Pratyush Anand wrote:
> > That seems fine from the DT bindings perspective but raises two other
> > questions:
> >
> > 1. Are you not lacking an interrupt-map property to enable legacy IntA
> > IRQs?
>
> As current pcie-designeware driver is not supporting legacy IntA IRQs,
> so we left it.
Hmm, that sounds hard to believe. Doesn't that exclude 90% of the add-on
cards? I noticed that imx also doesn't have it, but exynos does.
Can you check the data sheet again? Maybe the IntA IRQs are not mapped to
host (GIC) IRQs but instead get handled internally in the MSI controller?
IIRC, PCIe INTa IRQs are implemented as MSI on the bus, but normally
get turned into physical IRQ lines by the root complex. If the RC
contains the MSI controller itself, that may have a special register
for the LSI.
> > 2. If the MSI controller is integrated in the pcie host controller,
> > does that maintain the PCIe ordering guarantees between inbound
> > DMA and MSI, or is it possible that the <0 68 0x4> IRQ gets
> > raised at the CPU before the the DMA transfer becomes visible to
> > the CPU in main memory?
>
> If the system does not guarantee it, then won't be it a bug in the
> hardware?
> In our case, there is no separate interrupt for DMA completion. (I do
> not know if other system does have DMA interrupt). We have only one
> interrupt and when it is received SW will look into main memory (MSI
> address) for MSI data. If DMA transfer is yet not complete, then SW ll
> read junk data and which will be a bug.
>
> We have never seen any erroneous behaviour with MSI interrupt.
There should not be a separate interrupt for DMA, the typical behavior
of a PCIe adapter (SCSI, ethernet, ...) is that it sends an MSI after
data has arrived from an external interface and gets submitted as a
bus-master DMA into main memory. The actual data transfer may have the
'relaxed ordering' bit set on the PCIe transaction, but the MSI message
(which is essentially a 4-byte DMA) will not, which means that all buses
are required to only forward the MSI after the DMA is completed.
If the PCIe host is located on a bus that is not directly connected
to the memory controller, the RC may have seen the DMA complete and
signalled the IRC to the CPU while the data transfer is still in
progress on its way to the actual memory.
That kind of problem is extremely hard to debug and will only occur
in rare cases of bus congestion.
Arnd
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support
2014-01-31 19:01 ` Arnd Bergmann
@ 2014-02-01 6:32 ` Pratyush Anand
2014-02-03 0:06 ` Jingoo Han
0 siblings, 1 reply; 39+ messages in thread
From: Pratyush Anand @ 2014-02-01 6:32 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Pratyush Anand, Mohit KUMAR DCG, Jingoo Han, Viresh Kumar,
spear-devel, linux-pci
On 2/1/14, Arnd Bergmann <arnd@arndb.de> wrote:
> On Friday 31 January 2014, Pratyush Anand wrote:
>> > That seems fine from the DT bindings perspective but raises two other
>> > questions:
>> >
>> > 1. Are you not lacking an interrupt-map property to enable legacy IntA
>> > IRQs?
>>
>> As current pcie-designeware driver is not supporting legacy IntA IRQs,
>> so we left it.
>
> Hmm, that sounds hard to believe. Doesn't that exclude 90% of the add-on
> cards? I noticed that imx also doesn't have it, but exynos does.
>
> Can you check the data sheet again? Maybe the IntA IRQs are not mapped to
I did not say that designware controller does not supoort it.
It does support. But pcie-designware driver is not supporting
it as of now. I think, a common irq_chip for intx handling need
to be created in designware driver.
I am not sure even if exynos does define dt bindings for irq,
are they able to use it?
Jingoo can comment.
> host (GIC) IRQs but instead get handled internally in the MSI controller?
> IIRC, PCIe INTa IRQs are implemented as MSI on the bus, but normally
> get turned into physical IRQ lines by the root complex. If the RC
> contains the MSI controller itself, that may have a special register
> for the LSI.
I agree that in PCIe Intx is also handled as message only. As far as
designware controller is concerned, it has different intx and msi
controller. Now, a SoC can have two different irq line or can have
a single irq line at gic for MSI and INTx. In SPEAr13xx we have a single
IRQ line for both MSI and INTx.
Once this patch set gets into mainline, may be someone of us will work
to add irq chip for INTx in common designware driver, and also its wrapper
in SPEAr13xx pcie driver. At that time we will add interrupt-map property to
enable legacy IntA.
>
>> > 2. If the MSI controller is integrated in the pcie host controller,
>> > does that maintain the PCIe ordering guarantees between inbound
>> > DMA and MSI, or is it possible that the <0 68 0x4> IRQ gets
>> > raised at the CPU before the the DMA transfer becomes visible to
>> > the CPU in main memory?
>>
>> If the system does not guarantee it, then won't be it a bug in the
>> hardware?
>> In our case, there is no separate interrupt for DMA completion. (I do
>> not know if other system does have DMA interrupt). We have only one
>> interrupt and when it is received SW will look into main memory (MSI
>> address) for MSI data. If DMA transfer is yet not complete, then SW ll
>> read junk data and which will be a bug.
>>
>> We have never seen any erroneous behaviour with MSI interrupt.
>
> There should not be a separate interrupt for DMA, the typical behavior
> of a PCIe adapter (SCSI, ethernet, ...) is that it sends an MSI after
> data has arrived from an external interface and gets submitted as a
> bus-master DMA into main memory. The actual data transfer may have the
> 'relaxed ordering' bit set on the PCIe transaction, but the MSI message
> (which is essentially a 4-byte DMA) will not, which means that all buses
> are required to only forward the MSI after the DMA is completed.
> If the PCIe host is located on a bus that is not directly connected
> to the memory controller, the RC may have seen the DMA complete and
> signalled the IRC to the CPU while the data transfer is still in
> progress on its way to the actual memory.
>
> That kind of problem is extremely hard to debug and will only occur
> in rare cases of bus congestion.
Agreed, But there is anything special for software to do here?
Thanks a lot for your review.
Regards
Pratyush
>
> Arnd
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support
2014-02-01 6:32 ` Pratyush Anand
@ 2014-02-03 0:06 ` Jingoo Han
0 siblings, 0 replies; 39+ messages in thread
From: Jingoo Han @ 2014-02-03 0:06 UTC (permalink / raw)
To: 'Pratyush Anand', 'Arnd Bergmann'
Cc: 'Pratyush Anand', 'Mohit KUMAR DCG',
'Viresh Kumar', 'spear-devel',
linux-pci, 'Jingoo Han'
On Saturday, February 01, 2014 3:32 PM, Pratyush Anand wrote:
> On 2/1/14, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Friday 31 January 2014, Pratyush Anand wrote:
> >> > That seems fine from the DT bindings perspective but raises two other
> >> > questions:
> >> >
> >> > 1. Are you not lacking an interrupt-map property to enable legacy IntA
> >> > IRQs?
> >>
> >> As current pcie-designeware driver is not supporting legacy IntA IRQs,
> >> so we left it.
> >
> > Hmm, that sounds hard to believe. Doesn't that exclude 90% of the add-on
> > cards? I noticed that imx also doesn't have it, but exynos does.
> >
> > Can you check the data sheet again? Maybe the IntA IRQs are not mapped to
>
> I did not say that designware controller does not supoort it.
> It does support. But pcie-designware driver is not supporting
> it as of now. I think, a common irq_chip for intx handling need
> to be created in designware driver.
>
> I am not sure even if exynos does define dt bindings for irq,
> are they able to use it?
> Jingoo can comment.
In the case of Exynos, there are three interrupts for PCIe;
it has different INTx line and MSI line for interrupts.
./arch/arm/boot/dts/exynos5440.dtsi
interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
<0 20 0>: PCIe RC0 pulse interrupt,
INTA, INTB, INTC and INTD, etc
<0 21 0>: PCIe RC0 level interrupt,
MSI, etc
<0 22 0>: PCIe RC0 special interrupt,
PHY Link related interrupts, etc
Of course, legacy INTx is handled as message only.
Best regards,
Jingoo Han
>
> > host (GIC) IRQs but instead get handled internally in the MSI controller?
> > IIRC, PCIe INTa IRQs are implemented as MSI on the bus, but normally
> > get turned into physical IRQ lines by the root complex. If the RC
> > contains the MSI controller itself, that may have a special register
> > for the LSI.
>
> I agree that in PCIe Intx is also handled as message only. As far as
> designware controller is concerned, it has different intx and msi
> controller. Now, a SoC can have two different irq line or can have
> a single irq line at gic for MSI and INTx. In SPEAr13xx we have a single
> IRQ line for both MSI and INTx.
>
> Once this patch set gets into mainline, may be someone of us will work
> to add irq chip for INTx in common designware driver, and also its wrapper
> in SPEAr13xx pcie driver. At that time we will add interrupt-map property to
> enable legacy IntA.
>
> >
> >> > 2. If the MSI controller is integrated in the pcie host controller,
> >> > does that maintain the PCIe ordering guarantees between inbound
> >> > DMA and MSI, or is it possible that the <0 68 0x4> IRQ gets
> >> > raised at the CPU before the the DMA transfer becomes visible to
> >> > the CPU in main memory?
> >>
> >> If the system does not guarantee it, then won't be it a bug in the
> >> hardware?
> >> In our case, there is no separate interrupt for DMA completion. (I do
> >> not know if other system does have DMA interrupt). We have only one
> >> interrupt and when it is received SW will look into main memory (MSI
> >> address) for MSI data. If DMA transfer is yet not complete, then SW ll
> >> read junk data and which will be a bug.
> >>
> >> We have never seen any erroneous behaviour with MSI interrupt.
> >
> > There should not be a separate interrupt for DMA, the typical behavior
> > of a PCIe adapter (SCSI, ethernet, ...) is that it sends an MSI after
> > data has arrived from an external interface and gets submitted as a
> > bus-master DMA into main memory. The actual data transfer may have the
> > 'relaxed ordering' bit set on the PCIe transaction, but the MSI message
> > (which is essentially a 4-byte DMA) will not, which means that all buses
> > are required to only forward the MSI after the DMA is completed.
> > If the PCIe host is located on a bus that is not directly connected
> > to the memory controller, the RC may have seen the DMA complete and
> > signalled the IRC to the CPU while the data transfer is still in
> > progress on its way to the actual memory.
> >
> > That kind of problem is extremely hard to debug and will only occur
> > in rare cases of bus congestion.
>
> Agreed, But there is anything special for software to do here?
>
> Thanks a lot for your review.
>
> Regards
> Pratyush
> >
> > Arnd
> > --
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3 8/8] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
2014-01-30 10:48 ` [PATCH V3 8/8] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer Mohit Kumar
@ 2014-02-03 0:08 ` Jingoo Han
0 siblings, 0 replies; 39+ messages in thread
From: Jingoo Han @ 2014-02-03 0:08 UTC (permalink / raw)
To: 'Mohit Kumar', arnd
Cc: 'Pratyush Anand', linux-pci, 'Jingoo Han'
On Thursday, January 30, 2014 7:49 PM, Mohit Kumar wrote:
>
> Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
>
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Best regards,
Jingoo Han
> Cc: linux-pci@vger.kernel.org
> ---
> MAINTAINERS | 6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8285ed4..fd03da6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6462,6 +6462,12 @@ L: linux-pci@vger.kernel.org
> S: Maintained
> F: drivers/pci/host/pci-exynos.c
>
> +PCIE DRIVER FOR ST SPEAR13XX
> +M: Mohit Kumar <mohit.kumar@st.com>
> +L: linux-pci@vger.kernel.org
> +S: Maintained
> +F: drivers/pci/host/pcie-spear13xx.c
> +
> PCMCIA SUBSYSTEM
> P: Linux PCMCIA Team
> L: linux-pcmcia@lists.infradead.org
> --
> 1.7.0.1
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2014-02-03 0:09 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-01-30 10:48 [PATCH V3 0/8] PCI:Add SPEAr13xx PCie support Mohit Kumar
2014-01-30 10:48 ` Mohit Kumar
2014-01-30 10:48 ` Mohit Kumar
2014-01-30 10:48 ` [PATCH V3 1/8] clk: SPEAr13xx: Fix pcie clock name Mohit Kumar
2014-01-30 10:48 ` [PATCH V3 2/8] SPEAr13xx: Fix static mapping table Mohit Kumar
2014-01-30 10:48 ` [PATCH V3 3/8] SPEAr13xx: defconfig: Update Mohit Kumar
2014-01-30 13:02 ` Arnd Bergmann
2014-01-31 8:50 ` Mohit KUMAR DCG
2014-01-30 10:48 ` [PATCH V3 4/8] phy: Initialize phy core with subsys_initcall Mohit Kumar
2014-01-30 11:43 ` Kishon Vijay Abraham I
2014-01-30 11:52 ` Pratyush Anand
2014-01-30 12:10 ` Kishon Vijay Abraham I
2014-01-30 12:15 ` Pratyush Anand
2014-01-30 12:25 ` Kishon Vijay Abraham I
2014-01-30 12:44 ` Arnd Bergmann
2014-01-31 3:48 ` Pratyush Anand
2014-01-31 15:25 ` Arnd Bergmann
2014-01-30 10:48 ` [PATCH V3 5/8] ata: ahci platform: Add phy hooks to make it more generic Mohit Kumar
2014-01-30 13:06 ` Arnd Bergmann
2014-01-31 3:52 ` Pratyush Anand
[not found] ` <cover.1391077731.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
2014-01-30 10:48 ` [PATCH V3 6/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver Mohit Kumar
2014-01-30 10:48 ` Mohit Kumar
2014-01-30 13:21 ` Arnd Bergmann
2014-01-30 13:21 ` Arnd Bergmann
2014-01-31 4:12 ` Pratyush Anand
2014-01-31 4:12 ` Pratyush Anand
2014-01-31 15:27 ` Arnd Bergmann
2014-01-31 15:27 ` Arnd Bergmann
2014-01-30 10:48 ` [PATCH V3 7/8] pcie: SPEAr13xx: Add designware pcie support Mohit Kumar
2014-01-30 13:34 ` Arnd Bergmann
2014-01-30 13:44 ` Arnd Bergmann
2014-01-31 4:44 ` Pratyush Anand
2014-01-31 19:01 ` Arnd Bergmann
2014-02-01 6:32 ` Pratyush Anand
2014-02-03 0:06 ` Jingoo Han
2014-01-31 4:24 ` Pratyush Anand
2014-01-31 15:29 ` Arnd Bergmann
2014-01-30 10:48 ` [PATCH V3 8/8] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer Mohit Kumar
2014-02-03 0:08 ` Jingoo Han
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