[PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[Geert Uytterhoeven]

	Hi Simon, Magnus,

The following patch series completes r8a7790 SoC and Lager board
integration for the Renesas Quad Serial Peripheral Interface. It brings
r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
kernels.

    [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
    [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
    [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
    [4/7] ARM: shmobile: lager dts: Add QSPI nodes
    [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80
    [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
	  FLASH
    [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
         FLASH

Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
in the linux-spi tree for v3.15.

Thanks!

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[Geert Uytterhoeven]

	Hi Simon, Magnus,

The following patch series completes r8a7790 SoC and Lager board
integration for the Renesas Quad Serial Peripheral Interface. It brings
r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
kernels.

    [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
    [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
    [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
    [4/7] ARM: shmobile: lager dts: Add QSPI nodes
    [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80
    [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
	  FLASH
    [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
         FLASH

Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
in the linux-spi tree for v3.15.

Thanks!

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[Geert Uytterhoeven]

	Hi Simon, Magnus,

The following patch series completes r8a7790 SoC and Lager board
integration for the Renesas Quad Serial Peripheral Interface. It brings
r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
kernels.

    [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
    [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
    [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
    [4/7] ARM: shmobile: lager dts: Add QSPI nodes
    [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80
    [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
	  FLASH
    [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
         FLASH

Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
in the linux-spi tree for v3.15.

Thanks!

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

A QSPI function set consists of 3 groups:
  - qspi_ctrl (2 control wires)
  - qspi_data2 (2 data wires, for Single/Dual SPI)
  - qspi_data4 (4 data wires, for Quad SPI)

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c |   33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index c381ae63c508..bc9ced3ccd58 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -2389,6 +2389,29 @@ static const unsigned int msiof3_tx_pins[] = {
 static const unsigned int msiof3_tx_mux[] = {
 	MSIOF3_TXD_MARK,
 };
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+	/* SPCLK, SSL */
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+	SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+	/* MOSI_IO0, MISO_IO1 */
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int qspi_data2_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(1, 8),
+};
+static const unsigned int qspi_data4_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
+};
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX, TX */
@@ -3671,6 +3694,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(msiof3_ss2),
 	SH_PFC_PIN_GROUP(msiof3_rx),
 	SH_PFC_PIN_GROUP(msiof3_tx),
+	SH_PFC_PIN_GROUP(qspi_ctrl),
+	SH_PFC_PIN_GROUP(qspi_data2),
+	SH_PFC_PIN_GROUP(qspi_data4),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -3970,6 +3996,12 @@ static const char * const msiof3_groups[] = {
 	"msiof3_tx",
 };
 
+static const char * const qspi_groups[] = {
+	"qspi_ctrl",
+	"qspi_data2",
+	"qspi_data4",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -4212,6 +4244,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(msiof0),
 	SH_PFC_FUNCTION(msiof1),
 	SH_PFC_FUNCTION(msiof2),
+	SH_PFC_FUNCTION(qspi),
 	SH_PFC_FUNCTION(msiof3),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
-- 
1.7.9.5

[PATCH 1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

A QSPI function set consists of 3 groups:
  - qspi_ctrl (2 control wires)
  - qspi_data2 (2 data wires, for Single/Dual SPI)
  - qspi_data4 (4 data wires, for Quad SPI)

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c |   33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index c381ae63c508..bc9ced3ccd58 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -2389,6 +2389,29 @@ static const unsigned int msiof3_tx_pins[] = {
 static const unsigned int msiof3_tx_mux[] = {
 	MSIOF3_TXD_MARK,
 };
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+	/* SPCLK, SSL */
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+	SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+	/* MOSI_IO0, MISO_IO1 */
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int qspi_data2_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(1, 8),
+};
+static const unsigned int qspi_data4_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
+};
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX, TX */
@@ -3671,6 +3694,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(msiof3_ss2),
 	SH_PFC_PIN_GROUP(msiof3_rx),
 	SH_PFC_PIN_GROUP(msiof3_tx),
+	SH_PFC_PIN_GROUP(qspi_ctrl),
+	SH_PFC_PIN_GROUP(qspi_data2),
+	SH_PFC_PIN_GROUP(qspi_data4),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -3970,6 +3996,12 @@ static const char * const msiof3_groups[] = {
 	"msiof3_tx",
 };
 
+static const char * const qspi_groups[] = {
+	"qspi_ctrl",
+	"qspi_data2",
+	"qspi_data4",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -4212,6 +4244,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(msiof0),
 	SH_PFC_FUNCTION(msiof1),
 	SH_PFC_FUNCTION(msiof2),
+	SH_PFC_FUNCTION(qspi),
 	SH_PFC_FUNCTION(msiof3),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
-- 
1.7.9.5

[PATCH 1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

A QSPI function set consists of 3 groups:
  - qspi_ctrl (2 control wires)
  - qspi_data2 (2 data wires, for Single/Dual SPI)
  - qspi_data4 (4 data wires, for Quad SPI)

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c |   33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index c381ae63c508..bc9ced3ccd58 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -2389,6 +2389,29 @@ static const unsigned int msiof3_tx_pins[] = {
 static const unsigned int msiof3_tx_mux[] = {
 	MSIOF3_TXD_MARK,
 };
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+	/* SPCLK, SSL */
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+	SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+	/* MOSI_IO0, MISO_IO1 */
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int qspi_data2_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(1, 8),
+};
+static const unsigned int qspi_data4_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
+};
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX, TX */
@@ -3671,6 +3694,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(msiof3_ss2),
 	SH_PFC_PIN_GROUP(msiof3_rx),
 	SH_PFC_PIN_GROUP(msiof3_tx),
+	SH_PFC_PIN_GROUP(qspi_ctrl),
+	SH_PFC_PIN_GROUP(qspi_data2),
+	SH_PFC_PIN_GROUP(qspi_data4),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -3970,6 +3996,12 @@ static const char * const msiof3_groups[] = {
 	"msiof3_tx",
 };
 
+static const char * const qspi_groups[] = {
+	"qspi_ctrl",
+	"qspi_data2",
+	"qspi_data4",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -4212,6 +4244,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(msiof0),
 	SH_PFC_FUNCTION(msiof1),
 	SH_PFC_FUNCTION(msiof2),
+	SH_PFC_FUNCTION(qspi),
 	SH_PFC_FUNCTION(msiof3),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
-- 
1.7.9.5

[PATCH 2/7] ARM: shmobile: lager legacy: Add QSPI pinmux

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
 arch/arm/mach-shmobile/board-lager.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 317574864e7b..9e52efa2a457 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -606,6 +606,11 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
 	/* I2C2 */
 	PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar.2", "pfc-r8a7790",
 				  "i2c2", "i2c2"),
+	/* QSPI */
+	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
+				  "qspi_ctrl", "qspi"),
+	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
+				  "qspi_data4", "qspi"),
 	/* SCIF0 (CN19: DEBUG SERIAL0) */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
 				  "scif0_data", "scif0"),
-- 
1.7.9.5

[PATCH 2/7] ARM: shmobile: lager legacy: Add QSPI pinmux

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
 arch/arm/mach-shmobile/board-lager.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 317574864e7b..9e52efa2a457 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -606,6 +606,11 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
 	/* I2C2 */
 	PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar.2", "pfc-r8a7790",
 				  "i2c2", "i2c2"),
+	/* QSPI */
+	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
+				  "qspi_ctrl", "qspi"),
+	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
+				  "qspi_data4", "qspi"),
 	/* SCIF0 (CN19: DEBUG SERIAL0) */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
 				  "scif0_data", "scif0"),
-- 
1.7.9.5

[PATCH 2/7] ARM: shmobile: lager legacy: Add QSPI pinmux

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
 arch/arm/mach-shmobile/board-lager.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 317574864e7b..9e52efa2a457 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -606,6 +606,11 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
 	/* I2C2 */
 	PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar.2", "pfc-r8a7790",
 				  "i2c2", "i2c2"),
+	/* QSPI */
+	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
+				  "qspi_ctrl", "qspi"),
+	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
+				  "qspi_data4", "qspi"),
 	/* SCIF0 (CN19: DEBUG SERIAL0) */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
 				  "scif0_data", "scif0"),
-- 
1.7.9.5

[PATCH 3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
---
 arch/arm/boot/dts/r8a7790.dtsi |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 54ab318af712..16bc116e0df4 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -775,4 +775,16 @@
 				"rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
 		};
 	};
+
+	spi: spi@e6b10000 {
+		compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+		reg = <0 0xe6b10000 0 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
-- 
1.7.9.5

[PATCH 3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
---
 arch/arm/boot/dts/r8a7790.dtsi |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 54ab318af712..16bc116e0df4 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -775,4 +775,16 @@
 				"rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
 		};
 	};
+
+	spi: spi@e6b10000 {
+		compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+		reg = <0 0xe6b10000 0 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
-- 
1.7.9.5

[PATCH 3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: devicetree at vger.kernel.org
Cc: linux-spi at vger.kernel.org
---
 arch/arm/boot/dts/r8a7790.dtsi |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 54ab318af712..16bc116e0df4 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -775,4 +775,16 @@
 				"rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
 		};
 	};
+
+	spi: spi at e6b10000 {
+		compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+		reg = <0 0xe6b10000 0 0x2c>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
-- 
1.7.9.5

[PATCH 4/7] ARM: shmobile: lager dts: Add QSPI nodes

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Add pinctrl and SPI devices for QSPI on Lager.
Add Spansion s25fl512s SPI FLASH and MTD partitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
---
 arch/arm/boot/dts/r8a7790-lager.dts |   36 +++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 1081c5e91ac4..adff2dc4012d 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -80,6 +80,11 @@
 		renesas,groups = "mmc1_data8", "mmc1_ctrl";
 		renesas,function = "mmc1";
 	};
+
+	qspi_pins: spi {
+		renesas,groups = "qspi_ctrl", "qspi_data4";
+		renesas,function = "qspi";
+	};
 };
 
 &mmcif1 {
@@ -95,3 +100,34 @@
 &sata1 {
 	status = "okay";
 };
+
+&spi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25fl512s";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+		m25p,fast-read;
+
+		partition@0 {
+			label = "loader";
+			reg = <0x00000000 0x00040000>;
+			read-only;
+		};
+		partition@40000 {
+			label = "user";
+			reg = <0x00040000 0x00400000>;
+			read-only;
+		};
+		partition@440000 {
+			label = "flash";
+			reg = <0x00440000 0x03bc0000>;
+		};
+	};
+};
-- 
1.7.9.5

[PATCH 4/7] ARM: shmobile: lager dts: Add QSPI nodes

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Add pinctrl and SPI devices for QSPI on Lager.
Add Spansion s25fl512s SPI FLASH and MTD partitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
---
 arch/arm/boot/dts/r8a7790-lager.dts |   36 +++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 1081c5e91ac4..adff2dc4012d 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -80,6 +80,11 @@
 		renesas,groups = "mmc1_data8", "mmc1_ctrl";
 		renesas,function = "mmc1";
 	};
+
+	qspi_pins: spi {
+		renesas,groups = "qspi_ctrl", "qspi_data4";
+		renesas,function = "qspi";
+	};
 };
 
 &mmcif1 {
@@ -95,3 +100,34 @@
 &sata1 {
 	status = "okay";
 };
+
+&spi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25fl512s";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+		m25p,fast-read;
+
+		partition@0 {
+			label = "loader";
+			reg = <0x00000000 0x00040000>;
+			read-only;
+		};
+		partition@40000 {
+			label = "user";
+			reg = <0x00040000 0x00400000>;
+			read-only;
+		};
+		partition@440000 {
+			label = "flash";
+			reg = <0x00440000 0x03bc0000>;
+		};
+	};
+};
-- 
1.7.9.5

[PATCH 4/7] ARM: shmobile: lager dts: Add QSPI nodes

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>

Add pinctrl and SPI devices for QSPI on Lager.
Add Spansion s25fl512s SPI FLASH and MTD partitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/arm/boot/dts/r8a7790-lager.dts |   36 +++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 1081c5e91ac4..adff2dc4012d 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -80,6 +80,11 @@
 		renesas,groups = "mmc1_data8", "mmc1_ctrl";
 		renesas,function = "mmc1";
 	};
+
+	qspi_pins: spi {
+		renesas,groups = "qspi_ctrl", "qspi_data4";
+		renesas,function = "qspi";
+	};
 };
 
 &mmcif1 {
@@ -95,3 +100,34 @@
 &sata1 {
 	status = "okay";
 };
+
+&spi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25fl512s";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+		m25p,fast-read;
+
+		partition@0 {
+			label = "loader";
+			reg = <0x00000000 0x00040000>;
+			read-only;
+		};
+		partition@40000 {
+			label = "user";
+			reg = <0x00040000 0x00400000>;
+			read-only;
+		};
+		partition@440000 {
+			label = "flash";
+			reg = <0x00440000 0x03bc0000>;
+		};
+	};
+};
-- 
1.7.9.5

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[PATCH 4/7] ARM: shmobile: lager dts: Add QSPI nodes

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Add pinctrl and SPI devices for QSPI on Lager.
Add Spansion s25fl512s SPI FLASH and MTD partitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: devicetree at vger.kernel.org
Cc: linux-spi at vger.kernel.org
---
 arch/arm/boot/dts/r8a7790-lager.dts |   36 +++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 1081c5e91ac4..adff2dc4012d 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -80,6 +80,11 @@
 		renesas,groups = "mmc1_data8", "mmc1_ctrl";
 		renesas,function = "mmc1";
 	};
+
+	qspi_pins: spi {
+		renesas,groups = "qspi_ctrl", "qspi_data4";
+		renesas,function = "qspi";
+	};
 };
 
 &mmcif1 {
@@ -95,3 +100,34 @@
 &sata1 {
 	status = "okay";
 };
+
+&spi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash: flash at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25fl512s";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+		m25p,fast-read;
+
+		partition at 0 {
+			label = "loader";
+			reg = <0x00000000 0x00040000>;
+			read-only;
+		};
+		partition at 40000 {
+			label = "user";
+			reg = <0x00040000 0x00400000>;
+			read-only;
+		};
+		partition at 440000 {
+			label = "flash";
+			reg = <0x00440000 0x03bc0000>;
+		};
+	};
+};
-- 
1.7.9.5

[PATCH 5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

This enables support for the Spansion s25fl512s SPI FLASH on QSPI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
 arch/arm/configs/lager_defconfig |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 235772f7c81d..b17fc23ae676 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -51,6 +51,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_RCAR=y
@@ -86,6 +88,8 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_RSPI=y
 CONFIG_GPIO_SH_PFC=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_RCAR=y
-- 
1.7.9.5

[PATCH 5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

This enables support for the Spansion s25fl512s SPI FLASH on QSPI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
 arch/arm/configs/lager_defconfig |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 235772f7c81d..b17fc23ae676 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -51,6 +51,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_RCAR=y
@@ -86,6 +88,8 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_RSPI=y
 CONFIG_GPIO_SH_PFC=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_RCAR=y
-- 
1.7.9.5

[PATCH 5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

This enables support for the Spansion s25fl512s SPI FLASH on QSPI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
 arch/arm/configs/lager_defconfig |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 235772f7c81d..b17fc23ae676 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -51,6 +51,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_RCAR=y
@@ -86,6 +88,8 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_RSPI=y
 CONFIG_GPIO_SH_PFC=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_RCAR=y
-- 
1.7.9.5

[PATCH 6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI FLASH

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
This depends on spi-rspi updates

 arch/arm/mach-shmobile/board-lager.c |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 9e52efa2a457..d7155375a322 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -298,12 +298,12 @@ static const struct rspi_plat_data qspi_pdata __initconst = {
 
 static const struct spi_board_info spi_info[] __initconst = {
 	{
-		.modalias               = "m25p80",
-		.platform_data          = &spi_flash_data,
-		.mode                   = SPI_MODE_0,
-		.max_speed_hz           = 30000000,
-		.bus_num                = 0,
-		.chip_select            = 0,
+		.modalias	= "m25p80",
+		.platform_data	= &spi_flash_data,
+		.mode		= SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
+		.max_speed_hz	= 30000000,
+		.bus_num	= 0,
+		.chip_select	= 0,
 	},
 };
 
-- 
1.7.9.5

[PATCH 6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI FLASH

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
This depends on spi-rspi updates

 arch/arm/mach-shmobile/board-lager.c |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 9e52efa2a457..d7155375a322 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -298,12 +298,12 @@ static const struct rspi_plat_data qspi_pdata __initconst = {
 
 static const struct spi_board_info spi_info[] __initconst = {
 	{
-		.modalias               = "m25p80",
-		.platform_data          = &spi_flash_data,
-		.mode                   = SPI_MODE_0,
-		.max_speed_hz           = 30000000,
-		.bus_num                = 0,
-		.chip_select            = 0,
+		.modalias	= "m25p80",
+		.platform_data	= &spi_flash_data,
+		.mode		= SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
+		.max_speed_hz	= 30000000,
+		.bus_num	= 0,
+		.chip_select	= 0,
 	},
 };
 
-- 
1.7.9.5

[PATCH 6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI FLASH

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
This depends on spi-rspi updates

 arch/arm/mach-shmobile/board-lager.c |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 9e52efa2a457..d7155375a322 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -298,12 +298,12 @@ static const struct rspi_plat_data qspi_pdata __initconst = {
 
 static const struct spi_board_info spi_info[] __initconst = {
 	{
-		.modalias               = "m25p80",
-		.platform_data          = &spi_flash_data,
-		.mode                   = SPI_MODE_0,
-		.max_speed_hz           = 30000000,
-		.bus_num                = 0,
-		.chip_select            = 0,
+		.modalias	= "m25p80",
+		.platform_data	= &spi_flash_data,
+		.mode		= SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
+		.max_speed_hz	= 30000000,
+		.bus_num	= 0,
+		.chip_select	= 0,
 	},
 };
 
-- 
1.7.9.5

[PATCH 7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI FLASH

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
This depends on spi-rspi updates

 arch/arm/boot/dts/r8a7790-lager.dts |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index adff2dc4012d..0b47ade38340 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -113,6 +113,8 @@
 		compatible = "spansion,s25fl512s";
 		reg = <0>;
 		spi-max-frequency = <30000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 		m25p,fast-read;
 
 		partition@0 {
-- 
1.7.9.5

[PATCH 7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI FLASH

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
This depends on spi-rspi updates

 arch/arm/boot/dts/r8a7790-lager.dts |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index adff2dc4012d..0b47ade38340 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -113,6 +113,8 @@
 		compatible = "spansion,s25fl512s";
 		reg = <0>;
 		spi-max-frequency = <30000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 		m25p,fast-read;
 
 		partition@0 {
-- 
1.7.9.5

[PATCH 7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI FLASH

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
This depends on spi-rspi updates

 arch/arm/boot/dts/r8a7790-lager.dts |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index adff2dc4012d..0b47ade38340 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -113,6 +113,8 @@
 		compatible = "spansion,s25fl512s";
 		reg = <0>;
 		spi-max-frequency = <30000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 		m25p,fast-read;
 
 		partition at 0 {
-- 
1.7.9.5

Re: [PATCH 1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Monday 10 February 2014 11:47:27 Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> 
> A QSPI function set consists of 3 groups:
>   - qspi_ctrl (2 control wires)
>   - qspi_data2 (2 data wires, for Single/Dual SPI)
>   - qspi_data4 (4 data wires, for Quad SPI)
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a7790.c |   33 +++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index c381ae63c508..bc9ced3ccd58
> 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> @@ -2389,6 +2389,29 @@ static const unsigned int msiof3_tx_pins[] = {
>  static const unsigned int msiof3_tx_mux[] = {
>  	MSIOF3_TXD_MARK,
>  };
> +/* - QSPI -------------------------------------------------------------- */
> +static const unsigned int qspi_ctrl_pins[] = {
> +	/* SPCLK, SSL */
> +	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
> +};
> +static const unsigned int qspi_ctrl_mux[] = {
> +	SPCLK_MARK, SSL_MARK,
> +};
> +static const unsigned int qspi_data2_pins[] = {
> +	/* MOSI_IO0, MISO_IO1 */
> +	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
> +};
> +static const unsigned int qspi_data2_mux[] = {
> +	MOSI_IO0_MARK, MISO_IO1_MARK,
> +};
> +static const unsigned int qspi_data4_pins[] = {
> +	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
> +	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +	RCAR_GP_PIN(1, 8),
> +};
> +static const unsigned int qspi_data4_mux[] = {
> +	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
> +};
>  /* - SCIF0 ------------------------------------------------------------- */
> static const unsigned int scif0_data_pins[] = {
>  	/* RX, TX */
> @@ -3671,6 +3694,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] > { SH_PFC_PIN_GROUP(msiof3_ss2),
>  	SH_PFC_PIN_GROUP(msiof3_rx),
>  	SH_PFC_PIN_GROUP(msiof3_tx),
> +	SH_PFC_PIN_GROUP(qspi_ctrl),
> +	SH_PFC_PIN_GROUP(qspi_data2),
> +	SH_PFC_PIN_GROUP(qspi_data4),
>  	SH_PFC_PIN_GROUP(scif0_data),
>  	SH_PFC_PIN_GROUP(scif0_clk),
>  	SH_PFC_PIN_GROUP(scif0_ctrl),
> @@ -3970,6 +3996,12 @@ static const char * const msiof3_groups[] = {
>  	"msiof3_tx",
>  };
> 
> +static const char * const qspi_groups[] = {
> +	"qspi_ctrl",
> +	"qspi_data2",
> +	"qspi_data4",
> +};
> +
>  static const char * const scif0_groups[] = {
>  	"scif0_data",
>  	"scif0_clk",
> @@ -4212,6 +4244,7 @@ static const struct sh_pfc_function pinmux_functions[]
> = { SH_PFC_FUNCTION(msiof0),
>  	SH_PFC_FUNCTION(msiof1),
>  	SH_PFC_FUNCTION(msiof2),
> +	SH_PFC_FUNCTION(qspi),
>  	SH_PFC_FUNCTION(msiof3),

I believe qspi comes after msiof3 :-)

Apart from that the patch looks good.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>  	SH_PFC_FUNCTION(scif0),
>  	SH_PFC_FUNCTION(scif1),

-- 
Regards,

Laurent Pinchart

Re: [PATCH 1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Monday 10 February 2014 11:47:27 Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> 
> A QSPI function set consists of 3 groups:
>   - qspi_ctrl (2 control wires)
>   - qspi_data2 (2 data wires, for Single/Dual SPI)
>   - qspi_data4 (4 data wires, for Quad SPI)
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a7790.c |   33 +++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index c381ae63c508..bc9ced3ccd58
> 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> @@ -2389,6 +2389,29 @@ static const unsigned int msiof3_tx_pins[] = {
>  static const unsigned int msiof3_tx_mux[] = {
>  	MSIOF3_TXD_MARK,
>  };
> +/* - QSPI -------------------------------------------------------------- */
> +static const unsigned int qspi_ctrl_pins[] = {
> +	/* SPCLK, SSL */
> +	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
> +};
> +static const unsigned int qspi_ctrl_mux[] = {
> +	SPCLK_MARK, SSL_MARK,
> +};
> +static const unsigned int qspi_data2_pins[] = {
> +	/* MOSI_IO0, MISO_IO1 */
> +	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
> +};
> +static const unsigned int qspi_data2_mux[] = {
> +	MOSI_IO0_MARK, MISO_IO1_MARK,
> +};
> +static const unsigned int qspi_data4_pins[] = {
> +	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
> +	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +	RCAR_GP_PIN(1, 8),
> +};
> +static const unsigned int qspi_data4_mux[] = {
> +	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
> +};
>  /* - SCIF0 ------------------------------------------------------------- */
> static const unsigned int scif0_data_pins[] = {
>  	/* RX, TX */
> @@ -3671,6 +3694,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] =
> { SH_PFC_PIN_GROUP(msiof3_ss2),
>  	SH_PFC_PIN_GROUP(msiof3_rx),
>  	SH_PFC_PIN_GROUP(msiof3_tx),
> +	SH_PFC_PIN_GROUP(qspi_ctrl),
> +	SH_PFC_PIN_GROUP(qspi_data2),
> +	SH_PFC_PIN_GROUP(qspi_data4),
>  	SH_PFC_PIN_GROUP(scif0_data),
>  	SH_PFC_PIN_GROUP(scif0_clk),
>  	SH_PFC_PIN_GROUP(scif0_ctrl),
> @@ -3970,6 +3996,12 @@ static const char * const msiof3_groups[] = {
>  	"msiof3_tx",
>  };
> 
> +static const char * const qspi_groups[] = {
> +	"qspi_ctrl",
> +	"qspi_data2",
> +	"qspi_data4",
> +};
> +
>  static const char * const scif0_groups[] = {
>  	"scif0_data",
>  	"scif0_clk",
> @@ -4212,6 +4244,7 @@ static const struct sh_pfc_function pinmux_functions[]
> = { SH_PFC_FUNCTION(msiof0),
>  	SH_PFC_FUNCTION(msiof1),
>  	SH_PFC_FUNCTION(msiof2),
> +	SH_PFC_FUNCTION(qspi),
>  	SH_PFC_FUNCTION(msiof3),

I believe qspi comes after msiof3 :-)

Apart from that the patch looks good.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>  	SH_PFC_FUNCTION(scif0),
>  	SH_PFC_FUNCTION(scif1),

-- 
Regards,

Laurent Pinchart

[PATCH 1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Monday 10 February 2014 11:47:27 Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> 
> A QSPI function set consists of 3 groups:
>   - qspi_ctrl (2 control wires)
>   - qspi_data2 (2 data wires, for Single/Dual SPI)
>   - qspi_data4 (4 data wires, for Quad SPI)
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a7790.c |   33 +++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index c381ae63c508..bc9ced3ccd58
> 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> @@ -2389,6 +2389,29 @@ static const unsigned int msiof3_tx_pins[] = {
>  static const unsigned int msiof3_tx_mux[] = {
>  	MSIOF3_TXD_MARK,
>  };
> +/* - QSPI -------------------------------------------------------------- */
> +static const unsigned int qspi_ctrl_pins[] = {
> +	/* SPCLK, SSL */
> +	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
> +};
> +static const unsigned int qspi_ctrl_mux[] = {
> +	SPCLK_MARK, SSL_MARK,
> +};
> +static const unsigned int qspi_data2_pins[] = {
> +	/* MOSI_IO0, MISO_IO1 */
> +	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
> +};
> +static const unsigned int qspi_data2_mux[] = {
> +	MOSI_IO0_MARK, MISO_IO1_MARK,
> +};
> +static const unsigned int qspi_data4_pins[] = {
> +	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
> +	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +	RCAR_GP_PIN(1, 8),
> +};
> +static const unsigned int qspi_data4_mux[] = {
> +	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
> +};
>  /* - SCIF0 ------------------------------------------------------------- */
> static const unsigned int scif0_data_pins[] = {
>  	/* RX, TX */
> @@ -3671,6 +3694,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] =
> { SH_PFC_PIN_GROUP(msiof3_ss2),
>  	SH_PFC_PIN_GROUP(msiof3_rx),
>  	SH_PFC_PIN_GROUP(msiof3_tx),
> +	SH_PFC_PIN_GROUP(qspi_ctrl),
> +	SH_PFC_PIN_GROUP(qspi_data2),
> +	SH_PFC_PIN_GROUP(qspi_data4),
>  	SH_PFC_PIN_GROUP(scif0_data),
>  	SH_PFC_PIN_GROUP(scif0_clk),
>  	SH_PFC_PIN_GROUP(scif0_ctrl),
> @@ -3970,6 +3996,12 @@ static const char * const msiof3_groups[] = {
>  	"msiof3_tx",
>  };
> 
> +static const char * const qspi_groups[] = {
> +	"qspi_ctrl",
> +	"qspi_data2",
> +	"qspi_data4",
> +};
> +
>  static const char * const scif0_groups[] = {
>  	"scif0_data",
>  	"scif0_clk",
> @@ -4212,6 +4244,7 @@ static const struct sh_pfc_function pinmux_functions[]
> = { SH_PFC_FUNCTION(msiof0),
>  	SH_PFC_FUNCTION(msiof1),
>  	SH_PFC_FUNCTION(msiof2),
> +	SH_PFC_FUNCTION(qspi),
>  	SH_PFC_FUNCTION(msiof3),

I believe qspi comes after msiof3 :-)

Apart from that the patch looks good.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>  	SH_PFC_FUNCTION(scif0),
>  	SH_PFC_FUNCTION(scif1),

-- 
Regards,

Laurent Pinchart

Re: [PATCH 1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups

[Geert Uytterhoeven]

On Mon, Feb 10, 2014 at 1:48 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>> @@ -4212,6 +4244,7 @@ static const struct sh_pfc_function pinmux_functions[]
>> = { SH_PFC_FUNCTION(msiof0),
>>       SH_PFC_FUNCTION(msiof1),
>>       SH_PFC_FUNCTION(msiof2),
>> +     SH_PFC_FUNCTION(qspi),
>>       SH_PFC_FUNCTION(msiof3),
>
> I believe qspi comes after msiof3 :-)

Doh... silly me...

> Apart from that the patch looks good.
>
> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups

[Geert Uytterhoeven]

On Mon, Feb 10, 2014 at 1:48 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>> @@ -4212,6 +4244,7 @@ static const struct sh_pfc_function pinmux_functions[]
>> = { SH_PFC_FUNCTION(msiof0),
>>       SH_PFC_FUNCTION(msiof1),
>>       SH_PFC_FUNCTION(msiof2),
>> +     SH_PFC_FUNCTION(qspi),
>>       SH_PFC_FUNCTION(msiof3),
>
> I believe qspi comes after msiof3 :-)

Doh... silly me...

> Apart from that the patch looks good.
>
> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups

[Geert Uytterhoeven]

On Mon, Feb 10, 2014 at 1:48 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>> @@ -4212,6 +4244,7 @@ static const struct sh_pfc_function pinmux_functions[]
>> = { SH_PFC_FUNCTION(msiof0),
>>       SH_PFC_FUNCTION(msiof1),
>>       SH_PFC_FUNCTION(msiof2),
>> +     SH_PFC_FUNCTION(qspi),
>>       SH_PFC_FUNCTION(msiof3),
>
> I believe qspi comes after msiof3 :-)

Doh... silly me...

> Apart from that the patch looks good.
>
> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[Magnus Damm]

Hi Geert, Simon,

On Mon, Feb 10, 2014 at 7:47 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>         Hi Simon, Magnus,
>
> The following patch series completes r8a7790 SoC and Lager board
> integration for the Renesas Quad Serial Peripheral Interface. It brings
> r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
> to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
> kernels.
>
>     [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
>     [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
>     [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
>     [4/7] ARM: shmobile: lager dts: Add QSPI nodes
>     [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80

Thanks a lot for this! All patches included in this series look great to me.

I noticed that 1/7 turned into a v2, so feel free to omit or include
the below ack.

Acked-by: Magnus Damm <damm@opensource.se>

>     [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
>           FLASH
>     [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
>          FLASH
>
> Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
> dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
> in the linux-spi tree for v3.15.

That makes sense, thanks for pointing that out. You still have my Ack
though, so please include that when you resend.

Simon, can you please pick up 2-5?

Cheers,

/ magnus

Re: [PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[Magnus Damm]

Hi Geert, Simon,

On Mon, Feb 10, 2014 at 7:47 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>         Hi Simon, Magnus,
>
> The following patch series completes r8a7790 SoC and Lager board
> integration for the Renesas Quad Serial Peripheral Interface. It brings
> r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
> to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
> kernels.
>
>     [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
>     [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
>     [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
>     [4/7] ARM: shmobile: lager dts: Add QSPI nodes
>     [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80

Thanks a lot for this! All patches included in this series look great to me.

I noticed that 1/7 turned into a v2, so feel free to omit or include
the below ack.

Acked-by: Magnus Damm <damm@opensource.se>

>     [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
>           FLASH
>     [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
>          FLASH
>
> Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
> dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
> in the linux-spi tree for v3.15.

That makes sense, thanks for pointing that out. You still have my Ack
though, so please include that when you resend.

Simon, can you please pick up 2-5?

Cheers,

/ magnus

[PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[Magnus Damm]

Hi Geert, Simon,

On Mon, Feb 10, 2014 at 7:47 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>         Hi Simon, Magnus,
>
> The following patch series completes r8a7790 SoC and Lager board
> integration for the Renesas Quad Serial Peripheral Interface. It brings
> r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
> to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
> kernels.
>
>     [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
>     [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
>     [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
>     [4/7] ARM: shmobile: lager dts: Add QSPI nodes
>     [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80

Thanks a lot for this! All patches included in this series look great to me.

I noticed that 1/7 turned into a v2, so feel free to omit or include
the below ack.

Acked-by: Magnus Damm <damm@opensource.se>

>     [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
>           FLASH
>     [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
>          FLASH
>
> Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
> dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
> in the linux-spi tree for v3.15.

That makes sense, thanks for pointing that out. You still have my Ack
though, so please include that when you resend.

Simon, can you please pick up 2-5?

Cheers,

/ magnus

Re: [PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[Simon Horman]

On Wed, Feb 12, 2014 at 02:01:01PM +0900, Magnus Damm wrote:
> Hi Geert, Simon,
> 
> On Mon, Feb 10, 2014 at 7:47 PM, Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> >         Hi Simon, Magnus,
> >
> > The following patch series completes r8a7790 SoC and Lager board
> > integration for the Renesas Quad Serial Peripheral Interface. It brings
> > r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
> > to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
> > kernels.
> >
> >     [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
> >     [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
> >     [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
> >     [4/7] ARM: shmobile: lager dts: Add QSPI nodes
> >     [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80
> 
> Thanks a lot for this! All patches included in this series look great to me.
> 
> I noticed that 1/7 turned into a v2, so feel free to omit or include
> the below ack.
> 
> Acked-by: Magnus Damm <damm@opensource.se>
> 
> >     [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
> >           FLASH
> >     [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
> >          FLASH
> >
> > Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
> > dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
> > in the linux-spi tree for v3.15.
> 
> That makes sense, thanks for pointing that out. You still have my Ack
> though, so please include that when you resend.
> 
> Simon, can you please pick up 2-5?

Done.

Re: [PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[Simon Horman]

On Wed, Feb 12, 2014 at 02:01:01PM +0900, Magnus Damm wrote:
> Hi Geert, Simon,
> 
> On Mon, Feb 10, 2014 at 7:47 PM, Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> >         Hi Simon, Magnus,
> >
> > The following patch series completes r8a7790 SoC and Lager board
> > integration for the Renesas Quad Serial Peripheral Interface. It brings
> > r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
> > to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
> > kernels.
> >
> >     [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
> >     [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
> >     [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
> >     [4/7] ARM: shmobile: lager dts: Add QSPI nodes
> >     [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80
> 
> Thanks a lot for this! All patches included in this series look great to me.
> 
> I noticed that 1/7 turned into a v2, so feel free to omit or include
> the below ack.
> 
> Acked-by: Magnus Damm <damm@opensource.se>
> 
> >     [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
> >           FLASH
> >     [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
> >          FLASH
> >
> > Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
> > dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
> > in the linux-spi tree for v3.15.
> 
> That makes sense, thanks for pointing that out. You still have my Ack
> though, so please include that when you resend.
> 
> Simon, can you please pick up 2-5?

Done.

[PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration

[Simon Horman]

On Wed, Feb 12, 2014 at 02:01:01PM +0900, Magnus Damm wrote:
> Hi Geert, Simon,
> 
> On Mon, Feb 10, 2014 at 7:47 PM, Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> >         Hi Simon, Magnus,
> >
> > The following patch series completes r8a7790 SoC and Lager board
> > integration for the Renesas Quad Serial Peripheral Interface. It brings
> > r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
> > to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
> > kernels.
> >
> >     [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
> >     [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
> >     [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
> >     [4/7] ARM: shmobile: lager dts: Add QSPI nodes
> >     [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80
> 
> Thanks a lot for this! All patches included in this series look great to me.
> 
> I noticed that 1/7 turned into a v2, so feel free to omit or include
> the below ack.
> 
> Acked-by: Magnus Damm <damm@opensource.se>
> 
> >     [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
> >           FLASH
> >     [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
> >          FLASH
> >
> > Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
> > dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
> > in the linux-spi tree for v3.15.
> 
> That makes sense, thanks for pointing that out. You still have my Ack
> though, so please include that when you resend.
> 
> Simon, can you please pick up 2-5?

Done.