[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[Chao Xie]

PJ4 is based on V7, but it has some changes. For example, some
coprocessor settings.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
---
 arch/arm/include/asm/cputype.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 42f0889..c651e3b 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -221,4 +221,23 @@ static inline int cpu_is_xsc3(void)
 #define	cpu_is_xscale()	1
 #endif
 
+/*
+ * Marvell's PJ4 core is based on V7 version. It has some modification
+ * for coprocessor setting. For this reason, we need a way to distinguish
+ * it.
+ */
+#ifndef CONFIG_CPU_PJ4
+#define cpu_is_pj4()	0
+#else
+static inline int cpu_is_pj4(void)
+{
+	unsigned int id;
+
+	id = read_cpuid_id();
+	if ((id & 0xfffffff0) == 0x562f5840)
+		return 1;
+
+	return 0;
+}
+#endif
 #endif
-- 
1.8.3.2

[PATCH 2/2] ARM: PJ4: check cpu id for PJ4 cp0 access

[Chao Xie]

Check cpu id in pj4_cp0_init. So for no-PJ4 V7 cpus,
pj4_cpu0_init just return.
This fix will help to make the all the V7 cpus(PJ4 and no-PJ4)
use same platform code.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
---
 arch/arm/kernel/pj4-cp0.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
index 679cf4d..fc72086 100644
--- a/arch/arm/kernel/pj4-cp0.c
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <asm/thread_notify.h>
+#include <asm/cputype.h>
 
 static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
 {
@@ -80,6 +81,9 @@ static int __init pj4_cp0_init(void)
 {
 	u32 cp_access;
 
+	if (!cpu_is_pj4())
+		return 0;
+
 	cp_access = pj4_cp_access_read() & ~0xf;
 	pj4_cp_access_write(cp_access);
 
-- 
1.8.3.2

[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[Stephen Warren]

On 03/21/2014 01:01 AM, Chao Xie wrote:
> PJ4 is based on V7, but it has some changes. For example, some
> coprocessor settings.

The series,
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[Kevin Hilman]

Chao Xie <chao.xie@marvell.com> writes:

> PJ4 is based on V7, but it has some changes. For example, some
> coprocessor settings.
>
> Signed-off-by: Chao Xie <chao.xie@marvell.com>

For this updated series:

Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>

Can you submit this to Russell's patch tracking system ASAP please so we
can fix the multiple boot failures we're seeing in -next.

Thanks,

Kevin

[1] http://www.arm.linux.org.uk/developer/patches/

[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[Matt Porter]

On Fri, Mar 21, 2014 at 03:01:58PM +0800, Chao Xie wrote:
> PJ4 is based on V7, but it has some changes. For example, some
> coprocessor settings.
> 
> Signed-off-by: Chao Xie <chao.xie@marvell.com>

Retested on bcm28155-ap for the updated series:

Tested-by: Matt Porter <mporter@linaro.org>

-Matt

[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[Stephen Warren]

On 03/21/2014 01:01 AM, Chao Xie wrote:
> PJ4 is based on V7, but it has some changes. For example, some
> coprocessor settings.

I don't see this patch in linux-next, yet I think the runtime problem
has gone away somehow. How did that happen?

[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[Kevin Hilman]

Stephen Warren <swarren@wwwdotorg.org> writes:

> On 03/21/2014 01:01 AM, Chao Xie wrote:
>> PJ4 is based on V7, but it has some changes. For example, some
>> coprocessor settings.
>
> I don't see this patch in linux-next, yet I think the runtime problem
> has gone away somehow. How did that happen?

The multi_v7 change that introduced the regression (addtion of
MACH_DOVE) was reverted in arm-soc/for-next while waiting for the patch
to be submitted to Russell's tracker.

Looks like they've now been submitted to the tracker, so hopefully
Russell will get to them on his next pass.  They'll be needed for v3.15.

Kevin

[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[Thomas Petazzoni]

Dear Chao Xie,

On Fri, 21 Mar 2014 15:01:58 +0800, Chao Xie wrote:

> +/*
> + * Marvell's PJ4 core is based on V7 version. It has some modification
> + * for coprocessor setting. For this reason, we need a way to distinguish
> + * it.
> + */
> +#ifndef CONFIG_CPU_PJ4
> +#define cpu_is_pj4()	0
> +#else
> +static inline int cpu_is_pj4(void)
> +{
> +	unsigned int id;
> +
> +	id = read_cpuid_id();
> +	if ((id & 0xfffffff0) == 0x562f5840)
> +		return 1;

Unfortunately, this doesn't work correctly, because this cpuid check
also matches Armada XP, which uses the PJ4B-MP core, but does not have
the iWMMXt extension. Therefore, when you build mach-mvebu with Dove
support enabled, it does not boot on Armada XP: it fails with an
undefined instruction.

Also, I believe the test is not sufficient because the Dove Armada 510
uses a PJ4 core, but is not matched by the above test.

For reference, the cpuid of various platforms:

 * Armada XP, PJ4B-MP core, 0x562f5842
 * Armada 370, PJ4B core, 0x561f5811
 * Dove Armada 510, PJ4 core, 560f5815

Can you check on your platforms what was the exact cpuid, to see if we
can find a way of correcting this cpu_is_pj4() function? Can you also
check whether your CPU uses a PJ4, PJ4B or PJ4B-MP core?

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[Russell King - ARM Linux]

On Mon, Apr 14, 2014 at 03:12:36PM +0200, Thomas Petazzoni wrote:
> Dear Chao Xie,
> 
> On Fri, 21 Mar 2014 15:01:58 +0800, Chao Xie wrote:
> 
> > +/*
> > + * Marvell's PJ4 core is based on V7 version. It has some modification
> > + * for coprocessor setting. For this reason, we need a way to distinguish
> > + * it.
> > + */
> > +#ifndef CONFIG_CPU_PJ4
> > +#define cpu_is_pj4()	0
> > +#else
> > +static inline int cpu_is_pj4(void)
> > +{
> > +	unsigned int id;
> > +
> > +	id = read_cpuid_id();
> > +	if ((id & 0xfffffff0) == 0x562f5840)
> > +		return 1;
> 
> Unfortunately, this doesn't work correctly, because this cpuid check
> also matches Armada XP, which uses the PJ4B-MP core, but does not have
> the iWMMXt extension. Therefore, when you build mach-mvebu with Dove
> support enabled, it does not boot on Armada XP: it fails with an
> undefined instruction.

Grr, that's annoying.  And we can't just revert this because of the
arm-soc debacle - doing so will break the boot for a whole pile of
other platforms.

This is a nice illustration of why the arm-soc process - with arm-soc
effectively *forcing* me to take patches - is rather broken.  I hope
arm-soc people start behaving more responsibly in the future.

-- 
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

[PATCH 1/2] ARM: add cpu_is_pj4() to distinguish PJ4 core

[Arnd Bergmann]

On Monday 14 April 2014 14:43:53 Russell King - ARM Linux wrote:
> On Mon, Apr 14, 2014 at 03:12:36PM +0200, Thomas Petazzoni wrote:
> > Dear Chao Xie,
> > 
> > On Fri, 21 Mar 2014 15:01:58 +0800, Chao Xie wrote:
> > 
> > > +/*
> > > + * Marvell's PJ4 core is based on V7 version. It has some modification
> > > + * for coprocessor setting. For this reason, we need a way to distinguish
> > > + * it.
> > > + */
> > > +#ifndef CONFIG_CPU_PJ4
> > > +#define cpu_is_pj4()       0
> > > +#else
> > > +static inline int cpu_is_pj4(void)
> > > +{
> > > +   unsigned int id;
> > > +
> > > +   id = read_cpuid_id();
> > > +   if ((id & 0xfffffff0) == 0x562f5840)
> > > +           return 1;
> > 
> > Unfortunately, this doesn't work correctly, because this cpuid check
> > also matches Armada XP, which uses the PJ4B-MP core, but does not have
> > the iWMMXt extension. Therefore, when you build mach-mvebu with Dove
> > support enabled, it does not boot on Armada XP: it fails with an
> > undefined instruction.
> 
> Grr, that's annoying.  And we can't just revert this because of the
> arm-soc debacle - doing so will break the boot for a whole pile of
> other platforms.

It is very unfortunate that the bug didn't get caught earlier in order
to get fixed before the merge window. Having Marvell Dove enabled in
multi_v7_defconfig in the branch I submitted to Linus was a stupid
mistake of mine, no malicious intentions, and I already apologized
for that before.

> This is a nice illustration of why the arm-soc process - with arm-soc
> effectively *forcing* me to take patches - is rather broken.  I hope
> arm-soc people start behaving more responsibly in the future.

Do you have a better idea?

We could for the moment make Dove mutually exclusive with the other
platforms it breaks in Kconfig for the moment if you think that would
be better. That would at least avoid the regression against 3.14
at the expense of losing the dove multiplatform support.

We can then decide later after we have a proper fix whether we are
confident enough that it works in all cases, or whether it's too
late for 3.15 by then.

	Arnd

[PATCH 0/5] fixing regressions caused by Dove in MULTI_V7

[Sebastian Hesselbarth]

This is a patch set fixing regressions in v3.15-rc1 ultimately caused
by adding DT-enabled Marvell Dove to MULTI_V7. There was a fix
introduced late in the merge window to fix a related regression for
non-PJ4 architectures, that turned out to introduce another regression
on PJ4B-based Armada 370/XP.

Therefore, this now takes care of iWMMXt and PJ4[B] related code to
properly fix all regressions observed in v3.15-rc1. At the end, one
patch adding support for iWMMXt on PJ4B as found on Marvell Berlin
BG2 SoCs is added.

Patch 1 reworks iwmmxt.S preprocessor directives to allow to build
it only if a supported platform is enabled. Also, it rewrites them
to explicitly check for all CPUs of the currently supported
architectures.

Patch 2 fixes pj4_cp0_init to only enable iWMMXt capabilities, if
corresponding kernel support code is also enabled by CONFIG_IWMMXT.

Patch 3 fixes pj4_cp0_init to properly perform runtime checks for
absence/presence of iWMMXt coprocessor. This effectively fixes
boot regressions observed on Armada 370/XP.

Patch 4 fixes cpu_is_pj4's cpuid check to check for both PJ4 and
PJ4B. This effectively fixes iWMMXt support on MULTI_V7 Dove.

Patch 5 finally allows PJ4B to also enable iWMMXt support as there
are some PJ4B based SoCs, e.g. Marvell Armada 1500, that have those
coprocessors. This is _not_ a fix but an improvement and should be
treated as such, i.e. taken for v3.16.

As a side note, after looking into this: if XScale based SoCs also
properly perform runtime checks for iWMMXt presence, I'd be
interested on comments if iWMMXt can possibly also be reworked to
be build as a module dynamically adding/removing iWMMXt support?

I expect proper Tested-by's for Armada 370/XP, where some
preliminary patches have been boot tested by Thomas Petazzoni.
I boot tested it on Marvell Dove and Marvell Berlin BG2.
Any Tested-by's from XScale and/or non-PJ4[B] architectures are
also appreciated.

Russell, please let me know if/when you are happy with the fixes
and the improvement. I'll be adding them to your patch tracker then.

Sebastian

Sebastian Hesselbarth (5):
  ARM: iwmmxt: explicitly check for supported architectures
  ARM: pj4: enable iWMMXt only if CONFIG_IWMMXT is set
  ARM: pj4: properly detect existence of iWMMXt coprocessor
  ARM: pj4: fix cpu_is_pj4 check
  ARM: iwmmxt: allow to build iWMMXt on Marvell PJ4B

 arch/arm/Kconfig               |  6 +++---
 arch/arm/include/asm/cputype.h | 14 +++++++-------
 arch/arm/kernel/Makefile       |  1 +
 arch/arm/kernel/iwmmxt.S       |  8 ++++++--
 arch/arm/kernel/pj4-cp0.c      | 42 +++++++++++++++++++++++++++++++++++++++---
 5 files changed, 56 insertions(+), 15 deletions(-)

---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
-- 
1.9.1

[PATCH 0/5] fixing regressions caused by Dove in MULTI_V7

[Sebastian Hesselbarth]

This is a patch set fixing regressions in v3.15-rc1 ultimately caused
by adding DT-enabled Marvell Dove to MULTI_V7. There was a fix
introduced late in the merge window to fix a related regression for
non-PJ4 architectures, that turned out to introduce another regression
on PJ4B-based Armada 370/XP.

Therefore, this now takes care of iWMMXt and PJ4[B] related code to
properly fix all regressions observed in v3.15-rc1. At the end, one
patch adding support for iWMMXt on PJ4B as found on Marvell Berlin
BG2 SoCs is added.

Patch 1 reworks iwmmxt.S preprocessor directives to allow to build
it only if a supported platform is enabled. Also, it rewrites them
to explicitly check for all CPUs of the currently supported
architectures.

Patch 2 fixes pj4_cp0_init to only enable iWMMXt capabilities, if
corresponding kernel support code is also enabled by CONFIG_IWMMXT.

Patch 3 fixes pj4_cp0_init to properly perform runtime checks for
absence/presence of iWMMXt coprocessor. This effectively fixes
boot regressions observed on Armada 370/XP.

Patch 4 fixes cpu_is_pj4's cpuid check to check for both PJ4 and
PJ4B. This effectively fixes iWMMXt support on MULTI_V7 Dove.

Patch 5 finally allows PJ4B to also enable iWMMXt support as there
are some PJ4B based SoCs, e.g. Marvell Armada 1500, that have those
coprocessors. This is _not_ a fix but an improvement and should be
treated as such, i.e. taken for v3.16.

As a side note, after looking into this: if XScale based SoCs also
properly perform runtime checks for iWMMXt presence, I'd be
interested on comments if iWMMXt can possibly also be reworked to
be build as a module dynamically adding/removing iWMMXt support?

I expect proper Tested-by's for Armada 370/XP, where some
preliminary patches have been boot tested by Thomas Petazzoni.
I boot tested it on Marvell Dove and Marvell Berlin BG2.
Any Tested-by's from XScale and/or non-PJ4[B] architectures are
also appreciated.

Russell, please let me know if/when you are happy with the fixes
and the improvement. I'll be adding them to your patch tracker then.

Sebastian

Sebastian Hesselbarth (5):
  ARM: iwmmxt: explicitly check for supported architectures
  ARM: pj4: enable iWMMXt only if CONFIG_IWMMXT is set
  ARM: pj4: properly detect existence of iWMMXt coprocessor
  ARM: pj4: fix cpu_is_pj4 check
  ARM: iwmmxt: allow to build iWMMXt on Marvell PJ4B

 arch/arm/Kconfig               |  6 +++---
 arch/arm/include/asm/cputype.h | 14 +++++++-------
 arch/arm/kernel/Makefile       |  1 +
 arch/arm/kernel/iwmmxt.S       |  8 ++++++--
 arch/arm/kernel/pj4-cp0.c      | 42 +++++++++++++++++++++++++++++++++++++++---
 5 files changed, 56 insertions(+), 15 deletions(-)

---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
-- 
1.9.1

[PATCH 1/5] ARM: iwmmxt: explicitly check for supported architectures

[Sebastian Hesselbarth]

iwmmxt.S requires special treatment of coprocessor access registers
for PJ4 and XScale-based CPUs. It only checks for CPU_PJ4 and drops
down to XScale-based treatment on all other architectures.

As some PJ4B also come with iWMMXt and also need PJ4 treatment,
rework the corresponding preprocessor directives to explicitly
check for supported architectures and fail on unsupported ones.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/kernel/iwmmxt.S | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index a08783823b32..2452dd1bef53 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -19,12 +19,16 @@
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
 
-#if defined(CONFIG_CPU_PJ4)
+#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 #define PJ4(code...)		code
 #define XSC(code...)
-#else
+#elif defined(CONFIG_CPU_MOHAWK) || \
+	defined(CONFIG_CPU_XSC3) || \
+	defined(CONFIG_CPU_XSCALE)
 #define PJ4(code...)
 #define XSC(code...)		code
+#else
+#error "Unsupported iWMMXt architecture"
 #endif
 
 #define MMX_WR0		 	(0x00)
-- 
1.9.1

[PATCH 1/5] ARM: iwmmxt: explicitly check for supported architectures

[Sebastian Hesselbarth]

iwmmxt.S requires special treatment of coprocessor access registers
for PJ4 and XScale-based CPUs. It only checks for CPU_PJ4 and drops
down to XScale-based treatment on all other architectures.

As some PJ4B also come with iWMMXt and also need PJ4 treatment,
rework the corresponding preprocessor directives to explicitly
check for supported architectures and fail on unsupported ones.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/kernel/iwmmxt.S | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index a08783823b32..2452dd1bef53 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -19,12 +19,16 @@
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
 
-#if defined(CONFIG_CPU_PJ4)
+#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 #define PJ4(code...)		code
 #define XSC(code...)
-#else
+#elif defined(CONFIG_CPU_MOHAWK) || \
+	defined(CONFIG_CPU_XSC3) || \
+	defined(CONFIG_CPU_XSCALE)
 #define PJ4(code...)
 #define XSC(code...)		code
+#else
+#error "Unsupported iWMMXt architecture"
 #endif
 
 #define MMX_WR0		 	(0x00)
-- 
1.9.1

[PATCH 2/5] ARM: pj4: enable iWMMXt only if CONFIG_IWMMXT is set

[Sebastian Hesselbarth]

This fixes PJ4 coprocessor init to only expose iWMMXt capabilities,
if the corresponding kernel support for iWMMXt is enabled.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/kernel/pj4-cp0.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
index fc7208636284..12352cd30ab2 100644
--- a/arch/arm/kernel/pj4-cp0.c
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -45,7 +45,7 @@ static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
 	return NOTIFY_DONE;
 }
 
-static struct notifier_block iwmmxt_notifier_block = {
+static struct notifier_block __maybe_unused iwmmxt_notifier_block = {
 	.notifier_call	= iwmmxt_do,
 };
 
@@ -79,17 +79,21 @@ static void __init pj4_cp_access_write(u32 value)
  */
 static int __init pj4_cp0_init(void)
 {
-	u32 cp_access;
+	u32 __maybe_unused cp_access;
 
 	if (!cpu_is_pj4())
 		return 0;
 
+#ifndef CONFIG_IWMMXT
+	pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n");
+#else
 	cp_access = pj4_cp_access_read() & ~0xf;
 	pj4_cp_access_write(cp_access);
 
 	printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
 	elf_hwcap |= HWCAP_IWMMXT;
 	thread_register_notifier(&iwmmxt_notifier_block);
+#endif
 
 	return 0;
 }
-- 
1.9.1

[PATCH 2/5] ARM: pj4: enable iWMMXt only if CONFIG_IWMMXT is set

[Sebastian Hesselbarth]

This fixes PJ4 coprocessor init to only expose iWMMXt capabilities,
if the corresponding kernel support for iWMMXt is enabled.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/kernel/pj4-cp0.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
index fc7208636284..12352cd30ab2 100644
--- a/arch/arm/kernel/pj4-cp0.c
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -45,7 +45,7 @@ static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
 	return NOTIFY_DONE;
 }
 
-static struct notifier_block iwmmxt_notifier_block = {
+static struct notifier_block __maybe_unused iwmmxt_notifier_block = {
 	.notifier_call	= iwmmxt_do,
 };
 
@@ -79,17 +79,21 @@ static void __init pj4_cp_access_write(u32 value)
  */
 static int __init pj4_cp0_init(void)
 {
-	u32 cp_access;
+	u32 __maybe_unused cp_access;
 
 	if (!cpu_is_pj4())
 		return 0;
 
+#ifndef CONFIG_IWMMXT
+	pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n");
+#else
 	cp_access = pj4_cp_access_read() & ~0xf;
 	pj4_cp_access_write(cp_access);
 
 	printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
 	elf_hwcap |= HWCAP_IWMMXT;
 	thread_register_notifier(&iwmmxt_notifier_block);
+#endif
 
 	return 0;
 }
-- 
1.9.1

[PATCH 3/5] ARM: pj4: properly detect existence of iWMMXt coprocessor

[Sebastian Hesselbarth]

commit fdb487f5c961b94486a78fa61fa28b8eff1954ab
  ("ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it
    has some differences with V7")
introduced a fix for checking PJ4 cpuid to not use PJ4 specific
coprocessor access on non-PJ4 platforms.

Unfortunately, this in turn broke Marvell Armada 370/XP, both
comprising Marvell PJ4B CPUs without iWMMXt extension. Instead
of only checking for cpuid, which may not be sufficient to
determine iWMMXt support, the presence of iWMMXt coprocessors
can be checked by enabling and reading the Coprocessor ID
register (wCID, register 0 of CP1).

Therefore this adds an explicit check for the presence and correct
wCID value, before enabling iWMMXt capabilities. As a bonus, also
print the iWMMXt version of a detected coprocessor.

This has been tested to properly detect iWMMXt presence/absence on:
- PJ4,  CPUID 0x560f5815, wCID 0x56052001: Marvell Dove, iWMMXt v2
- PJ4B, CPUID 0x561f5811: Marvell Armada 370, no iWMMXt
- PJ4B, CPUID 0x562f5841, wCID 0x56052001: Marvell Armada 1500, iWMMXt v2
- PJ4B, CPUID 0x562f5842: Marvell Armada XP, no iWMMXt

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/kernel/pj4-cp0.c | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
index 12352cd30ab2..8153e36b2491 100644
--- a/arch/arm/kernel/pj4-cp0.c
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -72,6 +72,33 @@ static void __init pj4_cp_access_write(u32 value)
 		: "=r" (temp) : "r" (value));
 }
 
+static int __init pj4_get_iwmmxt_version(void)
+{
+	u32 cp_access, wcid;
+
+	cp_access = pj4_cp_access_read();
+	pj4_cp_access_write(cp_access | 0xf);
+
+	/* check if coprocessor 0 and 1 are available */
+	if ((pj4_cp_access_read() & 0xf) != 0xf) {
+		pj4_cp_access_write(cp_access);
+		return -ENODEV;
+	}
+
+	/* read iWMMXt coprocessor id register p1, c0 */
+	__asm__ __volatile__ ("mrc    p1, 0, %0, c0, c0, 0\n" : "=r" (wcid));
+
+	pj4_cp_access_write(cp_access);
+
+	/* iWMMXt v1 */
+	if ((wcid & 0xffffff00) == 0x56051000)
+		return 1;
+	/* iWMMXt v2 */
+	if ((wcid & 0xffffff00) == 0x56052000)
+		return 2;
+
+	return -EINVAL;
+}
 
 /*
  * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
@@ -80,17 +107,22 @@ static void __init pj4_cp_access_write(u32 value)
 static int __init pj4_cp0_init(void)
 {
 	u32 __maybe_unused cp_access;
+	int vers;
 
 	if (!cpu_is_pj4())
 		return 0;
 
+	vers = pj4_get_iwmmxt_version();
+	if (vers < 0)
+		return 0;
+
 #ifndef CONFIG_IWMMXT
 	pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n");
 #else
 	cp_access = pj4_cp_access_read() & ~0xf;
 	pj4_cp_access_write(cp_access);
 
-	printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
+	pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers);
 	elf_hwcap |= HWCAP_IWMMXT;
 	thread_register_notifier(&iwmmxt_notifier_block);
 #endif
-- 
1.9.1

[PATCH 3/5] ARM: pj4: properly detect existence of iWMMXt coprocessor

[Sebastian Hesselbarth]

commit fdb487f5c961b94486a78fa61fa28b8eff1954ab
  ("ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it
    has some differences with V7")
introduced a fix for checking PJ4 cpuid to not use PJ4 specific
coprocessor access on non-PJ4 platforms.

Unfortunately, this in turn broke Marvell Armada 370/XP, both
comprising Marvell PJ4B CPUs without iWMMXt extension. Instead
of only checking for cpuid, which may not be sufficient to
determine iWMMXt support, the presence of iWMMXt coprocessors
can be checked by enabling and reading the Coprocessor ID
register (wCID, register 0 of CP1).

Therefore this adds an explicit check for the presence and correct
wCID value, before enabling iWMMXt capabilities. As a bonus, also
print the iWMMXt version of a detected coprocessor.

This has been tested to properly detect iWMMXt presence/absence on:
- PJ4,  CPUID 0x560f5815, wCID 0x56052001: Marvell Dove, iWMMXt v2
- PJ4B, CPUID 0x561f5811: Marvell Armada 370, no iWMMXt
- PJ4B, CPUID 0x562f5841, wCID 0x56052001: Marvell Armada 1500, iWMMXt v2
- PJ4B, CPUID 0x562f5842: Marvell Armada XP, no iWMMXt

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/kernel/pj4-cp0.c | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
index 12352cd30ab2..8153e36b2491 100644
--- a/arch/arm/kernel/pj4-cp0.c
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -72,6 +72,33 @@ static void __init pj4_cp_access_write(u32 value)
 		: "=r" (temp) : "r" (value));
 }
 
+static int __init pj4_get_iwmmxt_version(void)
+{
+	u32 cp_access, wcid;
+
+	cp_access = pj4_cp_access_read();
+	pj4_cp_access_write(cp_access | 0xf);
+
+	/* check if coprocessor 0 and 1 are available */
+	if ((pj4_cp_access_read() & 0xf) != 0xf) {
+		pj4_cp_access_write(cp_access);
+		return -ENODEV;
+	}
+
+	/* read iWMMXt coprocessor id register p1, c0 */
+	__asm__ __volatile__ ("mrc    p1, 0, %0, c0, c0, 0\n" : "=r" (wcid));
+
+	pj4_cp_access_write(cp_access);
+
+	/* iWMMXt v1 */
+	if ((wcid & 0xffffff00) == 0x56051000)
+		return 1;
+	/* iWMMXt v2 */
+	if ((wcid & 0xffffff00) == 0x56052000)
+		return 2;
+
+	return -EINVAL;
+}
 
 /*
  * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
@@ -80,17 +107,22 @@ static void __init pj4_cp_access_write(u32 value)
 static int __init pj4_cp0_init(void)
 {
 	u32 __maybe_unused cp_access;
+	int vers;
 
 	if (!cpu_is_pj4())
 		return 0;
 
+	vers = pj4_get_iwmmxt_version();
+	if (vers < 0)
+		return 0;
+
 #ifndef CONFIG_IWMMXT
 	pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n");
 #else
 	cp_access = pj4_cp_access_read() & ~0xf;
 	pj4_cp_access_write(cp_access);
 
-	printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
+	pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers);
 	elf_hwcap |= HWCAP_IWMMXT;
 	thread_register_notifier(&iwmmxt_notifier_block);
 #endif
-- 
1.9.1

[PATCH 4/5] ARM: pj4: fix cpu_is_pj4 check

[Sebastian Hesselbarth]

Commit fdb487f5c961b94486a78fa61fa28b8eff1954ab
  ("ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it
    has some differences with V7")
introduced a cpuid check for Marvell PJ4 processors to fix a
regression caused by adding PJ4 based Marvell Dove into
multi_v7.

Unfortunately, this check is too narrow to catch PJ4 used on
Dove itself and breaks iWMMXt support.

This patch therefore relaxes the cpuid mask to match both PJ4
and PJ4B. Also, rework the given comment about PJ4/PJ4B
modifications to be a little bit more specific about the
differences.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/include/asm/cputype.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index c651e3b26ec7..4764344367d4 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -222,22 +222,22 @@ static inline int cpu_is_xsc3(void)
 #endif
 
 /*
- * Marvell's PJ4 core is based on V7 version. It has some modification
- * for coprocessor setting. For this reason, we need a way to distinguish
- * it.
+ * Marvell's PJ4 and PJ4B cores are based on V7 version,
+ * but require a specical sequence for enabling coprocessors.
+ * For this reason, we need a way to distinguish them.
  */
-#ifndef CONFIG_CPU_PJ4
-#define cpu_is_pj4()	0
-#else
+#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 static inline int cpu_is_pj4(void)
 {
 	unsigned int id;
 
 	id = read_cpuid_id();
-	if ((id & 0xfffffff0) == 0x562f5840)
+	if ((id & 0xff0fff00) == 0x560f5800)
 		return 1;
 
 	return 0;
 }
+#else
+#define cpu_is_pj4()	0
 #endif
 #endif
-- 
1.9.1

[PATCH 4/5] ARM: pj4: fix cpu_is_pj4 check

[Sebastian Hesselbarth]

Commit fdb487f5c961b94486a78fa61fa28b8eff1954ab
  ("ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it
    has some differences with V7")
introduced a cpuid check for Marvell PJ4 processors to fix a
regression caused by adding PJ4 based Marvell Dove into
multi_v7.

Unfortunately, this check is too narrow to catch PJ4 used on
Dove itself and breaks iWMMXt support.

This patch therefore relaxes the cpuid mask to match both PJ4
and PJ4B. Also, rework the given comment about PJ4/PJ4B
modifications to be a little bit more specific about the
differences.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/include/asm/cputype.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index c651e3b26ec7..4764344367d4 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -222,22 +222,22 @@ static inline int cpu_is_xsc3(void)
 #endif
 
 /*
- * Marvell's PJ4 core is based on V7 version. It has some modification
- * for coprocessor setting. For this reason, we need a way to distinguish
- * it.
+ * Marvell's PJ4 and PJ4B cores are based on V7 version,
+ * but require a specical sequence for enabling coprocessors.
+ * For this reason, we need a way to distinguish them.
  */
-#ifndef CONFIG_CPU_PJ4
-#define cpu_is_pj4()	0
-#else
+#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 static inline int cpu_is_pj4(void)
 {
 	unsigned int id;
 
 	id = read_cpuid_id();
-	if ((id & 0xfffffff0) == 0x562f5840)
+	if ((id & 0xff0fff00) == 0x560f5800)
 		return 1;
 
 	return 0;
 }
+#else
+#define cpu_is_pj4()	0
 #endif
 #endif
-- 
1.9.1

[PATCH 5/5] ARM: iwmmxt: allow to build iWMMXt on Marvell PJ4B

[Sebastian Hesselbarth]

Some Marvell PJ4B CPUs also implement iWMMXt extensions. With a
proper check for iWMMXt coprocessors now in place, enable it by
default on PJ4B. While at it, also allow to manually select
the corresponding Kconfig option.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/Kconfig         | 6 +++---
 arch/arm/kernel/Makefile | 1 +
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab438cb5af55..fcf36d11f922 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1110,9 +1110,9 @@ config ARM_NR_BANKS
 	default 8
 
 config IWMMXT
-	bool "Enable iWMMXt support" if !CPU_PJ4
-	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
-	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
+	bool "Enable iWMMXt support"
+	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
+	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 	help
 	  Enable support for iWMMXt context switching at run time if
 	  running on a CPU that supports it.
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index a766bcbaf8ad..040619c32d68 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -79,6 +79,7 @@ obj-$(CONFIG_CPU_XSCALE)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)		+= xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_PJ4)		+= pj4-cp0.o
+obj-$(CONFIG_CPU_PJ4B)		+= pj4-cp0.o
 obj-$(CONFIG_IWMMXT)		+= iwmmxt.o
 obj-$(CONFIG_PERF_EVENTS)	+= perf_regs.o
 obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o perf_event_cpu.o
-- 
1.9.1

[PATCH 5/5] ARM: iwmmxt: allow to build iWMMXt on Marvell PJ4B

[Sebastian Hesselbarth]

Some Marvell PJ4B CPUs also implement iWMMXt extensions. With a
proper check for iWMMXt coprocessors now in place, enable it by
default on PJ4B. While at it, also allow to manually select
the corresponding Kconfig option.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/Kconfig         | 6 +++---
 arch/arm/kernel/Makefile | 1 +
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab438cb5af55..fcf36d11f922 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1110,9 +1110,9 @@ config ARM_NR_BANKS
 	default 8
 
 config IWMMXT
-	bool "Enable iWMMXt support" if !CPU_PJ4
-	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
-	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
+	bool "Enable iWMMXt support"
+	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
+	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 	help
 	  Enable support for iWMMXt context switching at run time if
 	  running on a CPU that supports it.
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index a766bcbaf8ad..040619c32d68 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -79,6 +79,7 @@ obj-$(CONFIG_CPU_XSCALE)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)		+= xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_PJ4)		+= pj4-cp0.o
+obj-$(CONFIG_CPU_PJ4B)		+= pj4-cp0.o
 obj-$(CONFIG_IWMMXT)		+= iwmmxt.o
 obj-$(CONFIG_PERF_EVENTS)	+= perf_regs.o
 obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o perf_event_cpu.o
-- 
1.9.1

Re: [PATCH 0/5] fixing regressions caused by Dove in MULTI_V7

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Tue, 15 Apr 2014 20:15:58 +0200, Sebastian Hesselbarth wrote:

> Sebastian Hesselbarth (5):
>   ARM: iwmmxt: explicitly check for supported architectures
>   ARM: pj4: enable iWMMXt only if CONFIG_IWMMXT is set
>   ARM: pj4: properly detect existence of iWMMXt coprocessor
>   ARM: pj4: fix cpu_is_pj4 check
>   ARM: iwmmxt: allow to build iWMMXt on Marvell PJ4B

Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>.

It does fix the boot on PJ4B-MP based processors that don't have iWMMXt
extensions such as the Armada XP. I've tested the following cases:

 * Armada XP (PJ4B-MP), with CONFIG_MACH_DOVE disabled and enabled
 * Armada 370 (PJ4B), with CONFIG_MACH_DOVE disabled and enabled

and all of them boot, while before your patch series, 3.15-rc1 fails to
boot on Armada XP with CONFIG_MACH_DOVE enabled.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 0/5] fixing regressions caused by Dove in MULTI_V7

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Tue, 15 Apr 2014 20:15:58 +0200, Sebastian Hesselbarth wrote:

> Sebastian Hesselbarth (5):
>   ARM: iwmmxt: explicitly check for supported architectures
>   ARM: pj4: enable iWMMXt only if CONFIG_IWMMXT is set
>   ARM: pj4: properly detect existence of iWMMXt coprocessor
>   ARM: pj4: fix cpu_is_pj4 check
>   ARM: iwmmxt: allow to build iWMMXt on Marvell PJ4B

Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>.

It does fix the boot on PJ4B-MP based processors that don't have iWMMXt
extensions such as the Armada XP. I've tested the following cases:

 * Armada XP (PJ4B-MP), with CONFIG_MACH_DOVE disabled and enabled
 * Armada 370 (PJ4B), with CONFIG_MACH_DOVE disabled and enabled

and all of them boot, while before your patch series, 3.15-rc1 fails to
boot on Armada XP with CONFIG_MACH_DOVE enabled.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH 0/5] fixing regressions caused by Dove in MULTI_V7

[Thomas Petazzoni]

Sebastian, Russell,

On Tue, 15 Apr 2014 20:15:58 +0200, Sebastian Hesselbarth wrote:
> This is a patch set fixing regressions in v3.15-rc1 ultimately caused
> by adding DT-enabled Marvell Dove to MULTI_V7. There was a fix
> introduced late in the merge window to fix a related regression for
> non-PJ4 architectures, that turned out to introduce another regression
> on PJ4B-based Armada 370/XP.

[...]

> Russell, please let me know if/when you are happy with the fixes
> and the improvement. I'll be adding them to your patch tracker then.

Any plans towards merging those patches, or at least PATCH 1 to 4 ?
They fix a regression on 3.15-r1 affecting mvebu platforms, and it
would be good to have that fixed by 3.15 final.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 0/5] fixing regressions caused by Dove in MULTI_V7

[Thomas Petazzoni]

Sebastian, Russell,

On Tue, 15 Apr 2014 20:15:58 +0200, Sebastian Hesselbarth wrote:
> This is a patch set fixing regressions in v3.15-rc1 ultimately caused
> by adding DT-enabled Marvell Dove to MULTI_V7. There was a fix
> introduced late in the merge window to fix a related regression for
> non-PJ4 architectures, that turned out to introduce another regression
> on PJ4B-based Armada 370/XP.

[...]

> Russell, please let me know if/when you are happy with the fixes
> and the improvement. I'll be adding them to your patch tracker then.

Any plans towards merging those patches, or at least PATCH 1 to 4 ?
They fix a regression on 3.15-r1 affecting mvebu platforms, and it
would be good to have that fixed by 3.15 final.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH 0/5] fixing regressions caused by Dove in MULTI_V7

[Kevin Hilman]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> This is a patch set fixing regressions in v3.15-rc1 ultimately caused
> by adding DT-enabled Marvell Dove to MULTI_V7. There was a fix
> introduced late in the merge window to fix a related regression for
> non-PJ4 architectures, that turned out to introduce another regression
> on PJ4B-based Armada 370/XP.

Tested-by: Kevin Hilman <khilman@linaro.org>

FWIW, I tested this series on top of v3.15-rc1 using multi_v7_defconfig
on all of multi-platform boards I have (20), and they all passed the
boot test.  Full boot report below.

Kevin


Subject: test/dove-regression boot: 20 pass, 0 fail (v3.15-rc1-5-gc1d3c1beba74)

Tree/Branch: test/dove-regression
Git describe: v3.15-rc1-5-gc1d3c1beba74
Commit: c1d3c1beba ARM: iwmmxt: allow to build iWMMXt on Marvell PJ4B

Full Report
===========

arm-multi_v7_defconfig
----------------------
    qcom-apq8074-dragonboard     0 min 15.7 sec:     PASS
                ste-snowball     1 min 20.5 sec:     PASS
              tegra30-beaver     0 min 17.1 sec:     PASS
            am335x-boneblack     0 min 37.7 sec:     PASS
             omap3-beagle-xm     0 min 47.5 sec:     PASS
       sun7i-a20-cubieboard2     0 min 12.4 sec:     PASS
          armada-370-mirabox     0 min 22.4 sec:     PASS
                 omap4-panda     0 min 58.2 sec:     PASS
  armada-xp-openblocks-ax3-4     0 min 25.2 sec:     PASS
        sun4i-a10-cubieboard     0 min 19.1 sec:     PASS
                 bcm28155-ap     0 min 27.8 sec:     PASS
            omap3-overo-tobi     0 min 22.3 sec:     PASS  (Warnings: 1)
  imx6dl-wandboard,wand-solo     0 min 18.2 sec:     PASS
                 am335x-bone     0 min 26.7 sec:     PASS
      omap3-overo-storm-tobi     0 min 20.9 sec:     PASS
                  omap5-uevm     1 min 40.0 sec:     PASS  (Warnings: 1)
                  omap3-n900     0 min 34.5 sec:     PASS  (Warnings: 1)
             imx6q-wandboard     0 min 17.2 sec:     PASS
              omap4-panda-es     0 min 54.5 sec:     PASS
  imx6dl-wandboard,wand-dual     0 min 18.1 sec:     PASS

[PATCH 0/5] fixing regressions caused by Dove in MULTI_V7

[Kevin Hilman]

Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> writes:

> This is a patch set fixing regressions in v3.15-rc1 ultimately caused
> by adding DT-enabled Marvell Dove to MULTI_V7. There was a fix
> introduced late in the merge window to fix a related regression for
> non-PJ4 architectures, that turned out to introduce another regression
> on PJ4B-based Armada 370/XP.

Tested-by: Kevin Hilman <khilman@linaro.org>

FWIW, I tested this series on top of v3.15-rc1 using multi_v7_defconfig
on all of multi-platform boards I have (20), and they all passed the
boot test.  Full boot report below.

Kevin


Subject: test/dove-regression boot: 20 pass, 0 fail (v3.15-rc1-5-gc1d3c1beba74)

Tree/Branch: test/dove-regression
Git describe: v3.15-rc1-5-gc1d3c1beba74
Commit: c1d3c1beba ARM: iwmmxt: allow to build iWMMXt on Marvell PJ4B

Full Report
===========

arm-multi_v7_defconfig
----------------------
    qcom-apq8074-dragonboard     0 min 15.7 sec:     PASS
                ste-snowball     1 min 20.5 sec:     PASS
              tegra30-beaver     0 min 17.1 sec:     PASS
            am335x-boneblack     0 min 37.7 sec:     PASS
             omap3-beagle-xm     0 min 47.5 sec:     PASS
       sun7i-a20-cubieboard2     0 min 12.4 sec:     PASS
          armada-370-mirabox     0 min 22.4 sec:     PASS
                 omap4-panda     0 min 58.2 sec:     PASS
  armada-xp-openblocks-ax3-4     0 min 25.2 sec:     PASS
        sun4i-a10-cubieboard     0 min 19.1 sec:     PASS
                 bcm28155-ap     0 min 27.8 sec:     PASS
            omap3-overo-tobi     0 min 22.3 sec:     PASS  (Warnings: 1)
  imx6dl-wandboard,wand-solo     0 min 18.2 sec:     PASS
                 am335x-bone     0 min 26.7 sec:     PASS
      omap3-overo-storm-tobi     0 min 20.9 sec:     PASS
                  omap5-uevm     1 min 40.0 sec:     PASS  (Warnings: 1)
                  omap3-n900     0 min 34.5 sec:     PASS  (Warnings: 1)
             imx6q-wandboard     0 min 17.2 sec:     PASS
              omap4-panda-es     0 min 54.5 sec:     PASS
  imx6dl-wandboard,wand-dual     0 min 18.1 sec:     PASS