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* [PATCH 1/2] drm/i915/bdw: Add WT caching ability
@ 2014-03-29 22:56 Ben Widawsky
  2014-03-29 22:56 ` [PATCH 2/2] drm/i915/bdw: enable eDRAM Ben Widawsky
  2014-03-29 22:58 ` [PATCH 1/2] drm/i915/bdw: Add WT caching ability Ben Widawsky
  0 siblings, 2 replies; 3+ messages in thread
From: Ben Widawsky @ 2014-03-29 22:56 UTC (permalink / raw)
  To: Intel GFX

I don't have any insight on what parts can do what. The docs do seem to
suggest WT caching works in at least the same manner as it doesn't on
Haswell.

The addr = 0  is to shut up GCC:
drivers/gpu/drm/i915/i915_gem_gtt.c:80:7: warning: 'addr' may be used
uninitialized in this function [-Wmaybe-uninitialized]

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h     | 11 ++++++-----
 drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +++++++++++++----
 2 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e23bb73..896fe8e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,11 +1822,12 @@ struct drm_i915_cmd_table {
 #define BSD_RING		(1<<VCS)
 #define BLT_RING		(1<<BCS)
 #define VEBOX_RING		(1<<VECS)
-#define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
-#define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
-#define HAS_VEBOX(dev)            (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
-#define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
-#define HAS_WT(dev)            (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
+#define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
+#define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
+#define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
+#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
+#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
+				 to_i915(dev)->ellc_size)
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4467974..10d00ee 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -68,10 +68,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
 {
 	gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 	pte |= addr;
-	if (level != I915_CACHE_NONE)
-		pte |= PPAT_CACHED_INDEX;
-	else
+
+	switch (level) {
+	case I915_CACHE_NONE:
 		pte |= PPAT_UNCACHED_INDEX;
+		break;
+	case I915_CACHE_WT:
+		pte |= PPAT_DISPLAY_ELLC_INDEX;
+		break;
+	default:
+		pte |= PPAT_CACHED_INDEX;
+		break;
+	}
+
 	return pte;
 }
 
@@ -1367,7 +1376,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 		(gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 	int i = 0;
 	struct sg_page_iter sg_iter;
-	dma_addr_t addr;
+	dma_addr_t addr = 0;
 
 	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 		addr = sg_dma_address(sg_iter.sg) +
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* [PATCH 2/2] drm/i915/bdw: enable eDRAM.
  2014-03-29 22:56 [PATCH 1/2] drm/i915/bdw: Add WT caching ability Ben Widawsky
@ 2014-03-29 22:56 ` Ben Widawsky
  2014-03-29 22:58 ` [PATCH 1/2] drm/i915/bdw: Add WT caching ability Ben Widawsky
  1 sibling, 0 replies; 3+ messages in thread
From: Ben Widawsky @ 2014-03-29 22:56 UTC (permalink / raw)
  To: Intel GFX

The same register exists for querying and programming eDRAM AKA eLLC. So
we can simply use it. For now, use all the same defaults as we had
for Haswell, since like Haswell, I have no further details.

I do not actually have a part with eDRAM, so I cannot test this.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_uncore.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 823d699..f5e7240 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -370,7 +370,7 @@ void intel_uncore_early_sanitize(struct drm_device *dev)
 	if (HAS_FPGA_DBG_UNCLAIMED(dev))
 		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 
-	if (IS_HASWELL(dev) &&
+	if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
 		/* The docs do not explain exactly how the calculation can be
 		 * made. It is somewhat guessable, but for now, it's always
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] drm/i915/bdw: Add WT caching ability
  2014-03-29 22:56 [PATCH 1/2] drm/i915/bdw: Add WT caching ability Ben Widawsky
  2014-03-29 22:56 ` [PATCH 2/2] drm/i915/bdw: enable eDRAM Ben Widawsky
@ 2014-03-29 22:58 ` Ben Widawsky
  1 sibling, 0 replies; 3+ messages in thread
From: Ben Widawsky @ 2014-03-29 22:58 UTC (permalink / raw)
  To: Ben Widawsky; +Cc: Intel GFX

On Sat, Mar 29, 2014 at 03:56:41PM -0700, Ben Widawsky wrote:
> I don't have any insight on what parts can do what. The docs do seem to
> suggest WT caching works in at least the same manner as it doesn't on
> Haswell.
> 

That's a freudian slip... s/doesn't/does/

> The addr = 0  is to shut up GCC:
> drivers/gpu/drm/i915/i915_gem_gtt.c:80:7: warning: 'addr' may be used
> uninitialized in this function [-Wmaybe-uninitialized]
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_drv.h     | 11 ++++++-----
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +++++++++++++----
>  2 files changed, 19 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e23bb73..896fe8e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1822,11 +1822,12 @@ struct drm_i915_cmd_table {
>  #define BSD_RING		(1<<VCS)
>  #define BLT_RING		(1<<BCS)
>  #define VEBOX_RING		(1<<VECS)
> -#define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
> -#define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
> -#define HAS_VEBOX(dev)            (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
> -#define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
> -#define HAS_WT(dev)            (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
> +#define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
> +#define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
> +#define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
> +#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
> +#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
> +				 to_i915(dev)->ellc_size)
>  #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
>  
>  #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4467974..10d00ee 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -68,10 +68,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
>  {
>  	gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
>  	pte |= addr;
> -	if (level != I915_CACHE_NONE)
> -		pte |= PPAT_CACHED_INDEX;
> -	else
> +
> +	switch (level) {
> +	case I915_CACHE_NONE:
>  		pte |= PPAT_UNCACHED_INDEX;
> +		break;
> +	case I915_CACHE_WT:
> +		pte |= PPAT_DISPLAY_ELLC_INDEX;
> +		break;
> +	default:
> +		pte |= PPAT_CACHED_INDEX;
> +		break;
> +	}
> +
>  	return pte;
>  }
>  
> @@ -1367,7 +1376,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
>  		(gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
>  	int i = 0;
>  	struct sg_page_iter sg_iter;
> -	dma_addr_t addr;
> +	dma_addr_t addr = 0;
>  
>  	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
>  		addr = sg_dma_address(sg_iter.sg) +
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ben Widawsky, Intel Open Source Technology Center

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2014-03-29 22:58 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-03-29 22:56 [PATCH 1/2] drm/i915/bdw: Add WT caching ability Ben Widawsky
2014-03-29 22:56 ` [PATCH 2/2] drm/i915/bdw: enable eDRAM Ben Widawsky
2014-03-29 22:58 ` [PATCH 1/2] drm/i915/bdw: Add WT caching ability Ben Widawsky

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