* [PATCH 1/9] mtd: spi-nor: drop \t after #define @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Brian Norris, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut Spacing is a little non-standard here. Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- Series based on l2-mtd.git/spinor: http://git.infradead.org/l2-mtd.git include/linux/mtd/spi-nor.h | 68 ++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 41dae78fbd1d..558097e14932 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -2,50 +2,50 @@ #define __LINUX_MTD_SPI_NOR_H /* Flash opcodes. */ -#define OPCODE_WREN 0x06 /* Write enable */ -#define OPCODE_RDSR 0x05 /* Read status register */ -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ -#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ -#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ -#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ -#define OPCODE_RDCR 0x35 /* Read configuration register */ +#define OPCODE_WREN 0x06 /* Write enable */ +#define OPCODE_RDSR 0x05 /* Read status register */ +#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ +#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ +#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ +#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ +#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ +#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ +#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ +#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ +#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define OPCODE_RDID 0x9f /* Read JEDEC ID */ +#define OPCODE_RDCR 0x35 /* Read configuration register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ -#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ -#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ -#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ +#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ +#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ +#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ +#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ /* Used for SST flashes only. */ -#define OPCODE_BP 0x02 /* Byte program */ -#define OPCODE_WRDI 0x04 /* Write disable */ -#define OPCODE_AAI_WP 0xad /* Auto address increment word program */ +#define OPCODE_BP 0x02 /* Byte program */ +#define OPCODE_WRDI 0x04 /* Write disable */ +#define OPCODE_AAI_WP 0xad /* Auto address increment word program */ /* Used for Macronix and Winbond flashes. */ -#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ -#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ +#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ +#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ /* Used for Spansion flashes only. */ -#define OPCODE_BRWR 0x17 /* Bank register write */ +#define OPCODE_BRWR 0x17 /* Bank register write */ /* Status Register bits. */ -#define SR_WIP 1 /* Write in progress */ -#define SR_WEL 2 /* Write enable latch */ +#define SR_WIP 1 /* Write in progress */ +#define SR_WEL 2 /* Write enable latch */ /* meaning of other SR_* bits may differ between vendors */ -#define SR_BP0 4 /* Block protect 0 */ -#define SR_BP1 8 /* Block protect 1 */ -#define SR_BP2 0x10 /* Block protect 2 */ -#define SR_SRWD 0x80 /* SR write protect */ +#define SR_BP0 4 /* Block protect 0 */ +#define SR_BP1 8 /* Block protect 1 */ +#define SR_BP2 0x10 /* Block protect 2 */ +#define SR_SRWD 0x80 /* SR write protect */ #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */ @@ -86,7 +86,7 @@ struct spi_nor_xfer_cfg { u8 dummy_cycles; }; -#define SPI_NOR_MAX_CMD_SIZE 8 +#define SPI_NOR_MAX_CMD_SIZE 8 enum spi_nor_ops { SPI_NOR_OPS_READ = 0, SPI_NOR_OPS_WRITE, -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH 1/9] mtd: spi-nor: drop \t after #define @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd; +Cc: Marek Vasut, Huang Shijie, Brian Norris, Lee Jones, linux-spi Spacing is a little non-standard here. Signed-off-by: Brian Norris <computersforpeace@gmail.com> --- Series based on l2-mtd.git/spinor: http://git.infradead.org/l2-mtd.git include/linux/mtd/spi-nor.h | 68 ++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 41dae78fbd1d..558097e14932 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -2,50 +2,50 @@ #define __LINUX_MTD_SPI_NOR_H /* Flash opcodes. */ -#define OPCODE_WREN 0x06 /* Write enable */ -#define OPCODE_RDSR 0x05 /* Read status register */ -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ -#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ -#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ -#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ -#define OPCODE_RDCR 0x35 /* Read configuration register */ +#define OPCODE_WREN 0x06 /* Write enable */ +#define OPCODE_RDSR 0x05 /* Read status register */ +#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ +#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ +#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ +#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ +#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ +#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ +#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ +#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ +#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define OPCODE_RDID 0x9f /* Read JEDEC ID */ +#define OPCODE_RDCR 0x35 /* Read configuration register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ -#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ -#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ -#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ +#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ +#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ +#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ +#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ /* Used for SST flashes only. */ -#define OPCODE_BP 0x02 /* Byte program */ -#define OPCODE_WRDI 0x04 /* Write disable */ -#define OPCODE_AAI_WP 0xad /* Auto address increment word program */ +#define OPCODE_BP 0x02 /* Byte program */ +#define OPCODE_WRDI 0x04 /* Write disable */ +#define OPCODE_AAI_WP 0xad /* Auto address increment word program */ /* Used for Macronix and Winbond flashes. */ -#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ -#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ +#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ +#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ /* Used for Spansion flashes only. */ -#define OPCODE_BRWR 0x17 /* Bank register write */ +#define OPCODE_BRWR 0x17 /* Bank register write */ /* Status Register bits. */ -#define SR_WIP 1 /* Write in progress */ -#define SR_WEL 2 /* Write enable latch */ +#define SR_WIP 1 /* Write in progress */ +#define SR_WEL 2 /* Write enable latch */ /* meaning of other SR_* bits may differ between vendors */ -#define SR_BP0 4 /* Block protect 0 */ -#define SR_BP1 8 /* Block protect 1 */ -#define SR_BP2 0x10 /* Block protect 2 */ -#define SR_SRWD 0x80 /* SR write protect */ +#define SR_BP0 4 /* Block protect 0 */ +#define SR_BP1 8 /* Block protect 1 */ +#define SR_BP2 0x10 /* Block protect 2 */ +#define SR_SRWD 0x80 /* SR write protect */ #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */ @@ -86,7 +86,7 @@ struct spi_nor_xfer_cfg { u8 dummy_cycles; }; -#define SPI_NOR_MAX_CMD_SIZE 8 +#define SPI_NOR_MAX_CMD_SIZE 8 enum spi_nor_ops { SPI_NOR_OPS_READ = 0, SPI_NOR_OPS_WRITE, -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1397064774-31784-1-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* [PATCH 2/9] mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_* 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:32 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Brian Norris, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- drivers/mtd/devices/m25p80.c | 4 +-- drivers/mtd/spi-nor/fsl-quadspi.c | 58 +++++++++++++++++------------------ drivers/mtd/spi-nor/spi-nor.c | 64 +++++++++++++++++++-------------------- include/linux/mtd/spi-nor.h | 54 ++++++++++++++++----------------- 4 files changed, 90 insertions(+), 90 deletions(-) diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 4af6400ccd95..1557d8f672c1 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -86,7 +86,7 @@ static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len, spi_message_init(&m); - if (nor->program_opcode == OPCODE_AAI_WP && nor->sst_write_second) + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) cmd_sz = 1; flash->command[0] = nor->program_opcode; @@ -171,7 +171,7 @@ static int m25p80_erase(struct spi_nor *nor, loff_t offset) return ret; /* Send write enable, then erase commands. */ - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); if (ret) return ret; diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 6dc08ed950c8..2977f026f39d 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -294,12 +294,12 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) lut_base = SEQID_QUAD_READ * 4; if (q->nor_size <= SZ_16M) { - cmd = OPCODE_QUAD_READ; + cmd = SPINOR_OP_QUAD_READ; addrlen = ADDR24BIT; dummy = 8; } else { /* use the 4-byte address */ - cmd = OPCODE_QUAD_READ; + cmd = SPINOR_OP_QUAD_READ; addrlen = ADDR32BIT; dummy = 8; } @@ -311,17 +311,17 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Write enable */ lut_base = SEQID_WREN * 4; - writel(LUT0(CMD, PAD1, OPCODE_WREN), base + QUADSPI_LUT(lut_base)); + writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); /* Page Program */ lut_base = SEQID_PP * 4; if (q->nor_size <= SZ_16M) { - cmd = OPCODE_PP; + cmd = SPINOR_OP_PP; addrlen = ADDR24BIT; } else { /* use the 4-byte address */ - cmd = OPCODE_PP; + cmd = SPINOR_OP_PP; addrlen = ADDR32BIT; } @@ -331,18 +331,18 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Read Status */ lut_base = SEQID_RDSR * 4; - writel(LUT0(CMD, PAD1, OPCODE_RDSR) | LUT1(READ, PAD1, 0x1), + writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1), base + QUADSPI_LUT(lut_base)); /* Erase a sector */ lut_base = SEQID_SE * 4; if (q->nor_size <= SZ_16M) { - cmd = OPCODE_SE; + cmd = SPINOR_OP_SE; addrlen = ADDR24BIT; } else { /* use the 4-byte address */ - cmd = OPCODE_SE; + cmd = SPINOR_OP_SE; addrlen = ADDR32BIT; } @@ -351,35 +351,35 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Erase the whole chip */ lut_base = SEQID_CHIP_ERASE * 4; - writel(LUT0(CMD, PAD1, OPCODE_CHIP_ERASE), + writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), base + QUADSPI_LUT(lut_base)); /* READ ID */ lut_base = SEQID_RDID * 4; - writel(LUT0(CMD, PAD1, OPCODE_RDID) | LUT1(READ, PAD1, 0x8), + writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8), base + QUADSPI_LUT(lut_base)); /* Write Register */ lut_base = SEQID_WRSR * 4; - writel(LUT0(CMD, PAD1, OPCODE_WRSR) | LUT1(WRITE, PAD1, 0x2), + writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2), base + QUADSPI_LUT(lut_base)); /* Read Configuration Register */ lut_base = SEQID_RDCR * 4; - writel(LUT0(CMD, PAD1, OPCODE_RDCR) | LUT1(READ, PAD1, 0x1), + writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1), base + QUADSPI_LUT(lut_base)); /* Write disable */ lut_base = SEQID_WRDI * 4; - writel(LUT0(CMD, PAD1, OPCODE_WRDI), base + QUADSPI_LUT(lut_base)); + writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base)); /* Enter 4 Byte Mode (Micron) */ lut_base = SEQID_EN4B * 4; - writel(LUT0(CMD, PAD1, OPCODE_EN4B), base + QUADSPI_LUT(lut_base)); + writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base)); /* Enter 4 Byte Mode (Spansion) */ lut_base = SEQID_BRWR * 4; - writel(LUT0(CMD, PAD1, OPCODE_BRWR), base + QUADSPI_LUT(lut_base)); + writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); fsl_qspi_lock_lut(q); } @@ -388,29 +388,29 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { - case OPCODE_QUAD_READ: + case SPINOR_OP_QUAD_READ: return SEQID_QUAD_READ; - case OPCODE_WREN: + case SPINOR_OP_WREN: return SEQID_WREN; - case OPCODE_WRDI: + case SPINOR_OP_WRDI: return SEQID_WRDI; - case OPCODE_RDSR: + case SPINOR_OP_RDSR: return SEQID_RDSR; - case OPCODE_SE: + case SPINOR_OP_SE: return SEQID_SE; - case OPCODE_CHIP_ERASE: + case SPINOR_OP_CHIP_ERASE: return SEQID_CHIP_ERASE; - case OPCODE_PP: + case SPINOR_OP_PP: return SEQID_PP; - case OPCODE_RDID: + case SPINOR_OP_RDID: return SEQID_RDID; - case OPCODE_WRSR: + case SPINOR_OP_WRSR: return SEQID_WRSR; - case OPCODE_RDCR: + case SPINOR_OP_RDCR: return SEQID_RDCR; - case OPCODE_EN4B: + case SPINOR_OP_EN4B: return SEQID_EN4B; - case OPCODE_BRWR: + case SPINOR_OP_BRWR: return SEQID_BRWR; default: dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd); @@ -688,7 +688,7 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len, if (ret) return ret; - if (opcode == OPCODE_CHIP_ERASE) + if (opcode == SPINOR_OP_CHIP_ERASE) fsl_qspi_invalid(q); } else if (len > 0) { @@ -750,7 +750,7 @@ static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs) return ret; /* Send write enable, then erase commands. */ - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); if (ret) return ret; diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 5cd86eb2a5f0..462f1c8c3a7d 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -34,7 +34,7 @@ static int read_sr(struct spi_nor *nor) int ret; u8 val; - ret = nor->read_reg(nor, OPCODE_RDSR, &val, 1); + ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); if (ret < 0) { pr_err("error %d reading SR\n", (int) ret); return ret; @@ -53,7 +53,7 @@ static int read_cr(struct spi_nor *nor) int ret; u8 val; - ret = nor->read_reg(nor, OPCODE_RDCR, &val, 1); + ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); if (ret < 0) { dev_err(nor->dev, "error %d reading CR\n", ret); return ret; @@ -87,7 +87,7 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) static inline int write_sr(struct spi_nor *nor, u8 val) { nor->cmd_buf[0] = val; - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0); + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); } /* @@ -96,7 +96,7 @@ static inline int write_sr(struct spi_nor *nor, u8 val) */ static inline int write_enable(struct spi_nor *nor) { - return nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); + return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); } /* @@ -104,7 +104,7 @@ static inline int write_enable(struct spi_nor *nor) */ static inline int write_disable(struct spi_nor *nor) { - return nor->write_reg(nor, OPCODE_WRDI, NULL, 0, 0); + return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0); } static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) @@ -128,7 +128,7 @@ static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable) if (need_wren) write_enable(nor); - cmd = enable ? OPCODE_EN4B : OPCODE_EX4B; + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; status = nor->write_reg(nor, cmd, NULL, 0, 0); if (need_wren) write_disable(nor); @@ -137,7 +137,7 @@ static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable) default: /* Spansion style */ nor->cmd_buf[0] = enable << 7; - return nor->write_reg(nor, OPCODE_BRWR, nor->cmd_buf, 1, 0); + return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0); } } @@ -189,7 +189,7 @@ static int erase_chip(struct spi_nor *nor) /* Send write enable, then erase commands. */ write_enable(nor); - return nor->write_reg(nor, OPCODE_CHIP_ERASE, NULL, 0, 0); + return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0); } static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) @@ -249,7 +249,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) } /* REVISIT in some cases we could speed up erasing large regions - * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up * to use "small sector erase", but that's not always optimal. */ @@ -381,7 +381,7 @@ struct flash_info { u32 jedec_id; u16 ext_id; - /* The size listed here is what works with OPCODE_SE, which isn't + /* The size listed here is what works with SPINOR_OP_SE, which isn't * necessarily called a "sector" by the vendor. */ unsigned sector_size; @@ -391,11 +391,11 @@ struct flash_info { u16 addr_width; u16 flags; -#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ +#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ #define SST_WRITE 0x04 /* use SST byte programming */ #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ -#define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */ +#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ }; @@ -594,7 +594,7 @@ static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor) u16 ext_jedec; struct flash_info *info; - tmp = nor->read_reg(nor, OPCODE_RDID, id, 5); + tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5); if (tmp < 0) { dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp); return ERR_PTR(tmp); @@ -666,7 +666,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, actual = to % 2; /* Start write from odd address. */ if (actual) { - nor->program_opcode = OPCODE_BP; + nor->program_opcode = SPINOR_OP_BP; /* write one byte. */ nor->write(nor, to, 1, retlen, buf); @@ -678,7 +678,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, /* Write out most of the data here. */ for (; actual < len - 1; actual += 2) { - nor->program_opcode = OPCODE_AAI_WP; + nor->program_opcode = SPINOR_OP_AAI_WP; /* write two bytes. */ nor->write(nor, to, 2, retlen, buf + actual); @@ -699,7 +699,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, if (actual != len) { write_enable(nor); - nor->program_opcode = OPCODE_BP; + nor->program_opcode = SPINOR_OP_BP; nor->write(nor, to, 1, retlen, buf + actual); ret = wait_till_ready(nor); @@ -773,7 +773,7 @@ static int macronix_quad_enable(struct spi_nor *nor) write_enable(nor); nor->cmd_buf[0] = val | SR_QUAD_EN_MX; - nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0); + nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); if (wait_till_ready(nor)) return 1; @@ -798,7 +798,7 @@ static int write_sr_cr(struct spi_nor *nor, u16 val) nor->cmd_buf[0] = val & 0xff; nor->cmd_buf[1] = (val >> 8); - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 2, 0); + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0); } static int spansion_quad_enable(struct spi_nor *nor) @@ -963,13 +963,13 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* prefer "small sector" erase if possible */ if (info->flags & SECT_4K) { - nor->erase_opcode = OPCODE_BE_4K; + nor->erase_opcode = SPINOR_OP_BE_4K; mtd->erasesize = 4096; } else if (info->flags & SECT_4K_PMC) { - nor->erase_opcode = OPCODE_BE_4K_PMC; + nor->erase_opcode = SPINOR_OP_BE_4K_PMC; mtd->erasesize = 4096; } else { - nor->erase_opcode = OPCODE_SE; + nor->erase_opcode = SPINOR_OP_SE; mtd->erasesize = info->sector_size; } @@ -1010,23 +1010,23 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* Default commands */ switch (nor->flash_read) { case SPI_NOR_QUAD: - nor->read_opcode = OPCODE_QUAD_READ; + nor->read_opcode = SPINOR_OP_QUAD_READ; break; case SPI_NOR_DUAL: - nor->read_opcode = OPCODE_DUAL_READ; + nor->read_opcode = SPINOR_OP_DUAL_READ; break; case SPI_NOR_FAST: - nor->read_opcode = OPCODE_FAST_READ; + nor->read_opcode = SPINOR_OP_FAST_READ; break; case SPI_NOR_NORMAL: - nor->read_opcode = OPCODE_NORM_READ; + nor->read_opcode = SPINOR_OP_NORM_READ; break; default: dev_err(dev, "No Read opcode defined\n"); return -EINVAL; } - nor->program_opcode = OPCODE_PP; + nor->program_opcode = SPINOR_OP_PP; if (info->addr_width) nor->addr_width = info->addr_width; @@ -1037,21 +1037,21 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* Dedicated 4-byte command set */ switch (nor->flash_read) { case SPI_NOR_QUAD: - nor->read_opcode = OPCODE_QUAD_READ_4B; + nor->read_opcode = SPINOR_OP_QUAD_READ_4B; break; case SPI_NOR_DUAL: - nor->read_opcode = OPCODE_DUAL_READ_4B; + nor->read_opcode = SPINOR_OP_DUAL_READ_4B; break; case SPI_NOR_FAST: - nor->read_opcode = OPCODE_FAST_READ_4B; + nor->read_opcode = SPINOR_OP_FAST_READ_4B; break; case SPI_NOR_NORMAL: - nor->read_opcode = OPCODE_NORM_READ_4B; + nor->read_opcode = SPINOR_OP_NORM_READ_4B; break; } - nor->program_opcode = OPCODE_PP_4B; + nor->program_opcode = SPINOR_OP_PP_4B; /* No small sector erase for 4-byte command set */ - nor->erase_opcode = OPCODE_SE_4B; + nor->erase_opcode = SPINOR_OP_SE_4B; mtd->erasesize = info->sector_size; } else set_4byte(nor, info->jedec_id, 1); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 558097e14932..2c827b5bf773 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -2,41 +2,41 @@ #define __LINUX_MTD_SPI_NOR_H /* Flash opcodes. */ -#define OPCODE_WREN 0x06 /* Write enable */ -#define OPCODE_RDSR 0x05 /* Read status register */ -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ -#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ -#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ -#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ -#define OPCODE_RDCR 0x35 /* Read configuration register */ +#define SPINOR_OP_WREN 0x06 /* Write enable */ +#define SPINOR_OP_RDSR 0x05 /* Read status register */ +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ +#define SPINOR_OP_NORM_READ 0x03 /* Read data bytes (low frequency) */ +#define SPINOR_OP_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define SPINOR_OP_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ +#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ +#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ +#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ +#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ +#define SPINOR_OP_RDCR 0x35 /* Read configuration register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ -#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ -#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ -#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ +#define SPINOR_OP_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ +#define SPINOR_OP_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define SPINOR_OP_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ /* Used for SST flashes only. */ -#define OPCODE_BP 0x02 /* Byte program */ -#define OPCODE_WRDI 0x04 /* Write disable */ -#define OPCODE_AAI_WP 0xad /* Auto address increment word program */ +#define SPINOR_OP_BP 0x02 /* Byte program */ +#define SPINOR_OP_WRDI 0x04 /* Write disable */ +#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ /* Used for Macronix and Winbond flashes. */ -#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ -#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ /* Used for Spansion flashes only. */ -#define OPCODE_BRWR 0x17 /* Bank register write */ +#define SPINOR_OP_BRWR 0x17 /* Bank register write */ /* Status Register bits. */ #define SR_WIP 1 /* Write in progress */ -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH 2/9] mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_* @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd; +Cc: Marek Vasut, Huang Shijie, Brian Norris, Lee Jones, linux-spi Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> --- drivers/mtd/devices/m25p80.c | 4 +-- drivers/mtd/spi-nor/fsl-quadspi.c | 58 +++++++++++++++++------------------ drivers/mtd/spi-nor/spi-nor.c | 64 +++++++++++++++++++-------------------- include/linux/mtd/spi-nor.h | 54 ++++++++++++++++----------------- 4 files changed, 90 insertions(+), 90 deletions(-) diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 4af6400ccd95..1557d8f672c1 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -86,7 +86,7 @@ static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len, spi_message_init(&m); - if (nor->program_opcode == OPCODE_AAI_WP && nor->sst_write_second) + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) cmd_sz = 1; flash->command[0] = nor->program_opcode; @@ -171,7 +171,7 @@ static int m25p80_erase(struct spi_nor *nor, loff_t offset) return ret; /* Send write enable, then erase commands. */ - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); if (ret) return ret; diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 6dc08ed950c8..2977f026f39d 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -294,12 +294,12 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) lut_base = SEQID_QUAD_READ * 4; if (q->nor_size <= SZ_16M) { - cmd = OPCODE_QUAD_READ; + cmd = SPINOR_OP_QUAD_READ; addrlen = ADDR24BIT; dummy = 8; } else { /* use the 4-byte address */ - cmd = OPCODE_QUAD_READ; + cmd = SPINOR_OP_QUAD_READ; addrlen = ADDR32BIT; dummy = 8; } @@ -311,17 +311,17 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Write enable */ lut_base = SEQID_WREN * 4; - writel(LUT0(CMD, PAD1, OPCODE_WREN), base + QUADSPI_LUT(lut_base)); + writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); /* Page Program */ lut_base = SEQID_PP * 4; if (q->nor_size <= SZ_16M) { - cmd = OPCODE_PP; + cmd = SPINOR_OP_PP; addrlen = ADDR24BIT; } else { /* use the 4-byte address */ - cmd = OPCODE_PP; + cmd = SPINOR_OP_PP; addrlen = ADDR32BIT; } @@ -331,18 +331,18 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Read Status */ lut_base = SEQID_RDSR * 4; - writel(LUT0(CMD, PAD1, OPCODE_RDSR) | LUT1(READ, PAD1, 0x1), + writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1), base + QUADSPI_LUT(lut_base)); /* Erase a sector */ lut_base = SEQID_SE * 4; if (q->nor_size <= SZ_16M) { - cmd = OPCODE_SE; + cmd = SPINOR_OP_SE; addrlen = ADDR24BIT; } else { /* use the 4-byte address */ - cmd = OPCODE_SE; + cmd = SPINOR_OP_SE; addrlen = ADDR32BIT; } @@ -351,35 +351,35 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Erase the whole chip */ lut_base = SEQID_CHIP_ERASE * 4; - writel(LUT0(CMD, PAD1, OPCODE_CHIP_ERASE), + writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), base + QUADSPI_LUT(lut_base)); /* READ ID */ lut_base = SEQID_RDID * 4; - writel(LUT0(CMD, PAD1, OPCODE_RDID) | LUT1(READ, PAD1, 0x8), + writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8), base + QUADSPI_LUT(lut_base)); /* Write Register */ lut_base = SEQID_WRSR * 4; - writel(LUT0(CMD, PAD1, OPCODE_WRSR) | LUT1(WRITE, PAD1, 0x2), + writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2), base + QUADSPI_LUT(lut_base)); /* Read Configuration Register */ lut_base = SEQID_RDCR * 4; - writel(LUT0(CMD, PAD1, OPCODE_RDCR) | LUT1(READ, PAD1, 0x1), + writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1), base + QUADSPI_LUT(lut_base)); /* Write disable */ lut_base = SEQID_WRDI * 4; - writel(LUT0(CMD, PAD1, OPCODE_WRDI), base + QUADSPI_LUT(lut_base)); + writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base)); /* Enter 4 Byte Mode (Micron) */ lut_base = SEQID_EN4B * 4; - writel(LUT0(CMD, PAD1, OPCODE_EN4B), base + QUADSPI_LUT(lut_base)); + writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base)); /* Enter 4 Byte Mode (Spansion) */ lut_base = SEQID_BRWR * 4; - writel(LUT0(CMD, PAD1, OPCODE_BRWR), base + QUADSPI_LUT(lut_base)); + writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); fsl_qspi_lock_lut(q); } @@ -388,29 +388,29 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { - case OPCODE_QUAD_READ: + case SPINOR_OP_QUAD_READ: return SEQID_QUAD_READ; - case OPCODE_WREN: + case SPINOR_OP_WREN: return SEQID_WREN; - case OPCODE_WRDI: + case SPINOR_OP_WRDI: return SEQID_WRDI; - case OPCODE_RDSR: + case SPINOR_OP_RDSR: return SEQID_RDSR; - case OPCODE_SE: + case SPINOR_OP_SE: return SEQID_SE; - case OPCODE_CHIP_ERASE: + case SPINOR_OP_CHIP_ERASE: return SEQID_CHIP_ERASE; - case OPCODE_PP: + case SPINOR_OP_PP: return SEQID_PP; - case OPCODE_RDID: + case SPINOR_OP_RDID: return SEQID_RDID; - case OPCODE_WRSR: + case SPINOR_OP_WRSR: return SEQID_WRSR; - case OPCODE_RDCR: + case SPINOR_OP_RDCR: return SEQID_RDCR; - case OPCODE_EN4B: + case SPINOR_OP_EN4B: return SEQID_EN4B; - case OPCODE_BRWR: + case SPINOR_OP_BRWR: return SEQID_BRWR; default: dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd); @@ -688,7 +688,7 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len, if (ret) return ret; - if (opcode == OPCODE_CHIP_ERASE) + if (opcode == SPINOR_OP_CHIP_ERASE) fsl_qspi_invalid(q); } else if (len > 0) { @@ -750,7 +750,7 @@ static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs) return ret; /* Send write enable, then erase commands. */ - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); if (ret) return ret; diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 5cd86eb2a5f0..462f1c8c3a7d 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -34,7 +34,7 @@ static int read_sr(struct spi_nor *nor) int ret; u8 val; - ret = nor->read_reg(nor, OPCODE_RDSR, &val, 1); + ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); if (ret < 0) { pr_err("error %d reading SR\n", (int) ret); return ret; @@ -53,7 +53,7 @@ static int read_cr(struct spi_nor *nor) int ret; u8 val; - ret = nor->read_reg(nor, OPCODE_RDCR, &val, 1); + ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); if (ret < 0) { dev_err(nor->dev, "error %d reading CR\n", ret); return ret; @@ -87,7 +87,7 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) static inline int write_sr(struct spi_nor *nor, u8 val) { nor->cmd_buf[0] = val; - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0); + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); } /* @@ -96,7 +96,7 @@ static inline int write_sr(struct spi_nor *nor, u8 val) */ static inline int write_enable(struct spi_nor *nor) { - return nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); + return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); } /* @@ -104,7 +104,7 @@ static inline int write_enable(struct spi_nor *nor) */ static inline int write_disable(struct spi_nor *nor) { - return nor->write_reg(nor, OPCODE_WRDI, NULL, 0, 0); + return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0); } static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) @@ -128,7 +128,7 @@ static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable) if (need_wren) write_enable(nor); - cmd = enable ? OPCODE_EN4B : OPCODE_EX4B; + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; status = nor->write_reg(nor, cmd, NULL, 0, 0); if (need_wren) write_disable(nor); @@ -137,7 +137,7 @@ static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable) default: /* Spansion style */ nor->cmd_buf[0] = enable << 7; - return nor->write_reg(nor, OPCODE_BRWR, nor->cmd_buf, 1, 0); + return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0); } } @@ -189,7 +189,7 @@ static int erase_chip(struct spi_nor *nor) /* Send write enable, then erase commands. */ write_enable(nor); - return nor->write_reg(nor, OPCODE_CHIP_ERASE, NULL, 0, 0); + return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0); } static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) @@ -249,7 +249,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) } /* REVISIT in some cases we could speed up erasing large regions - * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up * to use "small sector erase", but that's not always optimal. */ @@ -381,7 +381,7 @@ struct flash_info { u32 jedec_id; u16 ext_id; - /* The size listed here is what works with OPCODE_SE, which isn't + /* The size listed here is what works with SPINOR_OP_SE, which isn't * necessarily called a "sector" by the vendor. */ unsigned sector_size; @@ -391,11 +391,11 @@ struct flash_info { u16 addr_width; u16 flags; -#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ +#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ #define SST_WRITE 0x04 /* use SST byte programming */ #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ -#define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */ +#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ }; @@ -594,7 +594,7 @@ static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor) u16 ext_jedec; struct flash_info *info; - tmp = nor->read_reg(nor, OPCODE_RDID, id, 5); + tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5); if (tmp < 0) { dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp); return ERR_PTR(tmp); @@ -666,7 +666,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, actual = to % 2; /* Start write from odd address. */ if (actual) { - nor->program_opcode = OPCODE_BP; + nor->program_opcode = SPINOR_OP_BP; /* write one byte. */ nor->write(nor, to, 1, retlen, buf); @@ -678,7 +678,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, /* Write out most of the data here. */ for (; actual < len - 1; actual += 2) { - nor->program_opcode = OPCODE_AAI_WP; + nor->program_opcode = SPINOR_OP_AAI_WP; /* write two bytes. */ nor->write(nor, to, 2, retlen, buf + actual); @@ -699,7 +699,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, if (actual != len) { write_enable(nor); - nor->program_opcode = OPCODE_BP; + nor->program_opcode = SPINOR_OP_BP; nor->write(nor, to, 1, retlen, buf + actual); ret = wait_till_ready(nor); @@ -773,7 +773,7 @@ static int macronix_quad_enable(struct spi_nor *nor) write_enable(nor); nor->cmd_buf[0] = val | SR_QUAD_EN_MX; - nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0); + nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); if (wait_till_ready(nor)) return 1; @@ -798,7 +798,7 @@ static int write_sr_cr(struct spi_nor *nor, u16 val) nor->cmd_buf[0] = val & 0xff; nor->cmd_buf[1] = (val >> 8); - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 2, 0); + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0); } static int spansion_quad_enable(struct spi_nor *nor) @@ -963,13 +963,13 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* prefer "small sector" erase if possible */ if (info->flags & SECT_4K) { - nor->erase_opcode = OPCODE_BE_4K; + nor->erase_opcode = SPINOR_OP_BE_4K; mtd->erasesize = 4096; } else if (info->flags & SECT_4K_PMC) { - nor->erase_opcode = OPCODE_BE_4K_PMC; + nor->erase_opcode = SPINOR_OP_BE_4K_PMC; mtd->erasesize = 4096; } else { - nor->erase_opcode = OPCODE_SE; + nor->erase_opcode = SPINOR_OP_SE; mtd->erasesize = info->sector_size; } @@ -1010,23 +1010,23 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* Default commands */ switch (nor->flash_read) { case SPI_NOR_QUAD: - nor->read_opcode = OPCODE_QUAD_READ; + nor->read_opcode = SPINOR_OP_QUAD_READ; break; case SPI_NOR_DUAL: - nor->read_opcode = OPCODE_DUAL_READ; + nor->read_opcode = SPINOR_OP_DUAL_READ; break; case SPI_NOR_FAST: - nor->read_opcode = OPCODE_FAST_READ; + nor->read_opcode = SPINOR_OP_FAST_READ; break; case SPI_NOR_NORMAL: - nor->read_opcode = OPCODE_NORM_READ; + nor->read_opcode = SPINOR_OP_NORM_READ; break; default: dev_err(dev, "No Read opcode defined\n"); return -EINVAL; } - nor->program_opcode = OPCODE_PP; + nor->program_opcode = SPINOR_OP_PP; if (info->addr_width) nor->addr_width = info->addr_width; @@ -1037,21 +1037,21 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* Dedicated 4-byte command set */ switch (nor->flash_read) { case SPI_NOR_QUAD: - nor->read_opcode = OPCODE_QUAD_READ_4B; + nor->read_opcode = SPINOR_OP_QUAD_READ_4B; break; case SPI_NOR_DUAL: - nor->read_opcode = OPCODE_DUAL_READ_4B; + nor->read_opcode = SPINOR_OP_DUAL_READ_4B; break; case SPI_NOR_FAST: - nor->read_opcode = OPCODE_FAST_READ_4B; + nor->read_opcode = SPINOR_OP_FAST_READ_4B; break; case SPI_NOR_NORMAL: - nor->read_opcode = OPCODE_NORM_READ_4B; + nor->read_opcode = SPINOR_OP_NORM_READ_4B; break; } - nor->program_opcode = OPCODE_PP_4B; + nor->program_opcode = SPINOR_OP_PP_4B; /* No small sector erase for 4-byte command set */ - nor->erase_opcode = OPCODE_SE_4B; + nor->erase_opcode = SPINOR_OP_SE_4B; mtd->erasesize = info->sector_size; } else set_4byte(nor, info->jedec_id, 1); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 558097e14932..2c827b5bf773 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -2,41 +2,41 @@ #define __LINUX_MTD_SPI_NOR_H /* Flash opcodes. */ -#define OPCODE_WREN 0x06 /* Write enable */ -#define OPCODE_RDSR 0x05 /* Read status register */ -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ -#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ -#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ -#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ -#define OPCODE_RDCR 0x35 /* Read configuration register */ +#define SPINOR_OP_WREN 0x06 /* Write enable */ +#define SPINOR_OP_RDSR 0x05 /* Read status register */ +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ +#define SPINOR_OP_NORM_READ 0x03 /* Read data bytes (low frequency) */ +#define SPINOR_OP_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define SPINOR_OP_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ +#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ +#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ +#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ +#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ +#define SPINOR_OP_RDCR 0x35 /* Read configuration register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ -#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ -#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ -#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ +#define SPINOR_OP_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ +#define SPINOR_OP_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define SPINOR_OP_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ /* Used for SST flashes only. */ -#define OPCODE_BP 0x02 /* Byte program */ -#define OPCODE_WRDI 0x04 /* Write disable */ -#define OPCODE_AAI_WP 0xad /* Auto address increment word program */ +#define SPINOR_OP_BP 0x02 /* Byte program */ +#define SPINOR_OP_WRDI 0x04 /* Write disable */ +#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ /* Used for Macronix and Winbond flashes. */ -#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ -#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ /* Used for Spansion flashes only. */ -#define OPCODE_BRWR 0x17 /* Bank register write */ +#define SPINOR_OP_BRWR 0x17 /* Bank register write */ /* Status Register bits. */ #define SR_WIP 1 /* Write in progress */ -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1397064774-31784-2-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 2/9] mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_* 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:41 ` Marek Vasut -1 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:41 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA On Wednesday, April 09, 2014 at 07:32:47 PM, Brian Norris wrote: > Qualify these with a better namespace, and prepare them for use in more > drivers. > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Reviewed-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 2/9] mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_* @ 2014-04-09 17:41 ` Marek Vasut 0 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:41 UTC (permalink / raw) To: Brian Norris; +Cc: Huang Shijie, Lee Jones, linux-mtd, linux-spi On Wednesday, April 09, 2014 at 07:32:47 PM, Brian Norris wrote: > Qualify these with a better namespace, and prepare them for use in more > drivers. > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 2/9] mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_* 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 7:42 ` Huang Shijie -1 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:42 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut On Wed, Apr 09, 2014 at 10:32:47AM -0700, Brian Norris wrote: > Qualify these with a better namespace, and prepare them for use in more > drivers. > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > drivers/mtd/devices/m25p80.c | 4 +-- > drivers/mtd/spi-nor/fsl-quadspi.c | 58 +++++++++++++++++------------------ > drivers/mtd/spi-nor/spi-nor.c | 64 +++++++++++++++++++-------------------- > include/linux/mtd/spi-nor.h | 54 ++++++++++++++++----------------- > 4 files changed, 90 insertions(+), 90 deletions(-) > > diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c > index 4af6400ccd95..1557d8f672c1 100644 > --- a/drivers/mtd/devices/m25p80.c > +++ b/drivers/mtd/devices/m25p80.c > @@ -86,7 +86,7 @@ static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len, > > spi_message_init(&m); > > - if (nor->program_opcode == OPCODE_AAI_WP && nor->sst_write_second) > + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) > cmd_sz = 1; > > flash->command[0] = nor->program_opcode; > @@ -171,7 +171,7 @@ static int m25p80_erase(struct spi_nor *nor, loff_t offset) > return ret; > > /* Send write enable, then erase commands. */ > - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); > + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); > if (ret) > return ret; > > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c > index 6dc08ed950c8..2977f026f39d 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -294,12 +294,12 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > lut_base = SEQID_QUAD_READ * 4; > > if (q->nor_size <= SZ_16M) { > - cmd = OPCODE_QUAD_READ; > + cmd = SPINOR_OP_QUAD_READ; > addrlen = ADDR24BIT; > dummy = 8; > } else { > /* use the 4-byte address */ > - cmd = OPCODE_QUAD_READ; > + cmd = SPINOR_OP_QUAD_READ; > addrlen = ADDR32BIT; > dummy = 8; > } > @@ -311,17 +311,17 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > > /* Write enable */ > lut_base = SEQID_WREN * 4; > - writel(LUT0(CMD, PAD1, OPCODE_WREN), base + QUADSPI_LUT(lut_base)); > + writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); > > /* Page Program */ > lut_base = SEQID_PP * 4; > > if (q->nor_size <= SZ_16M) { > - cmd = OPCODE_PP; > + cmd = SPINOR_OP_PP; > addrlen = ADDR24BIT; > } else { > /* use the 4-byte address */ > - cmd = OPCODE_PP; > + cmd = SPINOR_OP_PP; > addrlen = ADDR32BIT; > } > > @@ -331,18 +331,18 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > > /* Read Status */ > lut_base = SEQID_RDSR * 4; > - writel(LUT0(CMD, PAD1, OPCODE_RDSR) | LUT1(READ, PAD1, 0x1), > + writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1), > base + QUADSPI_LUT(lut_base)); > > /* Erase a sector */ > lut_base = SEQID_SE * 4; > > if (q->nor_size <= SZ_16M) { > - cmd = OPCODE_SE; > + cmd = SPINOR_OP_SE; > addrlen = ADDR24BIT; > } else { > /* use the 4-byte address */ > - cmd = OPCODE_SE; > + cmd = SPINOR_OP_SE; > addrlen = ADDR32BIT; > } > > @@ -351,35 +351,35 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > > /* Erase the whole chip */ > lut_base = SEQID_CHIP_ERASE * 4; > - writel(LUT0(CMD, PAD1, OPCODE_CHIP_ERASE), > + writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), > base + QUADSPI_LUT(lut_base)); > > /* READ ID */ > lut_base = SEQID_RDID * 4; > - writel(LUT0(CMD, PAD1, OPCODE_RDID) | LUT1(READ, PAD1, 0x8), > + writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8), > base + QUADSPI_LUT(lut_base)); > > /* Write Register */ > lut_base = SEQID_WRSR * 4; > - writel(LUT0(CMD, PAD1, OPCODE_WRSR) | LUT1(WRITE, PAD1, 0x2), > + writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2), > base + QUADSPI_LUT(lut_base)); > > /* Read Configuration Register */ > lut_base = SEQID_RDCR * 4; > - writel(LUT0(CMD, PAD1, OPCODE_RDCR) | LUT1(READ, PAD1, 0x1), > + writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1), > base + QUADSPI_LUT(lut_base)); > > /* Write disable */ > lut_base = SEQID_WRDI * 4; > - writel(LUT0(CMD, PAD1, OPCODE_WRDI), base + QUADSPI_LUT(lut_base)); > + writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base)); > > /* Enter 4 Byte Mode (Micron) */ > lut_base = SEQID_EN4B * 4; > - writel(LUT0(CMD, PAD1, OPCODE_EN4B), base + QUADSPI_LUT(lut_base)); > + writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base)); > > /* Enter 4 Byte Mode (Spansion) */ > lut_base = SEQID_BRWR * 4; > - writel(LUT0(CMD, PAD1, OPCODE_BRWR), base + QUADSPI_LUT(lut_base)); > + writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); > > fsl_qspi_lock_lut(q); > } > @@ -388,29 +388,29 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) > { > switch (cmd) { > - case OPCODE_QUAD_READ: > + case SPINOR_OP_QUAD_READ: > return SEQID_QUAD_READ; > - case OPCODE_WREN: > + case SPINOR_OP_WREN: > return SEQID_WREN; > - case OPCODE_WRDI: > + case SPINOR_OP_WRDI: > return SEQID_WRDI; > - case OPCODE_RDSR: > + case SPINOR_OP_RDSR: > return SEQID_RDSR; > - case OPCODE_SE: > + case SPINOR_OP_SE: > return SEQID_SE; > - case OPCODE_CHIP_ERASE: > + case SPINOR_OP_CHIP_ERASE: > return SEQID_CHIP_ERASE; > - case OPCODE_PP: > + case SPINOR_OP_PP: > return SEQID_PP; > - case OPCODE_RDID: > + case SPINOR_OP_RDID: > return SEQID_RDID; > - case OPCODE_WRSR: > + case SPINOR_OP_WRSR: > return SEQID_WRSR; > - case OPCODE_RDCR: > + case SPINOR_OP_RDCR: > return SEQID_RDCR; > - case OPCODE_EN4B: > + case SPINOR_OP_EN4B: > return SEQID_EN4B; > - case OPCODE_BRWR: > + case SPINOR_OP_BRWR: > return SEQID_BRWR; > default: > dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd); > @@ -688,7 +688,7 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len, > if (ret) > return ret; > > - if (opcode == OPCODE_CHIP_ERASE) > + if (opcode == SPINOR_OP_CHIP_ERASE) > fsl_qspi_invalid(q); > > } else if (len > 0) { > @@ -750,7 +750,7 @@ static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs) > return ret; > > /* Send write enable, then erase commands. */ > - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); > + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); > if (ret) > return ret; > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 5cd86eb2a5f0..462f1c8c3a7d 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -34,7 +34,7 @@ static int read_sr(struct spi_nor *nor) > int ret; > u8 val; > > - ret = nor->read_reg(nor, OPCODE_RDSR, &val, 1); > + ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); > if (ret < 0) { > pr_err("error %d reading SR\n", (int) ret); > return ret; > @@ -53,7 +53,7 @@ static int read_cr(struct spi_nor *nor) > int ret; > u8 val; > > - ret = nor->read_reg(nor, OPCODE_RDCR, &val, 1); > + ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); > if (ret < 0) { > dev_err(nor->dev, "error %d reading CR\n", ret); > return ret; > @@ -87,7 +87,7 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) > static inline int write_sr(struct spi_nor *nor, u8 val) > { > nor->cmd_buf[0] = val; > - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0); > + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); > } > > /* > @@ -96,7 +96,7 @@ static inline int write_sr(struct spi_nor *nor, u8 val) > */ > static inline int write_enable(struct spi_nor *nor) > { > - return nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); > + return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); > } > > /* > @@ -104,7 +104,7 @@ static inline int write_enable(struct spi_nor *nor) > */ > static inline int write_disable(struct spi_nor *nor) > { > - return nor->write_reg(nor, OPCODE_WRDI, NULL, 0, 0); > + return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0); > } > > static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) > @@ -128,7 +128,7 @@ static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable) > if (need_wren) > write_enable(nor); > > - cmd = enable ? OPCODE_EN4B : OPCODE_EX4B; > + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; > status = nor->write_reg(nor, cmd, NULL, 0, 0); > if (need_wren) > write_disable(nor); > @@ -137,7 +137,7 @@ static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable) > default: > /* Spansion style */ > nor->cmd_buf[0] = enable << 7; > - return nor->write_reg(nor, OPCODE_BRWR, nor->cmd_buf, 1, 0); > + return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0); > } > } > > @@ -189,7 +189,7 @@ static int erase_chip(struct spi_nor *nor) > /* Send write enable, then erase commands. */ > write_enable(nor); > > - return nor->write_reg(nor, OPCODE_CHIP_ERASE, NULL, 0, 0); > + return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0); > } > > static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) > @@ -249,7 +249,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) > } > > /* REVISIT in some cases we could speed up erasing large regions > - * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up > + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up > * to use "small sector erase", but that's not always optimal. > */ > > @@ -381,7 +381,7 @@ struct flash_info { > u32 jedec_id; > u16 ext_id; > > - /* The size listed here is what works with OPCODE_SE, which isn't > + /* The size listed here is what works with SPINOR_OP_SE, which isn't > * necessarily called a "sector" by the vendor. > */ > unsigned sector_size; > @@ -391,11 +391,11 @@ struct flash_info { > u16 addr_width; > > u16 flags; > -#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ > +#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ > #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ > #define SST_WRITE 0x04 /* use SST byte programming */ > #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ > -#define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */ > +#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ > #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ > #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ > }; > @@ -594,7 +594,7 @@ static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor) > u16 ext_jedec; > struct flash_info *info; > > - tmp = nor->read_reg(nor, OPCODE_RDID, id, 5); > + tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5); > if (tmp < 0) { > dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp); > return ERR_PTR(tmp); > @@ -666,7 +666,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, > actual = to % 2; > /* Start write from odd address. */ > if (actual) { > - nor->program_opcode = OPCODE_BP; > + nor->program_opcode = SPINOR_OP_BP; > > /* write one byte. */ > nor->write(nor, to, 1, retlen, buf); > @@ -678,7 +678,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, > > /* Write out most of the data here. */ > for (; actual < len - 1; actual += 2) { > - nor->program_opcode = OPCODE_AAI_WP; > + nor->program_opcode = SPINOR_OP_AAI_WP; > > /* write two bytes. */ > nor->write(nor, to, 2, retlen, buf + actual); > @@ -699,7 +699,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, > if (actual != len) { > write_enable(nor); > > - nor->program_opcode = OPCODE_BP; > + nor->program_opcode = SPINOR_OP_BP; > nor->write(nor, to, 1, retlen, buf + actual); > > ret = wait_till_ready(nor); > @@ -773,7 +773,7 @@ static int macronix_quad_enable(struct spi_nor *nor) > write_enable(nor); > > nor->cmd_buf[0] = val | SR_QUAD_EN_MX; > - nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0); > + nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); > > if (wait_till_ready(nor)) > return 1; > @@ -798,7 +798,7 @@ static int write_sr_cr(struct spi_nor *nor, u16 val) > nor->cmd_buf[0] = val & 0xff; > nor->cmd_buf[1] = (val >> 8); > > - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 2, 0); > + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0); > } > > static int spansion_quad_enable(struct spi_nor *nor) > @@ -963,13 +963,13 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > > /* prefer "small sector" erase if possible */ > if (info->flags & SECT_4K) { > - nor->erase_opcode = OPCODE_BE_4K; > + nor->erase_opcode = SPINOR_OP_BE_4K; > mtd->erasesize = 4096; > } else if (info->flags & SECT_4K_PMC) { > - nor->erase_opcode = OPCODE_BE_4K_PMC; > + nor->erase_opcode = SPINOR_OP_BE_4K_PMC; > mtd->erasesize = 4096; > } else { > - nor->erase_opcode = OPCODE_SE; > + nor->erase_opcode = SPINOR_OP_SE; > mtd->erasesize = info->sector_size; > } > > @@ -1010,23 +1010,23 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > /* Default commands */ > switch (nor->flash_read) { > case SPI_NOR_QUAD: > - nor->read_opcode = OPCODE_QUAD_READ; > + nor->read_opcode = SPINOR_OP_QUAD_READ; > break; > case SPI_NOR_DUAL: > - nor->read_opcode = OPCODE_DUAL_READ; > + nor->read_opcode = SPINOR_OP_DUAL_READ; > break; > case SPI_NOR_FAST: > - nor->read_opcode = OPCODE_FAST_READ; > + nor->read_opcode = SPINOR_OP_FAST_READ; > break; > case SPI_NOR_NORMAL: > - nor->read_opcode = OPCODE_NORM_READ; > + nor->read_opcode = SPINOR_OP_NORM_READ; > break; > default: > dev_err(dev, "No Read opcode defined\n"); > return -EINVAL; > } > > - nor->program_opcode = OPCODE_PP; > + nor->program_opcode = SPINOR_OP_PP; > > if (info->addr_width) > nor->addr_width = info->addr_width; > @@ -1037,21 +1037,21 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > /* Dedicated 4-byte command set */ > switch (nor->flash_read) { > case SPI_NOR_QUAD: > - nor->read_opcode = OPCODE_QUAD_READ_4B; > + nor->read_opcode = SPINOR_OP_QUAD_READ_4B; > break; > case SPI_NOR_DUAL: > - nor->read_opcode = OPCODE_DUAL_READ_4B; > + nor->read_opcode = SPINOR_OP_DUAL_READ_4B; > break; > case SPI_NOR_FAST: > - nor->read_opcode = OPCODE_FAST_READ_4B; > + nor->read_opcode = SPINOR_OP_FAST_READ_4B; > break; > case SPI_NOR_NORMAL: > - nor->read_opcode = OPCODE_NORM_READ_4B; > + nor->read_opcode = SPINOR_OP_NORM_READ_4B; > break; > } > - nor->program_opcode = OPCODE_PP_4B; > + nor->program_opcode = SPINOR_OP_PP_4B; > /* No small sector erase for 4-byte command set */ > - nor->erase_opcode = OPCODE_SE_4B; > + nor->erase_opcode = SPINOR_OP_SE_4B; > mtd->erasesize = info->sector_size; > } else > set_4byte(nor, info->jedec_id, 1); > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 558097e14932..2c827b5bf773 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -2,41 +2,41 @@ > #define __LINUX_MTD_SPI_NOR_H > > /* Flash opcodes. */ > -#define OPCODE_WREN 0x06 /* Write enable */ > -#define OPCODE_RDSR 0x05 /* Read status register */ > -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ > -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ > -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ > -#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > -#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ > -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ > -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ > -#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ > -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ > -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ > -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ > -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ > -#define OPCODE_RDCR 0x35 /* Read configuration register */ > +#define SPINOR_OP_WREN 0x06 /* Write enable */ > +#define SPINOR_OP_RDSR 0x05 /* Read status register */ > +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ > +#define SPINOR_OP_NORM_READ 0x03 /* Read data bytes (low frequency) */ > +#define SPINOR_OP_FAST_READ 0x0b /* Read data bytes (high frequency) */ > +#define SPINOR_OP_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > +#define SPINOR_OP_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ > +#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ > +#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ > +#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ > +#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ > +#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ > +#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ > +#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ > +#define SPINOR_OP_RDCR 0x35 /* Read configuration register */ > > /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ > -#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ > -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ > -#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ > -#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ > -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ > -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ > +#define SPINOR_OP_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ > +#define SPINOR_OP_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ > +#define SPINOR_OP_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ > +#define SPINOR_OP_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ > +#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ > +#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ > > /* Used for SST flashes only. */ > -#define OPCODE_BP 0x02 /* Byte program */ > -#define OPCODE_WRDI 0x04 /* Write disable */ > -#define OPCODE_AAI_WP 0xad /* Auto address increment word program */ > +#define SPINOR_OP_BP 0x02 /* Byte program */ > +#define SPINOR_OP_WRDI 0x04 /* Write disable */ > +#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ > > /* Used for Macronix and Winbond flashes. */ > -#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ > -#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ > +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ > +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ > > /* Used for Spansion flashes only. */ > -#define OPCODE_BRWR 0x17 /* Bank register write */ > +#define SPINOR_OP_BRWR 0x17 /* Bank register write */ > > /* Status Register bits. */ > #define SR_WIP 1 /* Write in progress */ > -- > 1.8.3.2 > > > Acked-by: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 2/9] mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_* @ 2014-04-10 7:42 ` Huang Shijie 0 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:42 UTC (permalink / raw) To: Brian Norris; +Cc: Marek Vasut, Lee Jones, linux-mtd, linux-spi On Wed, Apr 09, 2014 at 10:32:47AM -0700, Brian Norris wrote: > Qualify these with a better namespace, and prepare them for use in more > drivers. > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > --- > drivers/mtd/devices/m25p80.c | 4 +-- > drivers/mtd/spi-nor/fsl-quadspi.c | 58 +++++++++++++++++------------------ > drivers/mtd/spi-nor/spi-nor.c | 64 +++++++++++++++++++-------------------- > include/linux/mtd/spi-nor.h | 54 ++++++++++++++++----------------- > 4 files changed, 90 insertions(+), 90 deletions(-) > > diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c > index 4af6400ccd95..1557d8f672c1 100644 > --- a/drivers/mtd/devices/m25p80.c > +++ b/drivers/mtd/devices/m25p80.c > @@ -86,7 +86,7 @@ static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len, > > spi_message_init(&m); > > - if (nor->program_opcode == OPCODE_AAI_WP && nor->sst_write_second) > + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) > cmd_sz = 1; > > flash->command[0] = nor->program_opcode; > @@ -171,7 +171,7 @@ static int m25p80_erase(struct spi_nor *nor, loff_t offset) > return ret; > > /* Send write enable, then erase commands. */ > - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); > + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); > if (ret) > return ret; > > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c > index 6dc08ed950c8..2977f026f39d 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -294,12 +294,12 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > lut_base = SEQID_QUAD_READ * 4; > > if (q->nor_size <= SZ_16M) { > - cmd = OPCODE_QUAD_READ; > + cmd = SPINOR_OP_QUAD_READ; > addrlen = ADDR24BIT; > dummy = 8; > } else { > /* use the 4-byte address */ > - cmd = OPCODE_QUAD_READ; > + cmd = SPINOR_OP_QUAD_READ; > addrlen = ADDR32BIT; > dummy = 8; > } > @@ -311,17 +311,17 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > > /* Write enable */ > lut_base = SEQID_WREN * 4; > - writel(LUT0(CMD, PAD1, OPCODE_WREN), base + QUADSPI_LUT(lut_base)); > + writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); > > /* Page Program */ > lut_base = SEQID_PP * 4; > > if (q->nor_size <= SZ_16M) { > - cmd = OPCODE_PP; > + cmd = SPINOR_OP_PP; > addrlen = ADDR24BIT; > } else { > /* use the 4-byte address */ > - cmd = OPCODE_PP; > + cmd = SPINOR_OP_PP; > addrlen = ADDR32BIT; > } > > @@ -331,18 +331,18 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > > /* Read Status */ > lut_base = SEQID_RDSR * 4; > - writel(LUT0(CMD, PAD1, OPCODE_RDSR) | LUT1(READ, PAD1, 0x1), > + writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1), > base + QUADSPI_LUT(lut_base)); > > /* Erase a sector */ > lut_base = SEQID_SE * 4; > > if (q->nor_size <= SZ_16M) { > - cmd = OPCODE_SE; > + cmd = SPINOR_OP_SE; > addrlen = ADDR24BIT; > } else { > /* use the 4-byte address */ > - cmd = OPCODE_SE; > + cmd = SPINOR_OP_SE; > addrlen = ADDR32BIT; > } > > @@ -351,35 +351,35 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > > /* Erase the whole chip */ > lut_base = SEQID_CHIP_ERASE * 4; > - writel(LUT0(CMD, PAD1, OPCODE_CHIP_ERASE), > + writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), > base + QUADSPI_LUT(lut_base)); > > /* READ ID */ > lut_base = SEQID_RDID * 4; > - writel(LUT0(CMD, PAD1, OPCODE_RDID) | LUT1(READ, PAD1, 0x8), > + writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8), > base + QUADSPI_LUT(lut_base)); > > /* Write Register */ > lut_base = SEQID_WRSR * 4; > - writel(LUT0(CMD, PAD1, OPCODE_WRSR) | LUT1(WRITE, PAD1, 0x2), > + writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2), > base + QUADSPI_LUT(lut_base)); > > /* Read Configuration Register */ > lut_base = SEQID_RDCR * 4; > - writel(LUT0(CMD, PAD1, OPCODE_RDCR) | LUT1(READ, PAD1, 0x1), > + writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1), > base + QUADSPI_LUT(lut_base)); > > /* Write disable */ > lut_base = SEQID_WRDI * 4; > - writel(LUT0(CMD, PAD1, OPCODE_WRDI), base + QUADSPI_LUT(lut_base)); > + writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base)); > > /* Enter 4 Byte Mode (Micron) */ > lut_base = SEQID_EN4B * 4; > - writel(LUT0(CMD, PAD1, OPCODE_EN4B), base + QUADSPI_LUT(lut_base)); > + writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base)); > > /* Enter 4 Byte Mode (Spansion) */ > lut_base = SEQID_BRWR * 4; > - writel(LUT0(CMD, PAD1, OPCODE_BRWR), base + QUADSPI_LUT(lut_base)); > + writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); > > fsl_qspi_lock_lut(q); > } > @@ -388,29 +388,29 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) > { > switch (cmd) { > - case OPCODE_QUAD_READ: > + case SPINOR_OP_QUAD_READ: > return SEQID_QUAD_READ; > - case OPCODE_WREN: > + case SPINOR_OP_WREN: > return SEQID_WREN; > - case OPCODE_WRDI: > + case SPINOR_OP_WRDI: > return SEQID_WRDI; > - case OPCODE_RDSR: > + case SPINOR_OP_RDSR: > return SEQID_RDSR; > - case OPCODE_SE: > + case SPINOR_OP_SE: > return SEQID_SE; > - case OPCODE_CHIP_ERASE: > + case SPINOR_OP_CHIP_ERASE: > return SEQID_CHIP_ERASE; > - case OPCODE_PP: > + case SPINOR_OP_PP: > return SEQID_PP; > - case OPCODE_RDID: > + case SPINOR_OP_RDID: > return SEQID_RDID; > - case OPCODE_WRSR: > + case SPINOR_OP_WRSR: > return SEQID_WRSR; > - case OPCODE_RDCR: > + case SPINOR_OP_RDCR: > return SEQID_RDCR; > - case OPCODE_EN4B: > + case SPINOR_OP_EN4B: > return SEQID_EN4B; > - case OPCODE_BRWR: > + case SPINOR_OP_BRWR: > return SEQID_BRWR; > default: > dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd); > @@ -688,7 +688,7 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len, > if (ret) > return ret; > > - if (opcode == OPCODE_CHIP_ERASE) > + if (opcode == SPINOR_OP_CHIP_ERASE) > fsl_qspi_invalid(q); > > } else if (len > 0) { > @@ -750,7 +750,7 @@ static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs) > return ret; > > /* Send write enable, then erase commands. */ > - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); > + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); > if (ret) > return ret; > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 5cd86eb2a5f0..462f1c8c3a7d 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -34,7 +34,7 @@ static int read_sr(struct spi_nor *nor) > int ret; > u8 val; > > - ret = nor->read_reg(nor, OPCODE_RDSR, &val, 1); > + ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); > if (ret < 0) { > pr_err("error %d reading SR\n", (int) ret); > return ret; > @@ -53,7 +53,7 @@ static int read_cr(struct spi_nor *nor) > int ret; > u8 val; > > - ret = nor->read_reg(nor, OPCODE_RDCR, &val, 1); > + ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); > if (ret < 0) { > dev_err(nor->dev, "error %d reading CR\n", ret); > return ret; > @@ -87,7 +87,7 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) > static inline int write_sr(struct spi_nor *nor, u8 val) > { > nor->cmd_buf[0] = val; > - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0); > + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); > } > > /* > @@ -96,7 +96,7 @@ static inline int write_sr(struct spi_nor *nor, u8 val) > */ > static inline int write_enable(struct spi_nor *nor) > { > - return nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0); > + return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); > } > > /* > @@ -104,7 +104,7 @@ static inline int write_enable(struct spi_nor *nor) > */ > static inline int write_disable(struct spi_nor *nor) > { > - return nor->write_reg(nor, OPCODE_WRDI, NULL, 0, 0); > + return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0); > } > > static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) > @@ -128,7 +128,7 @@ static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable) > if (need_wren) > write_enable(nor); > > - cmd = enable ? OPCODE_EN4B : OPCODE_EX4B; > + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; > status = nor->write_reg(nor, cmd, NULL, 0, 0); > if (need_wren) > write_disable(nor); > @@ -137,7 +137,7 @@ static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable) > default: > /* Spansion style */ > nor->cmd_buf[0] = enable << 7; > - return nor->write_reg(nor, OPCODE_BRWR, nor->cmd_buf, 1, 0); > + return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0); > } > } > > @@ -189,7 +189,7 @@ static int erase_chip(struct spi_nor *nor) > /* Send write enable, then erase commands. */ > write_enable(nor); > > - return nor->write_reg(nor, OPCODE_CHIP_ERASE, NULL, 0, 0); > + return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0); > } > > static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) > @@ -249,7 +249,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) > } > > /* REVISIT in some cases we could speed up erasing large regions > - * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up > + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up > * to use "small sector erase", but that's not always optimal. > */ > > @@ -381,7 +381,7 @@ struct flash_info { > u32 jedec_id; > u16 ext_id; > > - /* The size listed here is what works with OPCODE_SE, which isn't > + /* The size listed here is what works with SPINOR_OP_SE, which isn't > * necessarily called a "sector" by the vendor. > */ > unsigned sector_size; > @@ -391,11 +391,11 @@ struct flash_info { > u16 addr_width; > > u16 flags; > -#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ > +#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ > #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ > #define SST_WRITE 0x04 /* use SST byte programming */ > #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ > -#define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */ > +#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ > #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ > #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ > }; > @@ -594,7 +594,7 @@ static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor) > u16 ext_jedec; > struct flash_info *info; > > - tmp = nor->read_reg(nor, OPCODE_RDID, id, 5); > + tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5); > if (tmp < 0) { > dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp); > return ERR_PTR(tmp); > @@ -666,7 +666,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, > actual = to % 2; > /* Start write from odd address. */ > if (actual) { > - nor->program_opcode = OPCODE_BP; > + nor->program_opcode = SPINOR_OP_BP; > > /* write one byte. */ > nor->write(nor, to, 1, retlen, buf); > @@ -678,7 +678,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, > > /* Write out most of the data here. */ > for (; actual < len - 1; actual += 2) { > - nor->program_opcode = OPCODE_AAI_WP; > + nor->program_opcode = SPINOR_OP_AAI_WP; > > /* write two bytes. */ > nor->write(nor, to, 2, retlen, buf + actual); > @@ -699,7 +699,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, > if (actual != len) { > write_enable(nor); > > - nor->program_opcode = OPCODE_BP; > + nor->program_opcode = SPINOR_OP_BP; > nor->write(nor, to, 1, retlen, buf + actual); > > ret = wait_till_ready(nor); > @@ -773,7 +773,7 @@ static int macronix_quad_enable(struct spi_nor *nor) > write_enable(nor); > > nor->cmd_buf[0] = val | SR_QUAD_EN_MX; > - nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0); > + nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); > > if (wait_till_ready(nor)) > return 1; > @@ -798,7 +798,7 @@ static int write_sr_cr(struct spi_nor *nor, u16 val) > nor->cmd_buf[0] = val & 0xff; > nor->cmd_buf[1] = (val >> 8); > > - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 2, 0); > + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0); > } > > static int spansion_quad_enable(struct spi_nor *nor) > @@ -963,13 +963,13 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > > /* prefer "small sector" erase if possible */ > if (info->flags & SECT_4K) { > - nor->erase_opcode = OPCODE_BE_4K; > + nor->erase_opcode = SPINOR_OP_BE_4K; > mtd->erasesize = 4096; > } else if (info->flags & SECT_4K_PMC) { > - nor->erase_opcode = OPCODE_BE_4K_PMC; > + nor->erase_opcode = SPINOR_OP_BE_4K_PMC; > mtd->erasesize = 4096; > } else { > - nor->erase_opcode = OPCODE_SE; > + nor->erase_opcode = SPINOR_OP_SE; > mtd->erasesize = info->sector_size; > } > > @@ -1010,23 +1010,23 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > /* Default commands */ > switch (nor->flash_read) { > case SPI_NOR_QUAD: > - nor->read_opcode = OPCODE_QUAD_READ; > + nor->read_opcode = SPINOR_OP_QUAD_READ; > break; > case SPI_NOR_DUAL: > - nor->read_opcode = OPCODE_DUAL_READ; > + nor->read_opcode = SPINOR_OP_DUAL_READ; > break; > case SPI_NOR_FAST: > - nor->read_opcode = OPCODE_FAST_READ; > + nor->read_opcode = SPINOR_OP_FAST_READ; > break; > case SPI_NOR_NORMAL: > - nor->read_opcode = OPCODE_NORM_READ; > + nor->read_opcode = SPINOR_OP_NORM_READ; > break; > default: > dev_err(dev, "No Read opcode defined\n"); > return -EINVAL; > } > > - nor->program_opcode = OPCODE_PP; > + nor->program_opcode = SPINOR_OP_PP; > > if (info->addr_width) > nor->addr_width = info->addr_width; > @@ -1037,21 +1037,21 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > /* Dedicated 4-byte command set */ > switch (nor->flash_read) { > case SPI_NOR_QUAD: > - nor->read_opcode = OPCODE_QUAD_READ_4B; > + nor->read_opcode = SPINOR_OP_QUAD_READ_4B; > break; > case SPI_NOR_DUAL: > - nor->read_opcode = OPCODE_DUAL_READ_4B; > + nor->read_opcode = SPINOR_OP_DUAL_READ_4B; > break; > case SPI_NOR_FAST: > - nor->read_opcode = OPCODE_FAST_READ_4B; > + nor->read_opcode = SPINOR_OP_FAST_READ_4B; > break; > case SPI_NOR_NORMAL: > - nor->read_opcode = OPCODE_NORM_READ_4B; > + nor->read_opcode = SPINOR_OP_NORM_READ_4B; > break; > } > - nor->program_opcode = OPCODE_PP_4B; > + nor->program_opcode = SPINOR_OP_PP_4B; > /* No small sector erase for 4-byte command set */ > - nor->erase_opcode = OPCODE_SE_4B; > + nor->erase_opcode = SPINOR_OP_SE_4B; > mtd->erasesize = info->sector_size; > } else > set_4byte(nor, info->jedec_id, 1); > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 558097e14932..2c827b5bf773 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -2,41 +2,41 @@ > #define __LINUX_MTD_SPI_NOR_H > > /* Flash opcodes. */ > -#define OPCODE_WREN 0x06 /* Write enable */ > -#define OPCODE_RDSR 0x05 /* Read status register */ > -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ > -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ > -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ > -#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > -#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ > -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ > -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ > -#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ > -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ > -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ > -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ > -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ > -#define OPCODE_RDCR 0x35 /* Read configuration register */ > +#define SPINOR_OP_WREN 0x06 /* Write enable */ > +#define SPINOR_OP_RDSR 0x05 /* Read status register */ > +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ > +#define SPINOR_OP_NORM_READ 0x03 /* Read data bytes (low frequency) */ > +#define SPINOR_OP_FAST_READ 0x0b /* Read data bytes (high frequency) */ > +#define SPINOR_OP_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > +#define SPINOR_OP_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ > +#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ > +#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ > +#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ > +#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ > +#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ > +#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ > +#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ > +#define SPINOR_OP_RDCR 0x35 /* Read configuration register */ > > /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ > -#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ > -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ > -#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ > -#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ > -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ > -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ > +#define SPINOR_OP_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ > +#define SPINOR_OP_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ > +#define SPINOR_OP_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ > +#define SPINOR_OP_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ > +#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ > +#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ > > /* Used for SST flashes only. */ > -#define OPCODE_BP 0x02 /* Byte program */ > -#define OPCODE_WRDI 0x04 /* Write disable */ > -#define OPCODE_AAI_WP 0xad /* Auto address increment word program */ > +#define SPINOR_OP_BP 0x02 /* Byte program */ > +#define SPINOR_OP_WRDI 0x04 /* Write disable */ > +#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ > > /* Used for Macronix and Winbond flashes. */ > -#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ > -#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ > +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ > +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ > > /* Used for Spansion flashes only. */ > -#define OPCODE_BRWR 0x17 /* Bank register write */ > +#define SPINOR_OP_BRWR 0x17 /* Bank register write */ > > /* Status Register bits. */ > #define SR_WIP 1 /* Write in progress */ > -- > 1.8.3.2 > > > Acked-by: Huang Shijie <b32955@freescale.com> ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:32 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Brian Norris, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut serial_flash_cmds.h defines our opcodes a little differently. Let's borrow its naming, since it's borrowed from the SFDP standard, and it's more extensible. This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode listing. Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++-------- include/linux/mtd/spi-nor.h | 24 ++++++++++++++++-------- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 462f1c8c3a7d..de04d6e2cf02 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1010,16 +1010,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* Default commands */ switch (nor->flash_read) { case SPI_NOR_QUAD: - nor->read_opcode = SPINOR_OP_QUAD_READ; + nor->read_opcode = SPINOR_OP_READ_1_1_4; break; case SPI_NOR_DUAL: - nor->read_opcode = SPINOR_OP_DUAL_READ; + nor->read_opcode = SPINOR_OP_READ_1_1_2; break; case SPI_NOR_FAST: - nor->read_opcode = SPINOR_OP_FAST_READ; + nor->read_opcode = SPINOR_OP_READ_FAST; break; case SPI_NOR_NORMAL: - nor->read_opcode = SPINOR_OP_NORM_READ; + nor->read_opcode = SPINOR_OP_READ; break; default: dev_err(dev, "No Read opcode defined\n"); @@ -1037,16 +1037,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* Dedicated 4-byte command set */ switch (nor->flash_read) { case SPI_NOR_QUAD: - nor->read_opcode = SPINOR_OP_QUAD_READ_4B; + nor->read_opcode = SPINOR_OP_READ4_1_1_4; break; case SPI_NOR_DUAL: - nor->read_opcode = SPINOR_OP_DUAL_READ_4B; + nor->read_opcode = SPINOR_OP_READ4_1_1_2; break; case SPI_NOR_FAST: - nor->read_opcode = SPINOR_OP_FAST_READ_4B; + nor->read_opcode = SPINOR_OP_READ4_FAST; break; case SPI_NOR_NORMAL: - nor->read_opcode = SPINOR_OP_NORM_READ_4B; + nor->read_opcode = SPINOR_OP_READ4; break; } nor->program_opcode = SPINOR_OP_PP_4B; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2c827b5bf773..2a5c30196749 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -1,14 +1,22 @@ #ifndef __LINUX_MTD_SPI_NOR_H #define __LINUX_MTD_SPI_NOR_H +/* + * Note on opcode nomenclature: some opcodes have a format like + * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number + * of I/O lines used for the opcode, address, and data (respectively). The + * FUNCTION has an optional suffix of '4', to represent an opcode which + * requires a 4-byte (32-bit) address. + */ + /* Flash opcodes. */ #define SPINOR_OP_WREN 0x06 /* Write enable */ #define SPINOR_OP_RDSR 0x05 /* Read status register */ #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ -#define SPINOR_OP_NORM_READ 0x03 /* Read data bytes (low frequency) */ -#define SPINOR_OP_FAST_READ 0x0b /* Read data bytes (high frequency) */ -#define SPINOR_OP_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ -#define SPINOR_OP_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ +#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ +#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */ #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ @@ -19,10 +27,10 @@ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ -#define SPINOR_OP_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ -#define SPINOR_OP_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ -#define SPINOR_OP_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ -#define SPINOR_OP_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */ +#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */ +#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd; +Cc: Marek Vasut, Huang Shijie, Brian Norris, Lee Jones, linux-spi serial_flash_cmds.h defines our opcodes a little differently. Let's borrow its naming, since it's borrowed from the SFDP standard, and it's more extensible. This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode listing. Signed-off-by: Brian Norris <computersforpeace@gmail.com> --- drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++-------- include/linux/mtd/spi-nor.h | 24 ++++++++++++++++-------- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 462f1c8c3a7d..de04d6e2cf02 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1010,16 +1010,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* Default commands */ switch (nor->flash_read) { case SPI_NOR_QUAD: - nor->read_opcode = SPINOR_OP_QUAD_READ; + nor->read_opcode = SPINOR_OP_READ_1_1_4; break; case SPI_NOR_DUAL: - nor->read_opcode = SPINOR_OP_DUAL_READ; + nor->read_opcode = SPINOR_OP_READ_1_1_2; break; case SPI_NOR_FAST: - nor->read_opcode = SPINOR_OP_FAST_READ; + nor->read_opcode = SPINOR_OP_READ_FAST; break; case SPI_NOR_NORMAL: - nor->read_opcode = SPINOR_OP_NORM_READ; + nor->read_opcode = SPINOR_OP_READ; break; default: dev_err(dev, "No Read opcode defined\n"); @@ -1037,16 +1037,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, /* Dedicated 4-byte command set */ switch (nor->flash_read) { case SPI_NOR_QUAD: - nor->read_opcode = SPINOR_OP_QUAD_READ_4B; + nor->read_opcode = SPINOR_OP_READ4_1_1_4; break; case SPI_NOR_DUAL: - nor->read_opcode = SPINOR_OP_DUAL_READ_4B; + nor->read_opcode = SPINOR_OP_READ4_1_1_2; break; case SPI_NOR_FAST: - nor->read_opcode = SPINOR_OP_FAST_READ_4B; + nor->read_opcode = SPINOR_OP_READ4_FAST; break; case SPI_NOR_NORMAL: - nor->read_opcode = SPINOR_OP_NORM_READ_4B; + nor->read_opcode = SPINOR_OP_READ4; break; } nor->program_opcode = SPINOR_OP_PP_4B; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2c827b5bf773..2a5c30196749 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -1,14 +1,22 @@ #ifndef __LINUX_MTD_SPI_NOR_H #define __LINUX_MTD_SPI_NOR_H +/* + * Note on opcode nomenclature: some opcodes have a format like + * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number + * of I/O lines used for the opcode, address, and data (respectively). The + * FUNCTION has an optional suffix of '4', to represent an opcode which + * requires a 4-byte (32-bit) address. + */ + /* Flash opcodes. */ #define SPINOR_OP_WREN 0x06 /* Write enable */ #define SPINOR_OP_RDSR 0x05 /* Read status register */ #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ -#define SPINOR_OP_NORM_READ 0x03 /* Read data bytes (low frequency) */ -#define SPINOR_OP_FAST_READ 0x0b /* Read data bytes (high frequency) */ -#define SPINOR_OP_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ -#define SPINOR_OP_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ +#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ +#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */ #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ @@ -19,10 +27,10 @@ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ -#define SPINOR_OP_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ -#define SPINOR_OP_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ -#define SPINOR_OP_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ -#define SPINOR_OP_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */ +#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */ +#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1397064774-31784-3-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:41 ` Marek Vasut -1 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:41 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA On Wednesday, April 09, 2014 at 07:32:48 PM, Brian Norris wrote: > serial_flash_cmds.h defines our opcodes a little differently. Let's > borrow its naming, since it's borrowed from the SFDP standard, and it's > more extensible. > > This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode > listing. > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Reviewed-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM @ 2014-04-09 17:41 ` Marek Vasut 0 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:41 UTC (permalink / raw) To: Brian Norris; +Cc: Huang Shijie, Lee Jones, linux-mtd, linux-spi On Wednesday, April 09, 2014 at 07:32:48 PM, Brian Norris wrote: > serial_flash_cmds.h defines our opcodes a little differently. Let's > borrow its naming, since it's borrowed from the SFDP standard, and it's > more extensible. > > This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode > listing. > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 7:43 ` Huang Shijie -1 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:43 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut On Wed, Apr 09, 2014 at 10:32:48AM -0700, Brian Norris wrote: > serial_flash_cmds.h defines our opcodes a little differently. Let's > borrow its naming, since it's borrowed from the SFDP standard, and it's > more extensible. > > This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode > listing. > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++-------- > include/linux/mtd/spi-nor.h | 24 ++++++++++++++++-------- > 2 files changed, 24 insertions(+), 16 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 462f1c8c3a7d..de04d6e2cf02 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -1010,16 +1010,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > /* Default commands */ > switch (nor->flash_read) { > case SPI_NOR_QUAD: > - nor->read_opcode = SPINOR_OP_QUAD_READ; > + nor->read_opcode = SPINOR_OP_READ_1_1_4; > break; > case SPI_NOR_DUAL: > - nor->read_opcode = SPINOR_OP_DUAL_READ; > + nor->read_opcode = SPINOR_OP_READ_1_1_2; > break; > case SPI_NOR_FAST: > - nor->read_opcode = SPINOR_OP_FAST_READ; > + nor->read_opcode = SPINOR_OP_READ_FAST; > break; > case SPI_NOR_NORMAL: > - nor->read_opcode = SPINOR_OP_NORM_READ; > + nor->read_opcode = SPINOR_OP_READ; > break; > default: > dev_err(dev, "No Read opcode defined\n"); > @@ -1037,16 +1037,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > /* Dedicated 4-byte command set */ > switch (nor->flash_read) { > case SPI_NOR_QUAD: > - nor->read_opcode = SPINOR_OP_QUAD_READ_4B; > + nor->read_opcode = SPINOR_OP_READ4_1_1_4; > break; > case SPI_NOR_DUAL: > - nor->read_opcode = SPINOR_OP_DUAL_READ_4B; > + nor->read_opcode = SPINOR_OP_READ4_1_1_2; > break; > case SPI_NOR_FAST: > - nor->read_opcode = SPINOR_OP_FAST_READ_4B; > + nor->read_opcode = SPINOR_OP_READ4_FAST; > break; > case SPI_NOR_NORMAL: > - nor->read_opcode = SPINOR_OP_NORM_READ_4B; > + nor->read_opcode = SPINOR_OP_READ4; > break; > } > nor->program_opcode = SPINOR_OP_PP_4B; > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 2c827b5bf773..2a5c30196749 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -1,14 +1,22 @@ > #ifndef __LINUX_MTD_SPI_NOR_H > #define __LINUX_MTD_SPI_NOR_H > > +/* > + * Note on opcode nomenclature: some opcodes have a format like > + * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number > + * of I/O lines used for the opcode, address, and data (respectively). The I like this naming. Acked-by: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM @ 2014-04-10 7:43 ` Huang Shijie 0 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:43 UTC (permalink / raw) To: Brian Norris; +Cc: Marek Vasut, Lee Jones, linux-mtd, linux-spi On Wed, Apr 09, 2014 at 10:32:48AM -0700, Brian Norris wrote: > serial_flash_cmds.h defines our opcodes a little differently. Let's > borrow its naming, since it's borrowed from the SFDP standard, and it's > more extensible. > > This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode > listing. > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > --- > drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++-------- > include/linux/mtd/spi-nor.h | 24 ++++++++++++++++-------- > 2 files changed, 24 insertions(+), 16 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 462f1c8c3a7d..de04d6e2cf02 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -1010,16 +1010,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > /* Default commands */ > switch (nor->flash_read) { > case SPI_NOR_QUAD: > - nor->read_opcode = SPINOR_OP_QUAD_READ; > + nor->read_opcode = SPINOR_OP_READ_1_1_4; > break; > case SPI_NOR_DUAL: > - nor->read_opcode = SPINOR_OP_DUAL_READ; > + nor->read_opcode = SPINOR_OP_READ_1_1_2; > break; > case SPI_NOR_FAST: > - nor->read_opcode = SPINOR_OP_FAST_READ; > + nor->read_opcode = SPINOR_OP_READ_FAST; > break; > case SPI_NOR_NORMAL: > - nor->read_opcode = SPINOR_OP_NORM_READ; > + nor->read_opcode = SPINOR_OP_READ; > break; > default: > dev_err(dev, "No Read opcode defined\n"); > @@ -1037,16 +1037,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, > /* Dedicated 4-byte command set */ > switch (nor->flash_read) { > case SPI_NOR_QUAD: > - nor->read_opcode = SPINOR_OP_QUAD_READ_4B; > + nor->read_opcode = SPINOR_OP_READ4_1_1_4; > break; > case SPI_NOR_DUAL: > - nor->read_opcode = SPINOR_OP_DUAL_READ_4B; > + nor->read_opcode = SPINOR_OP_READ4_1_1_2; > break; > case SPI_NOR_FAST: > - nor->read_opcode = SPINOR_OP_FAST_READ_4B; > + nor->read_opcode = SPINOR_OP_READ4_FAST; > break; > case SPI_NOR_NORMAL: > - nor->read_opcode = SPINOR_OP_NORM_READ_4B; > + nor->read_opcode = SPINOR_OP_READ4; > break; > } > nor->program_opcode = SPINOR_OP_PP_4B; > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 2c827b5bf773..2a5c30196749 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -1,14 +1,22 @@ > #ifndef __LINUX_MTD_SPI_NOR_H > #define __LINUX_MTD_SPI_NOR_H > > +/* > + * Note on opcode nomenclature: some opcodes have a format like > + * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number > + * of I/O lines used for the opcode, address, and data (respectively). The I like this naming. Acked-by: Huang Shijie <b32955@freescale.com> ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 7:47 ` Huang Shijie -1 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:47 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut On Wed, Apr 09, 2014 at 10:32:48AM -0700, Brian Norris wrote: > serial_flash_cmds.h defines our opcodes a little differently. Let's > borrow its naming, since it's borrowed from the SFDP standard, and it's > more extensible. > > This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode > listing. > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++-------- > include/linux/mtd/spi-nor.h | 24 ++++++++++++++++-------- Please also change the fsl-quadspi.c which also uses the opcodes. thanks Huang Shijie -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM @ 2014-04-10 7:47 ` Huang Shijie 0 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:47 UTC (permalink / raw) To: Brian Norris; +Cc: Marek Vasut, Lee Jones, linux-mtd, linux-spi On Wed, Apr 09, 2014 at 10:32:48AM -0700, Brian Norris wrote: > serial_flash_cmds.h defines our opcodes a little differently. Let's > borrow its naming, since it's borrowed from the SFDP standard, and it's > more extensible. > > This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode > listing. > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > --- > drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++-------- > include/linux/mtd/spi-nor.h | 24 ++++++++++++++++-------- Please also change the fsl-quadspi.c which also uses the opcodes. thanks Huang Shijie ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM 2014-04-10 7:47 ` Huang Shijie @ 2014-04-10 19:34 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-10 19:34 UTC (permalink / raw) To: Huang Shijie Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut On Thu, Apr 10, 2014 at 03:47:13PM +0800, Huang Shijie wrote: > On Wed, Apr 09, 2014 at 10:32:48AM -0700, Brian Norris wrote: > > serial_flash_cmds.h defines our opcodes a little differently. Let's > > borrow its naming, since it's borrowed from the SFDP standard, and it's > > more extensible. > > > > This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode > > listing. > > > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > > --- > > drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++-------- > > include/linux/mtd/spi-nor.h | 24 ++++++++++++++++-------- > Please also change the fsl-quadspi.c which also uses the opcodes. My bad. I missed compiling this driver. Fixed in v2. Thanks, Brian -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM @ 2014-04-10 19:34 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-10 19:34 UTC (permalink / raw) To: Huang Shijie; +Cc: Marek Vasut, Lee Jones, linux-mtd, linux-spi On Thu, Apr 10, 2014 at 03:47:13PM +0800, Huang Shijie wrote: > On Wed, Apr 09, 2014 at 10:32:48AM -0700, Brian Norris wrote: > > serial_flash_cmds.h defines our opcodes a little differently. Let's > > borrow its naming, since it's borrowed from the SFDP standard, and it's > > more extensible. > > > > This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode > > listing. > > > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > > --- > > drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++-------- > > include/linux/mtd/spi-nor.h | 24 ++++++++++++++++-------- > Please also change the fsl-quadspi.c which also uses the opcodes. My bad. I missed compiling this driver. Fixed in v2. Thanks, Brian ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 4/9] Documentation: spi-nor: rewrite some portions 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:32 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Brian Norris, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- WIP. This could be improved more (e.g., don't spend too much time documenting history; just document the current framework) Documentation/mtd/spi-nor.txt | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/Documentation/mtd/spi-nor.txt b/Documentation/mtd/spi-nor.txt index 294d5b06f892..bfcdeb94e053 100644 --- a/Documentation/mtd/spi-nor.txt +++ b/Documentation/mtd/spi-nor.txt @@ -1,16 +1,20 @@ SPI NOR framework ============================================ -Part I - why we need this framework? +Part I - Why do we need this framework? ------------------------------------- -The SPI bus controller only deals with the byte stream. -Some controller does not works like a SPI bus controller, it works -like a SPI NOR controller instead, such as the Freescale's QuadSPI controller. +SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus +controller operates agnostic of the specific device attached. However, some +controllers (such as Freescale's QuadSPI controller) cannot easily handle +arbitrary streams of bytes, but rather are designed specifically for SPI NOR. -The Freescale's QuadSPI controller should know the NOR commands to -find the right LUT sequence. Unfortunately, the old code can not meet -this requirement. +Specifically, Freescale's QuadSPI controller must know the NOR commands to +find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of +opcodes, addresses, or data payloads; a SPI controller simply knows to send or +receive bytes (Tx and Rx). Therefore, we must define a new layering scheme under +which the controller driver is aware of the opcodes, addressing, and other +details of the SPI NOR protocol. Part II - How does the framework work? ------------------------------------- @@ -40,7 +44,7 @@ m25p80 code anymore. ------------------------ SPI NOR chip - With the SPI NOR controller driver(Freescale QuadSPI), it looks like: + With the SPI NOR controller driver (Freescale QuadSPI), it looks like: MTD ------------------------ SPI NOR framework @@ -53,7 +57,6 @@ Part III - How can the drivers use the framework ------------------------------------- The main API is the spi_nor_scan(). Before you call the hook, you should -initialize the necessary fields for spi_nor{}. -Please see the drivers/mtd/spi-nor/spi-nor.c for detail. -Please also reference to the fsl-quadspi.c when you want to write a new driver -for a SPI NOR controller. +initialize the necessary fields for spi_nor{}. Please see the +drivers/mtd/spi-nor/spi-nor.c for detail. Please also refer to the fsl-quadspi.c +when you want to write a new driver for a SPI NOR controller. -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH 4/9] Documentation: spi-nor: rewrite some portions @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd; +Cc: Marek Vasut, Huang Shijie, Brian Norris, Lee Jones, linux-spi Signed-off-by: Brian Norris <computersforpeace@gmail.com> --- WIP. This could be improved more (e.g., don't spend too much time documenting history; just document the current framework) Documentation/mtd/spi-nor.txt | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/Documentation/mtd/spi-nor.txt b/Documentation/mtd/spi-nor.txt index 294d5b06f892..bfcdeb94e053 100644 --- a/Documentation/mtd/spi-nor.txt +++ b/Documentation/mtd/spi-nor.txt @@ -1,16 +1,20 @@ SPI NOR framework ============================================ -Part I - why we need this framework? +Part I - Why do we need this framework? ------------------------------------- -The SPI bus controller only deals with the byte stream. -Some controller does not works like a SPI bus controller, it works -like a SPI NOR controller instead, such as the Freescale's QuadSPI controller. +SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus +controller operates agnostic of the specific device attached. However, some +controllers (such as Freescale's QuadSPI controller) cannot easily handle +arbitrary streams of bytes, but rather are designed specifically for SPI NOR. -The Freescale's QuadSPI controller should know the NOR commands to -find the right LUT sequence. Unfortunately, the old code can not meet -this requirement. +Specifically, Freescale's QuadSPI controller must know the NOR commands to +find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of +opcodes, addresses, or data payloads; a SPI controller simply knows to send or +receive bytes (Tx and Rx). Therefore, we must define a new layering scheme under +which the controller driver is aware of the opcodes, addressing, and other +details of the SPI NOR protocol. Part II - How does the framework work? ------------------------------------- @@ -40,7 +44,7 @@ m25p80 code anymore. ------------------------ SPI NOR chip - With the SPI NOR controller driver(Freescale QuadSPI), it looks like: + With the SPI NOR controller driver (Freescale QuadSPI), it looks like: MTD ------------------------ SPI NOR framework @@ -53,7 +57,6 @@ Part III - How can the drivers use the framework ------------------------------------- The main API is the spi_nor_scan(). Before you call the hook, you should -initialize the necessary fields for spi_nor{}. -Please see the drivers/mtd/spi-nor/spi-nor.c for detail. -Please also reference to the fsl-quadspi.c when you want to write a new driver -for a SPI NOR controller. +initialize the necessary fields for spi_nor{}. Please see the +drivers/mtd/spi-nor/spi-nor.c for detail. Please also refer to the fsl-quadspi.c +when you want to write a new driver for a SPI NOR controller. -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1397064774-31784-4-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 4/9] Documentation: spi-nor: rewrite some portions 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:44 ` Marek Vasut -1 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:44 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA On Wednesday, April 09, 2014 at 07:32:49 PM, Brian Norris wrote: > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > WIP. This could be improved more (e.g., don't spend too much time > documenting history; just document the current framework) > > Documentation/mtd/spi-nor.txt | 27 +++++++++++++++------------ > 1 file changed, 15 insertions(+), 12 deletions(-) > > diff --git a/Documentation/mtd/spi-nor.txt b/Documentation/mtd/spi-nor.txt > index 294d5b06f892..bfcdeb94e053 100644 > --- a/Documentation/mtd/spi-nor.txt > +++ b/Documentation/mtd/spi-nor.txt > @@ -1,16 +1,20 @@ > SPI NOR framework > ============================================ > > -Part I - why we need this framework? > +Part I - Why do we need this framework? > ------------------------------------- The underline is not matching the length of the text now ;-) > > -The SPI bus controller only deals with the byte stream. > -Some controller does not works like a SPI bus controller, it works > -like a SPI NOR controller instead, such as the Freescale's QuadSPI > controller. +SPI bus controllers (drivers/spi/) only deal with streams of > bytes; the bus +controller operates agnostic of the specific device > attached. However, some +controllers (such as Freescale's QuadSPI > controller) cannot easily handle +arbitrary streams of bytes, but rather > are designed specifically for SPI NOR. You use the word 'specifically' here and below quick after one another, that doesn't sound nice when you read the text. > -The Freescale's QuadSPI controller should know the NOR commands to > -find the right LUT sequence. Unfortunately, the old code can not meet > -this requirement. > +Specifically, Freescale's QuadSPI controller must know the NOR commands to [...] Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 4/9] Documentation: spi-nor: rewrite some portions @ 2014-04-09 17:44 ` Marek Vasut 0 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:44 UTC (permalink / raw) To: Brian Norris; +Cc: Huang Shijie, Lee Jones, linux-mtd, linux-spi On Wednesday, April 09, 2014 at 07:32:49 PM, Brian Norris wrote: > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > --- > WIP. This could be improved more (e.g., don't spend too much time > documenting history; just document the current framework) > > Documentation/mtd/spi-nor.txt | 27 +++++++++++++++------------ > 1 file changed, 15 insertions(+), 12 deletions(-) > > diff --git a/Documentation/mtd/spi-nor.txt b/Documentation/mtd/spi-nor.txt > index 294d5b06f892..bfcdeb94e053 100644 > --- a/Documentation/mtd/spi-nor.txt > +++ b/Documentation/mtd/spi-nor.txt > @@ -1,16 +1,20 @@ > SPI NOR framework > ============================================ > > -Part I - why we need this framework? > +Part I - Why do we need this framework? > ------------------------------------- The underline is not matching the length of the text now ;-) > > -The SPI bus controller only deals with the byte stream. > -Some controller does not works like a SPI bus controller, it works > -like a SPI NOR controller instead, such as the Freescale's QuadSPI > controller. +SPI bus controllers (drivers/spi/) only deal with streams of > bytes; the bus +controller operates agnostic of the specific device > attached. However, some +controllers (such as Freescale's QuadSPI > controller) cannot easily handle +arbitrary streams of bytes, but rather > are designed specifically for SPI NOR. You use the word 'specifically' here and below quick after one another, that doesn't sound nice when you read the text. > -The Freescale's QuadSPI controller should know the NOR commands to > -find the right LUT sequence. Unfortunately, the old code can not meet > -this requirement. > +Specifically, Freescale's QuadSPI controller must know the NOR commands to [...] Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 58+ messages in thread
[parent not found: <201404091944.15631.marex-ynQEQJNshbs@public.gmane.org>]
* Re: [PATCH 4/9] Documentation: spi-nor: rewrite some portions 2014-04-09 17:44 ` Marek Vasut @ 2014-04-09 18:14 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 18:14 UTC (permalink / raw) To: Marek Vasut Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA On Wed, Apr 09, 2014 at 07:44:15PM +0200, Marek Vasut wrote: > On Wednesday, April 09, 2014 at 07:32:49 PM, Brian Norris wrote: > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > > --- > > WIP. This could be improved more (e.g., don't spend too much time > > documenting history; just document the current framework) > > > > Documentation/mtd/spi-nor.txt | 27 +++++++++++++++------------ > > 1 file changed, 15 insertions(+), 12 deletions(-) > > > > diff --git a/Documentation/mtd/spi-nor.txt b/Documentation/mtd/spi-nor.txt > > index 294d5b06f892..bfcdeb94e053 100644 > > --- a/Documentation/mtd/spi-nor.txt > > +++ b/Documentation/mtd/spi-nor.txt > > @@ -1,16 +1,20 @@ > > SPI NOR framework > > ============================================ > > > > -Part I - why we need this framework? > > +Part I - Why do we need this framework? > > ------------------------------------- > > The underline is not matching the length of the text now ;-) It wasn't exactly matching in the first place. But I'll adjust all the headings so the line is exactly as long as the text. > > > > -The SPI bus controller only deals with the byte stream. > > -Some controller does not works like a SPI bus controller, it works > > -like a SPI NOR controller instead, such as the Freescale's QuadSPI > > controller. +SPI bus controllers (drivers/spi/) only deal with streams of > > bytes; the bus +controller operates agnostic of the specific device > > attached. However, some +controllers (such as Freescale's QuadSPI > > controller) cannot easily handle +arbitrary streams of bytes, but rather > > are designed specifically for SPI NOR. > > You use the word 'specifically' here and below quick after one another, that > doesn't sound nice when you read the text. Sure, thanks for pointing it out. > > -The Freescale's QuadSPI controller should know the NOR commands to > > -find the right LUT sequence. Unfortunately, the old code can not meet > > -this requirement. > > +Specifically, Freescale's QuadSPI controller must know the NOR commands to My changes are pushed here temporarily, and I'll send v2 in the next day or so: http://git.infradead.org/users/norris/linux-mtd.git/shortlog/refs/heads/spinor Brian -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 4/9] Documentation: spi-nor: rewrite some portions @ 2014-04-09 18:14 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 18:14 UTC (permalink / raw) To: Marek Vasut; +Cc: Huang Shijie, Lee Jones, linux-mtd, linux-spi On Wed, Apr 09, 2014 at 07:44:15PM +0200, Marek Vasut wrote: > On Wednesday, April 09, 2014 at 07:32:49 PM, Brian Norris wrote: > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > > --- > > WIP. This could be improved more (e.g., don't spend too much time > > documenting history; just document the current framework) > > > > Documentation/mtd/spi-nor.txt | 27 +++++++++++++++------------ > > 1 file changed, 15 insertions(+), 12 deletions(-) > > > > diff --git a/Documentation/mtd/spi-nor.txt b/Documentation/mtd/spi-nor.txt > > index 294d5b06f892..bfcdeb94e053 100644 > > --- a/Documentation/mtd/spi-nor.txt > > +++ b/Documentation/mtd/spi-nor.txt > > @@ -1,16 +1,20 @@ > > SPI NOR framework > > ============================================ > > > > -Part I - why we need this framework? > > +Part I - Why do we need this framework? > > ------------------------------------- > > The underline is not matching the length of the text now ;-) It wasn't exactly matching in the first place. But I'll adjust all the headings so the line is exactly as long as the text. > > > > -The SPI bus controller only deals with the byte stream. > > -Some controller does not works like a SPI bus controller, it works > > -like a SPI NOR controller instead, such as the Freescale's QuadSPI > > controller. +SPI bus controllers (drivers/spi/) only deal with streams of > > bytes; the bus +controller operates agnostic of the specific device > > attached. However, some +controllers (such as Freescale's QuadSPI > > controller) cannot easily handle +arbitrary streams of bytes, but rather > > are designed specifically for SPI NOR. > > You use the word 'specifically' here and below quick after one another, that > doesn't sound nice when you read the text. Sure, thanks for pointing it out. > > -The Freescale's QuadSPI controller should know the NOR commands to > > -find the right LUT sequence. Unfortunately, the old code can not meet > > -this requirement. > > +Specifically, Freescale's QuadSPI controller must know the NOR commands to My changes are pushed here temporarily, and I'll send v2 in the next day or so: http://git.infradead.org/users/norris/linux-mtd.git/shortlog/refs/heads/spinor Brian ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 5/9] mtd: spi-nor: shorten Kconfig naming 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:32 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Brian Norris, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- drivers/mtd/Makefile | 2 +- drivers/mtd/devices/Kconfig | 2 +- drivers/mtd/spi-nor/Kconfig | 11 ++++++++--- drivers/mtd/spi-nor/Makefile | 2 +- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 40fd15344387..99bb9a1f6e16 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -32,5 +32,5 @@ inftl-objs := inftlcore.o inftlmount.o obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ -obj-$(CONFIG_MTD_SPI_NOR_BASE) += spi-nor/ +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ obj-$(CONFIG_MTD_UBI) += ubi/ diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig index 48aa1aa5820b..f9e32b53dfc6 100644 --- a/drivers/mtd/devices/Kconfig +++ b/drivers/mtd/devices/Kconfig @@ -80,7 +80,7 @@ config MTD_DATAFLASH_OTP config MTD_M25P80 tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)" - depends on SPI_MASTER && MTD_SPI_NOR_BASE + depends on SPI_MASTER && MTD_SPI_NOR help This enables access to most modern SPI flash chips, used for program and data storage. Series supported include Atmel AT26DF, diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 64cfc39ad17e..d682fb440e06 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -1,12 +1,17 @@ -config MTD_SPI_NOR_BASE - bool "the framework for SPI-NOR support" +config MTD_SPI_NOR + bool "SPI-NOR device support" depends on MTD help This is the framework for the SPI NOR which can be used by the SPI device drivers and the SPI-NOR device driver. + +if MTD_SPI_NOR + config SPI_FSL_QUADSPI tristate "Freescale Quad SPI controller" - depends on ARCH_MXC && MTD_SPI_NOR_BASE + depends on ARCH_MXC help This enables support for the Quad SPI controller in master mode. We only connect the NOR to this controller now. + +endif # MTD_SPI_NOR diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index 51f9d8b99ab7..6a7ce1462247 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -1,2 +1,2 @@ -obj-$(CONFIG_MTD_SPI_NOR_BASE) += spi-nor.o +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH 5/9] mtd: spi-nor: shorten Kconfig naming @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd; +Cc: Marek Vasut, Huang Shijie, Brian Norris, Lee Jones, linux-spi Signed-off-by: Brian Norris <computersforpeace@gmail.com> --- drivers/mtd/Makefile | 2 +- drivers/mtd/devices/Kconfig | 2 +- drivers/mtd/spi-nor/Kconfig | 11 ++++++++--- drivers/mtd/spi-nor/Makefile | 2 +- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 40fd15344387..99bb9a1f6e16 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -32,5 +32,5 @@ inftl-objs := inftlcore.o inftlmount.o obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ -obj-$(CONFIG_MTD_SPI_NOR_BASE) += spi-nor/ +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ obj-$(CONFIG_MTD_UBI) += ubi/ diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig index 48aa1aa5820b..f9e32b53dfc6 100644 --- a/drivers/mtd/devices/Kconfig +++ b/drivers/mtd/devices/Kconfig @@ -80,7 +80,7 @@ config MTD_DATAFLASH_OTP config MTD_M25P80 tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)" - depends on SPI_MASTER && MTD_SPI_NOR_BASE + depends on SPI_MASTER && MTD_SPI_NOR help This enables access to most modern SPI flash chips, used for program and data storage. Series supported include Atmel AT26DF, diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 64cfc39ad17e..d682fb440e06 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -1,12 +1,17 @@ -config MTD_SPI_NOR_BASE - bool "the framework for SPI-NOR support" +config MTD_SPI_NOR + bool "SPI-NOR device support" depends on MTD help This is the framework for the SPI NOR which can be used by the SPI device drivers and the SPI-NOR device driver. + +if MTD_SPI_NOR + config SPI_FSL_QUADSPI tristate "Freescale Quad SPI controller" - depends on ARCH_MXC && MTD_SPI_NOR_BASE + depends on ARCH_MXC help This enables support for the Quad SPI controller in master mode. We only connect the NOR to this controller now. + +endif # MTD_SPI_NOR diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index 51f9d8b99ab7..6a7ce1462247 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -1,2 +1,2 @@ -obj-$(CONFIG_MTD_SPI_NOR_BASE) += spi-nor.o +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1397064774-31784-5-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 5/9] mtd: spi-nor: shorten Kconfig naming 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:44 ` Marek Vasut -1 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:44 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA On Wednesday, April 09, 2014 at 07:32:50 PM, Brian Norris wrote: > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > drivers/mtd/Makefile | 2 +- > drivers/mtd/devices/Kconfig | 2 +- > drivers/mtd/spi-nor/Kconfig | 11 ++++++++--- > drivers/mtd/spi-nor/Makefile | 2 +- > 4 files changed, 11 insertions(+), 6 deletions(-) Reviewed-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 5/9] mtd: spi-nor: shorten Kconfig naming @ 2014-04-09 17:44 ` Marek Vasut 0 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:44 UTC (permalink / raw) To: Brian Norris; +Cc: Huang Shijie, Lee Jones, linux-mtd, linux-spi On Wednesday, April 09, 2014 at 07:32:50 PM, Brian Norris wrote: > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > --- > drivers/mtd/Makefile | 2 +- > drivers/mtd/devices/Kconfig | 2 +- > drivers/mtd/spi-nor/Kconfig | 11 ++++++++--- > drivers/mtd/spi-nor/Makefile | 2 +- > 4 files changed, 11 insertions(+), 6 deletions(-) Reviewed-by: Marek Vasut <marex@denx.de> Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 5/9] mtd: spi-nor: shorten Kconfig naming 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 7:39 ` Huang Shijie -1 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:39 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut On Wed, Apr 09, 2014 at 10:32:50AM -0700, Brian Norris wrote: > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > drivers/mtd/Makefile | 2 +- > drivers/mtd/devices/Kconfig | 2 +- > drivers/mtd/spi-nor/Kconfig | 11 ++++++++--- > drivers/mtd/spi-nor/Makefile | 2 +- > 4 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile > index 40fd15344387..99bb9a1f6e16 100644 > --- a/drivers/mtd/Makefile > +++ b/drivers/mtd/Makefile > @@ -32,5 +32,5 @@ inftl-objs := inftlcore.o inftlmount.o > > obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ > > -obj-$(CONFIG_MTD_SPI_NOR_BASE) += spi-nor/ > +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ > obj-$(CONFIG_MTD_UBI) += ubi/ > diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig > index 48aa1aa5820b..f9e32b53dfc6 100644 > --- a/drivers/mtd/devices/Kconfig > +++ b/drivers/mtd/devices/Kconfig > @@ -80,7 +80,7 @@ config MTD_DATAFLASH_OTP > > config MTD_M25P80 > tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)" > - depends on SPI_MASTER && MTD_SPI_NOR_BASE > + depends on SPI_MASTER && MTD_SPI_NOR > help > This enables access to most modern SPI flash chips, used for > program and data storage. Series supported include Atmel AT26DF, > diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig > index 64cfc39ad17e..d682fb440e06 100644 > --- a/drivers/mtd/spi-nor/Kconfig > +++ b/drivers/mtd/spi-nor/Kconfig > @@ -1,12 +1,17 @@ > -config MTD_SPI_NOR_BASE > - bool "the framework for SPI-NOR support" > +config MTD_SPI_NOR > + bool "SPI-NOR device support" > depends on MTD > help > This is the framework for the SPI NOR which can be used by the SPI > device drivers and the SPI-NOR device driver. > + > +if MTD_SPI_NOR > + > config SPI_FSL_QUADSPI > tristate "Freescale Quad SPI controller" > - depends on ARCH_MXC && MTD_SPI_NOR_BASE > + depends on ARCH_MXC > help > This enables support for the Quad SPI controller in master mode. > We only connect the NOR to this controller now. > + > +endif # MTD_SPI_NOR > diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile > index 51f9d8b99ab7..6a7ce1462247 100644 > --- a/drivers/mtd/spi-nor/Makefile > +++ b/drivers/mtd/spi-nor/Makefile > @@ -1,2 +1,2 @@ > -obj-$(CONFIG_MTD_SPI_NOR_BASE) += spi-nor.o > +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o > obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o > -- > 1.8.3.2 > > > Acked-by: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 5/9] mtd: spi-nor: shorten Kconfig naming @ 2014-04-10 7:39 ` Huang Shijie 0 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:39 UTC (permalink / raw) To: Brian Norris; +Cc: Marek Vasut, Lee Jones, linux-mtd, linux-spi On Wed, Apr 09, 2014 at 10:32:50AM -0700, Brian Norris wrote: > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > --- > drivers/mtd/Makefile | 2 +- > drivers/mtd/devices/Kconfig | 2 +- > drivers/mtd/spi-nor/Kconfig | 11 ++++++++--- > drivers/mtd/spi-nor/Makefile | 2 +- > 4 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile > index 40fd15344387..99bb9a1f6e16 100644 > --- a/drivers/mtd/Makefile > +++ b/drivers/mtd/Makefile > @@ -32,5 +32,5 @@ inftl-objs := inftlcore.o inftlmount.o > > obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ > > -obj-$(CONFIG_MTD_SPI_NOR_BASE) += spi-nor/ > +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ > obj-$(CONFIG_MTD_UBI) += ubi/ > diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig > index 48aa1aa5820b..f9e32b53dfc6 100644 > --- a/drivers/mtd/devices/Kconfig > +++ b/drivers/mtd/devices/Kconfig > @@ -80,7 +80,7 @@ config MTD_DATAFLASH_OTP > > config MTD_M25P80 > tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)" > - depends on SPI_MASTER && MTD_SPI_NOR_BASE > + depends on SPI_MASTER && MTD_SPI_NOR > help > This enables access to most modern SPI flash chips, used for > program and data storage. Series supported include Atmel AT26DF, > diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig > index 64cfc39ad17e..d682fb440e06 100644 > --- a/drivers/mtd/spi-nor/Kconfig > +++ b/drivers/mtd/spi-nor/Kconfig > @@ -1,12 +1,17 @@ > -config MTD_SPI_NOR_BASE > - bool "the framework for SPI-NOR support" > +config MTD_SPI_NOR > + bool "SPI-NOR device support" > depends on MTD > help > This is the framework for the SPI NOR which can be used by the SPI > device drivers and the SPI-NOR device driver. > + > +if MTD_SPI_NOR > + > config SPI_FSL_QUADSPI > tristate "Freescale Quad SPI controller" > - depends on ARCH_MXC && MTD_SPI_NOR_BASE > + depends on ARCH_MXC > help > This enables support for the Quad SPI controller in master mode. > We only connect the NOR to this controller now. > + > +endif # MTD_SPI_NOR > diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile > index 51f9d8b99ab7..6a7ce1462247 100644 > --- a/drivers/mtd/spi-nor/Makefile > +++ b/drivers/mtd/spi-nor/Makefile > @@ -1,2 +1,2 @@ > -obj-$(CONFIG_MTD_SPI_NOR_BASE) += spi-nor.o > +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o > obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o > -- > 1.8.3.2 > > > Acked-by: Huang Shijie <b32955@freescale.com> ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 6/9] mtd: st_spi_fsm: fixup Kconfig dependency 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:32 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Brian Norris, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut I hear that this driver should depend on ARCH_STI, and that "SH" is not actually a real symbol. At the same time, let's allow compile-testing on other ARCH'es. Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- drivers/mtd/devices/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig index f9e32b53dfc6..9aae1042c14f 100644 --- a/drivers/mtd/devices/Kconfig +++ b/drivers/mtd/devices/Kconfig @@ -212,7 +212,7 @@ config MTD_DOCG3 config MTD_ST_SPI_FSM tristate "ST Microelectronics SPI FSM Serial Flash Controller" - depends on ARM || SH + depends on ARCH_STI || COMPILE_TEST help This provides an MTD device driver for the ST Microelectronics SPI Fast Sequence Mode (FSM) Serial Flash Controller and support -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH 6/9] mtd: st_spi_fsm: fixup Kconfig dependency @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd; +Cc: Marek Vasut, Huang Shijie, Brian Norris, Lee Jones, linux-spi I hear that this driver should depend on ARCH_STI, and that "SH" is not actually a real symbol. At the same time, let's allow compile-testing on other ARCH'es. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Lee Jones <lee.jones@linaro.org> --- drivers/mtd/devices/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig index f9e32b53dfc6..9aae1042c14f 100644 --- a/drivers/mtd/devices/Kconfig +++ b/drivers/mtd/devices/Kconfig @@ -212,7 +212,7 @@ config MTD_DOCG3 config MTD_ST_SPI_FSM tristate "ST Microelectronics SPI FSM Serial Flash Controller" - depends on ARM || SH + depends on ARCH_STI || COMPILE_TEST help This provides an MTD device driver for the ST Microelectronics SPI Fast Sequence Mode (FSM) Serial Flash Controller and support -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1397064774-31784-6-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 6/9] mtd: st_spi_fsm: fixup Kconfig dependency 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 7:57 ` Lee Jones -1 siblings, 0 replies; 58+ messages in thread From: Lee Jones @ 2014-04-10 7:57 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut On Wed, 09 Apr 2014, Brian Norris wrote: > I hear that this driver should depend on ARCH_STI, and that "SH" is not > actually a real symbol. At the same time, let's allow compile-testing on > other ARCH'es. > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > drivers/mtd/devices/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 6/9] mtd: st_spi_fsm: fixup Kconfig dependency @ 2014-04-10 7:57 ` Lee Jones 0 siblings, 0 replies; 58+ messages in thread From: Lee Jones @ 2014-04-10 7:57 UTC (permalink / raw) To: Brian Norris; +Cc: Marek Vasut, Huang Shijie, linux-mtd, linux-spi On Wed, 09 Apr 2014, Brian Norris wrote: > I hear that this driver should depend on ARCH_STI, and that "SH" is not > actually a real symbol. At the same time, let's allow compile-testing on > other ARCH'es. > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > Cc: Lee Jones <lee.jones@linaro.org> > --- > drivers/mtd/devices/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Lee Jones <lee.jones@linaro.org> -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:32 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Brian Norris, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut These are also in serial_flash_cmds.h. (FWIW, I didn't know the C preprocessor allowed redefinitions without warning like this.) Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- drivers/mtd/devices/st_spi_fsm.c | 36 ------------------------------------ 1 file changed, 36 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 30082a09f68b..122a8a14ef84 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -201,42 +201,6 @@ #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */ -/* Flash Commands */ -#define FLASH_CMD_WREN 0x06 -#define FLASH_CMD_WRDI 0x04 -#define FLASH_CMD_RDID 0x9f -#define FLASH_CMD_RDSR 0x05 -#define FLASH_CMD_RDSR2 0x35 -#define FLASH_CMD_WRSR 0x01 -#define FLASH_CMD_SE_4K 0x20 -#define FLASH_CMD_SE_32K 0x52 -#define FLASH_CMD_SE 0xd8 -#define FLASH_CMD_CHIPERASE 0xc7 - -#define FLASH_CMD_READ 0x03 /* READ */ -#define FLASH_CMD_READ_FAST 0x0b /* FAST READ */ -#define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ -#define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */ -#define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ -#define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */ - -#define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */ -#define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */ -#define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */ -#define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ -#define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ - -#define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ -#define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ - -/* READ commands with 32-bit addressing (N25Q256 and S25FLxxxS) */ -#define FLASH_CMD_READ4 0x13 -#define FLASH_CMD_READ4_FAST 0x0c -#define FLASH_CMD_READ4_1_1_2 0x3c -#define FLASH_CMD_READ4_1_2_2 0xbc -#define FLASH_CMD_READ4_1_1_4 0x6c -#define FLASH_CMD_READ4_1_4_4 0xec - /* S25FLxxxS commands */ #define S25FL_CMD_WRITE4_1_1_4 0x34 #define S25FL_CMD_SE4 0xdc -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd; +Cc: Marek Vasut, Huang Shijie, Brian Norris, Lee Jones, linux-spi These are also in serial_flash_cmds.h. (FWIW, I didn't know the C preprocessor allowed redefinitions without warning like this.) Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Lee Jones <lee.jones@linaro.org> --- drivers/mtd/devices/st_spi_fsm.c | 36 ------------------------------------ 1 file changed, 36 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 30082a09f68b..122a8a14ef84 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -201,42 +201,6 @@ #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */ -/* Flash Commands */ -#define FLASH_CMD_WREN 0x06 -#define FLASH_CMD_WRDI 0x04 -#define FLASH_CMD_RDID 0x9f -#define FLASH_CMD_RDSR 0x05 -#define FLASH_CMD_RDSR2 0x35 -#define FLASH_CMD_WRSR 0x01 -#define FLASH_CMD_SE_4K 0x20 -#define FLASH_CMD_SE_32K 0x52 -#define FLASH_CMD_SE 0xd8 -#define FLASH_CMD_CHIPERASE 0xc7 - -#define FLASH_CMD_READ 0x03 /* READ */ -#define FLASH_CMD_READ_FAST 0x0b /* FAST READ */ -#define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ -#define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */ -#define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ -#define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */ - -#define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */ -#define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */ -#define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */ -#define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ -#define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ - -#define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ -#define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ - -/* READ commands with 32-bit addressing (N25Q256 and S25FLxxxS) */ -#define FLASH_CMD_READ4 0x13 -#define FLASH_CMD_READ4_FAST 0x0c -#define FLASH_CMD_READ4_1_1_2 0x3c -#define FLASH_CMD_READ4_1_2_2 0xbc -#define FLASH_CMD_READ4_1_1_4 0x6c -#define FLASH_CMD_READ4_1_4_4 0xec - /* S25FLxxxS commands */ #define S25FL_CMD_WRITE4_1_1_4 0x34 #define S25FL_CMD_SE4 0xdc -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1397064774-31784-7-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 7:56 ` Lee Jones -1 siblings, 0 replies; 58+ messages in thread From: Lee Jones @ 2014-04-10 7:56 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut > These are also in serial_flash_cmds.h. (FWIW, I didn't know the C > preprocessor allowed redefinitions without warning like this.) Right, I would have expected that too. I'll investigate. JOOI, have you build tested your changes? Non-tested: Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > drivers/mtd/devices/st_spi_fsm.c | 36 ------------------------------------ > 1 file changed, 36 deletions(-) > > diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c > index 30082a09f68b..122a8a14ef84 100644 > --- a/drivers/mtd/devices/st_spi_fsm.c > +++ b/drivers/mtd/devices/st_spi_fsm.c > @@ -201,42 +201,6 @@ > > #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */ > > -/* Flash Commands */ > -#define FLASH_CMD_WREN 0x06 > -#define FLASH_CMD_WRDI 0x04 > -#define FLASH_CMD_RDID 0x9f > -#define FLASH_CMD_RDSR 0x05 > -#define FLASH_CMD_RDSR2 0x35 > -#define FLASH_CMD_WRSR 0x01 > -#define FLASH_CMD_SE_4K 0x20 > -#define FLASH_CMD_SE_32K 0x52 > -#define FLASH_CMD_SE 0xd8 > -#define FLASH_CMD_CHIPERASE 0xc7 > - > -#define FLASH_CMD_READ 0x03 /* READ */ > -#define FLASH_CMD_READ_FAST 0x0b /* FAST READ */ > -#define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ > -#define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */ > -#define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ > -#define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */ > - > -#define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */ > -#define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */ > -#define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */ > -#define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ > -#define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ > - > -#define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ > -#define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ > - > -/* READ commands with 32-bit addressing (N25Q256 and S25FLxxxS) */ > -#define FLASH_CMD_READ4 0x13 > -#define FLASH_CMD_READ4_FAST 0x0c > -#define FLASH_CMD_READ4_1_1_2 0x3c > -#define FLASH_CMD_READ4_1_2_2 0xbc > -#define FLASH_CMD_READ4_1_1_4 0x6c > -#define FLASH_CMD_READ4_1_4_4 0xec > - > /* S25FLxxxS commands */ > #define S25FL_CMD_WRITE4_1_1_4 0x34 > #define S25FL_CMD_SE4 0xdc -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions @ 2014-04-10 7:56 ` Lee Jones 0 siblings, 0 replies; 58+ messages in thread From: Lee Jones @ 2014-04-10 7:56 UTC (permalink / raw) To: Brian Norris; +Cc: Marek Vasut, Huang Shijie, linux-mtd, linux-spi > These are also in serial_flash_cmds.h. (FWIW, I didn't know the C > preprocessor allowed redefinitions without warning like this.) Right, I would have expected that too. I'll investigate. JOOI, have you build tested your changes? Non-tested: Acked-by: Lee Jones <lee.jones@linaro.org> > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > Cc: Lee Jones <lee.jones@linaro.org> > --- > drivers/mtd/devices/st_spi_fsm.c | 36 ------------------------------------ > 1 file changed, 36 deletions(-) > > diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c > index 30082a09f68b..122a8a14ef84 100644 > --- a/drivers/mtd/devices/st_spi_fsm.c > +++ b/drivers/mtd/devices/st_spi_fsm.c > @@ -201,42 +201,6 @@ > > #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */ > > -/* Flash Commands */ > -#define FLASH_CMD_WREN 0x06 > -#define FLASH_CMD_WRDI 0x04 > -#define FLASH_CMD_RDID 0x9f > -#define FLASH_CMD_RDSR 0x05 > -#define FLASH_CMD_RDSR2 0x35 > -#define FLASH_CMD_WRSR 0x01 > -#define FLASH_CMD_SE_4K 0x20 > -#define FLASH_CMD_SE_32K 0x52 > -#define FLASH_CMD_SE 0xd8 > -#define FLASH_CMD_CHIPERASE 0xc7 > - > -#define FLASH_CMD_READ 0x03 /* READ */ > -#define FLASH_CMD_READ_FAST 0x0b /* FAST READ */ > -#define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ > -#define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */ > -#define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ > -#define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */ > - > -#define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */ > -#define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */ > -#define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */ > -#define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ > -#define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ > - > -#define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ > -#define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ > - > -/* READ commands with 32-bit addressing (N25Q256 and S25FLxxxS) */ > -#define FLASH_CMD_READ4 0x13 > -#define FLASH_CMD_READ4_FAST 0x0c > -#define FLASH_CMD_READ4_1_1_2 0x3c > -#define FLASH_CMD_READ4_1_2_2 0xbc > -#define FLASH_CMD_READ4_1_1_4 0x6c > -#define FLASH_CMD_READ4_1_4_4 0xec > - > /* S25FLxxxS commands */ > #define S25FL_CMD_WRITE4_1_1_4 0x34 > #define S25FL_CMD_SE4 0xdc -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions 2014-04-10 7:56 ` Lee Jones @ 2014-04-10 18:58 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-10 18:58 UTC (permalink / raw) To: Lee Jones Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut On Thu, Apr 10, 2014 at 08:56:53AM +0100, Lee Jones wrote: > JOOI, have you build tested your changes? Yes, I compile-tested yours. (But as Huang noticed, I failed to build fsl-quadspi; my bad.) > Non-tested: > Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Thanks. I'll be sending out v2 with a few tweaks to the other parts of this series. Brian -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions @ 2014-04-10 18:58 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-10 18:58 UTC (permalink / raw) To: Lee Jones; +Cc: Marek Vasut, Huang Shijie, linux-mtd, linux-spi On Thu, Apr 10, 2014 at 08:56:53AM +0100, Lee Jones wrote: > JOOI, have you build tested your changes? Yes, I compile-tested yours. (But as Huang noticed, I failed to build fsl-quadspi; my bad.) > Non-tested: > Acked-by: Lee Jones <lee.jones@linaro.org> Thanks. I'll be sending out v2 with a few tweaks to the other parts of this series. Brian ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 18:01 ` Geert Uytterhoeven -1 siblings, 0 replies; 58+ messages in thread From: Geert Uytterhoeven @ 2014-04-10 18:01 UTC (permalink / raw) To: Brian Norris Cc: MTD Maling List, Huang Shijie, Lee Jones, linux-spi, Marek Vasut On Wed, Apr 9, 2014 at 7:32 PM, Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > These are also in serial_flash_cmds.h. (FWIW, I didn't know the C > preprocessor allowed redefinitions without warning like this.) Cpp only complains when the redefinitions are different. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions @ 2014-04-10 18:01 ` Geert Uytterhoeven 0 siblings, 0 replies; 58+ messages in thread From: Geert Uytterhoeven @ 2014-04-10 18:01 UTC (permalink / raw) To: Brian Norris Cc: Marek Vasut, Huang Shijie, Lee Jones, MTD Maling List, linux-spi On Wed, Apr 9, 2014 at 7:32 PM, Brian Norris <computersforpeace@gmail.com> wrote: > These are also in serial_flash_cmds.h. (FWIW, I didn't know the C > preprocessor allowed redefinitions without warning like this.) Cpp only complains when the redefinitions are different. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 58+ messages in thread
[parent not found: <CAMuHMdWu7YVO_RD-SUfaTw1Jp97i5bm8iX5TzKeqgWAk_iN5qQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions 2014-04-10 18:01 ` Geert Uytterhoeven @ 2014-04-10 18:59 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-10 18:59 UTC (permalink / raw) To: Geert Uytterhoeven Cc: MTD Maling List, Huang Shijie, Lee Jones, linux-spi, Marek Vasut On Thu, Apr 10, 2014 at 08:01:55PM +0200, Geert Uytterhoeven wrote: > On Wed, Apr 9, 2014 at 7:32 PM, Brian Norris > <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > > These are also in serial_flash_cmds.h. (FWIW, I didn't know the C > > preprocessor allowed redefinitions without warning like this.) > > Cpp only complains when the redefinitions are different. Good to know. Thanks. Brian -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions @ 2014-04-10 18:59 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-10 18:59 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Marek Vasut, Huang Shijie, Lee Jones, MTD Maling List, linux-spi On Thu, Apr 10, 2014 at 08:01:55PM +0200, Geert Uytterhoeven wrote: > On Wed, Apr 9, 2014 at 7:32 PM, Brian Norris > <computersforpeace@gmail.com> wrote: > > These are also in serial_flash_cmds.h. (FWIW, I didn't know the C > > preprocessor allowed redefinitions without warning like this.) > > Cpp only complains when the redefinitions are different. Good to know. Thanks. Brian ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 8/9] mtd: st_spi_fsm: replace FLACH_CMD_* with SPINOR_OP_* 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:32 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Brian Norris, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut Begin to unify the differences between serial_flash_cmds.h and spi-nor.h. Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- drivers/mtd/devices/serial_flash_cmds.h | 62 +++++++++--------- drivers/mtd/devices/st_spi_fsm.c | 112 ++++++++++++++++---------------- 2 files changed, 87 insertions(+), 87 deletions(-) diff --git a/drivers/mtd/devices/serial_flash_cmds.h b/drivers/mtd/devices/serial_flash_cmds.h index 4f0c2c7c898e..82fa1687a2d3 100644 --- a/drivers/mtd/devices/serial_flash_cmds.h +++ b/drivers/mtd/devices/serial_flash_cmds.h @@ -13,43 +13,43 @@ #define _MTD_SERIAL_FLASH_CMDS_H /* Generic Flash Commands/OPCODEs */ -#define FLASH_CMD_WREN 0x06 -#define FLASH_CMD_WRDI 0x04 -#define FLASH_CMD_RDID 0x9f -#define FLASH_CMD_RDSR 0x05 -#define FLASH_CMD_RDSR2 0x35 -#define FLASH_CMD_WRSR 0x01 -#define FLASH_CMD_SE_4K 0x20 -#define FLASH_CMD_SE_32K 0x52 -#define FLASH_CMD_SE 0xd8 -#define FLASH_CMD_CHIPERASE 0xc7 -#define FLASH_CMD_WRVCR 0x81 -#define FLASH_CMD_RDVCR 0x85 +#define SPINOR_OP_WREN 0x06 +#define SPINOR_OP_WRDI 0x04 +#define SPINOR_OP_RDID 0x9f +#define SPINOR_OP_RDSR 0x05 +#define SPINOR_OP_RDSR2 0x35 +#define SPINOR_OP_WRSR 0x01 +#define SPINOR_OP_SE_4K 0x20 +#define SPINOR_OP_SE_32K 0x52 +#define SPINOR_OP_SE 0xd8 +#define SPINOR_OP_CHIPERASE 0xc7 +#define SPINOR_OP_WRVCR 0x81 +#define SPINOR_OP_RDVCR 0x85 /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */ -#define FLASH_CMD_READ 0x03 /* READ */ -#define FLASH_CMD_READ_FAST 0x0b /* FAST READ */ -#define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ -#define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */ -#define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ -#define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */ +#define SPINOR_OP_READ 0x03 /* READ */ +#define SPINOR_OP_READ_FAST 0x0b /* FAST READ */ +#define SPINOR_OP_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ +#define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */ +#define SPINOR_OP_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ +#define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */ -#define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */ -#define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */ -#define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */ -#define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ -#define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ +#define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */ +#define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */ +#define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */ +#define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ +#define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ -#define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ -#define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ +#define SPINOR_OP_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ +#define SPINOR_OP_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ /* READ commands with 32-bit addressing */ -#define FLASH_CMD_READ4 0x13 -#define FLASH_CMD_READ4_FAST 0x0c -#define FLASH_CMD_READ4_1_1_2 0x3c -#define FLASH_CMD_READ4_1_2_2 0xbc -#define FLASH_CMD_READ4_1_1_4 0x6c -#define FLASH_CMD_READ4_1_4_4 0xec +#define SPINOR_OP_READ4 0x13 +#define SPINOR_OP_READ4_FAST 0x0c +#define SPINOR_OP_READ4_1_1_2 0x3c +#define SPINOR_OP_READ4_1_2_2 0xbc +#define SPINOR_OP_READ4_1_1_4 0x6c +#define SPINOR_OP_READ4_1_4_4 0xec /* Configuration flags */ #define FLASH_FLAG_SINGLE 0x000000ff diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 122a8a14ef84..fc193a94307d 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -208,7 +208,7 @@ #define S25FL_CMD_DYBWR 0xe1 #define S25FL_CMD_DYBRD 0xe0 #define S25FL_CMD_WRITE4 0x12 /* Note, opcode clashes with - * 'FLASH_CMD_WRITE_1_4_4' + * 'SPINOR_OP_WRITE_1_4_4' * as found on N25Qxxx devices! */ /* Status register */ @@ -296,7 +296,7 @@ struct flash_info { u32 jedec_id; u16 ext_id; /* - * The size listed here is what works with FLASH_CMD_SE, which isn't + * The size listed here is what works with SPINOR_OP_SE, which isn't * necessarily called a "sector" by the vendor. */ unsigned sector_size; @@ -451,22 +451,22 @@ static struct flash_info flash_types[] = { /* Default READ configurations, in order of preference */ static struct seq_rw_config default_read_configs[] = { - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 2, 4}, - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 4, 0}, - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 4, 0}, - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 2, 4}, + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 4, 0}, + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 4, 0}, + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; /* Default WRITE configurations */ static struct seq_rw_config default_write_configs[] = { - {FLASH_FLAG_WRITE_1_4_4, FLASH_CMD_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0}, - {FLASH_FLAG_WRITE_1_1_4, FLASH_CMD_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0}, - {FLASH_FLAG_WRITE_1_2_2, FLASH_CMD_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0}, - {FLASH_FLAG_WRITE_1_1_2, FLASH_CMD_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_WRITE, 1, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_WRITE_1_4_4, SPINOR_OP_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0}, + {FLASH_FLAG_WRITE_1_1_4, SPINOR_OP_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0}, + {FLASH_FLAG_WRITE_1_2_2, SPINOR_OP_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0}, + {FLASH_FLAG_WRITE_1_1_2, SPINOR_OP_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_WRITE, 1, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; @@ -489,12 +489,12 @@ static struct seq_rw_config default_write_configs[] = { * cycles. */ static struct seq_rw_config n25q_read3_configs[] = { - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; @@ -504,12 +504,12 @@ static struct seq_rw_config n25q_read3_configs[] = { * - 'FAST' variants configured for 8 dummy cycles (see note above.) */ static struct seq_rw_config n25q_read4_configs[] = { - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ4, 0, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; @@ -522,7 +522,7 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq) { seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR) | + SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR) | SEQ_OPC_CSDEASSERT); seq->seq[0] = STFSM_INST_CMD1; @@ -550,12 +550,12 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq) * entering a state that is incompatible with the SPIBoot Controller. */ static struct seq_rw_config stfsm_s25fl_read4_configs[] = { - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4}, - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0}, - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ4, 0, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4}, + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0}, + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; @@ -574,7 +574,7 @@ static struct stfsm_seq stfsm_seq_read_jedec = { .data_size = TRANSFER_SIZE(8), .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_RDID)), + SEQ_OPC_OPCODE(SPINOR_OP_RDID)), .seq = { STFSM_INST_CMD1, STFSM_INST_DATA_READ, @@ -590,7 +590,7 @@ static struct stfsm_seq stfsm_seq_read_status_fifo = { .data_size = TRANSFER_SIZE(4), .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_RDSR)), + SEQ_OPC_OPCODE(SPINOR_OP_RDSR)), .seq = { STFSM_INST_CMD1, STFSM_INST_DATA_READ, @@ -606,10 +606,10 @@ static struct stfsm_seq stfsm_seq_erase_sector = { /* 'addr_cfg' configured during initialisation */ .seq_opc = { (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_SE)), + SEQ_OPC_OPCODE(SPINOR_OP_SE)), }, .seq = { STFSM_INST_CMD1, @@ -627,10 +627,10 @@ static struct stfsm_seq stfsm_seq_erase_sector = { static struct stfsm_seq stfsm_seq_erase_chip = { .seq_opc = { (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_CHIPERASE) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_CHIPERASE) | SEQ_OPC_CSDEASSERT), }, .seq = { STFSM_INST_CMD1, @@ -647,9 +647,9 @@ static struct stfsm_seq stfsm_seq_erase_chip = { static struct stfsm_seq stfsm_seq_write_status = { .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WRSR)), + SEQ_OPC_OPCODE(SPINOR_OP_WRSR)), .seq = { STFSM_INST_CMD1, STFSM_INST_CMD2, @@ -665,9 +665,9 @@ static struct stfsm_seq stfsm_seq_write_status = { static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq) { seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR)); + SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR)); seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT); seq->seq[0] = STFSM_INST_CMD2; @@ -788,7 +788,7 @@ static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf, static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) { struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; - uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR; + uint32_t cmd = enter ? SPINOR_OP_EN4B_ADDR : SPINOR_OP_EX4B_ADDR; seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | @@ -812,7 +812,7 @@ static uint8_t stfsm_wait_busy(struct stfsm *fsm) /* Use RDRS1 */ seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_RDSR)); + SEQ_OPC_OPCODE(SPINOR_OP_RDSR)); /* Load read_status sequence */ stfsm_load_seq(fsm, seq); @@ -985,7 +985,7 @@ static void stfsm_prepare_rw_seq(struct stfsm *fsm, if (cfg->write) seq->seq_opc[i++] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT); /* Address configuration (24 or 32-bit addresses) */ @@ -1121,21 +1121,21 @@ static int stfsm_mx25_config(struct stfsm *fsm) } /* Check status of 'QE' bit, update if required. */ - stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR, &sta, 1); data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { if (!(sta & MX25_STATUS_QE)) { /* Set 'QE' */ sta |= MX25_STATUS_QE; - stfsm_write_status(fsm, FLASH_CMD_WRSR, sta, 1, 1); + stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1); } } else { if (sta & MX25_STATUS_QE) { /* Clear 'QE' */ sta &= ~MX25_STATUS_QE; - stfsm_write_status(fsm, FLASH_CMD_WRSR, sta, 1, 1); + stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1); } } @@ -1260,7 +1260,7 @@ static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby) { struct stfsm_seq seq = { .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | SEQ_OPC_OPCODE(S25FL_CMD_DYBWR)), @@ -1300,7 +1300,7 @@ static int stfsm_s25fl_clear_status_reg(struct stfsm *fsm) SEQ_OPC_CSDEASSERT), .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WRDI) | + SEQ_OPC_OPCODE(SPINOR_OP_WRDI) | SEQ_OPC_CSDEASSERT), .seq = { STFSM_INST_CMD1, @@ -1379,7 +1379,7 @@ static int stfsm_s25fl_config(struct stfsm *fsm) } /* Check status of 'QE' bit, update if required. */ - stfsm_read_status(fsm, FLASH_CMD_RDSR2, &cr1, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR2, &cr1, 1); data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { @@ -1397,9 +1397,9 @@ static int stfsm_s25fl_config(struct stfsm *fsm) } } if (update_sr) { - stfsm_read_status(fsm, FLASH_CMD_RDSR, &sr1, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); sta_wr = ((uint16_t)cr1 << 8) | sr1; - stfsm_write_status(fsm, FLASH_CMD_WRSR, sta_wr, 2, 1); + stfsm_write_status(fsm, SPINOR_OP_WRSR, sta_wr, 2, 1); } /* @@ -1424,7 +1424,7 @@ static int stfsm_w25q_config(struct stfsm *fsm) return ret; /* Check status of 'QE' bit, update if required. */ - stfsm_read_status(fsm, FLASH_CMD_RDSR2, &sr2, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR2, &sr2, 1); data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { if (!(sr2 & W25Q_STATUS_QE)) { @@ -1441,9 +1441,9 @@ static int stfsm_w25q_config(struct stfsm *fsm) } if (update_sr) { /* Write status register */ - stfsm_read_status(fsm, FLASH_CMD_RDSR, &sr1, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); sr_wr = ((uint16_t)sr2 << 8) | sr1; - stfsm_write_status(fsm, FLASH_CMD_WRSR, sr_wr, 2, 1); + stfsm_write_status(fsm, SPINOR_OP_WRSR, sr_wr, 2, 1); } return 0; -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH 8/9] mtd: st_spi_fsm: replace FLACH_CMD_* with SPINOR_OP_* @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd; +Cc: Marek Vasut, Huang Shijie, Brian Norris, Lee Jones, linux-spi Begin to unify the differences between serial_flash_cmds.h and spi-nor.h. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Lee Jones <lee.jones@linaro.org> --- drivers/mtd/devices/serial_flash_cmds.h | 62 +++++++++--------- drivers/mtd/devices/st_spi_fsm.c | 112 ++++++++++++++++---------------- 2 files changed, 87 insertions(+), 87 deletions(-) diff --git a/drivers/mtd/devices/serial_flash_cmds.h b/drivers/mtd/devices/serial_flash_cmds.h index 4f0c2c7c898e..82fa1687a2d3 100644 --- a/drivers/mtd/devices/serial_flash_cmds.h +++ b/drivers/mtd/devices/serial_flash_cmds.h @@ -13,43 +13,43 @@ #define _MTD_SERIAL_FLASH_CMDS_H /* Generic Flash Commands/OPCODEs */ -#define FLASH_CMD_WREN 0x06 -#define FLASH_CMD_WRDI 0x04 -#define FLASH_CMD_RDID 0x9f -#define FLASH_CMD_RDSR 0x05 -#define FLASH_CMD_RDSR2 0x35 -#define FLASH_CMD_WRSR 0x01 -#define FLASH_CMD_SE_4K 0x20 -#define FLASH_CMD_SE_32K 0x52 -#define FLASH_CMD_SE 0xd8 -#define FLASH_CMD_CHIPERASE 0xc7 -#define FLASH_CMD_WRVCR 0x81 -#define FLASH_CMD_RDVCR 0x85 +#define SPINOR_OP_WREN 0x06 +#define SPINOR_OP_WRDI 0x04 +#define SPINOR_OP_RDID 0x9f +#define SPINOR_OP_RDSR 0x05 +#define SPINOR_OP_RDSR2 0x35 +#define SPINOR_OP_WRSR 0x01 +#define SPINOR_OP_SE_4K 0x20 +#define SPINOR_OP_SE_32K 0x52 +#define SPINOR_OP_SE 0xd8 +#define SPINOR_OP_CHIPERASE 0xc7 +#define SPINOR_OP_WRVCR 0x81 +#define SPINOR_OP_RDVCR 0x85 /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */ -#define FLASH_CMD_READ 0x03 /* READ */ -#define FLASH_CMD_READ_FAST 0x0b /* FAST READ */ -#define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ -#define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */ -#define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ -#define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */ +#define SPINOR_OP_READ 0x03 /* READ */ +#define SPINOR_OP_READ_FAST 0x0b /* FAST READ */ +#define SPINOR_OP_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ +#define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */ +#define SPINOR_OP_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ +#define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */ -#define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */ -#define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */ -#define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */ -#define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ -#define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ +#define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */ +#define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */ +#define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */ +#define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ +#define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ -#define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ -#define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ +#define SPINOR_OP_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ +#define SPINOR_OP_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ /* READ commands with 32-bit addressing */ -#define FLASH_CMD_READ4 0x13 -#define FLASH_CMD_READ4_FAST 0x0c -#define FLASH_CMD_READ4_1_1_2 0x3c -#define FLASH_CMD_READ4_1_2_2 0xbc -#define FLASH_CMD_READ4_1_1_4 0x6c -#define FLASH_CMD_READ4_1_4_4 0xec +#define SPINOR_OP_READ4 0x13 +#define SPINOR_OP_READ4_FAST 0x0c +#define SPINOR_OP_READ4_1_1_2 0x3c +#define SPINOR_OP_READ4_1_2_2 0xbc +#define SPINOR_OP_READ4_1_1_4 0x6c +#define SPINOR_OP_READ4_1_4_4 0xec /* Configuration flags */ #define FLASH_FLAG_SINGLE 0x000000ff diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 122a8a14ef84..fc193a94307d 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -208,7 +208,7 @@ #define S25FL_CMD_DYBWR 0xe1 #define S25FL_CMD_DYBRD 0xe0 #define S25FL_CMD_WRITE4 0x12 /* Note, opcode clashes with - * 'FLASH_CMD_WRITE_1_4_4' + * 'SPINOR_OP_WRITE_1_4_4' * as found on N25Qxxx devices! */ /* Status register */ @@ -296,7 +296,7 @@ struct flash_info { u32 jedec_id; u16 ext_id; /* - * The size listed here is what works with FLASH_CMD_SE, which isn't + * The size listed here is what works with SPINOR_OP_SE, which isn't * necessarily called a "sector" by the vendor. */ unsigned sector_size; @@ -451,22 +451,22 @@ static struct flash_info flash_types[] = { /* Default READ configurations, in order of preference */ static struct seq_rw_config default_read_configs[] = { - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 2, 4}, - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 4, 0}, - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 4, 0}, - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 2, 4}, + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 4, 0}, + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 4, 0}, + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; /* Default WRITE configurations */ static struct seq_rw_config default_write_configs[] = { - {FLASH_FLAG_WRITE_1_4_4, FLASH_CMD_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0}, - {FLASH_FLAG_WRITE_1_1_4, FLASH_CMD_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0}, - {FLASH_FLAG_WRITE_1_2_2, FLASH_CMD_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0}, - {FLASH_FLAG_WRITE_1_1_2, FLASH_CMD_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_WRITE, 1, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_WRITE_1_4_4, SPINOR_OP_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0}, + {FLASH_FLAG_WRITE_1_1_4, SPINOR_OP_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0}, + {FLASH_FLAG_WRITE_1_2_2, SPINOR_OP_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0}, + {FLASH_FLAG_WRITE_1_1_2, SPINOR_OP_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_WRITE, 1, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; @@ -489,12 +489,12 @@ static struct seq_rw_config default_write_configs[] = { * cycles. */ static struct seq_rw_config n25q_read3_configs[] = { - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; @@ -504,12 +504,12 @@ static struct seq_rw_config n25q_read3_configs[] = { * - 'FAST' variants configured for 8 dummy cycles (see note above.) */ static struct seq_rw_config n25q_read4_configs[] = { - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ4, 0, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; @@ -522,7 +522,7 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq) { seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR) | + SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR) | SEQ_OPC_CSDEASSERT); seq->seq[0] = STFSM_INST_CMD1; @@ -550,12 +550,12 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq) * entering a state that is incompatible with the SPIBoot Controller. */ static struct seq_rw_config stfsm_s25fl_read4_configs[] = { - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4}, - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0}, - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ4, 0, 1, 1, 0x00, 0, 0}, + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4}, + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0}, + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0}, {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; @@ -574,7 +574,7 @@ static struct stfsm_seq stfsm_seq_read_jedec = { .data_size = TRANSFER_SIZE(8), .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_RDID)), + SEQ_OPC_OPCODE(SPINOR_OP_RDID)), .seq = { STFSM_INST_CMD1, STFSM_INST_DATA_READ, @@ -590,7 +590,7 @@ static struct stfsm_seq stfsm_seq_read_status_fifo = { .data_size = TRANSFER_SIZE(4), .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_RDSR)), + SEQ_OPC_OPCODE(SPINOR_OP_RDSR)), .seq = { STFSM_INST_CMD1, STFSM_INST_DATA_READ, @@ -606,10 +606,10 @@ static struct stfsm_seq stfsm_seq_erase_sector = { /* 'addr_cfg' configured during initialisation */ .seq_opc = { (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_SE)), + SEQ_OPC_OPCODE(SPINOR_OP_SE)), }, .seq = { STFSM_INST_CMD1, @@ -627,10 +627,10 @@ static struct stfsm_seq stfsm_seq_erase_sector = { static struct stfsm_seq stfsm_seq_erase_chip = { .seq_opc = { (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_CHIPERASE) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_CHIPERASE) | SEQ_OPC_CSDEASSERT), }, .seq = { STFSM_INST_CMD1, @@ -647,9 +647,9 @@ static struct stfsm_seq stfsm_seq_erase_chip = { static struct stfsm_seq stfsm_seq_write_status = { .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WRSR)), + SEQ_OPC_OPCODE(SPINOR_OP_WRSR)), .seq = { STFSM_INST_CMD1, STFSM_INST_CMD2, @@ -665,9 +665,9 @@ static struct stfsm_seq stfsm_seq_write_status = { static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq) { seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR)); + SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR)); seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT); seq->seq[0] = STFSM_INST_CMD2; @@ -788,7 +788,7 @@ static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf, static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) { struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; - uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR; + uint32_t cmd = enter ? SPINOR_OP_EN4B_ADDR : SPINOR_OP_EX4B_ADDR; seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | @@ -812,7 +812,7 @@ static uint8_t stfsm_wait_busy(struct stfsm *fsm) /* Use RDRS1 */ seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_RDSR)); + SEQ_OPC_OPCODE(SPINOR_OP_RDSR)); /* Load read_status sequence */ stfsm_load_seq(fsm, seq); @@ -985,7 +985,7 @@ static void stfsm_prepare_rw_seq(struct stfsm *fsm, if (cfg->write) seq->seq_opc[i++] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT); /* Address configuration (24 or 32-bit addresses) */ @@ -1121,21 +1121,21 @@ static int stfsm_mx25_config(struct stfsm *fsm) } /* Check status of 'QE' bit, update if required. */ - stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR, &sta, 1); data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { if (!(sta & MX25_STATUS_QE)) { /* Set 'QE' */ sta |= MX25_STATUS_QE; - stfsm_write_status(fsm, FLASH_CMD_WRSR, sta, 1, 1); + stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1); } } else { if (sta & MX25_STATUS_QE) { /* Clear 'QE' */ sta &= ~MX25_STATUS_QE; - stfsm_write_status(fsm, FLASH_CMD_WRSR, sta, 1, 1); + stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1); } } @@ -1260,7 +1260,7 @@ static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby) { struct stfsm_seq seq = { .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | SEQ_OPC_OPCODE(S25FL_CMD_DYBWR)), @@ -1300,7 +1300,7 @@ static int stfsm_s25fl_clear_status_reg(struct stfsm *fsm) SEQ_OPC_CSDEASSERT), .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(FLASH_CMD_WRDI) | + SEQ_OPC_OPCODE(SPINOR_OP_WRDI) | SEQ_OPC_CSDEASSERT), .seq = { STFSM_INST_CMD1, @@ -1379,7 +1379,7 @@ static int stfsm_s25fl_config(struct stfsm *fsm) } /* Check status of 'QE' bit, update if required. */ - stfsm_read_status(fsm, FLASH_CMD_RDSR2, &cr1, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR2, &cr1, 1); data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { @@ -1397,9 +1397,9 @@ static int stfsm_s25fl_config(struct stfsm *fsm) } } if (update_sr) { - stfsm_read_status(fsm, FLASH_CMD_RDSR, &sr1, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); sta_wr = ((uint16_t)cr1 << 8) | sr1; - stfsm_write_status(fsm, FLASH_CMD_WRSR, sta_wr, 2, 1); + stfsm_write_status(fsm, SPINOR_OP_WRSR, sta_wr, 2, 1); } /* @@ -1424,7 +1424,7 @@ static int stfsm_w25q_config(struct stfsm *fsm) return ret; /* Check status of 'QE' bit, update if required. */ - stfsm_read_status(fsm, FLASH_CMD_RDSR2, &sr2, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR2, &sr2, 1); data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { if (!(sr2 & W25Q_STATUS_QE)) { @@ -1441,9 +1441,9 @@ static int stfsm_w25q_config(struct stfsm *fsm) } if (update_sr) { /* Write status register */ - stfsm_read_status(fsm, FLASH_CMD_RDSR, &sr1, 1); + stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); sr_wr = ((uint16_t)sr2 << 8) | sr1; - stfsm_write_status(fsm, FLASH_CMD_WRSR, sr_wr, 2, 1); + stfsm_write_status(fsm, SPINOR_OP_WRSR, sr_wr, 2, 1); } return 0; -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1397064774-31784-8-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 8/9] mtd: st_spi_fsm: replace FLACH_CMD_* with SPINOR_OP_* 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 7:52 ` Lee Jones -1 siblings, 0 replies; 58+ messages in thread From: Lee Jones @ 2014-04-10 7:52 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut > Begin to unify the differences between serial_flash_cmds.h and > spi-nor.h. > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > drivers/mtd/devices/serial_flash_cmds.h | 62 +++++++++--------- > drivers/mtd/devices/st_spi_fsm.c | 112 ++++++++++++++++---------------- > 2 files changed, 87 insertions(+), 87 deletions(-) Nice. Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 8/9] mtd: st_spi_fsm: replace FLACH_CMD_* with SPINOR_OP_* @ 2014-04-10 7:52 ` Lee Jones 0 siblings, 0 replies; 58+ messages in thread From: Lee Jones @ 2014-04-10 7:52 UTC (permalink / raw) To: Brian Norris; +Cc: Marek Vasut, Huang Shijie, linux-mtd, linux-spi > Begin to unify the differences between serial_flash_cmds.h and > spi-nor.h. > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > Cc: Lee Jones <lee.jones@linaro.org> > --- > drivers/mtd/devices/serial_flash_cmds.h | 62 +++++++++--------- > drivers/mtd/devices/st_spi_fsm.c | 112 ++++++++++++++++---------------- > 2 files changed, 87 insertions(+), 87 deletions(-) Nice. Acked-by: Lee Jones <lee.jones@linaro.org> -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 9/9] mtd: st_spi_fsm: begin using spi-nor.h opcodes 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:32 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: Brian Norris, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut Many of the serial_flash_cmds.h opcodes are duplicated with spi-nor.h. Let's begin to unify them. Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- drivers/mtd/devices/serial_flash_cmds.h | 20 -------------------- drivers/mtd/devices/st_spi_fsm.c | 9 +++++---- 2 files changed, 5 insertions(+), 24 deletions(-) diff --git a/drivers/mtd/devices/serial_flash_cmds.h b/drivers/mtd/devices/serial_flash_cmds.h index 82fa1687a2d3..f59a125295d0 100644 --- a/drivers/mtd/devices/serial_flash_cmds.h +++ b/drivers/mtd/devices/serial_flash_cmds.h @@ -13,25 +13,12 @@ #define _MTD_SERIAL_FLASH_CMDS_H /* Generic Flash Commands/OPCODEs */ -#define SPINOR_OP_WREN 0x06 -#define SPINOR_OP_WRDI 0x04 -#define SPINOR_OP_RDID 0x9f -#define SPINOR_OP_RDSR 0x05 #define SPINOR_OP_RDSR2 0x35 -#define SPINOR_OP_WRSR 0x01 -#define SPINOR_OP_SE_4K 0x20 -#define SPINOR_OP_SE_32K 0x52 -#define SPINOR_OP_SE 0xd8 -#define SPINOR_OP_CHIPERASE 0xc7 #define SPINOR_OP_WRVCR 0x81 #define SPINOR_OP_RDVCR 0x85 /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */ -#define SPINOR_OP_READ 0x03 /* READ */ -#define SPINOR_OP_READ_FAST 0x0b /* FAST READ */ -#define SPINOR_OP_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ #define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */ -#define SPINOR_OP_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ #define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */ #define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */ @@ -40,15 +27,8 @@ #define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ #define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ -#define SPINOR_OP_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ -#define SPINOR_OP_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ - /* READ commands with 32-bit addressing */ -#define SPINOR_OP_READ4 0x13 -#define SPINOR_OP_READ4_FAST 0x0c -#define SPINOR_OP_READ4_1_1_2 0x3c #define SPINOR_OP_READ4_1_2_2 0xbc -#define SPINOR_OP_READ4_1_1_4 0x6c #define SPINOR_OP_READ4_1_4_4 0xec /* Configuration flags */ diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index fc193a94307d..7cc49ba78f68 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -19,6 +19,7 @@ #include <linux/mfd/syscon.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/spi-nor.h> #include <linux/sched.h> #include <linux/delay.h> #include <linux/io.h> @@ -522,7 +523,7 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq) { seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR) | + SEQ_OPC_OPCODE(SPINOR_OP_EN4B) | SEQ_OPC_CSDEASSERT); seq->seq[0] = STFSM_INST_CMD1; @@ -630,7 +631,7 @@ static struct stfsm_seq stfsm_seq_erase_chip = { SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(SPINOR_OP_CHIPERASE) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_CHIP_ERASE) | SEQ_OPC_CSDEASSERT), }, .seq = { STFSM_INST_CMD1, @@ -665,7 +666,7 @@ static struct stfsm_seq stfsm_seq_write_status = { static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq) { seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR)); + SEQ_OPC_OPCODE(SPINOR_OP_EN4B)); seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT); @@ -788,7 +789,7 @@ static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf, static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) { struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; - uint32_t cmd = enter ? SPINOR_OP_EN4B_ADDR : SPINOR_OP_EX4B_ADDR; + uint32_t cmd = enter ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH 9/9] mtd: st_spi_fsm: begin using spi-nor.h opcodes @ 2014-04-09 17:32 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:32 UTC (permalink / raw) To: linux-mtd; +Cc: Marek Vasut, Huang Shijie, Brian Norris, Lee Jones, linux-spi Many of the serial_flash_cmds.h opcodes are duplicated with spi-nor.h. Let's begin to unify them. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Lee Jones <lee.jones@linaro.org> --- drivers/mtd/devices/serial_flash_cmds.h | 20 -------------------- drivers/mtd/devices/st_spi_fsm.c | 9 +++++---- 2 files changed, 5 insertions(+), 24 deletions(-) diff --git a/drivers/mtd/devices/serial_flash_cmds.h b/drivers/mtd/devices/serial_flash_cmds.h index 82fa1687a2d3..f59a125295d0 100644 --- a/drivers/mtd/devices/serial_flash_cmds.h +++ b/drivers/mtd/devices/serial_flash_cmds.h @@ -13,25 +13,12 @@ #define _MTD_SERIAL_FLASH_CMDS_H /* Generic Flash Commands/OPCODEs */ -#define SPINOR_OP_WREN 0x06 -#define SPINOR_OP_WRDI 0x04 -#define SPINOR_OP_RDID 0x9f -#define SPINOR_OP_RDSR 0x05 #define SPINOR_OP_RDSR2 0x35 -#define SPINOR_OP_WRSR 0x01 -#define SPINOR_OP_SE_4K 0x20 -#define SPINOR_OP_SE_32K 0x52 -#define SPINOR_OP_SE 0xd8 -#define SPINOR_OP_CHIPERASE 0xc7 #define SPINOR_OP_WRVCR 0x81 #define SPINOR_OP_RDVCR 0x85 /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */ -#define SPINOR_OP_READ 0x03 /* READ */ -#define SPINOR_OP_READ_FAST 0x0b /* FAST READ */ -#define SPINOR_OP_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ #define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */ -#define SPINOR_OP_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ #define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */ #define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */ @@ -40,15 +27,8 @@ #define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ #define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ -#define SPINOR_OP_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ -#define SPINOR_OP_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ - /* READ commands with 32-bit addressing */ -#define SPINOR_OP_READ4 0x13 -#define SPINOR_OP_READ4_FAST 0x0c -#define SPINOR_OP_READ4_1_1_2 0x3c #define SPINOR_OP_READ4_1_2_2 0xbc -#define SPINOR_OP_READ4_1_1_4 0x6c #define SPINOR_OP_READ4_1_4_4 0xec /* Configuration flags */ diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index fc193a94307d..7cc49ba78f68 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -19,6 +19,7 @@ #include <linux/mfd/syscon.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/spi-nor.h> #include <linux/sched.h> #include <linux/delay.h> #include <linux/io.h> @@ -522,7 +523,7 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq) { seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR) | + SEQ_OPC_OPCODE(SPINOR_OP_EN4B) | SEQ_OPC_CSDEASSERT); seq->seq[0] = STFSM_INST_CMD1; @@ -630,7 +631,7 @@ static struct stfsm_seq stfsm_seq_erase_chip = { SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(SPINOR_OP_CHIPERASE) | SEQ_OPC_CSDEASSERT), + SEQ_OPC_OPCODE(SPINOR_OP_CHIP_ERASE) | SEQ_OPC_CSDEASSERT), }, .seq = { STFSM_INST_CMD1, @@ -665,7 +666,7 @@ static struct stfsm_seq stfsm_seq_write_status = { static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq) { seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR)); + SEQ_OPC_OPCODE(SPINOR_OP_EN4B)); seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT); @@ -788,7 +789,7 @@ static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf, static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) { struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; - uint32_t cmd = enter ? SPINOR_OP_EN4B_ADDR : SPINOR_OP_EX4B_ADDR; + uint32_t cmd = enter ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1397064774-31784-9-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 9/9] mtd: st_spi_fsm: begin using spi-nor.h opcodes 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 7:50 ` Lee Jones -1 siblings, 0 replies; 58+ messages in thread From: Lee Jones @ 2014-04-10 7:50 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut On Wed, 09 Apr 2014, Brian Norris wrote: > Many of the serial_flash_cmds.h opcodes are duplicated with spi-nor.h. > Let's begin to unify them. > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > drivers/mtd/devices/serial_flash_cmds.h | 20 -------------------- > drivers/mtd/devices/st_spi_fsm.c | 9 +++++---- > 2 files changed, 5 insertions(+), 24 deletions(-) So long as the underlying Op Codes havent changed: Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 9/9] mtd: st_spi_fsm: begin using spi-nor.h opcodes @ 2014-04-10 7:50 ` Lee Jones 0 siblings, 0 replies; 58+ messages in thread From: Lee Jones @ 2014-04-10 7:50 UTC (permalink / raw) To: Brian Norris; +Cc: Marek Vasut, Huang Shijie, linux-mtd, linux-spi On Wed, 09 Apr 2014, Brian Norris wrote: > Many of the serial_flash_cmds.h opcodes are duplicated with spi-nor.h. > Let's begin to unify them. > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > Cc: Lee Jones <lee.jones@linaro.org> > --- > drivers/mtd/devices/serial_flash_cmds.h | 20 -------------------- > drivers/mtd/devices/st_spi_fsm.c | 9 +++++---- > 2 files changed, 5 insertions(+), 24 deletions(-) So long as the underlying Op Codes havent changed: Acked-by: Lee Jones <lee.jones@linaro.org> -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 1/9] mtd: spi-nor: drop \t after #define 2014-04-09 17:32 ` Brian Norris @ 2014-04-09 17:40 ` Marek Vasut -1 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:40 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA On Wednesday, April 09, 2014 at 07:32:46 PM, Brian Norris wrote: > Spacing is a little non-standard here. > > Signed-off-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > Series based on l2-mtd.git/spinor: > > http://git.infradead.org/l2-mtd.git > > include/linux/mtd/spi-nor.h | 68 > ++++++++++++++++++++++----------------------- 1 file changed, 34 > insertions(+), 34 deletions(-) > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 41dae78fbd1d..558097e14932 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -2,50 +2,50 @@ > #define __LINUX_MTD_SPI_NOR_H > > /* Flash opcodes. */ > -#define OPCODE_WREN 0x06 /* Write enable */ > -#define OPCODE_RDSR 0x05 /* Read status register */ > -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ > -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ > -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ > -#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > -#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ > -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ > -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ > -#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ > -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ > -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ > -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ > -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ > -#define OPCODE_RDCR 0x35 /* Read configuration register */ > +#define OPCODE_WREN 0x06 /* Write enable */ > +#define OPCODE_RDSR 0x05 /* Read status register */ > +#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ > +#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ > +#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ > +#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > +#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ This is still a little non-standard -- or rather -- inconsistent here. You should use space after #define and \t after the name I'd say. I'd also say these two slipped your attention as the others do it just like that. > +#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ > +#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ > +#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ > +#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ > +#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ > +#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ > +#define OPCODE_RDID 0x9f /* Read JEDEC ID */ > +#define OPCODE_RDCR 0x35 /* Read configuration register */ DTTO here. > /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ > -#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ > -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ > -#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ > -#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ > -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ > -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ > +#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ > +#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ > +#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ > +#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ This comment here is indented with spaces, while the other comments are indented with tabs ;-/ [...] -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 1/9] mtd: spi-nor: drop \t after #define @ 2014-04-09 17:40 ` Marek Vasut 0 siblings, 0 replies; 58+ messages in thread From: Marek Vasut @ 2014-04-09 17:40 UTC (permalink / raw) To: Brian Norris; +Cc: Huang Shijie, Lee Jones, linux-mtd, linux-spi On Wednesday, April 09, 2014 at 07:32:46 PM, Brian Norris wrote: > Spacing is a little non-standard here. > > Signed-off-by: Brian Norris <computersforpeace@gmail.com> > --- > Series based on l2-mtd.git/spinor: > > http://git.infradead.org/l2-mtd.git > > include/linux/mtd/spi-nor.h | 68 > ++++++++++++++++++++++----------------------- 1 file changed, 34 > insertions(+), 34 deletions(-) > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 41dae78fbd1d..558097e14932 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -2,50 +2,50 @@ > #define __LINUX_MTD_SPI_NOR_H > > /* Flash opcodes. */ > -#define OPCODE_WREN 0x06 /* Write enable */ > -#define OPCODE_RDSR 0x05 /* Read status register */ > -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ > -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ > -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ > -#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > -#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ > -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ > -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ > -#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ > -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ > -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ > -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ > -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ > -#define OPCODE_RDCR 0x35 /* Read configuration register */ > +#define OPCODE_WREN 0x06 /* Write enable */ > +#define OPCODE_RDSR 0x05 /* Read status register */ > +#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ > +#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ > +#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ > +#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > +#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ This is still a little non-standard -- or rather -- inconsistent here. You should use space after #define and \t after the name I'd say. I'd also say these two slipped your attention as the others do it just like that. > +#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ > +#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ > +#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ > +#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ > +#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ > +#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ > +#define OPCODE_RDID 0x9f /* Read JEDEC ID */ > +#define OPCODE_RDCR 0x35 /* Read configuration register */ DTTO here. > /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ > -#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ > -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ > -#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ > -#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ > -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ > -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ > +#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ > +#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ > +#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */ > +#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */ This comment here is indented with spaces, while the other comments are indented with tabs ;-/ [...] ^ permalink raw reply [flat|nested] 58+ messages in thread
[parent not found: <201404091940.14392.marex-ynQEQJNshbs@public.gmane.org>]
* Re: [PATCH 1/9] mtd: spi-nor: drop \t after #define 2014-04-09 17:40 ` Marek Vasut @ 2014-04-09 17:56 ` Brian Norris -1 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:56 UTC (permalink / raw) To: Marek Vasut Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Huang Shijie, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA On Wed, Apr 09, 2014 at 07:40:14PM +0200, Marek Vasut wrote: > On Wednesday, April 09, 2014 at 07:32:46 PM, Brian Norris wrote: > > +#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > > +#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ > > This is still a little non-standard -- or rather -- inconsistent here. You > should use space after #define and \t after the name I'd say. I'd also say these > two slipped your attention as the others do it just like that. Thanks. I think I noticed this at one point, but in my patch juggling, I never straightened it out. I'll send v2 eventually. And in the meantime, I'm keeping my patches here: http://git.infradead.org/users/norris/linux-mtd.git/shortlog/refs/heads/spinor Brian -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 1/9] mtd: spi-nor: drop \t after #define @ 2014-04-09 17:56 ` Brian Norris 0 siblings, 0 replies; 58+ messages in thread From: Brian Norris @ 2014-04-09 17:56 UTC (permalink / raw) To: Marek Vasut; +Cc: Huang Shijie, Lee Jones, linux-mtd, linux-spi On Wed, Apr 09, 2014 at 07:40:14PM +0200, Marek Vasut wrote: > On Wednesday, April 09, 2014 at 07:32:46 PM, Brian Norris wrote: > > +#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */ > > +#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */ > > This is still a little non-standard -- or rather -- inconsistent here. You > should use space after #define and \t after the name I'd say. I'd also say these > two slipped your attention as the others do it just like that. Thanks. I think I noticed this at one point, but in my patch juggling, I never straightened it out. I'll send v2 eventually. And in the meantime, I'm keeping my patches here: http://git.infradead.org/users/norris/linux-mtd.git/shortlog/refs/heads/spinor Brian ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 1/9] mtd: spi-nor: drop \t after #define 2014-04-09 17:32 ` Brian Norris @ 2014-04-10 7:34 ` Huang Shijie -1 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:34 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Lee Jones, linux-spi-u79uwXL29TY76Z2rM5mHXA, Marek Vasut On Wed, Apr 09, 2014 at 10:32:46AM -0700, Brian Norris wrote: > Spacing is a little non-standard here. > -- > 1.8.3.2 > > > Acked-by: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 1/9] mtd: spi-nor: drop \t after #define @ 2014-04-10 7:34 ` Huang Shijie 0 siblings, 0 replies; 58+ messages in thread From: Huang Shijie @ 2014-04-10 7:34 UTC (permalink / raw) To: Brian Norris; +Cc: Marek Vasut, Lee Jones, linux-mtd, linux-spi On Wed, Apr 09, 2014 at 10:32:46AM -0700, Brian Norris wrote: > Spacing is a little non-standard here. > -- > 1.8.3.2 > > > Acked-by: Huang Shijie <b32955@freescale.com> ^ permalink raw reply [flat|nested] 58+ messages in thread
end of thread, other threads:[~2014-04-10 19:34 UTC | newest]
Thread overview: 58+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-04-09 17:32 [PATCH 1/9] mtd: spi-nor: drop \t after #define Brian Norris
2014-04-09 17:32 ` Brian Norris
[not found] ` <1397064774-31784-1-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-04-09 17:32 ` [PATCH 2/9] mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_* Brian Norris
2014-04-09 17:32 ` Brian Norris
[not found] ` <1397064774-31784-2-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-04-09 17:41 ` Marek Vasut
2014-04-09 17:41 ` Marek Vasut
2014-04-10 7:42 ` Huang Shijie
2014-04-10 7:42 ` Huang Shijie
2014-04-09 17:32 ` [PATCH 3/9] mtd: spi-nor: unify read opcode variants with ST SPI FSM Brian Norris
2014-04-09 17:32 ` Brian Norris
[not found] ` <1397064774-31784-3-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-04-09 17:41 ` Marek Vasut
2014-04-09 17:41 ` Marek Vasut
2014-04-10 7:43 ` Huang Shijie
2014-04-10 7:43 ` Huang Shijie
2014-04-10 7:47 ` Huang Shijie
2014-04-10 7:47 ` Huang Shijie
2014-04-10 19:34 ` Brian Norris
2014-04-10 19:34 ` Brian Norris
2014-04-09 17:32 ` [PATCH 4/9] Documentation: spi-nor: rewrite some portions Brian Norris
2014-04-09 17:32 ` Brian Norris
[not found] ` <1397064774-31784-4-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-04-09 17:44 ` Marek Vasut
2014-04-09 17:44 ` Marek Vasut
[not found] ` <201404091944.15631.marex-ynQEQJNshbs@public.gmane.org>
2014-04-09 18:14 ` Brian Norris
2014-04-09 18:14 ` Brian Norris
2014-04-09 17:32 ` [PATCH 5/9] mtd: spi-nor: shorten Kconfig naming Brian Norris
2014-04-09 17:32 ` Brian Norris
[not found] ` <1397064774-31784-5-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-04-09 17:44 ` Marek Vasut
2014-04-09 17:44 ` Marek Vasut
2014-04-10 7:39 ` Huang Shijie
2014-04-10 7:39 ` Huang Shijie
2014-04-09 17:32 ` [PATCH 6/9] mtd: st_spi_fsm: fixup Kconfig dependency Brian Norris
2014-04-09 17:32 ` Brian Norris
[not found] ` <1397064774-31784-6-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-04-10 7:57 ` Lee Jones
2014-04-10 7:57 ` Lee Jones
2014-04-09 17:32 ` [PATCH 7/9] mtd: st_spi_fsm: kill duplicate CMD definitions Brian Norris
2014-04-09 17:32 ` Brian Norris
[not found] ` <1397064774-31784-7-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-04-10 7:56 ` Lee Jones
2014-04-10 7:56 ` Lee Jones
2014-04-10 18:58 ` Brian Norris
2014-04-10 18:58 ` Brian Norris
2014-04-10 18:01 ` Geert Uytterhoeven
2014-04-10 18:01 ` Geert Uytterhoeven
[not found] ` <CAMuHMdWu7YVO_RD-SUfaTw1Jp97i5bm8iX5TzKeqgWAk_iN5qQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-04-10 18:59 ` Brian Norris
2014-04-10 18:59 ` Brian Norris
2014-04-09 17:32 ` [PATCH 8/9] mtd: st_spi_fsm: replace FLACH_CMD_* with SPINOR_OP_* Brian Norris
2014-04-09 17:32 ` Brian Norris
[not found] ` <1397064774-31784-8-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-04-10 7:52 ` Lee Jones
2014-04-10 7:52 ` Lee Jones
2014-04-09 17:32 ` [PATCH 9/9] mtd: st_spi_fsm: begin using spi-nor.h opcodes Brian Norris
2014-04-09 17:32 ` Brian Norris
[not found] ` <1397064774-31784-9-git-send-email-computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-04-10 7:50 ` Lee Jones
2014-04-10 7:50 ` Lee Jones
2014-04-09 17:40 ` [PATCH 1/9] mtd: spi-nor: drop \t after #define Marek Vasut
2014-04-09 17:40 ` Marek Vasut
[not found] ` <201404091940.14392.marex-ynQEQJNshbs@public.gmane.org>
2014-04-09 17:56 ` Brian Norris
2014-04-09 17:56 ` Brian Norris
2014-04-10 7:34 ` Huang Shijie
2014-04-10 7:34 ` Huang Shijie
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