From: Stephen Rothwell <sfr@canb.auug.org.au> To: Daniel Vetter <daniel.vetter@ffwll.ch>, <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: linux-next@vger.kernel.org, linux-kernel@vger.kernel.org, Jani Nikula <jani.nikula@intel.com> Subject: linux-next: manual merge of the drm-intel tree with the drm-intel-fixes tree Date: Wed, 30 Apr 2014 12:37:53 +1000 [thread overview] Message-ID: <20140430123753.16dd13b23d29e09548a4bd56@canb.auug.org.au> (raw) [-- Attachment #1: Type: text/plain, Size: 4232 bytes --] Hi all, Today's linux-next merge of the drm-intel tree got a conflict in drivers/gpu/drm/i915/i915_gem_gtt.c between commitcfa7c862982b ("drm/i915: Sanitize the enable_ppgtt module option once") from the drm-intel-fixes tree tree and commit 5db6c735ead5 ("drm/i915: dmesg output for VT-d testing") from the drm-intel tree. I fixed it up (see below) and can carry the fix as necessary (no action is required). -- Cheers, Stephen Rothwell sfr@canb.auug.org.au diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c index 154b0f8bb88d,496916298e8a..000000000000 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@@ -62,62 -48,13 +62,9 @@@ static int sanitize_enable_ppgtt(struc } #endif - /* Full ppgtt disabled by default for now due to issues. */ - if (full) - return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2); - else - return HAS_ALIASING_PPGTT(dev); + return HAS_ALIASING_PPGTT(dev) ? 1 : 0; } - #define GEN6_PPGTT_PD_ENTRIES 512 - #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) - typedef uint64_t gen8_gtt_pte_t; - typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; - - /* PPGTT stuff */ - #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) - #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) - - #define GEN6_PDE_VALID (1 << 0) - /* gen6+ has bit 11-4 for physical addr bit 39-32 */ - #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) - - #define GEN6_PTE_VALID (1 << 0) - #define GEN6_PTE_UNCACHED (1 << 1) - #define HSW_PTE_UNCACHED (0) - #define GEN6_PTE_CACHE_LLC (2 << 1) - #define GEN7_PTE_CACHE_L3_LLC (3 << 1) - #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) - #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) - - /* Cacheability Control is a 4-bit value. The low three bits are stored in * - * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. - */ - #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ - (((bits) & 0x8) << (11 - 3))) - #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) - #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) - #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) - #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) - #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) - #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) - - #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) - #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) - - /* GEN8 legacy style addressis defined as a 3 level page table: - * 31:30 | 29:21 | 20:12 | 11:0 - * PDPE | PDE | PTE | offset - * The difference as compared to normal x86 3 level page table is the PDPEs are - * programmed via register. - */ - #define GEN8_PDPE_SHIFT 30 - #define GEN8_PDPE_MASK 0x3 - #define GEN8_PDE_SHIFT 21 - #define GEN8_PDE_MASK 0x1ff - #define GEN8_PTE_SHIFT 12 - #define GEN8_PTE_MASK 0x1ff - - #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) - #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ - #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ - #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ static void ppgtt_bind_vma(struct i915_vma *vma, enum i915_cache_level cache_level, @@@ -2041,14 -1971,10 +1981,18 @@@ int i915_gem_gtt_init(struct drm_devic gtt->base.total >> 20); DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); + /* + * i915.enable_ppgtt is read-only, so do an early pass to validate the + * user's requested state against the hardware/driver capabilities. We + * do this now so that we can print out any log messages once rather + * than every time we check intel_enable_ppgtt(). + */ + i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); + DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); + #ifdef CONFIG_INTEL_IOMMU + if (intel_iommu_gfx_mapped) + DRM_INFO("VT-d active for gfx access\n"); + #endif return 0; } [-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Rothwell <sfr@canb.auug.org.au> To: Daniel Vetter <daniel.vetter@ffwll.ch>, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@intel.com>, linux-next@vger.kernel.org, linux-kernel@vger.kernel.org Subject: linux-next: manual merge of the drm-intel tree with the drm-intel-fixes tree Date: Wed, 30 Apr 2014 12:37:53 +1000 [thread overview] Message-ID: <20140430123753.16dd13b23d29e09548a4bd56@canb.auug.org.au> (raw) [-- Attachment #1.1: Type: text/plain, Size: 4232 bytes --] Hi all, Today's linux-next merge of the drm-intel tree got a conflict in drivers/gpu/drm/i915/i915_gem_gtt.c between commitcfa7c862982b ("drm/i915: Sanitize the enable_ppgtt module option once") from the drm-intel-fixes tree tree and commit 5db6c735ead5 ("drm/i915: dmesg output for VT-d testing") from the drm-intel tree. I fixed it up (see below) and can carry the fix as necessary (no action is required). -- Cheers, Stephen Rothwell sfr@canb.auug.org.au diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c index 154b0f8bb88d,496916298e8a..000000000000 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@@ -62,62 -48,13 +62,9 @@@ static int sanitize_enable_ppgtt(struc } #endif - /* Full ppgtt disabled by default for now due to issues. */ - if (full) - return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2); - else - return HAS_ALIASING_PPGTT(dev); + return HAS_ALIASING_PPGTT(dev) ? 1 : 0; } - #define GEN6_PPGTT_PD_ENTRIES 512 - #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) - typedef uint64_t gen8_gtt_pte_t; - typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; - - /* PPGTT stuff */ - #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) - #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) - - #define GEN6_PDE_VALID (1 << 0) - /* gen6+ has bit 11-4 for physical addr bit 39-32 */ - #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) - - #define GEN6_PTE_VALID (1 << 0) - #define GEN6_PTE_UNCACHED (1 << 1) - #define HSW_PTE_UNCACHED (0) - #define GEN6_PTE_CACHE_LLC (2 << 1) - #define GEN7_PTE_CACHE_L3_LLC (3 << 1) - #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) - #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) - - /* Cacheability Control is a 4-bit value. The low three bits are stored in * - * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. - */ - #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ - (((bits) & 0x8) << (11 - 3))) - #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) - #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) - #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) - #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) - #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) - #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) - - #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) - #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) - - /* GEN8 legacy style addressis defined as a 3 level page table: - * 31:30 | 29:21 | 20:12 | 11:0 - * PDPE | PDE | PTE | offset - * The difference as compared to normal x86 3 level page table is the PDPEs are - * programmed via register. - */ - #define GEN8_PDPE_SHIFT 30 - #define GEN8_PDPE_MASK 0x3 - #define GEN8_PDE_SHIFT 21 - #define GEN8_PDE_MASK 0x1ff - #define GEN8_PTE_SHIFT 12 - #define GEN8_PTE_MASK 0x1ff - - #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) - #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ - #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ - #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ static void ppgtt_bind_vma(struct i915_vma *vma, enum i915_cache_level cache_level, @@@ -2041,14 -1971,10 +1981,18 @@@ int i915_gem_gtt_init(struct drm_devic gtt->base.total >> 20); DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); + /* + * i915.enable_ppgtt is read-only, so do an early pass to validate the + * user's requested state against the hardware/driver capabilities. We + * do this now so that we can print out any log messages once rather + * than every time we check intel_enable_ppgtt(). + */ + i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); + DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); + #ifdef CONFIG_INTEL_IOMMU + if (intel_iommu_gfx_mapped) + DRM_INFO("VT-d active for gfx access\n"); + #endif return 0; } [-- Attachment #1.2: Type: application/pgp-signature, Size: 836 bytes --] [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
next reply other threads:[~2014-04-30 2:38 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-04-30 2:37 Stephen Rothwell [this message] 2014-04-30 2:37 ` linux-next: manual merge of the drm-intel tree with the drm-intel-fixes tree Stephen Rothwell [not found] ` <87r44fidgp.fsf@intel.com> 2014-04-30 6:12 ` [Intel-gfx] " Daniel Vetter -- strict thread matches above, loose matches on Subject: below -- 2022-02-25 17:08 broonie 2022-02-25 17:08 ` broonie 2022-02-23 14:46 broonie 2022-02-23 14:46 ` broonie 2022-02-02 23:59 Stephen Rothwell 2022-02-02 23:59 ` Stephen Rothwell 2021-08-02 15:18 Mark Brown 2020-06-30 1:52 Stephen Rothwell 2020-06-30 1:52 ` Stephen Rothwell 2020-07-06 1:51 ` Stephen Rothwell 2020-07-06 1:51 ` Stephen Rothwell 2020-03-11 2:36 Stephen Rothwell 2020-03-11 2:36 ` Stephen Rothwell 2020-03-20 1:57 ` Stephen Rothwell 2020-03-20 1:57 ` Stephen Rothwell 2019-03-21 23:57 Stephen Rothwell 2019-03-21 23:57 ` Stephen Rothwell 2019-03-31 22:59 ` Stephen Rothwell 2017-10-18 9:27 Mark Brown 2017-10-18 9:27 ` Mark Brown 2017-10-16 11:35 Mark Brown 2017-10-16 11:35 ` Mark Brown 2017-10-17 8:11 ` Arnd Bergmann 2017-10-17 8:11 ` Arnd Bergmann 2017-10-17 8:30 ` Mark Brown 2017-10-17 8:30 ` Mark Brown 2017-10-12 18:44 Mark Brown 2017-10-12 18:44 ` Mark Brown 2017-10-12 18:36 Mark Brown 2017-10-12 18:36 ` Mark Brown 2017-06-08 3:07 Stephen Rothwell 2017-06-08 3:04 Stephen Rothwell 2017-03-21 0:37 Stephen Rothwell 2017-03-21 0:37 ` Stephen Rothwell 2016-08-24 1:42 Stephen Rothwell 2016-08-24 1:42 ` Stephen Rothwell 2016-08-24 1:32 Stephen Rothwell 2016-08-24 1:32 ` Stephen Rothwell 2016-06-22 1:40 Stephen Rothwell 2016-06-22 1:40 ` Stephen Rothwell 2015-11-18 0:30 Stephen Rothwell 2015-11-18 0:30 ` Stephen Rothwell 2015-09-30 1:32 Stephen Rothwell 2015-09-30 1:32 ` Stephen Rothwell 2015-09-24 1:25 Stephen Rothwell 2015-09-24 1:25 ` Stephen Rothwell 2015-09-24 8:57 ` Jani Nikula 2015-09-24 8:57 ` Jani Nikula 2015-09-24 11:52 ` Stephen Rothwell 2015-07-15 0:15 Stephen Rothwell 2015-07-15 0:15 ` Stephen Rothwell 2015-07-14 2:11 Stephen Rothwell 2015-07-14 2:11 ` Stephen Rothwell 2015-07-14 7:34 ` Daniel Vetter 2015-07-14 7:34 ` Daniel Vetter 2015-07-10 2:15 Stephen Rothwell 2015-07-10 2:15 ` Stephen Rothwell 2015-07-10 2:08 Stephen Rothwell 2015-07-10 2:08 ` Stephen Rothwell 2015-02-27 0:36 Stephen Rothwell 2015-02-27 0:36 ` Stephen Rothwell 2015-02-26 0:15 Stephen Rothwell 2015-02-26 0:15 ` Stephen Rothwell 2015-02-25 1:05 Stephen Rothwell 2015-02-25 1:05 ` Stephen Rothwell 2015-01-09 2:06 Stephen Rothwell 2015-01-09 2:06 ` Stephen Rothwell 2014-05-22 5:58 Stephen Rothwell 2014-05-22 5:58 ` Stephen Rothwell 2013-12-16 1:45 Stephen Rothwell 2013-12-16 1:45 ` Stephen Rothwell 2013-12-02 1:04 Stephen Rothwell 2013-12-02 1:04 ` Stephen Rothwell 2013-12-02 1:13 ` Stephen Rothwell 2013-12-02 1:13 ` Stephen Rothwell 2013-09-25 2:00 Stephen Rothwell 2013-09-25 2:00 ` Stephen Rothwell 2013-09-20 1:40 Stephen Rothwell 2013-09-20 1:40 ` Stephen Rothwell 2013-07-26 3:14 Stephen Rothwell 2013-07-26 3:14 ` Stephen Rothwell 2013-07-26 3:10 Stephen Rothwell 2013-07-26 3:10 ` Stephen Rothwell 2013-07-18 2:07 Stephen Rothwell 2013-07-18 2:07 ` Stephen Rothwell 2013-07-18 1:44 Stephen Rothwell 2013-07-18 1:44 ` Stephen Rothwell 2013-07-16 2:05 Stephen Rothwell 2013-07-16 2:05 ` Stephen Rothwell
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