* [PATCH] drm/i915: Fix VLV CRC reading.
@ 2014-06-05 21:28 Rodrigo Vivi
2014-06-09 11:42 ` Ville Syrjälä
2014-06-10 7:05 ` Daniel Vetter
0 siblings, 2 replies; 3+ messages in thread
From: Rodrigo Vivi @ 2014-06-05 21:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Adding missing Display mmio reg offset.
Credits-to: Laws, Philip <philip.laws@intel.com>
Cc: He, Shuang <shuang.he@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 286f05c..05e2541 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2627,7 +2627,7 @@ enum punit_power_well {
#define PORT_DFT_I9XX 0x61150
#define DC_BALANCE_RESET (1 << 25)
-#define PORT_DFT2_G4X 0x61154
+#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
#define DC_BALANCE_RESET_VLV (1 << 31)
#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
#define PIPE_B_SCRAMBLE_RESET (1 << 1)
--
1.9.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915: Fix VLV CRC reading.
2014-06-05 21:28 [PATCH] drm/i915: Fix VLV CRC reading Rodrigo Vivi
@ 2014-06-09 11:42 ` Ville Syrjälä
2014-06-10 7:05 ` Daniel Vetter
1 sibling, 0 replies; 3+ messages in thread
From: Ville Syrjälä @ 2014-06-09 11:42 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Thu, Jun 05, 2014 at 02:28:17PM -0700, Rodrigo Vivi wrote:
> Adding missing Display mmio reg offset.
>
> Credits-to: Laws, Philip <philip.laws@intel.com>
> Cc: He, Shuang <shuang.he@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 286f05c..05e2541 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2627,7 +2627,7 @@ enum punit_power_well {
>
> #define PORT_DFT_I9XX 0x61150
> #define DC_BALANCE_RESET (1 << 25)
> -#define PORT_DFT2_G4X 0x61154
> +#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
> #define DC_BALANCE_RESET_VLV (1 << 31)
> #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
> #define PIPE_B_SCRAMBLE_RESET (1 << 1)
> --
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915: Fix VLV CRC reading.
2014-06-05 21:28 [PATCH] drm/i915: Fix VLV CRC reading Rodrigo Vivi
2014-06-09 11:42 ` Ville Syrjälä
@ 2014-06-10 7:05 ` Daniel Vetter
1 sibling, 0 replies; 3+ messages in thread
From: Daniel Vetter @ 2014-06-10 7:05 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Thu, Jun 05, 2014 at 02:28:17PM -0700, Rodrigo Vivi wrote:
> Adding missing Display mmio reg offset.
>
> Credits-to: Laws, Philip <philip.laws@intel.com>
> Cc: He, Shuang <shuang.he@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Is there no bugzilla that pipe crc tests on DP/eDP ports aren't working on
byt? Can you please chase this down with QA?
Patch is queued for -next.
Thanks, Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 286f05c..05e2541 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2627,7 +2627,7 @@ enum punit_power_well {
>
> #define PORT_DFT_I9XX 0x61150
> #define DC_BALANCE_RESET (1 << 25)
> -#define PORT_DFT2_G4X 0x61154
> +#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
> #define DC_BALANCE_RESET_VLV (1 << 31)
> #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
> #define PIPE_B_SCRAMBLE_RESET (1 << 1)
> --
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-06-05 21:28 [PATCH] drm/i915: Fix VLV CRC reading Rodrigo Vivi
2014-06-09 11:42 ` Ville Syrjälä
2014-06-10 7:05 ` Daniel Vetter
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