* [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
@ 2014-06-11 15:57 ` Chew Chiau Ee
0 siblings, 0 replies; 6+ messages in thread
From: Chew Chiau Ee @ 2014-06-11 15:57 UTC (permalink / raw)
To: Eric Miao, Russell King, Haojian Zhuang, Mark Brown
Cc: Mika Westerberg, LKML, linux-arm-kernel, linux-spi, Chew Chiau Ee
From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
drivers/spi/spi-pxa2xx.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index a98df7e..cfaf3e6 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -126,7 +126,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
goto detection_done;
}
- value &= ~SPI_CS_CONTROL_SW_MODE;
+ orig = value &= ~SPI_CS_CONTROL_SW_MODE;
writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
if (value != orig) {
--
1.7.4.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
@ 2014-06-11 15:57 ` Chew Chiau Ee
0 siblings, 0 replies; 6+ messages in thread
From: Chew Chiau Ee @ 2014-06-11 15:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
drivers/spi/spi-pxa2xx.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index a98df7e..cfaf3e6 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -126,7 +126,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
goto detection_done;
}
- value &= ~SPI_CS_CONTROL_SW_MODE;
+ orig = value &= ~SPI_CS_CONTROL_SW_MODE;
writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
if (value != orig) {
--
1.7.4.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
@ 2014-06-11 15:57 ` Chew Chiau Ee
0 siblings, 0 replies; 6+ messages in thread
From: Chew Chiau Ee @ 2014-06-11 15:57 UTC (permalink / raw)
To: Eric Miao, Russell King, Haojian Zhuang, Mark Brown
Cc: Mika Westerberg, LKML,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-spi-u79uwXL29TY76Z2rM5mHXA, Chew Chiau Ee
From: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Acked-by: Mika Westerberg <mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
drivers/spi/spi-pxa2xx.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index a98df7e..cfaf3e6 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -126,7 +126,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
goto detection_done;
}
- value &= ~SPI_CS_CONTROL_SW_MODE;
+ orig = value &= ~SPI_CS_CONTROL_SW_MODE;
writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
if (value != orig) {
--
1.7.4.4
--
To unsubscribe from this list: send the line "unsubscribe linux-spi" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
@ 2014-06-11 23:42 ` Mark Brown
0 siblings, 0 replies; 6+ messages in thread
From: Mark Brown @ 2014-06-11 23:42 UTC (permalink / raw)
To: Chew Chiau Ee
Cc: Eric Miao, Russell King, Haojian Zhuang, Mika Westerberg, LKML,
linux-arm-kernel, linux-spi
[-- Attachment #1: Type: text/plain, Size: 848 bytes --]
On Wed, Jun 11, 2014 at 11:57:02PM +0800, Chew Chiau Ee wrote:
> It was observed that after module removal followed by insertion,
> the SW mode chipselect is not properly set. Thus causing transfer
> failure due to incorrect CS toggling.
> - value &= ~SPI_CS_CONTROL_SW_MODE;
> + orig = value &= ~SPI_CS_CONTROL_SW_MODE;
> writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
> value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
> if (value != orig) {
This is a *really* non-obvious fix, I'd have expected the original value
to be re-read from the hardware here rather than just tweaked, or at
least some comment explaining what's going on. Possibly also saving to
a differently named temporary variable would do it but whatever I had to
go look at the context to figure out what was happening and even there I
was unclear.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
@ 2014-06-11 23:42 ` Mark Brown
0 siblings, 0 replies; 6+ messages in thread
From: Mark Brown @ 2014-06-11 23:42 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jun 11, 2014 at 11:57:02PM +0800, Chew Chiau Ee wrote:
> It was observed that after module removal followed by insertion,
> the SW mode chipselect is not properly set. Thus causing transfer
> failure due to incorrect CS toggling.
> - value &= ~SPI_CS_CONTROL_SW_MODE;
> + orig = value &= ~SPI_CS_CONTROL_SW_MODE;
> writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
> value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
> if (value != orig) {
This is a *really* non-obvious fix, I'd have expected the original value
to be re-read from the hardware here rather than just tweaked, or at
least some comment explaining what's going on. Possibly also saving to
a differently named temporary variable would do it but whatever I had to
go look at the context to figure out what was happening and even there I
was unclear.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140612/37f43ef6/attachment.sig>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
@ 2014-06-11 23:42 ` Mark Brown
0 siblings, 0 replies; 6+ messages in thread
From: Mark Brown @ 2014-06-11 23:42 UTC (permalink / raw)
To: Chew Chiau Ee
Cc: Eric Miao, Russell King, Haojian Zhuang, Mika Westerberg, LKML,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-spi-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 848 bytes --]
On Wed, Jun 11, 2014 at 11:57:02PM +0800, Chew Chiau Ee wrote:
> It was observed that after module removal followed by insertion,
> the SW mode chipselect is not properly set. Thus causing transfer
> failure due to incorrect CS toggling.
> - value &= ~SPI_CS_CONTROL_SW_MODE;
> + orig = value &= ~SPI_CS_CONTROL_SW_MODE;
> writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
> value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
> if (value != orig) {
This is a *really* non-obvious fix, I'd have expected the original value
to be re-read from the hardware here rather than just tweaked, or at
least some comment explaining what's going on. Possibly also saving to
a differently named temporary variable would do it but whatever I had to
go look at the context to figure out what was happening and even there I
was unclear.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-06-11 23:43 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-06-11 15:57 [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI Chew Chiau Ee
2014-06-11 15:57 ` Chew Chiau Ee
2014-06-11 15:57 ` Chew Chiau Ee
2014-06-11 23:42 ` Mark Brown
2014-06-11 23:42 ` Mark Brown
2014-06-11 23:42 ` Mark Brown
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.