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* Re: [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic
  2014-07-10  7:46 ` [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic deepak.s
@ 2014-07-09 12:03   ` Daniel Vetter
  2014-07-11  4:26     ` Deepak S
  0 siblings, 1 reply; 24+ messages in thread
From: Daniel Vetter @ 2014-07-09 12:03 UTC (permalink / raw)
  To: deepak.s; +Cc: intel-gfx

On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
> 
> Since freq/encode conversion formula changes from platform to platform,
> create a generic wrapper function and having platform check inside this
> help to simpilfy adding newer platform freq/opcode conversion.
> 
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++-----
>  drivers/gpu/drm/i915/i915_drv.h     |  4 +--
>  drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++-------
>  drivers/gpu/drm/i915/intel_pm.c     | 52 +++++++++++++++++++++++++++----------
>  4 files changed, 56 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index b3b56c4..dd7078d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1140,14 +1140,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  
>  		val = valleyview_rps_max_freq(dev_priv);
>  		seq_printf(m, "max GPU freq: %d MHz\n",
> -			   vlv_gpu_freq(dev_priv, val));
> +			   intel_gpu_freq(dev_priv, val));

intel_ is a bit too generic a prefix for a function which seems to be only
used on byt+chv. I'd just add a if (IS_CHERRYVIEW) ... else /* vlv code */
to both functions and not extract further.

Aside: Since marketing stopped using vlv and switched to byt we're using
vlv for code shared by byt and chv and byt_ for byt-only code. Helps a bit
to keep things appart.
-Daniel

>  
>  		val = valleyview_rps_min_freq(dev_priv);
>  		seq_printf(m, "min GPU freq: %d MHz\n",
> -			   vlv_gpu_freq(dev_priv, val));
> +			   intel_gpu_freq(dev_priv, val));
>  
>  		seq_printf(m, "current GPU freq: %d MHz\n",
> -			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> +			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
>  		mutex_unlock(&dev_priv->rps.hw_lock);
>  	} else {
>  		seq_puts(m, "no P-state info available\n");
> @@ -3667,7 +3667,7 @@ i915_max_freq_get(void *data, u64 *val)
>  		return ret;
>  
>  	if (IS_VALLEYVIEW(dev))
> -		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
> +		*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
>  	else
>  		*val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
>  	mutex_unlock(&dev_priv->rps.hw_lock);
> @@ -3698,7 +3698,7 @@ i915_max_freq_set(void *data, u64 val)
>  	 * Turbo will still be enabled, but won't go above the set value.
>  	 */
>  	if (IS_VALLEYVIEW(dev)) {
> -		val = vlv_freq_opcode(dev_priv, val);
> +		val = intel_freq_opcode(dev_priv, val);
>  
>  		hw_max = valleyview_rps_max_freq(dev_priv);
>  		hw_min = valleyview_rps_min_freq(dev_priv);
> @@ -3748,7 +3748,7 @@ i915_min_freq_get(void *data, u64 *val)
>  		return ret;
>  
>  	if (IS_VALLEYVIEW(dev))
> -		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
> +		*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
>  	else
>  		*val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
>  	mutex_unlock(&dev_priv->rps.hw_lock);
> @@ -3779,7 +3779,7 @@ i915_min_freq_set(void *data, u64 val)
>  	 * Turbo will still be enabled, but won't go below the set value.
>  	 */
>  	if (IS_VALLEYVIEW(dev)) {
> -		val = vlv_freq_opcode(dev_priv, val);
> +		val = intel_freq_opcode(dev_priv, val);
>  
>  		hw_max = valleyview_rps_max_freq(dev_priv);
>  		hw_min = valleyview_rps_min_freq(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 90216bb..bce4654 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2749,8 +2749,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
>  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  
> -int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
> -int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
> +int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> +int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>  
>  #define FORCEWAKE_RENDER	(1 << 0)
>  #define FORCEWAKE_MEDIA		(1 << 1)
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index b15c8ce..adfc4b9 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -269,7 +269,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
>  	if (IS_VALLEYVIEW(dev_priv->dev)) {
>  		u32 freq;
>  		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> -		ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
> +		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
>  	} else {
>  		ret = dev_priv->rps.cur_freq * GT_FREQUENCY_MULTIPLIER;
>  	}
> @@ -288,7 +288,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	return snprintf(buf, PAGE_SIZE, "%d\n",
> -			vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> +			intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
>  }
>  
>  static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
> @@ -302,7 +302,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  	if (IS_VALLEYVIEW(dev_priv->dev))
> -		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
> +		ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
>  	else
>  		ret = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
>  	mutex_unlock(&dev_priv->rps.hw_lock);
> @@ -329,7 +329,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  
>  	if (IS_VALLEYVIEW(dev_priv->dev))
> -		val = vlv_freq_opcode(dev_priv, val);
> +		val = intel_freq_opcode(dev_priv, val);
>  	else
>  		val /= GT_FREQUENCY_MULTIPLIER;
>  
> @@ -374,7 +374,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  	if (IS_VALLEYVIEW(dev_priv->dev))
> -		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
> +		ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
>  	else
>  		ret = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
>  	mutex_unlock(&dev_priv->rps.hw_lock);
> @@ -401,7 +401,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  
>  	if (IS_VALLEYVIEW(dev))
> -		val = vlv_freq_opcode(dev_priv, val);
> +		val = intel_freq_opcode(dev_priv, val);
>  	else
>  		val /= GT_FREQUENCY_MULTIPLIER;
>  
> @@ -462,17 +462,17 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
>  
>  	if (attr == &dev_attr_gt_RP0_freq_mhz) {
>  		if (IS_VALLEYVIEW(dev))
> -			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
> +			val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
>  		else
>  			val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
>  	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
>  		if (IS_VALLEYVIEW(dev))
> -			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
> +			val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
>  		else
>  			val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
>  	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
>  		if (IS_VALLEYVIEW(dev))
> -			val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq);
> +			val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
>  		else
>  			val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b8e7afc..9dfebab 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3328,9 +3328,9 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
>  	WARN_ON(val < dev_priv->rps.min_freq_softlimit);
>  
>  	DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>  			 dev_priv->rps.cur_freq,
> -			 vlv_gpu_freq(dev_priv, val), val);
> +			 intel_gpu_freq(dev_priv, val), val);
>  
>  	if (val != dev_priv->rps.cur_freq)
>  		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
> @@ -3338,7 +3338,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
>  	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
>  
>  	dev_priv->rps.cur_freq = val;
> -	trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
> +	trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
>  }
>  
>  static void gen8_disable_rps_interrupts(struct drm_device *dev)
> @@ -3961,22 +3961,22 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>  	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
>  	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>  	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>  			 dev_priv->rps.max_freq);
>  
>  	dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
>  	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>  			 dev_priv->rps.efficient_freq);
>  
>  	dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
>  	DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
>  			 dev_priv->rps.rp1_freq);
>  
>  	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
>  	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>  			 dev_priv->rps.min_freq);
>  
>  	/* Preserve min/max settings in case of re-init */
> @@ -4000,17 +4000,17 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
>  	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
>  	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>  	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>  			 dev_priv->rps.max_freq);
>  
>  	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
>  	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>  			 dev_priv->rps.efficient_freq);
>  
>  	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
>  	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>  			 dev_priv->rps.min_freq);
>  
>  	/* Preserve min/max settings in case of re-init */
> @@ -4106,11 +4106,11 @@ static void cherryview_enable_rps(struct drm_device *dev)
>  
>  	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
>  	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>  			 dev_priv->rps.cur_freq);
>  
>  	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>  			 dev_priv->rps.efficient_freq);
>  
>  	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
> @@ -4184,11 +4184,11 @@ static void valleyview_enable_rps(struct drm_device *dev)
>  
>  	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
>  	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>  			 dev_priv->rps.cur_freq);
>  
>  	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>  			 dev_priv->rps.efficient_freq);
>  
>  	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
> @@ -6946,6 +6946,30 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>  	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
>  }
>  
> +int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
> +{
> +	int ret;
> +
> +	if (!IS_VALLEYVIEW(dev_priv->dev))
> +		return -1;
> +
> +	ret = vlv_gpu_freq(dev_priv, val);
> +
> +	return ret;
> +}
> +
> +int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
> +{
> +	int ret;
> +
> +	if (!IS_VALLEYVIEW(dev_priv->dev))
> +		return -1;
> +
> +	ret = vlv_freq_opcode(dev_priv, val);
> +
> +	return ret;
> +}
> +
>  void intel_pm_setup(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic
  2014-07-11  4:26     ` Deepak S
@ 2014-07-10  6:28       ` Daniel Vetter
  2014-07-11  6:50         ` Deepak S
  0 siblings, 1 reply; 24+ messages in thread
From: Daniel Vetter @ 2014-07-10  6:28 UTC (permalink / raw)
  To: Deepak S; +Cc: intel-gfx

On Fri, Jul 11, 2014 at 09:56:35AM +0530, Deepak S wrote:
> 
> On Wednesday 09 July 2014 05:33 PM, Daniel Vetter wrote:
> >On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepak.s@linux.intel.com wrote:
> >>From: Deepak S <deepak.s@linux.intel.com>
> >>
> >>Since freq/encode conversion formula changes from platform to platform,
> >>create a generic wrapper function and having platform check inside this
> >>help to simpilfy adding newer platform freq/opcode conversion.
> >>
> >>Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> >>---
> >>  drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++-----
> >>  drivers/gpu/drm/i915/i915_drv.h     |  4 +--
> >>  drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++-------
> >>  drivers/gpu/drm/i915/intel_pm.c     | 52 +++++++++++++++++++++++++++----------
> >>  4 files changed, 56 insertions(+), 32 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> >>index b3b56c4..dd7078d 100644
> >>--- a/drivers/gpu/drm/i915/i915_debugfs.c
> >>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >>@@ -1140,14 +1140,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >>  		val = valleyview_rps_max_freq(dev_priv);
> >>  		seq_printf(m, "max GPU freq: %d MHz\n",
> >>-			   vlv_gpu_freq(dev_priv, val));
> >>+			   intel_gpu_freq(dev_priv, val));
> >intel_ is a bit too generic a prefix for a function which seems to be only
> >used on byt+chv. I'd just add a if (IS_CHERRYVIEW) ... else /* vlv code */
> >to both functions and not extract further.
> >
> >Aside: Since marketing stopped using vlv and switched to byt we're using
> >vlv for code shared by byt and chv and byt_ for byt-only code. Helps a bit
> >to keep things appart.
> >-Daniel
> 
> Ok. Will it be Ok to use "vlv_gpu_freq" and have BYT and CHV check under
> this function?

Yeah, that's my idea.

> The reason why i made more generic is it will help us to add conversion
> logic for future platforms

We can look at this again when it happpens. With the current code this
doesn't include desktop rps so the intel_ prefix was a bit confusing.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt
@ 2014-07-10  7:46 deepak.s
  2014-07-10  7:46 ` [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview deepak.s
                   ` (8 more replies)
  0 siblings, 9 replies; 24+ messages in thread
From: deepak.s @ 2014-07-10  7:46 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt for verifying the freq on VLV and CHV

Deepak S (7):
  drm/i915: Read guaranteed freq for valleyview
  drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs
  drm/i915: keep freq/opcode conversion function more generic
  drm/i915: populate mem_freq/cz_clock for chv
  drm/i915: CHV GPU frequency to opcode functions
  drm/i915/chv: Add basic PM interrupt support for CHV
  drm/i915: Add RP1 render P state thresholds in CHV

 drivers/gpu/drm/i915/i915_debugfs.c |  14 +--
 drivers/gpu/drm/i915/i915_drv.h     |   5 +-
 drivers/gpu/drm/i915/i915_irq.c     |   2 +-
 drivers/gpu/drm/i915/i915_reg.h     |   6 ++
 drivers/gpu/drm/i915/i915_sysfs.c   |  30 +++++--
 drivers/gpu/drm/i915/intel_pm.c     | 164 +++++++++++++++++++++++++++++++++---
 6 files changed, 189 insertions(+), 32 deletions(-)

-- 
1.9.1

^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview
  2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
@ 2014-07-10  7:46 ` deepak.s
  2014-07-11 14:42   ` Mika Kuoppala
  2014-07-10  7:46 ` [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs deepak.s
                   ` (7 subsequent siblings)
  8 siblings, 1 reply; 24+ messages in thread
From: deepak.s @ 2014-07-10  7:46 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

Reading RP1 for valleyview to help us enable "pm_rps" i-g-t testcase
execution.

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1af641..b8e7afc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3816,6 +3816,17 @@ int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
 	return rpn;
 }
 
+int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp1;
+
+	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
+
+	rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
+
+	return rp1;
+}
+
 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rp0;
@@ -3958,6 +3969,11 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
 			 dev_priv->rps.efficient_freq);
 
+	dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
+			 dev_priv->rps.rp1_freq);
+
 	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
 	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs
  2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
  2014-07-10  7:46 ` [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview deepak.s
@ 2014-07-10  7:46 ` deepak.s
  2014-07-11 14:44   ` Mika Kuoppala
  2014-07-11 16:00   ` Daniel Vetter
  2014-07-10  7:46 ` [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic deepak.s
                   ` (6 subsequent siblings)
  8 siblings, 2 replies; 24+ messages in thread
From: deepak.s @ 2014-07-10  7:46 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

This is useful for userspace utilities to verify and micromanaging the
increase/decrease frequncy.

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 86ce39a..b15c8ce 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -461,11 +461,20 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
 	mutex_unlock(&dev->struct_mutex);
 
 	if (attr == &dev_attr_gt_RP0_freq_mhz) {
-		val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
+		if (IS_VALLEYVIEW(dev))
+			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
+		else
+			val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
 	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
-		val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
+		if (IS_VALLEYVIEW(dev))
+			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
+		else
+			val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
 	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
-		val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
+		if (IS_VALLEYVIEW(dev))
+			val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq);
+		else
+			val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
 	} else {
 		BUG();
 	}
@@ -486,6 +495,9 @@ static const struct attribute *vlv_attrs[] = {
 	&dev_attr_gt_cur_freq_mhz.attr,
 	&dev_attr_gt_max_freq_mhz.attr,
 	&dev_attr_gt_min_freq_mhz.attr,
+	&dev_attr_gt_RP0_freq_mhz.attr,
+	&dev_attr_gt_RP1_freq_mhz.attr,
+	&dev_attr_gt_RPn_freq_mhz.attr,
 	&dev_attr_vlv_rpe_freq_mhz.attr,
 	NULL,
 };
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic
  2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
  2014-07-10  7:46 ` [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview deepak.s
  2014-07-10  7:46 ` [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs deepak.s
@ 2014-07-10  7:46 ` deepak.s
  2014-07-09 12:03   ` Daniel Vetter
  2014-07-10  7:46 ` [PATCH 4/7] drm/i915: populate mem_freq/cz_clock for chv deepak.s
                   ` (5 subsequent siblings)
  8 siblings, 1 reply; 24+ messages in thread
From: deepak.s @ 2014-07-10  7:46 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

Since freq/encode conversion formula changes from platform to platform,
create a generic wrapper function and having platform check inside this
help to simpilfy adding newer platform freq/opcode conversion.

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++-----
 drivers/gpu/drm/i915/i915_drv.h     |  4 +--
 drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++-------
 drivers/gpu/drm/i915/intel_pm.c     | 52 +++++++++++++++++++++++++++----------
 4 files changed, 56 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b3b56c4..dd7078d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1140,14 +1140,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 		val = valleyview_rps_max_freq(dev_priv);
 		seq_printf(m, "max GPU freq: %d MHz\n",
-			   vlv_gpu_freq(dev_priv, val));
+			   intel_gpu_freq(dev_priv, val));
 
 		val = valleyview_rps_min_freq(dev_priv);
 		seq_printf(m, "min GPU freq: %d MHz\n",
-			   vlv_gpu_freq(dev_priv, val));
+			   intel_gpu_freq(dev_priv, val));
 
 		seq_printf(m, "current GPU freq: %d MHz\n",
-			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
+			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
 		mutex_unlock(&dev_priv->rps.hw_lock);
 	} else {
 		seq_puts(m, "no P-state info available\n");
@@ -3667,7 +3667,7 @@ i915_max_freq_get(void *data, u64 *val)
 		return ret;
 
 	if (IS_VALLEYVIEW(dev))
-		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
+		*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
 	else
 		*val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -3698,7 +3698,7 @@ i915_max_freq_set(void *data, u64 val)
 	 * Turbo will still be enabled, but won't go above the set value.
 	 */
 	if (IS_VALLEYVIEW(dev)) {
-		val = vlv_freq_opcode(dev_priv, val);
+		val = intel_freq_opcode(dev_priv, val);
 
 		hw_max = valleyview_rps_max_freq(dev_priv);
 		hw_min = valleyview_rps_min_freq(dev_priv);
@@ -3748,7 +3748,7 @@ i915_min_freq_get(void *data, u64 *val)
 		return ret;
 
 	if (IS_VALLEYVIEW(dev))
-		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
+		*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
 	else
 		*val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -3779,7 +3779,7 @@ i915_min_freq_set(void *data, u64 val)
 	 * Turbo will still be enabled, but won't go below the set value.
 	 */
 	if (IS_VALLEYVIEW(dev)) {
-		val = vlv_freq_opcode(dev_priv, val);
+		val = intel_freq_opcode(dev_priv, val);
 
 		hw_max = valleyview_rps_max_freq(dev_priv);
 		hw_min = valleyview_rps_min_freq(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90216bb..bce4654 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2749,8 +2749,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
-int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
-int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
+int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
+int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
 #define FORCEWAKE_RENDER	(1 << 0)
 #define FORCEWAKE_MEDIA		(1 << 1)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index b15c8ce..adfc4b9 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -269,7 +269,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 	if (IS_VALLEYVIEW(dev_priv->dev)) {
 		u32 freq;
 		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-		ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
+		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
 	} else {
 		ret = dev_priv->rps.cur_freq * GT_FREQUENCY_MULTIPLIER;
 	}
@@ -288,7 +288,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	return snprintf(buf, PAGE_SIZE, "%d\n",
-			vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
+			intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
 }
 
 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
@@ -302,7 +302,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (IS_VALLEYVIEW(dev_priv->dev))
-		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
+		ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
 	else
 		ret = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -329,7 +329,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 	mutex_lock(&dev_priv->rps.hw_lock);
 
 	if (IS_VALLEYVIEW(dev_priv->dev))
-		val = vlv_freq_opcode(dev_priv, val);
+		val = intel_freq_opcode(dev_priv, val);
 	else
 		val /= GT_FREQUENCY_MULTIPLIER;
 
@@ -374,7 +374,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (IS_VALLEYVIEW(dev_priv->dev))
-		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
+		ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
 	else
 		ret = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -401,7 +401,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 	mutex_lock(&dev_priv->rps.hw_lock);
 
 	if (IS_VALLEYVIEW(dev))
-		val = vlv_freq_opcode(dev_priv, val);
+		val = intel_freq_opcode(dev_priv, val);
 	else
 		val /= GT_FREQUENCY_MULTIPLIER;
 
@@ -462,17 +462,17 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
 
 	if (attr == &dev_attr_gt_RP0_freq_mhz) {
 		if (IS_VALLEYVIEW(dev))
-			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
+			val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
 		else
 			val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
 	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
 		if (IS_VALLEYVIEW(dev))
-			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
+			val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
 		else
 			val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
 	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
 		if (IS_VALLEYVIEW(dev))
-			val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq);
+			val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
 		else
 			val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b8e7afc..9dfebab 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3328,9 +3328,9 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
 	WARN_ON(val < dev_priv->rps.min_freq_softlimit);
 
 	DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
 			 dev_priv->rps.cur_freq,
-			 vlv_gpu_freq(dev_priv, val), val);
+			 intel_gpu_freq(dev_priv, val), val);
 
 	if (val != dev_priv->rps.cur_freq)
 		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
@@ -3338,7 +3338,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
 	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 
 	dev_priv->rps.cur_freq = val;
-	trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
+	trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
 }
 
 static void gen8_disable_rps_interrupts(struct drm_device *dev)
@@ -3961,22 +3961,22 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
 	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
 	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
 			 dev_priv->rps.max_freq);
 
 	dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
 	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
 			 dev_priv->rps.efficient_freq);
 
 	dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
 	DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
 			 dev_priv->rps.rp1_freq);
 
 	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
 	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
 			 dev_priv->rps.min_freq);
 
 	/* Preserve min/max settings in case of re-init */
@@ -4000,17 +4000,17 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
 	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
 	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
 	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
 			 dev_priv->rps.max_freq);
 
 	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
 	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
 			 dev_priv->rps.efficient_freq);
 
 	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
 	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
 			 dev_priv->rps.min_freq);
 
 	/* Preserve min/max settings in case of re-init */
@@ -4106,11 +4106,11 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
 	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
 	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
 			 dev_priv->rps.cur_freq);
 
 	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
 			 dev_priv->rps.efficient_freq);
 
 	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
@@ -4184,11 +4184,11 @@ static void valleyview_enable_rps(struct drm_device *dev)
 
 	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
 	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
 			 dev_priv->rps.cur_freq);
 
 	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
 			 dev_priv->rps.efficient_freq);
 
 	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
@@ -6946,6 +6946,30 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
 }
 
+int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
+{
+	int ret;
+
+	if (!IS_VALLEYVIEW(dev_priv->dev))
+		return -1;
+
+	ret = vlv_gpu_freq(dev_priv, val);
+
+	return ret;
+}
+
+int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
+{
+	int ret;
+
+	if (!IS_VALLEYVIEW(dev_priv->dev))
+		return -1;
+
+	ret = vlv_freq_opcode(dev_priv, val);
+
+	return ret;
+}
+
 void intel_pm_setup(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH 4/7] drm/i915: populate mem_freq/cz_clock for chv
  2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
                   ` (2 preceding siblings ...)
  2014-07-10  7:46 ` [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic deepak.s
@ 2014-07-10  7:46 ` deepak.s
  2014-07-11 14:50   ` Mika Kuoppala
  2014-07-10  7:46 ` [PATCH 5/7] drm/i915: CHV GPU frequency to opcode functions deepak.s
                   ` (4 subsequent siblings)
  8 siblings, 1 reply; 24+ messages in thread
From: deepak.s @ 2014-07-10  7:46 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

We need mem_freq or cz clock for freq/opcode conversion

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_reg.h |  6 ++++++
 drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bce4654..568b39c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -932,6 +932,7 @@ struct intel_gen6_power_mgmt {
 	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
 	u8 rp1_freq;		/* "less than" RP0 power/freqency */
 	u8 rp0_freq;		/* Non-overclocked max frequency. */
+	u32 cz_freq;
 
 	u32 ei_interrupt_count;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 490f031..e533efa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5541,6 +5541,12 @@ enum punit_power_well {
 						 GEN6_PM_RP_DOWN_THRESHOLD | \
 						 GEN6_PM_RP_DOWN_TIMEOUT)
 
+#define CHV_CZ_CLOCK_FREQ_MODE_200			200
+#define CHV_CZ_CLOCK_FREQ_MODE_267			267
+#define CHV_CZ_CLOCK_FREQ_MODE_320			320
+#define CHV_CZ_CLOCK_FREQ_MODE_333			333
+#define CHV_CZ_CLOCK_FREQ_MODE_400			400
+
 #define GEN7_GT_SCRATCH_BASE			0x4F100
 #define GEN7_GT_SCRATCH_REG_NUM			8
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9dfebab..6c19ce5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5706,6 +5706,35 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+	switch ((val >> 2) & 0x7) {
+	case 0:
+	case 1:
+			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
+			dev_priv->mem_freq = 1600;
+			break;
+	case 2:
+			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
+			dev_priv->mem_freq = 1600;
+			break;
+	case 3:
+			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
+			dev_priv->mem_freq = 2000;
+			break;
+	case 4:
+			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
+			dev_priv->mem_freq = 1600;
+			break;
+	case 5:
+			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
+			dev_priv->mem_freq = 1600;
+			break;
+	}
+	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH 5/7] drm/i915: CHV GPU frequency to opcode functions
  2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
                   ` (3 preceding siblings ...)
  2014-07-10  7:46 ` [PATCH 4/7] drm/i915: populate mem_freq/cz_clock for chv deepak.s
@ 2014-07-10  7:46 ` deepak.s
  2014-07-10  7:46 ` [PATCH 6/7] drm/i915/chv: Add basic PM interrupt support for CHV deepak.s
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 24+ messages in thread
From: deepak.s @ 2014-07-10  7:46 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

Adding chv specific fre/encode conversion.

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 68 +++++++++++++++++++++++++++++++++++------
 1 file changed, 59 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6c19ce5..6abd05b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6975,26 +6975,76 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
 }
 
-int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
+int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
 {
-	int ret;
+	int div, freq;
 
-	if (!IS_VALLEYVIEW(dev_priv->dev))
+	switch (dev_priv->rps.cz_freq) {
+	case 200:
+		div = 5;
+		break;
+	case 267:
+		div = 6;
+		break;
+	case 320:
+	case 333:
+	case 400:
+		div = 8;
+		break;
+	default:
 		return -1;
+	}
 
-	ret = vlv_gpu_freq(dev_priv, val);
+	freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
 
-	return ret;
+	return freq;
 }
 
-int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
+int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
-	int ret;
+	int mul, opcode;
 
-	if (!IS_VALLEYVIEW(dev_priv->dev))
+	switch (dev_priv->rps.cz_freq) {
+	case 200:
+		mul = 5;
+		break;
+	case 267:
+		mul = 6;
+		break;
+	case 320:
+	case 333:
+	case 400:
+		mul = 8;
+		break;
+	default:
 		return -1;
+	}
+
+	opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
+
+	return opcode;
+}
+
+int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
+{
+	int ret = -1;
+
+	if (IS_CHERRYVIEW(dev_priv->dev))
+		ret = chv_gpu_freq(dev_priv, val);
+	else if (IS_VALLEYVIEW(dev_priv->dev))
+		ret = vlv_gpu_freq(dev_priv, val);
+
+	return ret;
+}
+
+int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
+{
+	int ret = -1;
 
-	ret = vlv_freq_opcode(dev_priv, val);
+	if (IS_CHERRYVIEW(dev_priv->dev))
+		ret = chv_freq_opcode(dev_priv, val);
+	else if (IS_VALLEYVIEW(dev_priv->dev))
+		ret = vlv_freq_opcode(dev_priv, val);
 
 	return ret;
 }
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH 6/7] drm/i915/chv: Add basic PM interrupt support for CHV
  2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
                   ` (4 preceding siblings ...)
  2014-07-10  7:46 ` [PATCH 5/7] drm/i915: CHV GPU frequency to opcode functions deepak.s
@ 2014-07-10  7:46 ` deepak.s
  2014-07-11 15:03   ` Mika Kuoppala
  2014-07-10  7:46 ` [PATCH 7/7] drm/i915: Add RP1 render P state thresholds in CHV deepak.s
                   ` (2 subsequent siblings)
  8 siblings, 1 reply; 24+ messages in thread
From: deepak.s @ 2014-07-10  7:46 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

Enabled PM interrupt programming for CHV. Re-using gen8 code and extending same for CHV.

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 2 +-
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 38e6de1..ae6246c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1403,7 +1403,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
 	spin_lock_irq(&dev_priv->irq_lock);
 	pm_iir = dev_priv->rps.pm_iir;
 	dev_priv->rps.pm_iir = 0;
-	if (IS_BROADWELL(dev_priv->dev))
+	if (IS_BROADWELL(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))
 		bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 	else {
 		/* Make sure not to corrupt PMIMR state used by ringbuffer */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6abd05b..7da3719 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3398,6 +3398,8 @@ static void cherryview_disable_rps(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	gen8_disable_rps_interrupts(dev);
 }
 
 static void valleyview_disable_rps(struct drm_device *dev)
@@ -4115,6 +4117,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
 	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
 
+	gen8_enable_rps_interrupts(dev);
+
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 }
 
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH 7/7] drm/i915: Add RP1 render P state thresholds in CHV
  2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
                   ` (5 preceding siblings ...)
  2014-07-10  7:46 ` [PATCH 6/7] drm/i915/chv: Add basic PM interrupt support for CHV deepak.s
@ 2014-07-10  7:46 ` deepak.s
  2014-07-12  9:24 ` [PATCH v2 1/3] drm/i915: CHV GPU frequency to opcode functions deepak.s
  2014-07-12 13:16 ` [PATCH v2] drm/i915: Add RP1 render P state thresholds in CHV deepak.s
  8 siblings, 0 replies; 24+ messages in thread
From: deepak.s @ 2014-07-10  7:46 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

This is useful for userspace utilities to verify and micromanaging
the increase/decrease frequncy.

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7da3719..733505a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3809,6 +3809,16 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
 	return rpe;
 }
 
+int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp1;
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+
+	return rp1;
+}
+
 int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rpn;
@@ -4010,6 +4020,11 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
 			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
 			 dev_priv->rps.efficient_freq);
 
+	dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
+			 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
+			 dev_priv->rps.rp1_freq);
+
 	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
 	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
 			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic
  2014-07-09 12:03   ` Daniel Vetter
@ 2014-07-11  4:26     ` Deepak S
  2014-07-10  6:28       ` Daniel Vetter
  0 siblings, 1 reply; 24+ messages in thread
From: Deepak S @ 2014-07-11  4:26 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: intel-gfx


On Wednesday 09 July 2014 05:33 PM, Daniel Vetter wrote:
> On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepak.s@linux.intel.com wrote:
>> From: Deepak S <deepak.s@linux.intel.com>
>>
>> Since freq/encode conversion formula changes from platform to platform,
>> create a generic wrapper function and having platform check inside this
>> help to simpilfy adding newer platform freq/opcode conversion.
>>
>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++-----
>>   drivers/gpu/drm/i915/i915_drv.h     |  4 +--
>>   drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++-------
>>   drivers/gpu/drm/i915/intel_pm.c     | 52 +++++++++++++++++++++++++++----------
>>   4 files changed, 56 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index b3b56c4..dd7078d 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1140,14 +1140,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>   
>>   		val = valleyview_rps_max_freq(dev_priv);
>>   		seq_printf(m, "max GPU freq: %d MHz\n",
>> -			   vlv_gpu_freq(dev_priv, val));
>> +			   intel_gpu_freq(dev_priv, val));
> intel_ is a bit too generic a prefix for a function which seems to be only
> used on byt+chv. I'd just add a if (IS_CHERRYVIEW) ... else /* vlv code */
> to both functions and not extract further.
>
> Aside: Since marketing stopped using vlv and switched to byt we're using
> vlv for code shared by byt and chv and byt_ for byt-only code. Helps a bit
> to keep things appart.
> -Daniel

Ok. Will it be Ok to use "vlv_gpu_freq" and have BYT and CHV check under this function?

The reason why i made more generic is it will help us to add conversion logic for future platforms

Thanks
Deepak


>>   
>>   		val = valleyview_rps_min_freq(dev_priv);
>>   		seq_printf(m, "min GPU freq: %d MHz\n",
>> -			   vlv_gpu_freq(dev_priv, val));
>> +			   intel_gpu_freq(dev_priv, val));
>>   
>>   		seq_printf(m, "current GPU freq: %d MHz\n",
>> -			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
>> +			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
>>   		mutex_unlock(&dev_priv->rps.hw_lock);
>>   	} else {
>>   		seq_puts(m, "no P-state info available\n");
>> @@ -3667,7 +3667,7 @@ i915_max_freq_get(void *data, u64 *val)
>>   		return ret;
>>   
>>   	if (IS_VALLEYVIEW(dev))
>> -		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
>> +		*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
>>   	else
>>   		*val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
>>   	mutex_unlock(&dev_priv->rps.hw_lock);
>> @@ -3698,7 +3698,7 @@ i915_max_freq_set(void *data, u64 val)
>>   	 * Turbo will still be enabled, but won't go above the set value.
>>   	 */
>>   	if (IS_VALLEYVIEW(dev)) {
>> -		val = vlv_freq_opcode(dev_priv, val);
>> +		val = intel_freq_opcode(dev_priv, val);
>>   
>>   		hw_max = valleyview_rps_max_freq(dev_priv);
>>   		hw_min = valleyview_rps_min_freq(dev_priv);
>> @@ -3748,7 +3748,7 @@ i915_min_freq_get(void *data, u64 *val)
>>   		return ret;
>>   
>>   	if (IS_VALLEYVIEW(dev))
>> -		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
>> +		*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
>>   	else
>>   		*val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
>>   	mutex_unlock(&dev_priv->rps.hw_lock);
>> @@ -3779,7 +3779,7 @@ i915_min_freq_set(void *data, u64 val)
>>   	 * Turbo will still be enabled, but won't go below the set value.
>>   	 */
>>   	if (IS_VALLEYVIEW(dev)) {
>> -		val = vlv_freq_opcode(dev_priv, val);
>> +		val = intel_freq_opcode(dev_priv, val);
>>   
>>   		hw_max = valleyview_rps_max_freq(dev_priv);
>>   		hw_min = valleyview_rps_min_freq(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 90216bb..bce4654 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2749,8 +2749,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>>   u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
>>   void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>>   
>> -int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
>> -int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
>> +int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>> +int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>>   
>>   #define FORCEWAKE_RENDER	(1 << 0)
>>   #define FORCEWAKE_MEDIA		(1 << 1)
>> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
>> index b15c8ce..adfc4b9 100644
>> --- a/drivers/gpu/drm/i915/i915_sysfs.c
>> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
>> @@ -269,7 +269,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
>>   	if (IS_VALLEYVIEW(dev_priv->dev)) {
>>   		u32 freq;
>>   		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>> -		ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
>> +		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
>>   	} else {
>>   		ret = dev_priv->rps.cur_freq * GT_FREQUENCY_MULTIPLIER;
>>   	}
>> @@ -288,7 +288,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>   
>>   	return snprintf(buf, PAGE_SIZE, "%d\n",
>> -			vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
>> +			intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
>>   }
>>   
>>   static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
>> @@ -302,7 +302,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
>>   
>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>   	if (IS_VALLEYVIEW(dev_priv->dev))
>> -		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
>> +		ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
>>   	else
>>   		ret = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
>>   	mutex_unlock(&dev_priv->rps.hw_lock);
>> @@ -329,7 +329,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>   
>>   	if (IS_VALLEYVIEW(dev_priv->dev))
>> -		val = vlv_freq_opcode(dev_priv, val);
>> +		val = intel_freq_opcode(dev_priv, val);
>>   	else
>>   		val /= GT_FREQUENCY_MULTIPLIER;
>>   
>> @@ -374,7 +374,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
>>   
>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>   	if (IS_VALLEYVIEW(dev_priv->dev))
>> -		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
>> +		ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
>>   	else
>>   		ret = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
>>   	mutex_unlock(&dev_priv->rps.hw_lock);
>> @@ -401,7 +401,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>   
>>   	if (IS_VALLEYVIEW(dev))
>> -		val = vlv_freq_opcode(dev_priv, val);
>> +		val = intel_freq_opcode(dev_priv, val);
>>   	else
>>   		val /= GT_FREQUENCY_MULTIPLIER;
>>   
>> @@ -462,17 +462,17 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
>>   
>>   	if (attr == &dev_attr_gt_RP0_freq_mhz) {
>>   		if (IS_VALLEYVIEW(dev))
>> -			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
>> +			val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
>>   		else
>>   			val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
>>   	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
>>   		if (IS_VALLEYVIEW(dev))
>> -			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
>> +			val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
>>   		else
>>   			val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
>>   	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
>>   		if (IS_VALLEYVIEW(dev))
>> -			val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq);
>> +			val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
>>   		else
>>   			val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
>>   	} else {
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index b8e7afc..9dfebab 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -3328,9 +3328,9 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
>>   	WARN_ON(val < dev_priv->rps.min_freq_softlimit);
>>   
>>   	DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>>   			 dev_priv->rps.cur_freq,
>> -			 vlv_gpu_freq(dev_priv, val), val);
>> +			 intel_gpu_freq(dev_priv, val), val);
>>   
>>   	if (val != dev_priv->rps.cur_freq)
>>   		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
>> @@ -3338,7 +3338,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
>>   	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
>>   
>>   	dev_priv->rps.cur_freq = val;
>> -	trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
>> +	trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
>>   }
>>   
>>   static void gen8_disable_rps_interrupts(struct drm_device *dev)
>> @@ -3961,22 +3961,22 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>>   	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
>>   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>>   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>>   			 dev_priv->rps.max_freq);
>>   
>>   	dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
>>   	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>>   			 dev_priv->rps.efficient_freq);
>>   
>>   	dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
>>   	DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
>>   			 dev_priv->rps.rp1_freq);
>>   
>>   	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
>>   	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>>   			 dev_priv->rps.min_freq);
>>   
>>   	/* Preserve min/max settings in case of re-init */
>> @@ -4000,17 +4000,17 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
>>   	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
>>   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>>   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>>   			 dev_priv->rps.max_freq);
>>   
>>   	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
>>   	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>>   			 dev_priv->rps.efficient_freq);
>>   
>>   	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
>>   	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>>   			 dev_priv->rps.min_freq);
>>   
>>   	/* Preserve min/max settings in case of re-init */
>> @@ -4106,11 +4106,11 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>   
>>   	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
>>   	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>>   			 dev_priv->rps.cur_freq);
>>   
>>   	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>>   			 dev_priv->rps.efficient_freq);
>>   
>>   	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
>> @@ -4184,11 +4184,11 @@ static void valleyview_enable_rps(struct drm_device *dev)
>>   
>>   	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
>>   	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>>   			 dev_priv->rps.cur_freq);
>>   
>>   	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
>> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>> +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>>   			 dev_priv->rps.efficient_freq);
>>   
>>   	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
>> @@ -6946,6 +6946,30 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>>   	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
>>   }
>>   
>> +int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
>> +{
>> +	int ret;
>> +
>> +	if (!IS_VALLEYVIEW(dev_priv->dev))
>> +		return -1;
>> +
>> +	ret = vlv_gpu_freq(dev_priv, val);
>> +
>> +	return ret;
>> +}
>> +
>> +int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
>> +{
>> +	int ret;
>> +
>> +	if (!IS_VALLEYVIEW(dev_priv->dev))
>> +		return -1;
>> +
>> +	ret = vlv_freq_opcode(dev_priv, val);
>> +
>> +	return ret;
>> +}
>> +
>>   void intel_pm_setup(struct drm_device *dev)
>>   {
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>> -- 
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic
  2014-07-10  6:28       ` Daniel Vetter
@ 2014-07-11  6:50         ` Deepak S
  0 siblings, 0 replies; 24+ messages in thread
From: Deepak S @ 2014-07-11  6:50 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: intel-gfx


On Thursday 10 July 2014 11:58 AM, Daniel Vetter wrote:
> On Fri, Jul 11, 2014 at 09:56:35AM +0530, Deepak S wrote:
>> On Wednesday 09 July 2014 05:33 PM, Daniel Vetter wrote:
>>> On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepak.s@linux.intel.com wrote:
>>>> From: Deepak S <deepak.s@linux.intel.com>
>>>>
>>>> Since freq/encode conversion formula changes from platform to platform,
>>>> create a generic wrapper function and having platform check inside this
>>>> help to simpilfy adding newer platform freq/opcode conversion.
>>>>
>>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++-----
>>>>   drivers/gpu/drm/i915/i915_drv.h     |  4 +--
>>>>   drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++-------
>>>>   drivers/gpu/drm/i915/intel_pm.c     | 52 +++++++++++++++++++++++++++----------
>>>>   4 files changed, 56 insertions(+), 32 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>>>> index b3b56c4..dd7078d 100644
>>>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>>>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>>>> @@ -1140,14 +1140,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>>>   		val = valleyview_rps_max_freq(dev_priv);
>>>>   		seq_printf(m, "max GPU freq: %d MHz\n",
>>>> -			   vlv_gpu_freq(dev_priv, val));
>>>> +			   intel_gpu_freq(dev_priv, val));
>>> intel_ is a bit too generic a prefix for a function which seems to be only
>>> used on byt+chv. I'd just add a if (IS_CHERRYVIEW) ... else /* vlv code */
>>> to both functions and not extract further.
>>>
>>> Aside: Since marketing stopped using vlv and switched to byt we're using
>>> vlv for code shared by byt and chv and byt_ for byt-only code. Helps a bit
>>> to keep things appart.
>>> -Daniel
>> Ok. Will it be Ok to use "vlv_gpu_freq" and have BYT and CHV check under
>> this function?
> Yeah, that's my idea.
>
>> The reason why i made more generic is it will help us to add conversion
>> logic for future platforms
> We can look at this again when it happpens. With the current code this
> doesn't include desktop rps so the intel_ prefix was a bit confusing.
> -Daniel

Ok. Thanks for the feedback. I will update and send new patch set

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview
  2014-07-10  7:46 ` [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview deepak.s
@ 2014-07-11 14:42   ` Mika Kuoppala
  2014-07-11 15:56     ` Daniel Vetter
  0 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2014-07-11 14:42 UTC (permalink / raw)
  To: deepak.s, intel-gfx

deepak.s@linux.intel.com writes:

> From: Deepak S <deepak.s@linux.intel.com>
>
> Reading RP1 for valleyview to help us enable "pm_rps" i-g-t testcase
> execution.
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d1af641..b8e7afc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3816,6 +3816,17 @@ int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
>  	return rpn;
>  }
>  
> +int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
> +{
> +	u32 val, rp1;
> +
> +	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
> +
> +	rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
> +
> +	return rp1;
> +}
> +
>  int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
>  {
>  	u32 val, rp0;
> @@ -3958,6 +3969,11 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>  			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>  			 dev_priv->rps.efficient_freq);
>  
> +	dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
> +	DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
> +			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
> +			 dev_priv->rps.rp1_freq);
> +
>  	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
>  	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>  			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs
  2014-07-10  7:46 ` [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs deepak.s
@ 2014-07-11 14:44   ` Mika Kuoppala
  2014-07-11 16:00   ` Daniel Vetter
  1 sibling, 0 replies; 24+ messages in thread
From: Mika Kuoppala @ 2014-07-11 14:44 UTC (permalink / raw)
  To: deepak.s, intel-gfx

deepak.s@linux.intel.com writes:

> From: Deepak S <deepak.s@linux.intel.com>
>
> This is useful for userspace utilities to verify and micromanaging the
> increase/decrease frequncy.
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_sysfs.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 86ce39a..b15c8ce 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -461,11 +461,20 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
>  	mutex_unlock(&dev->struct_mutex);
>  
>  	if (attr == &dev_attr_gt_RP0_freq_mhz) {
> -		val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
> +		if (IS_VALLEYVIEW(dev))
> +			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
> +		else
> +			val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
>  	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
> -		val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
> +		if (IS_VALLEYVIEW(dev))
> +			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
> +		else
> +			val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
>  	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
> -		val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
> +		if (IS_VALLEYVIEW(dev))
> +			val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq);
> +		else
> +			val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
>  	} else {
>  		BUG();
>  	}
> @@ -486,6 +495,9 @@ static const struct attribute *vlv_attrs[] = {
>  	&dev_attr_gt_cur_freq_mhz.attr,
>  	&dev_attr_gt_max_freq_mhz.attr,
>  	&dev_attr_gt_min_freq_mhz.attr,
> +	&dev_attr_gt_RP0_freq_mhz.attr,
> +	&dev_attr_gt_RP1_freq_mhz.attr,
> +	&dev_attr_gt_RPn_freq_mhz.attr,
>  	&dev_attr_vlv_rpe_freq_mhz.attr,
>  	NULL,
>  };
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH 4/7] drm/i915: populate mem_freq/cz_clock for chv
  2014-07-10  7:46 ` [PATCH 4/7] drm/i915: populate mem_freq/cz_clock for chv deepak.s
@ 2014-07-11 14:50   ` Mika Kuoppala
  0 siblings, 0 replies; 24+ messages in thread
From: Mika Kuoppala @ 2014-07-11 14:50 UTC (permalink / raw)
  To: deepak.s, intel-gfx

deepak.s@linux.intel.com writes:

> From: Deepak S <deepak.s@linux.intel.com>
>
> We need mem_freq or cz clock for freq/opcode conversion
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_reg.h |  6 ++++++
>  drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++++++++++++++++
>  3 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bce4654..568b39c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -932,6 +932,7 @@ struct intel_gen6_power_mgmt {
>  	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
>  	u8 rp1_freq;		/* "less than" RP0 power/freqency */
>  	u8 rp0_freq;		/* Non-overclocked max frequency. */
> +	u32 cz_freq;
>  
>  	u32 ei_interrupt_count;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 490f031..e533efa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5541,6 +5541,12 @@ enum punit_power_well {
>  						 GEN6_PM_RP_DOWN_THRESHOLD | \
>  						 GEN6_PM_RP_DOWN_TIMEOUT)
>  
> +#define CHV_CZ_CLOCK_FREQ_MODE_200			200
> +#define CHV_CZ_CLOCK_FREQ_MODE_267			267
> +#define CHV_CZ_CLOCK_FREQ_MODE_320			320
> +#define CHV_CZ_CLOCK_FREQ_MODE_333			333
> +#define CHV_CZ_CLOCK_FREQ_MODE_400			400
> +

No need to define these in my opinion as it is 1:1. Just use
the numbers straight.


>  #define GEN7_GT_SCRATCH_BASE			0x4F100
>  #define GEN7_GT_SCRATCH_REG_NUM			8
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9dfebab..6c19ce5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5706,6 +5706,35 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  static void cherryview_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);

s/punit/cck (?)

With the changes mentioned above:
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +	switch ((val >> 2) & 0x7) {
> +	case 0:
> +	case 1:
> +			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
> +			dev_priv->mem_freq = 1600;
> +			break;
> +	case 2:
> +			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
> +			dev_priv->mem_freq = 1600;
> +			break;
> +	case 3:
> +			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
> +			dev_priv->mem_freq = 2000;
> +			break;
> +	case 4:
> +			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
> +			dev_priv->mem_freq = 1600;
> +			break;
> +	case 5:
> +			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
> +			dev_priv->mem_freq = 1600;
> +			break;
> +	}
> +	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>  
>  	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>  
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] drm/i915/chv: Add basic PM interrupt support for CHV
  2014-07-10  7:46 ` [PATCH 6/7] drm/i915/chv: Add basic PM interrupt support for CHV deepak.s
@ 2014-07-11 15:03   ` Mika Kuoppala
  0 siblings, 0 replies; 24+ messages in thread
From: Mika Kuoppala @ 2014-07-11 15:03 UTC (permalink / raw)
  To: deepak.s, intel-gfx

deepak.s@linux.intel.com writes:

> From: Deepak S <deepak.s@linux.intel.com>
>
> Enabled PM interrupt programming for CHV. Re-using gen8 code and extending same for CHV.
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 2 +-
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 38e6de1..ae6246c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1403,7 +1403,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	pm_iir = dev_priv->rps.pm_iir;
>  	dev_priv->rps.pm_iir = 0;
> -	if (IS_BROADWELL(dev_priv->dev))
> +	if (IS_BROADWELL(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))
>  		bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
>  	else {
>  		/* Make sure not to corrupt PMIMR state used by ringbuffer */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6abd05b..7da3719 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3398,6 +3398,8 @@ static void cherryview_disable_rps(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	I915_WRITE(GEN6_RC_CONTROL, 0);
> +
> +	gen8_disable_rps_interrupts(dev);
>  }
>  
>  static void valleyview_disable_rps(struct drm_device *dev)
> @@ -4115,6 +4117,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
>  
>  	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
>  
> +	gen8_enable_rps_interrupts(dev);
> +
>  	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
>  }
>  
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] drm/i915: CHV GPU frequency to opcode functions
  2014-07-12  9:24 ` [PATCH v2 1/3] drm/i915: CHV GPU frequency to opcode functions deepak.s
@ 2014-07-11 15:53   ` Mika Kuoppala
  2014-07-11 15:58   ` Daniel Vetter
  1 sibling, 0 replies; 24+ messages in thread
From: Mika Kuoppala @ 2014-07-11 15:53 UTC (permalink / raw)
  To: deepak.s, intel-gfx

deepak.s@linux.intel.com writes:

> From: Deepak S <deepak.s@linux.intel.com>
>
> Adding chv specific fre/encode conversion.
>
> v2: Remove generic function and platform check (Daniel)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 78 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 76 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6892421..f673e1b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6931,7 +6931,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>  	return 0;
>  }
>  
> -int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
> +int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
>  {
>  	int div;
>  
> @@ -6953,7 +6953,7 @@ int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
>  	return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
>  }
>  
> -int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
> +int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
>  {
>  	int mul;
>  
> @@ -6975,6 +6975,80 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>  	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
>  }
>  
> +int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
> +{
> +	int div, freq;
> +
> +	switch (dev_priv->rps.cz_freq) {
> +	case 200:
> +		div = 5;
> +		break;
> +	case 267:
> +		div = 6;
> +		break;
> +	case 320:
> +	case 333:
> +	case 400:
> +		div = 8;
> +		break;
> +	default:
> +		return -1;
> +	}
> +
> +	freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
> +
> +	return freq;
> +}
> +
> +int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
> +{
> +	int mul, opcode;
> +
> +	switch (dev_priv->rps.cz_freq) {
> +	case 200:
> +		mul = 5;
> +		break;
> +	case 267:
> +		mul = 6;
> +		break;
> +	case 320:
> +	case 333:
> +	case 400:
> +		mul = 8;
> +		break;
> +	default:
> +		return -1;
> +	}
> +
> +	opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
> +
> +	return opcode;
> +}
> +
> +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
> +{
> +	int ret = -1;
> +
> +	if (IS_CHERRYVIEW(dev_priv->dev))
> +		ret = chv_gpu_freq(dev_priv, val);
> +	else if (IS_VALLEYVIEW(dev_priv->dev))
> +		ret = byt_gpu_freq(dev_priv, val);
> +
> +	return ret;
> +}
> +
> +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
> +{
> +	int ret = -1;
> +
> +	if (IS_CHERRYVIEW(dev_priv->dev))
> +		ret = chv_freq_opcode(dev_priv, val);
> +	else if (IS_VALLEYVIEW(dev_priv->dev))
> +		ret = byt_freq_opcode(dev_priv, val);
> +
> +	return ret;
> +}
> +
>  void intel_pm_setup(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview
  2014-07-11 14:42   ` Mika Kuoppala
@ 2014-07-11 15:56     ` Daniel Vetter
  0 siblings, 0 replies; 24+ messages in thread
From: Daniel Vetter @ 2014-07-11 15:56 UTC (permalink / raw)
  To: Mika Kuoppala; +Cc: intel-gfx

On Fri, Jul 11, 2014 at 05:42:48PM +0300, Mika Kuoppala wrote:
> deepak.s@linux.intel.com writes:
> 
> > From: Deepak S <deepak.s@linux.intel.com>
> >
> > Reading RP1 for valleyview to help us enable "pm_rps" i-g-t testcase
> > execution.
> >
> > Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index d1af641..b8e7afc 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3816,6 +3816,17 @@ int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> >  	return rpn;
> >  }
> >  
> > +int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)

Missing static here. Fixed and queued for -next, thanks for the patch.
-Daniel
> > +{
> > +	u32 val, rp1;
> > +
> > +	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
> > +
> > +	rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
> > +
> > +	return rp1;
> > +}
> > +
> >  int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
> >  {
> >  	u32 val, rp0;
> > @@ -3958,6 +3969,11 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
> >  			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> >  			 dev_priv->rps.efficient_freq);
> >  
> > +	dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
> > +	DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
> > +			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
> > +			 dev_priv->rps.rp1_freq);
> > +
> >  	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
> >  	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> >  			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> > -- 
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/3] drm/i915: CHV GPU frequency to opcode functions
  2014-07-12  9:24 ` [PATCH v2 1/3] drm/i915: CHV GPU frequency to opcode functions deepak.s
  2014-07-11 15:53   ` Mika Kuoppala
@ 2014-07-11 15:58   ` Daniel Vetter
  1 sibling, 0 replies; 24+ messages in thread
From: Daniel Vetter @ 2014-07-11 15:58 UTC (permalink / raw)
  To: deepak.s; +Cc: intel-gfx

On Sat, Jul 12, 2014 at 02:54:33PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
> 
> Adding chv specific fre/encode conversion.
> 
> v2: Remove generic function and platform check (Daniel)
> 
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>

When resubmitting patches into an existing patchbomb thread please use
--in-reply-to the old patch this new one here replaces. Otherwise I'll
have a good chance to pick up patches out of order or the wrong ones.

Thanks, Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 78 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 76 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6892421..f673e1b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6931,7 +6931,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>  	return 0;
>  }
>  
> -int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
> +int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
>  {
>  	int div;
>  
> @@ -6953,7 +6953,7 @@ int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
>  	return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
>  }
>  
> -int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
> +int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
>  {
>  	int mul;
>  
> @@ -6975,6 +6975,80 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>  	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
>  }
>  
> +int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
> +{
> +	int div, freq;
> +
> +	switch (dev_priv->rps.cz_freq) {
> +	case 200:
> +		div = 5;
> +		break;
> +	case 267:
> +		div = 6;
> +		break;
> +	case 320:
> +	case 333:
> +	case 400:
> +		div = 8;
> +		break;
> +	default:
> +		return -1;
> +	}
> +
> +	freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
> +
> +	return freq;
> +}
> +
> +int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
> +{
> +	int mul, opcode;
> +
> +	switch (dev_priv->rps.cz_freq) {
> +	case 200:
> +		mul = 5;
> +		break;
> +	case 267:
> +		mul = 6;
> +		break;
> +	case 320:
> +	case 333:
> +	case 400:
> +		mul = 8;
> +		break;
> +	default:
> +		return -1;
> +	}
> +
> +	opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
> +
> +	return opcode;
> +}
> +
> +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
> +{
> +	int ret = -1;
> +
> +	if (IS_CHERRYVIEW(dev_priv->dev))
> +		ret = chv_gpu_freq(dev_priv, val);
> +	else if (IS_VALLEYVIEW(dev_priv->dev))
> +		ret = byt_gpu_freq(dev_priv, val);
> +
> +	return ret;
> +}
> +
> +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
> +{
> +	int ret = -1;
> +
> +	if (IS_CHERRYVIEW(dev_priv->dev))
> +		ret = chv_freq_opcode(dev_priv, val);
> +	else if (IS_VALLEYVIEW(dev_priv->dev))
> +		ret = byt_freq_opcode(dev_priv, val);
> +
> +	return ret;
> +}
> +
>  void intel_pm_setup(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs
  2014-07-10  7:46 ` [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs deepak.s
  2014-07-11 14:44   ` Mika Kuoppala
@ 2014-07-11 16:00   ` Daniel Vetter
  1 sibling, 0 replies; 24+ messages in thread
From: Daniel Vetter @ 2014-07-11 16:00 UTC (permalink / raw)
  To: deepak.s; +Cc: intel-gfx

On Thu, Jul 10, 2014 at 01:16:22PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
> 
> This is useful for userspace utilities to verify and micromanaging the
> increase/decrease frequncy.
> 
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_sysfs.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 86ce39a..b15c8ce 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -461,11 +461,20 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
>  	mutex_unlock(&dev->struct_mutex);
>  
>  	if (attr == &dev_attr_gt_RP0_freq_mhz) {
> -		val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
> +		if (IS_VALLEYVIEW(dev))
> +			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
> +		else
> +			val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
>  	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
> -		val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
> +		if (IS_VALLEYVIEW(dev))
> +			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
> +		else
> +			val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
>  	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
> -		val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
> +		if (IS_VALLEYVIEW(dev))
> +			val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq);
> +		else
> +			val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
>  	} else {
>  		BUG();
>  	}
> @@ -486,6 +495,9 @@ static const struct attribute *vlv_attrs[] = {
>  	&dev_attr_gt_cur_freq_mhz.attr,
>  	&dev_attr_gt_max_freq_mhz.attr,
>  	&dev_attr_gt_min_freq_mhz.attr,
> +	&dev_attr_gt_RP0_freq_mhz.attr,
> +	&dev_attr_gt_RP1_freq_mhz.attr,
> +	&dev_attr_gt_RPn_freq_mhz.attr,
>  	&dev_attr_vlv_rpe_freq_mhz.attr,
>  	NULL,
>  };

This now exactly matches gen6_attrs, so I've killed it while applying.
-Daniel

> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2] drm/i915: Add RP1 render P state thresholds in CHV
  2014-07-12 13:16 ` [PATCH v2] drm/i915: Add RP1 render P state thresholds in CHV deepak.s
@ 2014-07-11 16:07   ` Mika Kuoppala
  2014-07-11 16:22     ` Daniel Vetter
  0 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2014-07-11 16:07 UTC (permalink / raw)
  To: deepak.s, intel-gfx

deepak.s@linux.intel.com writes:

> From: Deepak S <deepak.s@linux.intel.com>
>
> This is useful for userspace utilities to verify and micromanaging
> the increase/decrease frequncy.
>
> v2: Use vlv_gpu_freq to get freq (Deepak)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3fb65e9..225b6cb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3809,6 +3809,16 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
>  	return rpe;
>  }
>  
> +int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
^^static
Daniel said he will add it, missing in other patches too.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> +{
> +	u32 val, rp1;
> +
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> +
> +	return rp1;
> +}
> +
>  int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
>  {
>  	u32 val, rpn;
> @@ -4010,6 +4020,11 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
>  			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>  			 dev_priv->rps.efficient_freq);
>  
> +	dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
> +	DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
> +			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
> +			 dev_priv->rps.rp1_freq);
> +
>  	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
>  	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>  			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v2] drm/i915: Add RP1 render P state thresholds in CHV
  2014-07-11 16:07   ` Mika Kuoppala
@ 2014-07-11 16:22     ` Daniel Vetter
  0 siblings, 0 replies; 24+ messages in thread
From: Daniel Vetter @ 2014-07-11 16:22 UTC (permalink / raw)
  To: Mika Kuoppala; +Cc: intel-gfx

On Fri, Jul 11, 2014 at 07:07:33PM +0300, Mika Kuoppala wrote:
> deepak.s@linux.intel.com writes:
> 
> > From: Deepak S <deepak.s@linux.intel.com>
> >
> > This is useful for userspace utilities to verify and micromanaging
> > the increase/decrease frequncy.
> >
> > v2: Use vlv_gpu_freq to get freq (Deepak)
> >
> > Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 3fb65e9..225b6cb 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3809,6 +3809,16 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> >  	return rpe;
> >  }
> >  
> > +int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
> ^^static
> Daniel said he will add it, missing in other patches too.
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Ok, I've stitched it together and merged to dinq, thanks.
-Daniel

> 
> > +{
> > +	u32 val, rp1;
> > +
> > +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > +	rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> > +
> > +	return rp1;
> > +}
> > +
> >  int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> >  {
> >  	u32 val, rpn;
> > @@ -4010,6 +4020,11 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
> >  			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> >  			 dev_priv->rps.efficient_freq);
> >  
> > +	dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
> > +	DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
> > +			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
> > +			 dev_priv->rps.rp1_freq);
> > +
> >  	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> >  	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> >  			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> > -- 
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v2 1/3] drm/i915: CHV GPU frequency to opcode functions
  2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
                   ` (6 preceding siblings ...)
  2014-07-10  7:46 ` [PATCH 7/7] drm/i915: Add RP1 render P state thresholds in CHV deepak.s
@ 2014-07-12  9:24 ` deepak.s
  2014-07-11 15:53   ` Mika Kuoppala
  2014-07-11 15:58   ` Daniel Vetter
  2014-07-12 13:16 ` [PATCH v2] drm/i915: Add RP1 render P state thresholds in CHV deepak.s
  8 siblings, 2 replies; 24+ messages in thread
From: deepak.s @ 2014-07-12  9:24 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

Adding chv specific fre/encode conversion.

v2: Remove generic function and platform check (Daniel)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 78 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 76 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6892421..f673e1b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6931,7 +6931,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
 	return 0;
 }
 
-int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
+int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
 {
 	int div;
 
@@ -6953,7 +6953,7 @@ int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
 	return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
 }
 
-int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
+int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
 	int mul;
 
@@ -6975,6 +6975,80 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
 }
 
+int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
+{
+	int div, freq;
+
+	switch (dev_priv->rps.cz_freq) {
+	case 200:
+		div = 5;
+		break;
+	case 267:
+		div = 6;
+		break;
+	case 320:
+	case 333:
+	case 400:
+		div = 8;
+		break;
+	default:
+		return -1;
+	}
+
+	freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
+
+	return freq;
+}
+
+int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
+{
+	int mul, opcode;
+
+	switch (dev_priv->rps.cz_freq) {
+	case 200:
+		mul = 5;
+		break;
+	case 267:
+		mul = 6;
+		break;
+	case 320:
+	case 333:
+	case 400:
+		mul = 8;
+		break;
+	default:
+		return -1;
+	}
+
+	opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
+
+	return opcode;
+}
+
+int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
+{
+	int ret = -1;
+
+	if (IS_CHERRYVIEW(dev_priv->dev))
+		ret = chv_gpu_freq(dev_priv, val);
+	else if (IS_VALLEYVIEW(dev_priv->dev))
+		ret = byt_gpu_freq(dev_priv, val);
+
+	return ret;
+}
+
+int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
+{
+	int ret = -1;
+
+	if (IS_CHERRYVIEW(dev_priv->dev))
+		ret = chv_freq_opcode(dev_priv, val);
+	else if (IS_VALLEYVIEW(dev_priv->dev))
+		ret = byt_freq_opcode(dev_priv, val);
+
+	return ret;
+}
+
 void intel_pm_setup(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v2] drm/i915: Add RP1 render P state thresholds in CHV
  2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
                   ` (7 preceding siblings ...)
  2014-07-12  9:24 ` [PATCH v2 1/3] drm/i915: CHV GPU frequency to opcode functions deepak.s
@ 2014-07-12 13:16 ` deepak.s
  2014-07-11 16:07   ` Mika Kuoppala
  8 siblings, 1 reply; 24+ messages in thread
From: deepak.s @ 2014-07-12 13:16 UTC (permalink / raw)
  To: intel-gfx

From: Deepak S <deepak.s@linux.intel.com>

This is useful for userspace utilities to verify and micromanaging
the increase/decrease frequncy.

v2: Use vlv_gpu_freq to get freq (Deepak)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3fb65e9..225b6cb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3809,6 +3809,16 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
 	return rpe;
 }
 
+int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp1;
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+
+	return rp1;
+}
+
 int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rpn;
@@ -4010,6 +4020,11 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
 			 dev_priv->rps.efficient_freq);
 
+	dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
+			 dev_priv->rps.rp1_freq);
+
 	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
 	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
end of thread, other threads:[~2014-07-11 16:22 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
2014-07-10  7:46 ` [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview deepak.s
2014-07-11 14:42   ` Mika Kuoppala
2014-07-11 15:56     ` Daniel Vetter
2014-07-10  7:46 ` [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs deepak.s
2014-07-11 14:44   ` Mika Kuoppala
2014-07-11 16:00   ` Daniel Vetter
2014-07-10  7:46 ` [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic deepak.s
2014-07-09 12:03   ` Daniel Vetter
2014-07-11  4:26     ` Deepak S
2014-07-10  6:28       ` Daniel Vetter
2014-07-11  6:50         ` Deepak S
2014-07-10  7:46 ` [PATCH 4/7] drm/i915: populate mem_freq/cz_clock for chv deepak.s
2014-07-11 14:50   ` Mika Kuoppala
2014-07-10  7:46 ` [PATCH 5/7] drm/i915: CHV GPU frequency to opcode functions deepak.s
2014-07-10  7:46 ` [PATCH 6/7] drm/i915/chv: Add basic PM interrupt support for CHV deepak.s
2014-07-11 15:03   ` Mika Kuoppala
2014-07-10  7:46 ` [PATCH 7/7] drm/i915: Add RP1 render P state thresholds in CHV deepak.s
2014-07-12  9:24 ` [PATCH v2 1/3] drm/i915: CHV GPU frequency to opcode functions deepak.s
2014-07-11 15:53   ` Mika Kuoppala
2014-07-11 15:58   ` Daniel Vetter
2014-07-12 13:16 ` [PATCH v2] drm/i915: Add RP1 render P state thresholds in CHV deepak.s
2014-07-11 16:07   ` Mika Kuoppala
2014-07-11 16:22     ` Daniel Vetter

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