[RFC 0/8] Audio clocks for sun[457]i, SoC revision detection

[RFC 0/8] Audio clocks for sun[457]i, SoC revision detection

[Emilio López]

Hi everyone,

This series adds support for PLL2 on A10 rev B and higher, A10S, A13 
and A20. It also includes support for the codec clock as well as
module 1 clocks, used in the audio blocks. There's also two patches
fixing sparse warnings on the driver.

I'm sending this as RFC as this does not support the A10 rev A PLL2
clock. It seems from the Allwinner code that rev A has a different
register layout, and is programmed with different values. Unfortunately
there's no mention of this on the User Manual, so I'm left to guess
for the most part.

The clock code is not the only part in where rev A is special cased;
there's some register writes just for it on the analog audio driver
as well, so we probably need a way to support this in a generic way.

So, how should we proceed with this? Here are some ideas:
  * Make different device trees with different compatibles. Pros:
    not much extra code. Cons: we don't know the SoC revision on
    devices and/or they may change during the product lifecycle.
  * Use different compatibles and change them on U-Boot. Pros: it
    keeps Linux simple. Cons: dependency on a newer bootloader.
  * Use different compatibles and change them on early boot.
    Pros: compatibility with existing bootloaders. Cons: Need
    code in Linux to fixup the DT
  * Have a function "int sunxi_soc_revision(void)" that drivers
    can use to check which SoC revision they're running on.
    Pros: no DT fixup. Cons: ugly and less portable if the driver
    ever needs to run on a non-sunxi platform.
  * <your idea here>

I'd like to hear everyone's thoughts on this. From what I've seen
around on LAKML, it seems the last option is the one in widest use, but
I'd appreciate a confirmation. If this is the way forward,
where should the code live in? The SoC detection is done by
reading a register on the timer block on sun4i, and SID on sun5i.

As usual, all comments on the code are welcome as well.

Thanks!

Emilio

Emilio L?pez (8):
  clk: sunxi: PLL2 support for sun4i, sun5i and sun7i
  clk: sunxi: codec clock support
  clk: sunxi: mod1 clock support
  clk: sunxi: add __iomem markings to MMIO pointers
  clk: sunxi: staticize structures and arrays
  ARM: sunxi: Add PLL2 support
  ARM: sunxi: Add codec clock support
  ARM: sun7i: Add mod1 clock nodes

 arch/arm/boot/dts/sun4i-a10.dtsi         |  16 ++
 arch/arm/boot/dts/sun5i-a10s.dtsi        |  16 ++
 arch/arm/boot/dts/sun5i-a13.dtsi         |  16 ++
 arch/arm/boot/dts/sun7i-a20.dtsi         |  55 +++++++
 drivers/clk/sunxi/Makefile               |   3 +
 drivers/clk/sunxi/clk-a10-codec.c        |  41 +++++
 drivers/clk/sunxi/clk-a10-mod1.c         |  69 +++++++++
 drivers/clk/sunxi/clk-a10-pll2.c         | 249 +++++++++++++++++++++++++++++++
 drivers/clk/sunxi/clk-a20-gmac.c         |   2 +-
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c |   2 +-
 drivers/clk/sunxi/clk-sun6i-apb0.c       |   2 +-
 drivers/clk/sunxi/clk-sun6i-ar100.c      |   4 +-
 drivers/clk/sunxi/clk-sun8i-apb0.c       |   2 +-
 drivers/clk/sunxi/clk-sunxi.c            |  10 +-
 14 files changed, 476 insertions(+), 11 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-a10-codec.c
 create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c
 create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c

-- 
2.0.3

[RFC 1/8] clk: sunxi: PLL2 support for sun4i, sun5i and sun7i

[Emilio López]

This patch adds support for PLL2 and derivates on A10 revision B and
higher, as well as on sun5i and sun7i SoCs. As this PLL is only used for
audio and requires good accuracy, we only support two known good rates.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
 drivers/clk/sunxi/Makefile       |   1 +
 drivers/clk/sunxi/clk-a10-pll2.c | 249 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 250 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 6850cba..dcd5709 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -4,6 +4,7 @@
 
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
+obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c
new file mode 100644
index 0000000..bdbf1e9
--- /dev/null
+++ b/drivers/clk/sunxi/clk-a10-pll2.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright 2013 Emilio L?pez
+ *
+ * Emilio L?pez <emilio@elopez.com.ar>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define SUN4I_PLL2_ENABLE		31
+#define SUN4I_PLL2_POST_DIV		26
+#define SUN4I_PLL2_POST_DIV_MASK	0xF
+#define SUN4I_PLL2_N			8
+#define SUN4I_PLL2_N_MASK		0x7F
+#define SUN4I_PLL2_PRE_DIV		0
+#define SUN4I_PLL2_PRE_DIV_MASK		0x1F
+
+#define SUN4I_PLL2_OUTPUTS		4
+
+struct sun4i_pll2_clk {
+	struct clk_hw hw;
+	void __iomem *reg;
+};
+
+static inline struct sun4i_pll2_clk *to_sun4i_pll2_clk(struct clk_hw *hw)
+{
+	return container_of(hw, struct sun4i_pll2_clk, hw);
+}
+
+static unsigned long sun4i_pll2_1x_recalc_rate(struct clk_hw *hw,
+					    unsigned long parent_rate)
+{
+	struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+	int n, prediv, postdiv;
+
+	u32 val = readl(clk->reg);
+	n = (val >> SUN4I_PLL2_N) & SUN4I_PLL2_N_MASK;
+	prediv = (val >> SUN4I_PLL2_PRE_DIV) & SUN4I_PLL2_PRE_DIV_MASK;
+	postdiv = (val >> SUN4I_PLL2_POST_DIV) & SUN4I_PLL2_POST_DIV_MASK;
+
+	/* 0 is a special case and means 1 */
+	if (n == 0)
+		n = 1;
+	if (prediv == 0)
+		prediv = 1;
+	if (postdiv == 0)
+		postdiv = 1;
+
+	return ((parent_rate * n) / prediv) / postdiv;
+}
+
+static unsigned long sun4i_pll2_8x_recalc_rate(struct clk_hw *hw,
+					       unsigned long parent_rate)
+{
+	struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+	int n, prediv;
+
+	u32 val = readl(clk->reg);
+	n = (val >> SUN4I_PLL2_N) & SUN4I_PLL2_N_MASK;
+	prediv = (val >> SUN4I_PLL2_PRE_DIV) & SUN4I_PLL2_PRE_DIV_MASK;
+
+	/* 0 is a special case and means 1 */
+	if (n == 0)
+		n = 1;
+	if (prediv == 0)
+		prediv = 1;
+
+	return ((parent_rate * 2 * n) / prediv);
+}
+
+static unsigned long sun4i_pll2_4x_recalc_rate(struct clk_hw *hw,
+					       unsigned long parent_rate)
+{
+	return sun4i_pll2_8x_recalc_rate(hw, parent_rate / 2);
+}
+
+static unsigned long sun4i_pll2_2x_recalc_rate(struct clk_hw *hw,
+					       unsigned long parent_rate)
+{
+	return sun4i_pll2_8x_recalc_rate(hw, parent_rate / 4);
+}
+
+static long sun4i_pll2_1x_round_rate(struct clk_hw *hw, unsigned long rate,
+				     unsigned long *parent_rate)
+{
+	/*
+	 * There is only two interesting rates for the audio PLL, the
+	 * rest isn't really usable due to accuracy concerns. Therefore,
+	 * we specifically round to those rates here
+	 */
+	if (rate < 22579200)
+		return -EINVAL;
+
+	if (rate >= 22579200 && rate < 24576000)
+		return 22579200;
+
+	return 24576000;
+}
+
+static long sun4i_pll2_8x_round_rate(struct clk_hw *hw, unsigned long rate,
+				     unsigned long *parent_rate)
+{
+	/*
+	 * We should account for the postdiv that we're undoing on PLL2x8,
+	 * which is always 4 in the usable configurations. The division
+	 * by two is done because PLL2x8 also doubles the rate
+	 */
+	*parent_rate = (rate * 4) / 2;
+
+	return rate;
+}
+
+static long sun4i_pll2_4x_round_rate(struct clk_hw *hw, unsigned long rate,
+				     unsigned long *parent_rate)
+{
+	/* PLL2x4 * 2 = PLL2x8 */
+	return sun4i_pll2_8x_round_rate(hw, rate * 2, parent_rate);
+}
+
+static long sun4i_pll2_2x_round_rate(struct clk_hw *hw, unsigned long rate,
+				     unsigned long *parent_rate)
+{
+	/* PLL2x2 * 4 = PLL2x8 */
+	return sun4i_pll2_8x_round_rate(hw, rate * 4, parent_rate);
+}
+
+static int sun4i_pll2_set_rate(struct clk_hw *hw, unsigned long rate,
+			       unsigned long parent_rate)
+{
+	struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+	u32 val = readl(clk->reg);
+
+	val &= ~(SUN4I_PLL2_N_MASK << SUN4I_PLL2_N);
+	val &= ~(SUN4I_PLL2_PRE_DIV_MASK << SUN4I_PLL2_PRE_DIV);
+	val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV);
+
+	val |= (21 << SUN4I_PLL2_PRE_DIV) | (4 << SUN4I_PLL2_POST_DIV);
+
+	if (rate == 22579200)
+		val |= (79 << SUN4I_PLL2_N);
+	else if (rate == 24576000)
+		val |= (86 << SUN4I_PLL2_N);
+	else
+		return -EINVAL;
+
+	writel(val, clk->reg);
+
+	return 0;
+}
+
+static struct clk_ops sun4i_pll2_ops_1x = {
+	.recalc_rate = sun4i_pll2_1x_recalc_rate,
+	.round_rate = sun4i_pll2_1x_round_rate,
+	.set_rate = sun4i_pll2_set_rate,
+};
+
+static struct clk_ops sun4i_pll2_ops_2x = {
+	.recalc_rate = sun4i_pll2_2x_recalc_rate,
+	.round_rate = sun4i_pll2_2x_round_rate,
+};
+
+static struct clk_ops sun4i_pll2_ops_4x = {
+	.recalc_rate = sun4i_pll2_4x_recalc_rate,
+	.round_rate = sun4i_pll2_4x_round_rate,
+};
+
+static struct clk_ops sun4i_pll2_ops_8x = {
+	.recalc_rate = sun4i_pll2_8x_recalc_rate,
+	.round_rate = sun4i_pll2_8x_round_rate,
+};
+
+static void __init sun4i_pll2_setup(struct device_node *np)
+{
+	const char *clk_name = np->name, *parent;
+	struct clk_onecell_data *clk_data;
+	struct sun4i_pll2_clk *pll2;
+	struct clk_gate *gate;
+	struct clk **clks;
+	void __iomem *reg;
+
+	pll2 = kzalloc(sizeof(*pll2), GFP_KERNEL);
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+	clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
+	if (!pll2 || !gate || !clk_data || !clks)
+		goto free_mem;
+
+	reg = of_iomap(np, 0);
+	parent = of_clk_get_parent_name(np, 0);
+	of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+
+	pll2->reg = reg;
+	gate->reg = reg;
+	gate->bit_idx = SUN4I_PLL2_ENABLE;
+
+	/* PLL2, also known as PLL2x1 */
+	of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+	clks[0] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
+					 &pll2->hw, &sun4i_pll2_ops_1x,
+					 &gate->hw, &clk_gate_ops, 0);
+	WARN_ON(IS_ERR(clks[0]));
+	parent = clk_name;
+
+	/* PLL2x2, 1/4 the rate of PLL2x8 */
+	of_property_read_string_index(np, "clock-output-names", 1, &clk_name);
+	clks[1] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
+					 &pll2->hw, &sun4i_pll2_ops_2x,
+					 NULL, NULL, CLK_SET_RATE_PARENT);
+	WARN_ON(IS_ERR(clks[1]));
+
+	/* PLL2x4, 1/2 the rate of PLL2x8 */
+	of_property_read_string_index(np, "clock-output-names", 2, &clk_name);
+	clks[2] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
+					 &pll2->hw, &sun4i_pll2_ops_4x,
+					 NULL, NULL, CLK_SET_RATE_PARENT);
+	WARN_ON(IS_ERR(clks[2]));
+
+	/* PLL2x8, double of PLL2 without the post divisor */
+	of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
+	clks[3] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
+					 &pll2->hw, &sun4i_pll2_ops_8x,
+					 NULL, NULL, CLK_SET_RATE_PARENT);
+	WARN_ON(IS_ERR(clks[3]));
+
+	clk_data->clks = clks;
+	clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
+	of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+
+	return;
+
+free_mem:
+	kfree(pll2);
+	kfree(gate);
+	kfree(clk_data);
+	kfree(clks);
+}
+CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-b-pll2-clk", sun4i_pll2_setup);
-- 
2.0.3

[RFC 2/8] clk: sunxi: codec clock support

[Emilio López]

The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as
parent.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
 drivers/clk/sunxi/Makefile        |  1 +
 drivers/clk/sunxi/clk-a10-codec.c | 41 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-codec.c

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index dcd5709..a7a96f8 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-y += clk-sunxi.o clk-factors.o
+obj-y += clk-a10-codec.o
 obj-y += clk-a10-hosc.o
 obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
diff --git a/drivers/clk/sunxi/clk-a10-codec.c b/drivers/clk/sunxi/clk-a10-codec.c
new file mode 100644
index 0000000..c70acbf
--- /dev/null
+++ b/drivers/clk/sunxi/clk-a10-codec.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2013 Emilio L?pez
+ *
+ * Emilio L?pez <emilio@elopez.com.ar>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SUN4I_CODEC_GATE	31
+
+static void __init sun4i_codec_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name, *parent_name;
+	void __iomem *reg;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	parent_name = of_clk_get_parent_name(node, 0);
+	reg = of_iomap(node, 0);
+
+	clk = clk_register_gate(NULL, clk_name, parent_name,
+				CLK_SET_RATE_PARENT, reg,
+				SUN4I_CODEC_GATE, 0, NULL);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(sun4i_codec, "allwinner,sun4i-a10-codec-clk", sun4i_codec_clk_setup);
-- 
2.0.3

[RFC 3/8] clk: sunxi: mod1 clock support

[Emilio López]

The module 1 type of clocks consist of a gate and a mux and are used on
the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
SPDIF. This commit adds support for them on the sunxi clock driver.

Not-signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---

As I have no clients for these clocks, this is untested. It would be 
great to get an ack from the guys working on IIS or SPDIF

 drivers/clk/sunxi/Makefile       |  1 +
 drivers/clk/sunxi/clk-a10-mod1.c | 69 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index a7a96f8..75d113d 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -5,6 +5,7 @@
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-codec.o
 obj-y += clk-a10-hosc.o
+obj-y += clk-a10-mod1.o
 obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 
diff --git a/drivers/clk/sunxi/clk-a10-mod1.c b/drivers/clk/sunxi/clk-a10-mod1.c
new file mode 100644
index 0000000..1357641
--- /dev/null
+++ b/drivers/clk/sunxi/clk-a10-mod1.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2013 Emilio L?pez
+ *
+ * Emilio L?pez <emilio@elopez.com.ar>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+static DEFINE_SPINLOCK(mod1_lock);
+
+#define SUN4I_MOD1_ENABLE	31
+#define SUN4I_MOD1_MUX		16
+#define SUN4I_MOD1_MUX_WIDTH	2
+#define SUN4I_MOD1_MAX_PARENTS	4
+
+static void __init sun4i_mod1_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_mux *mux;
+	struct clk_gate *gate;
+	const char *parents[4];
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	int i = 0;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!mux || !gate) {
+		kfree(mux);
+		kfree(gate);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	reg = of_iomap(node, 0);
+
+	while (i < SUN4I_MOD1_MAX_PARENTS &&
+	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+
+	gate->reg = reg;
+	gate->bit_idx = SUN4I_MOD1_ENABLE;
+	gate->lock = &mod1_lock;
+	mux->reg = reg;
+	mux->shift = SUN4I_MOD1_MUX;
+	mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
+	mux->lock = &mod1_lock;
+
+	clk = clk_register_composite(NULL, clk_name, parents, i,
+				     &mux->hw, &clk_mux_ops,
+				     NULL, NULL,
+				     &gate->hw, &clk_gate_ops, 0);
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk", sun4i_mod1_clk_setup);
-- 
2.0.3

[RFC 4/8] clk: sunxi: add __iomem markings to MMIO pointers

[Emilio López]

This commit adds __iomem thoughout the sunxi clock driver, in places
where it was ommited. This cleans most of the sparse warnings we
are getting here.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---

These are just non-critical fixes, they can wait until the next release
if desired, although I feel they're trivial enough to go on -rc1 as well.

 drivers/clk/sunxi/clk-a20-gmac.c |  2 +-
 drivers/clk/sunxi/clk-sunxi.c    | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c
index 633ddc4..5296fd6 100644
--- a/drivers/clk/sunxi/clk-a20-gmac.c
+++ b/drivers/clk/sunxi/clk-a20-gmac.c
@@ -60,7 +60,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
 	struct clk_gate *gate;
 	const char *clk_name = node->name;
 	const char *parents[SUN7I_A20_GMAC_PARENTS];
-	void *reg;
+	void __iomem *reg;
 
 	if (of_property_read_string(node, "clock-output-names", &clk_name))
 		return;
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 8975972..b654b7b 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -593,7 +593,7 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 	struct clk_hw *mux_hw = NULL;
 	const char *clk_name = node->name;
 	const char *parents[SUNXI_MAX_PARENTS];
-	void *reg;
+	void __iomem *reg;
 	int i = 0;
 
 	reg = of_iomap(node, 0);
@@ -698,7 +698,7 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
 	struct clk *clk;
 	const char *clk_name = node->name;
 	const char *parents[SUNXI_MAX_PARENTS];
-	void *reg;
+	void __iomem *reg;
 	int i = 0;
 
 	reg = of_iomap(node, 0);
@@ -780,7 +780,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
 	struct clk *clk;
 	const char *clk_name = node->name;
 	const char *clk_parent;
-	void *reg;
+	void __iomem *reg;
 
 	reg = of_iomap(node, 0);
 
@@ -962,7 +962,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
 	struct gates_reset_data *reset_data;
 	const char *clk_parent;
 	const char *clk_name;
-	void *reg;
+	void __iomem *reg;
 	int qty;
 	int i = 0;
 	int j = 0;
@@ -1084,7 +1084,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 	struct clk_gate *gate = NULL;
 	struct clk_fixed_factor *fix_factor;
 	struct clk_divider *divider;
-	void *reg;
+	void __iomem *reg;
 	int i = 0;
 	int flags, clkflags;
 
-- 
2.0.3

[RFC 5/8] clk: sunxi: staticize structures and arrays

[Emilio López]

There are some structs and arrays on the driver that are not used
anywhere else. Let's mark them as static.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---

These are just non-critical fixes, they can wait until the next release
if desired, although I feel they're trivial enough to go on -rc1 as well.

 drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 2 +-
 drivers/clk/sunxi/clk-sun6i-apb0.c       | 2 +-
 drivers/clk/sunxi/clk-sun6i-ar100.c      | 4 ++--
 drivers/clk/sunxi/clk-sun8i-apb0.c       | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index ef5e419..e10d052 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -29,7 +29,7 @@ static const struct gates_data sun8i_a23_apb0_gates __initconst = {
 	.mask = {0x5D},
 };
 
-const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
+static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
 	{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
 	{ /* sentinel */ }
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0.c b/drivers/clk/sunxi/clk-sun6i-apb0.c
index 11f17c3..1fa2337 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0.c
@@ -57,7 +57,7 @@ static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev)
 	return of_clk_add_provider(np, of_clk_src_simple_get, clk);
 }
 
-const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
+static const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-apb0-clk" },
 	{ /* sentinel */ }
 };
diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c
index f73cc05..eca8ca0 100644
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -160,7 +160,7 @@ static int ar100_set_rate(struct clk_hw *hw, unsigned long rate,
 	return 0;
 }
 
-struct clk_ops ar100_ops = {
+static struct clk_ops ar100_ops = {
 	.recalc_rate = ar100_recalc_rate,
 	.determine_rate = ar100_determine_rate,
 	.set_parent = ar100_set_parent,
@@ -213,7 +213,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
 	return of_clk_add_provider(np, of_clk_src_simple_get, clk);
 }
 
-const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
+static const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-ar100-clk" },
 	{ /* sentinel */ }
 };
diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c b/drivers/clk/sunxi/clk-sun8i-apb0.c
index 196a499..1f5ba9b 100644
--- a/drivers/clk/sunxi/clk-sun8i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -48,7 +48,7 @@ static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
 	return of_clk_add_provider(np, of_clk_src_simple_get, clk);
 }
 
-const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {
+static const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {
 	{ .compatible = "allwinner,sun8i-a23-apb0-clk" },
 	{ /* sentinel */ }
 };
-- 
2.0.3

[RFC 6/8] ARM: sunxi: Add PLL2 support

[Emilio López]

This commit adds the PLL2 definition to the sun4i, sun5i and sun7i
device trees. PLL2 is used to clock audio devices.

Not-signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---

Note that there is no handling of A10 rev A here, this should not go 
in as-is.

 arch/arm/boot/dts/sun4i-a10.dtsi  | 8 ++++++++
 arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi  | 8 ++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi  | 8 ++++++++
 4 files changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index faf41e3..7671e56 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -81,6 +81,14 @@
 			clock-output-names = "pll1";
 		};
 
+		pll2: clk at 01c20008 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-b-pll2-clk";
+			reg = <0x01c20008 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
+		};
+
 		pll4: clk at 01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-pll1-clk";
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 92b5d1c..75e9632 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -74,6 +74,14 @@
 			clock-output-names = "pll1";
 		};
 
+		pll2: clk at 01c20008 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-b-pll2-clk";
+			reg = <0x01c20008 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
+		};
+
 		pll4: clk at 01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-pll1-clk";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index d8f02ee..61c8331 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -75,6 +75,14 @@
 			clock-output-names = "pll1";
 		};
 
+		pll2: clk at 01c20008 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-b-pll2-clk";
+			reg = <0x01c20008 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
+		};
+
 		pll4: clk at 01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-pll1-clk";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index b1f3776..766ad81 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -91,6 +91,14 @@
 			clock-output-names = "pll1";
 		};
 
+		pll2: clk at 01c20008 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-b-pll2-clk";
+			reg = <0x01c20008 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
+		};
+
 		pll4: clk at 01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun7i-a20-pll4-clk";
-- 
2.0.3

[RFC 7/8] ARM: sunxi: Add codec clock support

[Emilio López]

This commit adds the codec clock definition to the sun4i, sun5i and
sun7i device trees. The codec clock is used in the analog codec block.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
 arch/arm/boot/dts/sun4i-a10.dtsi  | 8 ++++++++
 arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi  | 8 ++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi  | 8 ++++++++
 4 files changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 7671e56..6b33eb1 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -339,6 +339,14 @@
 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 			clock-output-names = "spi3";
 		};
+
+		codec_clk: clk at 01c20140 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-codec-clk";
+			reg = <0x01c20140 0x4>;
+			clocks = <&pll2 0>;
+			clock-output-names = "codec";
+		};
 	};
 
 	soc at 01c00000 {
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 75e9632..c0abe24 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -293,6 +293,14 @@
 			clock-output-names = "usb_ohci0", "usb_phy";
 		};
 
+		codec_clk: clk at 01c20140 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-codec-clk";
+			reg = <0x01c20140 0x4>;
+			clocks = <&pll2 0>;
+			clock-output-names = "codec";
+		};
+
 		mbus_clk: clk at 01c2015c {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 61c8331..05ce717 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -291,6 +291,14 @@
 			clock-output-names = "usb_ohci0", "usb_phy";
 		};
 
+		codec_clk: clk at 01c20140 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-codec-clk";
+			reg = <0x01c20140 0x4>;
+			clocks = <&pll2 0>;
+			clock-output-names = "codec";
+		};
+
 		mbus_clk: clk at 01c2015c {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 766ad81..5d0265a 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -352,6 +352,14 @@
 			clock-output-names = "spi3";
 		};
 
+		codec_clk: clk at 01c20140 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-codec-clk";
+			reg = <0x01c20140 0x4>;
+			clocks = <&pll2 0>;
+			clock-output-names = "codec";
+		};
+
 		mbus_clk: clk at 01c2015c {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
-- 
2.0.3

[RFC 8/8] ARM: sun7i: Add mod1 clock nodes

[Emilio López]

This commit adds all the mod1 clocks available on A20 to its device
tree. This list was created by looking at the A20 user manual.

Not-signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---

As mentioned on an earlier patch, note that this is untested, and I 
only added them to sun7i. It'd be great if actual users of these clocks 
could comment :)

 arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 5d0265a..c57f7ad 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -335,6 +335,29 @@
 			clock-output-names = "ir1";
 		};
 
+		iis0_clk: clk at 01c200b8 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200b8 0x4>;
+			clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
+			clock-output-names = "iis0";
+		};
+
+		ac97_clk: clk at 01c200bc {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200bc 0x4>;
+			clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>;
+			clock-output-names = "ac97";
+		};
+
+		spdif_clk: clk at 01c200c0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200c0 0x4>;
+			clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
+			clock-output-names = "spdif";
+		};
 		usb_clk: clk at 01c200cc {
 			#clock-cells = <1>;
 		        #reset-cells = <1>;
@@ -352,6 +375,22 @@
 			clock-output-names = "spi3";
 		};
 
+		iis1_clk: clk at 01c200d8 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200d8 0x4>;
+			clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
+			clock-output-names = "iis1";
+		};
+
+		iis2_clk: clk at 01c200dc {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200dc 0x4>;
+			clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
+			clock-output-names = "iis2";
+		};
+
 		codec_clk: clk at 01c20140 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-codec-clk";
-- 
2.0.3

[RFC 8/8] ARM: sun7i: Add mod1 clock nodes

[Chen-Yu Tsai]

Hi,

First I suggest adding "DT: " to the commit line of all the DT patches.

On Mon, Jul 28, 2014 at 11:49 AM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> This commit adds all the mod1 clocks available on A20 to its device
> tree. This list was created by looking at the A20 user manual.
>
> Not-signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
>
> As mentioned on an earlier patch, note that this is untested, and I
> only added them to sun7i. It'd be great if actual users of these clocks
> could comment :)
>
>  arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 5d0265a..c57f7ad 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -335,6 +335,29 @@
>                         clock-output-names = "ir1";
>                 };
>
> +               iis0_clk: clk at 01c200b8 {
> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
> +                       reg = <0x01c200b8 0x4>;
> +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;

User manual says pll2x8, pll2x4, pll2x2, pll2 for all the the clocks.
So the order here should be reversed. Same for the others.

> +                       clock-output-names = "iis0";
> +               };
> +
> +               ac97_clk: clk at 01c200bc {
> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
> +                       reg = <0x01c200bc 0x4>;
> +                       clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>;
> +                       clock-output-names = "ac97";
> +               };
> +
> +               spdif_clk: clk at 01c200c0 {
> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
> +                       reg = <0x01c200c0 0x4>;
> +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
> +                       clock-output-names = "spdif";
> +               };

Newline. And the manuals don't have anything on the SPDIF clock,
so I can't comment on it.

>                 usb_clk: clk at 01c200cc {
>                         #clock-cells = <1>;
>                         #reset-cells = <1>;
> @@ -352,6 +375,22 @@
>                         clock-output-names = "spi3";
>                 };
>
> +               iis1_clk: clk at 01c200d8 {
> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
> +                       reg = <0x01c200d8 0x4>;
> +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
> +                       clock-output-names = "iis1";
> +               };
> +
> +               iis2_clk: clk at 01c200dc {
> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
> +                       reg = <0x01c200dc 0x4>;
> +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
> +                       clock-output-names = "iis2";
> +               };
> +
>                 codec_clk: clk at 01c20140 {
>                         #clock-cells = <0>;
>                         compatible = "allwinner,sun4i-a10-codec-clk";
> --

Apart from the title and the clock orders, everything looks good.
Jon should test this with the above corrected.


Cheers
ChenYu

[RFC 0/8] Audio clocks for sun[457]i, SoC revision detection

[Maxime Ripard]

Hi Emilio,

On Mon, Jul 28, 2014 at 12:49:38AM -0300, Emilio L?pez wrote:
> Hi everyone,
> 
> This series adds support for PLL2 on A10 rev B and higher, A10S, A13 
> and A20. It also includes support for the codec clock as well as
> module 1 clocks, used in the audio blocks. There's also two patches
> fixing sparse warnings on the driver.

And where is the SoC revision detection you were talking about ? :)

> I'm sending this as RFC as this does not support the A10 rev A PLL2
> clock. It seems from the Allwinner code that rev A has a different
> register layout, and is programmed with different values. Unfortunately
> there's no mention of this on the User Manual, so I'm left to guess
> for the most part.

Do you have any reference pointing this out?

> The clock code is not the only part in where rev A is special cased;
> there's some register writes just for it on the analog audio driver
> as well, so we probably need a way to support this in a generic way.
> 
> So, how should we proceed with this? Here are some ideas:
>   * Make different device trees with different compatibles. Pros:
>     not much extra code. Cons: we don't know the SoC revision on
>     devices and/or they may change during the product lifecycle.

Which makes it a pretty poor solution :)

>   * Use different compatibles and change them on U-Boot. Pros: it
>     keeps Linux simple. Cons: dependency on a newer bootloader.

Which is a no-go.

>   * Use different compatibles and change them on early boot.
>     Pros: compatibility with existing bootloaders. Cons: Need
>     code in Linux to fixup the DT

Plus, we don't need to care about having different DT, and let the
user indentify which revision it has. I'm very much in favor of this
solution. And it works for all the boards.

>   * Have a function "int sunxi_soc_revision(void)" that drivers
>     can use to check which SoC revision they're running on.
>     Pros: no DT fixup. Cons: ugly and less portable if the driver
>     ever needs to run on a non-sunxi platform.

Yep.

> I'd like to hear everyone's thoughts on this. From what I've seen
> around on LAKML, it seems the last option is the one in widest use, but
> I'd appreciate a confirmation.

Mostly for historical reason I'd say. All the newer platforms seem to
handle this by fixing up the DT at the early stages.

> If this is the way forward, where should the code live in? The SoC
> detection is done by reading a register on the timer block on sun4i,
> and SID on sun5i.

In mach-sunxi I'd say. I've started working on it a few weeks back, in
order to use soc-device too, but it's pretty much wip for now.

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[RFC 2/8] clk: sunxi: codec clock support

[Maxime Ripard]

On Mon, Jul 28, 2014 at 12:49:40AM -0300, Emilio L?pez wrote:
> The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as
> parent.
> 
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[RFC 4/8] clk: sunxi: add __iomem markings to MMIO pointers

[Maxime Ripard]

On Mon, Jul 28, 2014 at 12:49:42AM -0300, Emilio L?pez wrote:
> This commit adds __iomem thoughout the sunxi clock driver, in places
> where it was ommited. This cleans most of the sparse warnings we
> are getting here.
> 
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[RFC 5/8] clk: sunxi: staticize structures and arrays

[Maxime Ripard]

On Mon, Jul 28, 2014 at 12:49:43AM -0300, Emilio L?pez wrote:
> There are some structs and arrays on the driver that are not used
> anywhere else. Let's mark them as static.
> 
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[RFC 6/8] ARM: sunxi: Add PLL2 support

[Maxime Ripard]

On Mon, Jul 28, 2014 at 12:49:44AM -0300, Emilio L?pez wrote:
> This commit adds the PLL2 definition to the sun4i, sun5i and sun7i
> device trees. PLL2 is used to clock audio devices.
> 
> Not-signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
> 
> Note that there is no handling of A10 rev A here, this should not go 
> in as-is.
> 
>  arch/arm/boot/dts/sun4i-a10.dtsi  | 8 ++++++++
>  arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
>  arch/arm/boot/dts/sun5i-a13.dtsi  | 8 ++++++++
>  arch/arm/boot/dts/sun7i-a20.dtsi  | 8 ++++++++
>  4 files changed, 32 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> index faf41e3..7671e56 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -81,6 +81,14 @@
>  			clock-output-names = "pll1";
>  		};
>  
> +		pll2: clk at 01c20008 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-b-pll2-clk";
> +			reg = <0x01c20008 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";

Why don't you just declare the fixed factors as fixed factors? It
would simplify greatly your driver, and be more accurate.

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[RFC 8/8] ARM: sun7i: Add mod1 clock nodes

[Maxime Ripard]

On Mon, Jul 28, 2014 at 12:49:46AM -0300, Emilio L?pez wrote:
> This commit adds all the mod1 clocks available on A20 to its device
> tree. This list was created by looking at the A20 user manual.
> 
> Not-signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
> 
> As mentioned on an earlier patch, note that this is untested, and I 
> only added them to sun7i. It'd be great if actual users of these clocks 
> could comment :)
> 
>  arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 5d0265a..c57f7ad 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -335,6 +335,29 @@
>  			clock-output-names = "ir1";
>  		};
>  
> +		iis0_clk: clk at 01c200b8 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod1-clk";
> +			reg = <0x01c200b8 0x4>;
> +			clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
> +			clock-output-names = "iis0";

Usually, it's called i2s.

Otherwise, beside Chen-Yu's comment, it looks fine.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[RFC 0/8] Audio clocks for sun[457]i, SoC revision detection

[jonsmirl at gmail.com]

On Mon, Jul 28, 2014 at 8:42 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Emilio,
>
> On Mon, Jul 28, 2014 at 12:49:38AM -0300, Emilio L?pez wrote:
>> Hi everyone,
>>
>> This series adds support for PLL2 on A10 rev B and higher, A10S, A13
>> and A20. It also includes support for the codec clock as well as
>> module 1 clocks, used in the audio blocks. There's also two patches
>> fixing sparse warnings on the driver.
>
> And where is the SoC revision detection you were talking about ? :)
>
>> I'm sending this as RFC as this does not support the A10 rev A PLL2
>> clock. It seems from the Allwinner code that rev A has a different
>> register layout, and is programmed with different values. Unfortunately
>> there's no mention of this on the User Manual, so I'm left to guess
>> for the most part.
>
> Do you have any reference pointing this out?
>
>> The clock code is not the only part in where rev A is special cased;
>> there's some register writes just for it on the analog audio driver
>> as well, so we probably need a way to support this in a generic way.
>>
>> So, how should we proceed with this? Here are some ideas:
>>   * Make different device trees with different compatibles. Pros:
>>     not much extra code. Cons: we don't know the SoC revision on
>>     devices and/or they may change during the product lifecycle.
>
> Which makes it a pretty poor solution :)
>
>>   * Use different compatibles and change them on U-Boot. Pros: it
>>     keeps Linux simple. Cons: dependency on a newer bootloader.
>
> Which is a no-go.
>
>>   * Use different compatibles and change them on early boot.
>>     Pros: compatibility with existing bootloaders. Cons: Need
>>     code in Linux to fixup the DT
>
> Plus, we don't need to care about having different DT, and let the
> user indentify which revision it has. I'm very much in favor of this
> solution. And it works for all the boards.
>
>>   * Have a function "int sunxi_soc_revision(void)" that drivers
>>     can use to check which SoC revision they're running on.
>>     Pros: no DT fixup. Cons: ugly and less portable if the driver
>>     ever needs to run on a non-sunxi platform.
>
> Yep.
>
>> I'd like to hear everyone's thoughts on this. From what I've seen
>> around on LAKML, it seems the last option is the one in widest use, but
>> I'd appreciate a confirmation.
>
> Mostly for historical reason I'd say. All the newer platforms seem to
> handle this by fixing up the DT at the early stages.

I thought we were going to do it like this..
http://lxr.free-electrons.com/source/arch/arm/mach-mvebu/board-v7.c#L71

The machine driver for the A10 would check the CPU revision and then
alter the compatible strings as needed to create new ones that encode
the chip revision level.

In this case it would look for  "allwinner,sun4i-a10-codec" and then
add a compatible string like "allwinner,sun4i-a10a-codec" to the front
of the list so that it will be bound first.

>
>> If this is the way forward, where should the code live in? The SoC
>> detection is done by reading a register on the timer block on sun4i,
>> and SID on sun5i.
>
> In mach-sunxi I'd say. I've started working on it a few weeks back, in
> order to use soc-device too, but it's pretty much wip for now.
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com



-- 
Jon Smirl
jonsmirl at gmail.com

[RFC 8/8] ARM: sun7i: Add mod1 clock nodes

[jonsmirl at gmail.com]

On Mon, Jul 28, 2014 at 9:25 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Mon, Jul 28, 2014 at 12:49:46AM -0300, Emilio L?pez wrote:
>> This commit adds all the mod1 clocks available on A20 to its device
>> tree. This list was created by looking at the A20 user manual.
>>
>> Not-signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>> ---
>>
>> As mentioned on an earlier patch, note that this is untested, and I
>> only added them to sun7i. It'd be great if actual users of these clocks
>> could comment :)
>>
>>  arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 39 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
>> index 5d0265a..c57f7ad 100644
>> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
>> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
>> @@ -335,6 +335,29 @@
>>                       clock-output-names = "ir1";
>>               };
>>
>> +             iis0_clk: clk at 01c200b8 {
>> +                     #clock-cells = <0>;
>> +                     compatible = "allwinner,sun4i-a10-mod1-clk";
>> +                     reg = <0x01c200b8 0x4>;
>> +                     clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
>> +                     clock-output-names = "iis0";
>
> Usually, it's called i2s.

I'd preferred i2s, but Allwinner used iis everywhere in the manual. So
which wins in the device tree?

Same issue happens with twi vs i2c.


>
> Otherwise, beside Chen-Yu's comment, it looks fine.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com



-- 
Jon Smirl
jonsmirl at gmail.com

[RFC 8/8] ARM: sun7i: Add mod1 clock nodes

[jonsmirl at gmail.com]

On Mon, Jul 28, 2014 at 12:28 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> Hi,
>
> First I suggest adding "DT: " to the commit line of all the DT patches.
>
> On Mon, Jul 28, 2014 at 11:49 AM, Emilio L?pez <emilio@elopez.com.ar> wrote:
>> This commit adds all the mod1 clocks available on A20 to its device
>> tree. This list was created by looking at the A20 user manual.
>>
>> Not-signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>> ---
>>
>> As mentioned on an earlier patch, note that this is untested, and I
>> only added them to sun7i. It'd be great if actual users of these clocks
>> could comment :)
>>
>>  arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 39 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
>> index 5d0265a..c57f7ad 100644
>> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
>> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
>> @@ -335,6 +335,29 @@
>>                         clock-output-names = "ir1";
>>                 };
>>
>> +               iis0_clk: clk at 01c200b8 {
>> +                       #clock-cells = <0>;
>> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
>> +                       reg = <0x01c200b8 0x4>;
>> +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
>
> User manual says pll2x8, pll2x4, pll2x2, pll2 for all the the clocks.
> So the order here should be reversed. Same for the others.
>
>> +                       clock-output-names = "iis0";
>> +               };
>> +
>> +               ac97_clk: clk at 01c200bc {
>> +                       #clock-cells = <0>;
>> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
>> +                       reg = <0x01c200bc 0x4>;
>> +                       clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>;
>> +                       clock-output-names = "ac97";
>> +               };
>> +
>> +               spdif_clk: clk at 01c200c0 {
>> +                       #clock-cells = <0>;
>> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
>> +                       reg = <0x01c200c0 0x4>;
>> +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
>> +                       clock-output-names = "spdif";
>> +               };
>
> Newline. And the manuals don't have anything on the SPDIF clock,
> so I can't comment on it.

We do have this much SPDIF doc.
http://linux-sunxi.org/SPDIF

Based on the Allwinner code I see no reason to think that the SPDIF
clock varies from any of the other audio clocks.  Who knows why they
left SPDIF out of the manual.


>
>>                 usb_clk: clk at 01c200cc {
>>                         #clock-cells = <1>;
>>                         #reset-cells = <1>;
>> @@ -352,6 +375,22 @@
>>                         clock-output-names = "spi3";
>>                 };
>>
>> +               iis1_clk: clk at 01c200d8 {
>> +                       #clock-cells = <0>;
>> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
>> +                       reg = <0x01c200d8 0x4>;
>> +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
>> +                       clock-output-names = "iis1";
>> +               };
>> +
>> +               iis2_clk: clk at 01c200dc {
>> +                       #clock-cells = <0>;
>> +                       compatible = "allwinner,sun4i-a10-mod1-clk";
>> +                       reg = <0x01c200dc 0x4>;
>> +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
>> +                       clock-output-names = "iis2";
>> +               };
>> +
>>                 codec_clk: clk at 01c20140 {
>>                         #clock-cells = <0>;
>>                         compatible = "allwinner,sun4i-a10-codec-clk";
>> --
>
> Apart from the title and the clock orders, everything looks good.
> Jon should test this with the above corrected.

I don't have i2s hardware available yet. Maybe by end of the week.

>
>
> Cheers
> ChenYu



-- 
Jon Smirl
jonsmirl at gmail.com

[RFC 4/8] clk: sunxi: add __iomem markings to MMIO pointers

[Mike Turquette]

Quoting Maxime Ripard (2014-07-28 06:21:18)
> On Mon, Jul 28, 2014 at 12:49:42AM -0300, Emilio L?pez wrote:
> > This commit adds __iomem thoughout the sunxi clock driver, in places
> > where it was ommited. This cleans most of the sparse warnings we
> > are getting here.
> > 
> > Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> 
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

I've applied patches 4 & 5 to clk-next since they are useful fixes and
you have already sent me a pull request for 3.17. Let me know if you
would prefer for me to hold off on them for any reason.

Regards,
Mike

> 
> Maxime
> 
> -- 
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

[RFC 8/8] ARM: sun7i: Add mod1 clock nodes

[Maxime Ripard]

On Mon, Jul 28, 2014 at 10:47:16AM -0400, jonsmirl at gmail.com wrote:
> On Mon, Jul 28, 2014 at 9:25 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Mon, Jul 28, 2014 at 12:49:46AM -0300, Emilio L?pez wrote:
> >> This commit adds all the mod1 clocks available on A20 to its device
> >> tree. This list was created by looking at the A20 user manual.
> >>
> >> Not-signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> >> ---
> >>
> >> As mentioned on an earlier patch, note that this is untested, and I
> >> only added them to sun7i. It'd be great if actual users of these clocks
> >> could comment :)
> >>
> >>  arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
> >>  1 file changed, 39 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> >> index 5d0265a..c57f7ad 100644
> >> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> >> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> >> @@ -335,6 +335,29 @@
> >>                       clock-output-names = "ir1";
> >>               };
> >>
> >> +             iis0_clk: clk at 01c200b8 {
> >> +                     #clock-cells = <0>;
> >> +                     compatible = "allwinner,sun4i-a10-mod1-clk";
> >> +                     reg = <0x01c200b8 0x4>;
> >> +                     clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
> >> +                     clock-output-names = "iis0";
> >
> > Usually, it's called i2s.
> 
> I'd preferred i2s, but Allwinner used iis everywhere in the manual. So
> which wins in the device tree?
> 
> Same issue happens with twi vs i2c.

I'd say whatever is the most common, this is why we ended up using i2c
instead of allwinner's twi, pinctrl over port controller, etc.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[RFC 0/8] Audio clocks for sun[457]i, SoC revision detection

[Maxime Ripard]

On Mon, Jul 28, 2014 at 10:40:31AM -0400, jonsmirl at gmail.com wrote:
> On Mon, Jul 28, 2014 at 8:42 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi Emilio,
> >
> > On Mon, Jul 28, 2014 at 12:49:38AM -0300, Emilio L?pez wrote:
> >> Hi everyone,
> >>
> >> This series adds support for PLL2 on A10 rev B and higher, A10S, A13
> >> and A20. It also includes support for the codec clock as well as
> >> module 1 clocks, used in the audio blocks. There's also two patches
> >> fixing sparse warnings on the driver.
> >
> > And where is the SoC revision detection you were talking about ? :)
> >
> >> I'm sending this as RFC as this does not support the A10 rev A PLL2
> >> clock. It seems from the Allwinner code that rev A has a different
> >> register layout, and is programmed with different values. Unfortunately
> >> there's no mention of this on the User Manual, so I'm left to guess
> >> for the most part.
> >
> > Do you have any reference pointing this out?
> >
> >> The clock code is not the only part in where rev A is special cased;
> >> there's some register writes just for it on the analog audio driver
> >> as well, so we probably need a way to support this in a generic way.
> >>
> >> So, how should we proceed with this? Here are some ideas:
> >>   * Make different device trees with different compatibles. Pros:
> >>     not much extra code. Cons: we don't know the SoC revision on
> >>     devices and/or they may change during the product lifecycle.
> >
> > Which makes it a pretty poor solution :)
> >
> >>   * Use different compatibles and change them on U-Boot. Pros: it
> >>     keeps Linux simple. Cons: dependency on a newer bootloader.
> >
> > Which is a no-go.
> >
> >>   * Use different compatibles and change them on early boot.
> >>     Pros: compatibility with existing bootloaders. Cons: Need
> >>     code in Linux to fixup the DT
> >
> > Plus, we don't need to care about having different DT, and let the
> > user indentify which revision it has. I'm very much in favor of this
> > solution. And it works for all the boards.
> >
> >>   * Have a function "int sunxi_soc_revision(void)" that drivers
> >>     can use to check which SoC revision they're running on.
> >>     Pros: no DT fixup. Cons: ugly and less portable if the driver
> >>     ever needs to run on a non-sunxi platform.
> >
> > Yep.
> >
> >> I'd like to hear everyone's thoughts on this. From what I've seen
> >> around on LAKML, it seems the last option is the one in widest use, but
> >> I'd appreciate a confirmation.
> >
> > Mostly for historical reason I'd say. All the newer platforms seem to
> > handle this by fixing up the DT at the early stages.
> 
> I thought we were going to do it like this..
> http://lxr.free-electrons.com/source/arch/arm/mach-mvebu/board-v7.c#L71
> 
> The machine driver for the A10 would check the CPU revision and then
> alter the compatible strings as needed to create new ones that encode
> the chip revision level.
> 
> In this case it would look for  "allwinner,sun4i-a10-codec" and then
> add a compatible string like "allwinner,sun4i-a10a-codec" to the front
> of the list so that it will be bound first.

This is what I meant by "fixing up the DT at the early stages", sorry
if it wasn't clear enough :)

Note that we don't add a new compatible, but replace it entirely.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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