* Re: [PATCH v2] drm/i915: Add sprite watermark programming for VLV and CHV
2014-08-05 17:51 ` [PATCH v2] drm/i915: Add sprite watermark programming for VLV and CHV Gajanan Bhat
@ 2014-08-05 14:39 ` Ville Syrjälä
2014-08-07 11:33 ` [PATCH V3] " Gajanan Bhat
0 siblings, 1 reply; 4+ messages in thread
From: Ville Syrjälä @ 2014-08-05 14:39 UTC (permalink / raw)
To: Gajanan Bhat; +Cc: intel-gfx
On Tue, Aug 05, 2014 at 11:21:38PM +0530, Gajanan Bhat wrote:
> Program DDL register as part of sprite watermark programming for CHV and VLV.
>
> v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK
>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5e81c49..9126295 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1416,6 +1416,48 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
> intel_set_memory_cxsr(dev_priv, true);
> }
>
> +static void valleyview_update_sprite_wm(struct drm_plane *plane,
> + struct drm_crtc *crtc,
> + uint32_t sprite_width,
> + uint32_t sprite_height,
> + int pixel_size,
> + bool enabled, bool scaled)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int pipe = to_intel_plane(plane)->pipe;
> + int drain_latency;
> + int plane_prec;
> + int sprite_dl;
> + int prec_mult;
> +
> + if (to_intel_plane(plane)->plane == 0)
> + sprite_dl = I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE0_PRECISION_64 &
> + ~(DRAIN_LATENCY_MASK << DDL_SPRITE0_SHIFT);
> + else
> + sprite_dl = I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE1_PRECISION_64 &
> + ~(DRAIN_LATENCY_MASK << DDL_SPRITE1_SHIFT);
I was thinking we migth want to parametrize the DDL_SPRITE bits to avoid
these if-else things. So something like this:
#define DDL_SPRITE_PRECISION_64(sprite) (1<<(15+8*(sprite)))
#define DDL_SPRITE_PRECISION_32(sprite) (0<<(15+8*(sprite)))
#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
Also you should again use the more customary form for masking the bits:
I915_READ() & ~(DDL_SPRITE_PRECISION_64 |
(DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT));
> +
> + if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
> + &drain_latency)) {
> + if (to_intel_plane(plane)->plane == 0) {
> + plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
> + DDL_SPRITE0_PRECISION_64 :
> + DDL_SPRITE0_PRECISION_32;
> + sprite_dl = sprite_dl | plane_prec |
> + drain_latency << DDL_SPRITE0_SHIFT;
> + } else {
> + plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
> + DDL_SPRITE1_PRECISION_64 :
> + DDL_SPRITE1_PRECISION_32;
> + sprite_dl = sprite_dl | plane_prec |
> + drain_latency << DDL_SPRITE1_SHIFT;
> + }
> + }
> +
> + I915_WRITE(VLV_DDL(pipe), sprite_dl);
> +}
> +
> static void g4x_update_wm(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> @@ -7134,10 +7176,12 @@ void intel_init_pm(struct drm_device *dev)
> dev_priv->display.init_clock_gating = gen8_init_clock_gating;
> } else if (IS_CHERRYVIEW(dev)) {
> dev_priv->display.update_wm = valleyview_update_wm;
> + dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
> dev_priv->display.init_clock_gating =
> cherryview_init_clock_gating;
> } else if (IS_VALLEYVIEW(dev)) {
> dev_priv->display.update_wm = valleyview_update_wm;
> + dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
> dev_priv->display.init_clock_gating =
> valleyview_init_clock_gating;
> } else if (IS_PINEVIEW(dev)) {
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2] drm/i915: Add sprite watermark programming for VLV and CHV
[not found] <1405513395-7014-4-git-send-email-gajanan.bhat@intel.com>
@ 2014-08-05 17:51 ` Gajanan Bhat
2014-08-05 14:39 ` Ville Syrjälä
0 siblings, 1 reply; 4+ messages in thread
From: Gajanan Bhat @ 2014-08-05 17:51 UTC (permalink / raw)
To: intel-gfx
Program DDL register as part of sprite watermark programming for CHV and VLV.
v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5e81c49..9126295 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1416,6 +1416,48 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
intel_set_memory_cxsr(dev_priv, true);
}
+static void valleyview_update_sprite_wm(struct drm_plane *plane,
+ struct drm_crtc *crtc,
+ uint32_t sprite_width,
+ uint32_t sprite_height,
+ int pixel_size,
+ bool enabled, bool scaled)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe = to_intel_plane(plane)->pipe;
+ int drain_latency;
+ int plane_prec;
+ int sprite_dl;
+ int prec_mult;
+
+ if (to_intel_plane(plane)->plane == 0)
+ sprite_dl = I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE0_PRECISION_64 &
+ ~(DRAIN_LATENCY_MASK << DDL_SPRITE0_SHIFT);
+ else
+ sprite_dl = I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE1_PRECISION_64 &
+ ~(DRAIN_LATENCY_MASK << DDL_SPRITE1_SHIFT);
+
+ if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
+ &drain_latency)) {
+ if (to_intel_plane(plane)->plane == 0) {
+ plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
+ DDL_SPRITE0_PRECISION_64 :
+ DDL_SPRITE0_PRECISION_32;
+ sprite_dl = sprite_dl | plane_prec |
+ drain_latency << DDL_SPRITE0_SHIFT;
+ } else {
+ plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
+ DDL_SPRITE1_PRECISION_64 :
+ DDL_SPRITE1_PRECISION_32;
+ sprite_dl = sprite_dl | plane_prec |
+ drain_latency << DDL_SPRITE1_SHIFT;
+ }
+ }
+
+ I915_WRITE(VLV_DDL(pipe), sprite_dl);
+}
+
static void g4x_update_wm(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -7134,10 +7176,12 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.init_clock_gating = gen8_init_clock_gating;
} else if (IS_CHERRYVIEW(dev)) {
dev_priv->display.update_wm = valleyview_update_wm;
+ dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
dev_priv->display.init_clock_gating =
cherryview_init_clock_gating;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.update_wm = valleyview_update_wm;
+ dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
dev_priv->display.init_clock_gating =
valleyview_init_clock_gating;
} else if (IS_PINEVIEW(dev)) {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH V3] drm/i915: Add sprite watermark programming for VLV and CHV
2014-08-07 11:33 ` [PATCH V3] " Gajanan Bhat
@ 2014-08-07 8:26 ` Ville Syrjälä
0 siblings, 0 replies; 4+ messages in thread
From: Ville Syrjälä @ 2014-08-07 8:26 UTC (permalink / raw)
To: Gajanan Bhat; +Cc: intel-gfx
On Thu, Aug 07, 2014 at 05:03:30PM +0530, Gajanan Bhat wrote:
> Program DDL register as part of sprite watermark programming for CHV and VLV.
>
> v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK
>
> v3: Addressed review comments by Ville
> - Changed Sprite DDL definitions to more generic to avoid multiple if-else
> - Changed bit masking to customary form
> - Changed to bitwise shorthand operator for sprite_dl assignment
>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Looks good.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +++------
> drivers/gpu/drm/i915/intel_pm.c | 33 +++++++++++++++++++++++++++++++++
> 2 files changed, 36 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 08916df..f8aaf0b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4000,12 +4000,9 @@ enum punit_power_well {
> #define DDL_CURSOR_PRECISION_64 (1<<31)
> #define DDL_CURSOR_PRECISION_32 (0<<31)
> #define DDL_CURSOR_SHIFT 24
> -#define DDL_SPRITE1_PRECISION_64 (1<<23)
> -#define DDL_SPRITE1_PRECISION_32 (0<<23)
> -#define DDL_SPRITE1_SHIFT 16
> -#define DDL_SPRITE0_PRECISION_64 (1<<15)
> -#define DDL_SPRITE0_PRECISION_32 (0<<15)
> -#define DDL_SPRITE0_SHIFT 8
> +#define DDL_SPRITE_PRECISION_64(sprite) (1<<(15+8*(sprite)))
> +#define DDL_SPRITE_PRECISION_32(sprite) (0<<(15+8*(sprite)))
> +#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
> #define DDL_PLANE_PRECISION_64 (1<<7)
> #define DDL_PLANE_PRECISION_32 (0<<7)
> #define DDL_PLANE_SHIFT 0
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 86d6048..974aeea 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1500,6 +1500,37 @@ static void cherryview_update_wm(struct drm_crtc *crtc)
> intel_set_memory_cxsr(dev_priv, true);
> }
>
> +static void valleyview_update_sprite_wm(struct drm_plane *plane,
> + struct drm_crtc *crtc,
> + uint32_t sprite_width,
> + uint32_t sprite_height,
> + int pixel_size,
> + bool enabled, bool scaled)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int pipe = to_intel_plane(plane)->pipe;
> + int sprite = to_intel_plane(plane)->plane;
> + int drain_latency;
> + int plane_prec;
> + int sprite_dl;
> + int prec_mult;
> +
> + sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
> + (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
> +
> + if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
> + &drain_latency)) {
> + plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
> + DDL_SPRITE_PRECISION_64(sprite) :
> + DDL_SPRITE_PRECISION_32(sprite);
> + sprite_dl |= plane_prec |
> + (drain_latency << DDL_SPRITE_SHIFT(sprite));
> + }
> +
> + I915_WRITE(VLV_DDL(pipe), sprite_dl);
> +}
> +
> static void g4x_update_wm(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> @@ -7231,10 +7262,12 @@ void intel_init_pm(struct drm_device *dev)
> dev_priv->display.init_clock_gating = gen8_init_clock_gating;
> } else if (IS_CHERRYVIEW(dev)) {
> dev_priv->display.update_wm = cherryview_update_wm;
> + dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
> dev_priv->display.init_clock_gating =
> cherryview_init_clock_gating;
> } else if (IS_VALLEYVIEW(dev)) {
> dev_priv->display.update_wm = valleyview_update_wm;
> + dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
> dev_priv->display.init_clock_gating =
> valleyview_init_clock_gating;
> } else if (IS_PINEVIEW(dev)) {
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH V3] drm/i915: Add sprite watermark programming for VLV and CHV
2014-08-05 14:39 ` Ville Syrjälä
@ 2014-08-07 11:33 ` Gajanan Bhat
2014-08-07 8:26 ` Ville Syrjälä
0 siblings, 1 reply; 4+ messages in thread
From: Gajanan Bhat @ 2014-08-07 11:33 UTC (permalink / raw)
To: intel-gfx
Program DDL register as part of sprite watermark programming for CHV and VLV.
v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK
v3: Addressed review comments by Ville
- Changed Sprite DDL definitions to more generic to avoid multiple if-else
- Changed bit masking to customary form
- Changed to bitwise shorthand operator for sprite_dl assignment
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++------
drivers/gpu/drm/i915/intel_pm.c | 33 +++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 08916df..f8aaf0b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4000,12 +4000,9 @@ enum punit_power_well {
#define DDL_CURSOR_PRECISION_64 (1<<31)
#define DDL_CURSOR_PRECISION_32 (0<<31)
#define DDL_CURSOR_SHIFT 24
-#define DDL_SPRITE1_PRECISION_64 (1<<23)
-#define DDL_SPRITE1_PRECISION_32 (0<<23)
-#define DDL_SPRITE1_SHIFT 16
-#define DDL_SPRITE0_PRECISION_64 (1<<15)
-#define DDL_SPRITE0_PRECISION_32 (0<<15)
-#define DDL_SPRITE0_SHIFT 8
+#define DDL_SPRITE_PRECISION_64(sprite) (1<<(15+8*(sprite)))
+#define DDL_SPRITE_PRECISION_32(sprite) (0<<(15+8*(sprite)))
+#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
#define DDL_PLANE_PRECISION_64 (1<<7)
#define DDL_PLANE_PRECISION_32 (0<<7)
#define DDL_PLANE_SHIFT 0
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 86d6048..974aeea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1500,6 +1500,37 @@ static void cherryview_update_wm(struct drm_crtc *crtc)
intel_set_memory_cxsr(dev_priv, true);
}
+static void valleyview_update_sprite_wm(struct drm_plane *plane,
+ struct drm_crtc *crtc,
+ uint32_t sprite_width,
+ uint32_t sprite_height,
+ int pixel_size,
+ bool enabled, bool scaled)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe = to_intel_plane(plane)->pipe;
+ int sprite = to_intel_plane(plane)->plane;
+ int drain_latency;
+ int plane_prec;
+ int sprite_dl;
+ int prec_mult;
+
+ sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
+ (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
+
+ if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
+ &drain_latency)) {
+ plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
+ DDL_SPRITE_PRECISION_64(sprite) :
+ DDL_SPRITE_PRECISION_32(sprite);
+ sprite_dl |= plane_prec |
+ (drain_latency << DDL_SPRITE_SHIFT(sprite));
+ }
+
+ I915_WRITE(VLV_DDL(pipe), sprite_dl);
+}
+
static void g4x_update_wm(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -7231,10 +7262,12 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.init_clock_gating = gen8_init_clock_gating;
} else if (IS_CHERRYVIEW(dev)) {
dev_priv->display.update_wm = cherryview_update_wm;
+ dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
dev_priv->display.init_clock_gating =
cherryview_init_clock_gating;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.update_wm = valleyview_update_wm;
+ dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
dev_priv->display.init_clock_gating =
valleyview_init_clock_gating;
} else if (IS_PINEVIEW(dev)) {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-08-07 8:26 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <1405513395-7014-4-git-send-email-gajanan.bhat@intel.com>
2014-08-05 17:51 ` [PATCH v2] drm/i915: Add sprite watermark programming for VLV and CHV Gajanan Bhat
2014-08-05 14:39 ` Ville Syrjälä
2014-08-07 11:33 ` [PATCH V3] " Gajanan Bhat
2014-08-07 8:26 ` Ville Syrjälä
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