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From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org, Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 03/15] drm/i915: Upgrade execbuffer fail after resume failure to EIO
Date: Fri, 8 Aug 2014 10:52:23 +0100	[thread overview]
Message-ID: <20140808095223.GF3021@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <20140808094607.GP8727@phenom.ffwll.local>

On Fri, Aug 08, 2014 at 11:46:07AM +0200, Daniel Vetter wrote:
> On Fri, Aug 08, 2014 at 10:17:10AM +0100, Chris Wilson wrote:
> > On Wed, Aug 06, 2014 at 10:39:16AM +0200, Daniel Vetter wrote:
> > > On Wed, Aug 06, 2014 at 09:12:32AM +0100, Chris Wilson wrote:
> > > > On Wed, Aug 06, 2014 at 09:56:45AM +0200, Daniel Vetter wrote:
> > > > > On Tue, Aug 05, 2014 at 07:51:14AM -0700, Rodrigo Vivi wrote:
> > > > > > From: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > > 
> > > > > > If we try to execute on a known ring, but it has failed to be
> > > > > > initialised correctly, report that the GPU is hung rather than the
> > > > > > command invalid. This leaves us reporting EINVAL only if the user
> > > > > > requests execution on a ring that is not supported by the device.
> > > > > > 
> > > > > > This should prevent UXA from getting stuck in a null render loop after a
> > > > > > failed resume.
> > > > > > 
> > > > > > v2 (Rodrigo): Fix conflict and add VCS2 ring and
> > > > > >    	      s/intel_ring_buffer/intel_engine_cs.
> > > > > > 
> > > > > > Reported-by: Jiri Kosina <jikos@jikos.cz>
> > > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=76554
> > > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > 
> > > > > This isn't required any more, see
> > > > > 
> > > > > commit 074c6adaf4e7d1423d373bd5d1afc20b683cb4d0
> > > > > Author: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > Date:   Wed Apr 9 09:19:43 2014 +0100
> > > > > 
> > > > >     drm/i915: Mark device as wedged if we fail to resume
> > > > > 
> > > > > for the alternate merged patch.
> > > > 
> > > > Hmm, there is still a path that ends here, but the example above is
> > > > already fixed as you say.
> > > 
> > > We have the EIO check both in the resume and driver load paths. Which
> > > other path are we missing?
> > 
> > The GPU may be set to wedged, but this check in execbuffer occurs before
> > we check for a wedged GPU.
> 
> But we no longer free the ring structures over suspedn/resume, so at least
> the commit message is outdated.

Went off on an incorrect tangent.
 
> I wonder whether the easier fix wouldn't be to continue ring init if we
> get an -EIO.

Right, that's the problem I remember. But I am not sure if it is really
worth it. It's only to hide log spew in a corner case of a corner case in
UXA.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

  reply	other threads:[~2014-08-08  9:52 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-05 14:51 [PATCH 00/15] drm-intel-collector - update Rodrigo Vivi
2014-08-05 14:51 ` [PATCH 01/15] drm/i915: Bring UP Power Wells before disabling RC6 Rodrigo Vivi
2014-08-05 14:51 ` [PATCH 02/15] drm/i915: Don't save/restore RS when not used Rodrigo Vivi
2014-08-05 14:51 ` [PATCH 03/15] drm/i915: Upgrade execbuffer fail after resume failure to EIO Rodrigo Vivi
2014-08-06  7:56   ` Daniel Vetter
2014-08-06  8:12     ` Chris Wilson
2014-08-06  8:39       ` Daniel Vetter
2014-08-08  9:17         ` Chris Wilson
2014-08-08  9:46           ` Daniel Vetter
2014-08-08  9:52             ` Chris Wilson [this message]
2014-08-05 14:51 ` [PATCH 04/15] drm/i915: honour forced connector modes Rodrigo Vivi
2014-08-06  8:15   ` Daniel Vetter
2014-08-06 15:00   ` Jesse Barnes
2014-08-05 14:51 ` [PATCH 05/15] drm/i915: Don't promote UC to WT automagically Rodrigo Vivi
2014-08-06  7:57   ` Daniel Vetter
2014-08-05 14:51 ` [PATCH 06/15] drm/i915: Refactor the physical and virtual page hws setup Rodrigo Vivi
2014-08-06  8:17   ` Daniel Vetter
2014-08-05 14:51 ` [PATCH 07/15] drm/i915: clean up PPGTT checking logic Rodrigo Vivi
2014-08-06  8:21   ` Daniel Vetter
2014-08-05 14:51 ` [PATCH 08/15] drm/i915: re-order ppgtt sanitize logic v2 Rodrigo Vivi
2014-08-06  8:22   ` Daniel Vetter
2014-08-05 14:51 ` [PATCH 09/15] drm/i915: Bring GPU Freq to min while suspending Rodrigo Vivi
2014-08-06  8:23   ` Daniel Vetter
2014-08-05 14:51 ` [PATCH 10/15] drm/i915/bdw: Map unused PDPs to a scratch page Rodrigo Vivi
2014-08-05 14:51 ` [PATCH 11/15] drm/i915: Set M2_N2 registers during mode set Rodrigo Vivi
2014-08-05 21:55   ` Jesse Barnes
2014-08-05 14:51 ` [PATCH 12/15] drm/i915: State readout and cross-checking for dp_m2_n2 Rodrigo Vivi
2014-08-06  8:25   ` Daniel Vetter
2014-08-05 14:51 ` [PATCH 13/15] drm/i915: HDMI detection based on HPD pin live status Rodrigo Vivi
2014-08-06  3:32   ` Sharma, Shashank
2014-08-06  6:44   ` Dave Airlie
2014-08-05 14:51 ` [PATCH 14/15] drm/i915: capture_reg_state interrupt registers for Gen8 Rodrigo Vivi
2014-08-06  8:27   ` Daniel Vetter
2014-08-06  8:56     ` Thierry, Michel
2014-08-05 14:51 ` [PATCH 15/15] drm/i915/chv: Use timeout mode for RC6 on chv Rodrigo Vivi
2014-08-06  0:51   ` O'Rourke, Tom

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