* [PATCH resend 0/2] i2c: hix5hd2: add i2c controller driver
@ 2014-08-26 5:25 ` Zhangfei Gao
0 siblings, 0 replies; 14+ messages in thread
From: Zhangfei Gao @ 2014-08-26 5:25 UTC (permalink / raw)
To: Wolfram Sang, Arnd Bergmann, haifeng.yan-QSEj5FYQhm4dnm+yROfE0A,
jchxue-Re5JQEeQqe8AvxtiuMwx3w
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, Zhangfei Gao
Resend: verified on 3.17-rc1
Wei Yan (2):
i2c: hix5hd2: add devicetree documentation
i2c: hix5hd2: add i2c controller driver
.../devicetree/bindings/i2c/i2c-hix5hd2.txt | 31 ++
drivers/i2c/busses/Kconfig | 16 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-hix5hd2.c | 576 ++++++++++++++++++++
4 files changed, 624 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c
--
1.7.9.5
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH resend 0/2] i2c: hix5hd2: add i2c controller driver
@ 2014-08-26 5:25 ` Zhangfei Gao
0 siblings, 0 replies; 14+ messages in thread
From: Zhangfei Gao @ 2014-08-26 5:25 UTC (permalink / raw)
To: linux-arm-kernel
Resend: verified on 3.17-rc1
Wei Yan (2):
i2c: hix5hd2: add devicetree documentation
i2c: hix5hd2: add i2c controller driver
.../devicetree/bindings/i2c/i2c-hix5hd2.txt | 31 ++
drivers/i2c/busses/Kconfig | 16 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-hix5hd2.c | 576 ++++++++++++++++++++
4 files changed, 624 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c
--
1.7.9.5
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH resend 1/2] i2c: hix5hd2: add devicetree documentation
2014-08-26 5:25 ` Zhangfei Gao
@ 2014-08-26 5:25 ` Zhangfei Gao
-1 siblings, 0 replies; 14+ messages in thread
From: Zhangfei Gao @ 2014-08-26 5:25 UTC (permalink / raw)
To: Wolfram Sang, Arnd Bergmann, haifeng.yan-QSEj5FYQhm4dnm+yROfE0A,
jchxue-Re5JQEeQqe8AvxtiuMwx3w
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, Wei Yan, Zhangfei Gao
From: Wei Yan <sledge.yanwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Wei Yan <sledge.yanwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
.../devicetree/bindings/i2c/i2c-hix5hd2.txt | 31 ++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
new file mode 100644
index 0000000..2ecc8a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
@@ -0,0 +1,31 @@
+I2C for Hisilicon hix5hd2 chipset platforms (3716,3719,3798...)
+
+Required properties:
+- compatible: Must be "hisilicon,hix5hd2-i2c"
+ Specifically, the following versions of the chipset are supported:
+ Hi3716CV200 (support six I2C module)
+ Hi3719CV100 (support six I2C module)
+ Hi3718CV100 (support six I2C module)
+ Hi3719MV100 (support two I2C module)
+ Hi3718MV100 (support two I2C module)
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks: phandles to input clocks.
+
+Optional properties:
+- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 400000
+- Child nodes conforming to i2c bus binding
+
+Examples:
+I2C0@f8b10000 {
+ compatible = "hisilicon,hix5hd2-i2c";
+ reg = <0xf8b10000 0x1000>;
+ interrupts = <0 38 4>;
+ clocks = <&clock HIX5HD2_I2C0_RST>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH resend 1/2] i2c: hix5hd2: add devicetree documentation
@ 2014-08-26 5:25 ` Zhangfei Gao
0 siblings, 0 replies; 14+ messages in thread
From: Zhangfei Gao @ 2014-08-26 5:25 UTC (permalink / raw)
To: linux-arm-kernel
From: Wei Yan <sledge.yanwei@huawei.com>
Signed-off-by: Wei Yan <sledge.yanwei@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
.../devicetree/bindings/i2c/i2c-hix5hd2.txt | 31 ++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
new file mode 100644
index 0000000..2ecc8a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
@@ -0,0 +1,31 @@
+I2C for Hisilicon hix5hd2 chipset platforms (3716,3719,3798...)
+
+Required properties:
+- compatible: Must be "hisilicon,hix5hd2-i2c"
+ Specifically, the following versions of the chipset are supported:
+ Hi3716CV200 (support six I2C module)
+ Hi3719CV100 (support six I2C module)
+ Hi3718CV100 (support six I2C module)
+ Hi3719MV100 (support two I2C module)
+ Hi3718MV100 (support two I2C module)
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks: phandles to input clocks.
+
+Optional properties:
+- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 400000
+- Child nodes conforming to i2c bus binding
+
+Examples:
+I2C0 at f8b10000 {
+ compatible = "hisilicon,hix5hd2-i2c";
+ reg = <0xf8b10000 0x1000>;
+ interrupts = <0 38 4>;
+ clocks = <&clock HIX5HD2_I2C0_RST>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH resend 2/2] i2c: hix5hd2: add i2c controller driver
2014-08-26 5:25 ` Zhangfei Gao
@ 2014-08-26 5:25 ` Zhangfei Gao
-1 siblings, 0 replies; 14+ messages in thread
From: Zhangfei Gao @ 2014-08-26 5:25 UTC (permalink / raw)
To: Wolfram Sang, Arnd Bergmann, haifeng.yan-QSEj5FYQhm4dnm+yROfE0A,
jchxue-Re5JQEeQqe8AvxtiuMwx3w
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, Wei Yan, Zhangfei Gao
From: Wei Yan <sledge.yanwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
I2C drivers for hix5hd2 soc series, including following chipset
Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100.
Signed-off-by: Wei Yan <sledge.yanwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
drivers/i2c/busses/Kconfig | 15 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-hix5hd2.c | 573 ++++++++++++++++++++++++++++++++++++++
3 files changed, 589 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2ac87fa..6c66b9e 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -77,6 +77,21 @@ config I2C_AMD8111
This driver can also be built as a module. If so, the module
will be called i2c-amd8111.
+config I2C_HIX5HD2
+ tristate "Hix5hd2 high-speed I2C driver"
+ help
+ Say Y here to include support for high-speed I2C controller in the
+ Hisilicon based hix5hd2 SoCs. Specifically, the following versions
+ of the chipset are supported:
+ Hi3716CV200 (support six I2C module)
+ Hi3719CV100 (support six I2C module)
+ Hi3718CV100 (support six I2C module)
+ Hi3719MV100 (support two I2C module)
+ Hi3718MV100 (support two I2C module)
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-hix5hd2.
+
config I2C_I801
tristate "Intel 82801 (ICH/PCH)"
depends on PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 49bf07e..9739938 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
+obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
obj-$(CONFIG_I2C_IMX) += i2c-imx.o
obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
diff --git a/drivers/i2c/busses/i2c-hix5hd2.c b/drivers/i2c/busses/i2c-hix5hd2.c
new file mode 100644
index 0000000..2f6b87c
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hix5hd2.c
@@ -0,0 +1,573 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ * Now only support 7 bit address.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+/* Register Map */
+#define HIX5I2C_CTRL 0x00
+#define HIX5I2C_COM 0x04
+#define HIX5I2C_ICR 0x08
+#define HIX5I2C_SR 0x0c
+#define HIX5I2C_SCL_H 0x10
+#define HIX5I2C_SCL_L 0x14
+#define HIX5I2C_TXR 0x18
+#define HIX5I2C_RXR 0x1c
+
+/* I2C_CTRL_REG */
+#define I2C_ENABLE BIT(8)
+#define I2C_UNMASK_TOTAL BIT(7)
+#define I2C_UNMASK_START BIT(6)
+#define I2C_UNMASK_END BIT(5)
+#define I2C_UNMASK_SEND BIT(4)
+#define I2C_UNMASK_RECEIVE BIT(3)
+#define I2C_UNMASK_ACK BIT(2)
+#define I2C_UNMASK_ARBITRATE BIT(1)
+#define I2C_UNMASK_OVER BIT(0)
+#define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
+
+/* I2C_COM_REG */
+#define I2C_NO_ACK BIT(4)
+#define I2C_START BIT(3)
+#define I2C_READ BIT(2)
+#define I2C_WRITE BIT(1)
+#define I2C_STOP BIT(0)
+
+/* I2C_ICR_REG */
+#define I2C_CLEAR_START BIT(6)
+#define I2C_CLEAR_END BIT(5)
+#define I2C_CLEAR_SEND BIT(4)
+#define I2C_CLEAR_RECEIVE BIT(3)
+#define I2C_CLEAR_ACK BIT(2)
+#define I2C_CLEAR_ARBITRATE BIT(1)
+#define I2C_CLEAR_OVER BIT(0)
+#define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \
+ I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
+ I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
+ I2C_CLEAR_OVER)
+
+/* I2C_SR_REG */
+#define I2C_BUSY BIT(7)
+#define I2C_START_INTR BIT(6)
+#define I2C_END_INTR BIT(5)
+#define I2C_SEND_INTR BIT(4)
+#define I2C_RECEIVE_INTR BIT(3)
+#define I2C_ACK_INTR BIT(2)
+#define I2C_ARBITRATE_INTR BIT(1)
+#define I2C_OVER_INTR BIT(0)
+
+/*
+ * Controller operating frequency, timing values for operation
+ * are calculated against this frequency
+ */
+#define HIX5I2C_NS_TX_CLOCK 100000 /* 100k */
+#define HIX5I2C_HS_TX_CLOCK 400000 /* 400k */
+
+#define HIX5I2C_READ_OPERATION 0x01
+#define HIX5I2C_WRITE_OPERATION 0xfe
+
+enum hix5hd2_i2c_state {
+ HIX5I2C_STAT_RW_ERR = -1,
+ HIX5I2C_STAT_INIT,
+ HIX5I2C_STAT_RW,
+ HIX5I2C_STAT_SND_STOP,
+ HIX5I2C_STAT_RW_SUCCESS,
+};
+
+enum hix5hd2_i2c_speed {
+ HIX5I2C_NORMAL_SPD, /* Fast speed upto 1Mbps */
+ HIX5I2C_HIG_SPD, /* High speed upto 3.4Mbps */
+};
+
+struct hix5hd2_i2c {
+ struct i2c_adapter adap;
+ struct i2c_msg *msg;
+ unsigned int msg_ptr; /* msg index */
+ unsigned int len; /* msg length */
+ int stop;
+ struct completion msg_complete;
+
+ unsigned int irq;
+ void __iomem *regs;
+ struct clk *clk;
+ struct device *dev;
+ spinlock_t lock; /* IRQ synchronization */
+
+ int err;
+ enum hix5hd2_i2c_state state;
+ enum hix5hd2_i2c_speed speed_mode;
+
+ /* Controller frequency */
+ unsigned int s_clock;
+};
+
+static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c *i2c)
+{
+ u32 val = readl_relaxed(i2c->regs + HIX5I2C_SR);
+
+ writel_relaxed(val, i2c->regs + HIX5I2C_ICR);
+
+ return val;
+}
+
+static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c *i2c)
+{
+ writel_relaxed(I2C_CLEAR_ALL, i2c->regs + HIX5I2C_ICR);
+}
+
+static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c *i2c)
+{
+ writel_relaxed(0, i2c->regs + HIX5I2C_CTRL);
+}
+
+static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c *i2c)
+{
+ writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL,
+ i2c->regs + HIX5I2C_CTRL);
+}
+
+static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c *i2c)
+{
+ u32 rate, val;
+ u32 sclh, scll, sysclock;
+
+ /* close all i2c interrupt */
+ val = readl_relaxed(i2c->regs + HIX5I2C_CTRL);
+ writel_relaxed(val & (~I2C_UNMASK_TOTAL), i2c->regs + HIX5I2C_CTRL);
+
+ rate = i2c->s_clock;
+ sysclock = clk_get_rate(i2c->clk);
+ sclh = (sysclock / (rate * 2)) / 2 - 1;
+ writel_relaxed(sclh, i2c->regs + HIX5I2C_SCL_H);
+ scll = (sysclock / (rate * 2)) / 2 - 1;
+ writel_relaxed(scll, i2c->regs + HIX5I2C_SCL_L);
+
+ /* restore original interrupt*/
+ writel_relaxed(val, i2c->regs + HIX5I2C_CTRL);
+
+ dev_dbg(i2c->dev, "%s: sysclock=%d, rate=%d, sclh=%d, scll=%d\n",
+ __func__, sysclock, rate, sclh, scll);
+}
+
+static void hix5hd2_i2c_init(struct hix5hd2_i2c *i2c)
+{
+ hix5hd2_i2c_disable_irq(i2c);
+ hix5hd2_i2c_drv_setrate(i2c);
+ hix5hd2_i2c_clr_all_irq(i2c);
+ hix5hd2_i2c_enable_irq(i2c);
+}
+
+static void hix5hd2_i2c_reset(struct hix5hd2_i2c *i2c)
+{
+ clk_disable_unprepare(i2c->clk);
+ msleep(20);
+ clk_prepare_enable(i2c->clk);
+ hix5hd2_i2c_init(i2c);
+}
+
+static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c *i2c)
+{
+ unsigned long stop_time;
+ u32 int_status;
+
+ /* wait for 100 milli seconds for the bus to be idle */
+ stop_time = jiffies + msecs_to_jiffies(100);
+ do {
+ int_status = hix5hd2_i2c_clr_pend_irq(i2c);
+ if (!(int_status & I2C_BUSY))
+ return 0;
+
+ usleep_range(50, 200);
+ } while (time_before(jiffies, stop_time));
+
+ return -EBUSY;
+}
+
+static void hix5hd2_rw_over(struct hix5hd2_i2c *i2c)
+{
+ if (HIX5I2C_STAT_SND_STOP == i2c->state)
+ dev_dbg(i2c->dev, "%s: rw and send stop over\n", __func__);
+ else
+ dev_dbg(i2c->dev, "%s: have not data to send\n", __func__);
+
+ i2c->state = HIX5I2C_STAT_RW_SUCCESS;
+ i2c->err = 0;
+}
+
+static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c *i2c)
+{
+ if (i2c->stop) {
+ i2c->state = HIX5I2C_STAT_SND_STOP;
+ writel_relaxed(I2C_STOP, i2c->regs + HIX5I2C_COM);
+ } else {
+ hix5hd2_rw_over(i2c);
+ }
+}
+
+static void hix5hd2_read_handle(struct hix5hd2_i2c *i2c)
+{
+ if (1 == i2c->len) {
+ /* the last byte don't need send ACK */
+ writel_relaxed(I2C_READ | I2C_NO_ACK, i2c->regs + HIX5I2C_COM);
+ } else if (i2c->len > 1) {
+ /* if i2c master receive data will send ACK */
+ writel_relaxed(I2C_READ, i2c->regs + HIX5I2C_COM);
+ } else {
+ hix5hd2_rw_handle_stop(i2c);
+ }
+}
+
+static void hix5hd2_write_handle(struct hix5hd2_i2c *i2c)
+{
+ u8 data;
+
+ if (i2c->len > 0) {
+ data = i2c->msg->buf[i2c->msg_ptr++];
+ writel_relaxed(data, i2c->regs + HIX5I2C_TXR);
+ writel_relaxed(I2C_WRITE, i2c->regs + HIX5I2C_COM);
+ } else {
+ hix5hd2_rw_handle_stop(i2c);
+ }
+}
+
+static int hix5hd2_rw_preprocess(struct hix5hd2_i2c *i2c)
+{
+ u8 data;
+
+ if (HIX5I2C_STAT_INIT == i2c->state) {
+ i2c->state = HIX5I2C_STAT_RW;
+ } else if (HIX5I2C_STAT_RW == i2c->state) {
+ if (i2c->msg->flags & I2C_M_RD) {
+ data = readl_relaxed(i2c->regs + HIX5I2C_RXR);
+ i2c->msg->buf[i2c->msg_ptr++] = data;
+ }
+ i2c->len--;
+ } else {
+ dev_dbg(i2c->dev, "%s: error: i2c->state = %d, len = %d\n",
+ __func__, i2c->state, i2c->len);
+ return -EAGAIN;
+ }
+ return 0;
+}
+
+static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id)
+{
+ struct hix5hd2_i2c *i2c = dev_id;
+ u32 int_status;
+ int ret;
+
+ spin_lock(&i2c->lock);
+
+ int_status = hix5hd2_i2c_clr_pend_irq(i2c);
+
+ /* handle error */
+ if (int_status & I2C_ARBITRATE_INTR) {
+ /*Bus error */
+ dev_dbg(i2c->dev, "ARB bus loss\n");
+ i2c->err = -ENXIO;
+ i2c->state = HIX5I2C_STAT_RW_ERR;
+ goto stop;
+ } else if (int_status & I2C_ACK_INTR) {
+ /* ack error */
+ dev_dbg(i2c->dev, "No ACK from device\n");
+ i2c->err = -ENXIO;
+ i2c->state = HIX5I2C_STAT_RW_ERR;
+ goto stop;
+ }
+
+ if (int_status & I2C_OVER_INTR) {
+ if (i2c->len > 0) {
+ ret = hix5hd2_rw_preprocess(i2c);
+ if (ret) {
+ i2c->err = ret;
+ i2c->state = HIX5I2C_STAT_RW_ERR;
+ goto stop;
+ }
+ if (i2c->msg->flags & I2C_M_RD)
+ hix5hd2_read_handle(i2c);
+ else
+ hix5hd2_write_handle(i2c);
+ } else {
+ hix5hd2_rw_over(i2c);
+ }
+ }
+
+stop:
+ if ((HIX5I2C_STAT_RW_SUCCESS == i2c->state &&
+ i2c->msg->len == i2c->msg_ptr) ||
+ (HIX5I2C_STAT_RW_ERR == i2c->state)) {
+ hix5hd2_i2c_disable_irq(i2c);
+ hix5hd2_i2c_clr_pend_irq(i2c);
+ complete(&i2c->msg_complete);
+ }
+
+ spin_unlock(&i2c->lock);
+
+ return IRQ_HANDLED;
+}
+
+static void hix5hd2_i2c_message_start(struct hix5hd2_i2c *i2c, int stop)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&i2c->lock, flags);
+ hix5hd2_i2c_clr_all_irq(i2c);
+ hix5hd2_i2c_enable_irq(i2c);
+
+ if (i2c->msg->flags & I2C_M_RD)
+ writel_relaxed(i2c->msg->addr | HIX5I2C_READ_OPERATION,
+ i2c->regs + HIX5I2C_TXR);
+ else
+ writel_relaxed(i2c->msg->addr & HIX5I2C_WRITE_OPERATION,
+ i2c->regs + HIX5I2C_TXR);
+
+ writel_relaxed(I2C_WRITE | I2C_START, i2c->regs + HIX5I2C_COM);
+ spin_unlock_irqrestore(&i2c->lock, flags);
+}
+
+static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c *i2c,
+ struct i2c_msg *msgs, int stop)
+{
+ unsigned long timeout;
+ int ret;
+
+ i2c->msg = msgs;
+ i2c->msg_ptr = 0;
+ i2c->len = i2c->msg->len;
+ i2c->stop = stop;
+ i2c->err = 0;
+ i2c->state = HIX5I2C_STAT_INIT;
+
+ reinit_completion(&i2c->msg_complete);
+ hix5hd2_i2c_message_start(i2c, stop);
+
+ timeout = wait_for_completion_timeout(&i2c->msg_complete,
+ i2c->adap.timeout);
+ if (timeout == 0) {
+ i2c->state = HIX5I2C_STAT_RW_ERR;
+ i2c->err = -ETIMEDOUT;
+ dev_warn(i2c->dev, "%s timeout=%d\n",
+ msgs->flags & I2C_M_RD ? "rx" : "tx",
+ i2c->adap.timeout);
+ }
+ ret = i2c->state;
+
+ /*
+ * If this is the last message to be transfered (stop == 1)
+ * Then check if the bus can be brought back to idle.
+ */
+ if (i2c->state == HIX5I2C_STAT_RW_SUCCESS && stop)
+ ret = hix5hd2_i2c_wait_bus_idle(i2c);
+
+ if (ret < 0)
+ hix5hd2_i2c_reset(i2c);
+
+ return i2c->err;
+}
+
+static int hix5hd2_i2c_xfer(struct i2c_adapter *adap,
+ struct i2c_msg *msgs, int num)
+{
+ struct hix5hd2_i2c *i2c = i2c_get_adapdata(adap);
+ int i, ret, stop;
+
+ pm_runtime_get_sync(i2c->dev);
+
+ for (i = 0; i < num; i++, msgs++) {
+ stop = (i == num - 1);
+ ret = hix5hd2_i2c_xfer_msg(i2c, msgs, stop);
+ if (ret < 0)
+ goto out;
+ }
+
+ if (i == num) {
+ ret = num;
+ } else {
+ /* Only one message, cannot access the device */
+ if (i == 1)
+ ret = -EREMOTEIO;
+ else
+ ret = i;
+
+ dev_warn(i2c->dev, "xfer message failed\n");
+ }
+
+out:
+ pm_runtime_mark_last_busy(i2c->dev);
+ pm_runtime_put_autosuspend(i2c->dev);
+ return ret;
+}
+
+static u32 hix5hd2_i2c_func(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
+}
+
+static const struct i2c_algorithm hix5hd2_i2c_algorithm = {
+ .master_xfer = hix5hd2_i2c_xfer,
+ .functionality = hix5hd2_i2c_func,
+};
+
+static int hix5hd2_i2c_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct hix5hd2_i2c *i2c;
+ struct resource *mem;
+ unsigned int op_clock;
+ int ret;
+
+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct hix5hd2_i2c), GFP_KERNEL);
+ if (!i2c)
+ return -ENOMEM;
+
+ if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
+ /* use default value */
+ i2c->speed_mode = HIX5I2C_HIG_SPD;
+ i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
+ } else {
+ if (op_clock >= HIX5I2C_HS_TX_CLOCK) {
+ i2c->speed_mode = HIX5I2C_HIG_SPD;
+ i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
+ } else {
+ i2c->speed_mode = HIX5I2C_NORMAL_SPD;
+ i2c->s_clock = op_clock;
+ }
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(i2c->regs))
+ return PTR_ERR(i2c->regs);
+
+ i2c->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(i2c->clk)) {
+ dev_err(&pdev->dev, "cannot get clock\n");
+ return -ENOENT;
+ }
+ clk_prepare_enable(i2c->clk);
+
+ i2c->irq = platform_get_irq(pdev, 0);
+ if (i2c->irq <= 0) {
+ dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
+ ret = -EINVAL;
+ goto err_clk;
+ }
+
+ strlcpy(i2c->adap.name, "hix5hd2-i2c", sizeof(i2c->adap.name));
+ i2c->dev = &pdev->dev;
+ i2c->adap.owner = THIS_MODULE;
+ i2c->adap.algo = &hix5hd2_i2c_algorithm;
+ i2c->adap.retries = 3;
+ i2c->adap.dev.of_node = np;
+ i2c->adap.algo_data = i2c;
+ i2c->adap.dev.parent = &pdev->dev;
+ i2c_set_adapdata(&i2c->adap, i2c);
+ platform_set_drvdata(pdev, i2c);
+ spin_lock_init(&i2c->lock);
+ init_completion(&i2c->msg_complete);
+
+ hix5hd2_i2c_init(i2c);
+
+ ret = devm_request_irq(&pdev->dev, i2c->irq, hix5hd2_i2c_irq,
+ IRQF_NO_SUSPEND | IRQF_ONESHOT,
+ dev_name(&pdev->dev), i2c);
+ if (ret != 0) {
+ dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
+ goto err_clk;
+ }
+
+ ret = i2c_add_adapter(&i2c->adap);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to add bus to i2c core\n");
+ goto err_clk;
+ }
+
+ pm_suspend_ignore_children(&pdev->dev, true);
+ pm_runtime_set_autosuspend_delay(i2c->dev, MSEC_PER_SEC);
+ pm_runtime_use_autosuspend(i2c->dev);
+ pm_runtime_set_active(i2c->dev);
+ pm_runtime_enable(i2c->dev);
+
+ return ret;
+
+err_clk:
+ clk_disable_unprepare(i2c->clk);
+ return ret;
+}
+
+static int hix5hd2_i2c_remove(struct platform_device *pdev)
+{
+ struct hix5hd2_i2c *i2c = platform_get_drvdata(pdev);
+
+ i2c_del_adapter(&i2c->adap);
+ pm_runtime_disable(i2c->dev);
+ pm_runtime_set_suspended(i2c->dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int hix5hd2_i2c_runtime_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct hix5hd2_i2c *i2c = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(i2c->clk);
+
+ return 0;
+}
+
+static int hix5hd2_i2c_runtime_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct hix5hd2_i2c *i2c = platform_get_drvdata(pdev);
+
+ clk_prepare_enable(i2c->clk);
+ hix5hd2_i2c_init(i2c);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops hix5hd2_i2c_pm_ops = {
+ SET_PM_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend,
+ hix5hd2_i2c_runtime_resume,
+ NULL)
+};
+
+static const struct of_device_id hix5hd2_i2c_match[] = {
+ { .compatible = "hisilicon,hix5hd2-i2c" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match);
+
+static struct platform_driver hix5hd2_i2c_driver = {
+ .probe = hix5hd2_i2c_probe,
+ .remove = hix5hd2_i2c_remove,
+ .driver = {
+ .name = "hix5hd2-i2c",
+ .pm = &hix5hd2_i2c_pm_ops,
+ .of_match_table = hix5hd2_i2c_match,
+ },
+};
+
+module_platform_driver(hix5hd2_i2c_driver);
+
+MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver");
+MODULE_AUTHOR("Wei Yan <sledge.yanwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:i2c-hix5hd2");
--
1.7.9.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH resend 2/2] i2c: hix5hd2: add i2c controller driver
@ 2014-08-26 5:25 ` Zhangfei Gao
0 siblings, 0 replies; 14+ messages in thread
From: Zhangfei Gao @ 2014-08-26 5:25 UTC (permalink / raw)
To: linux-arm-kernel
From: Wei Yan <sledge.yanwei@huawei.com>
I2C drivers for hix5hd2 soc series, including following chipset
Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100.
Signed-off-by: Wei Yan <sledge.yanwei@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/i2c/busses/Kconfig | 15 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-hix5hd2.c | 573 ++++++++++++++++++++++++++++++++++++++
3 files changed, 589 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2ac87fa..6c66b9e 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -77,6 +77,21 @@ config I2C_AMD8111
This driver can also be built as a module. If so, the module
will be called i2c-amd8111.
+config I2C_HIX5HD2
+ tristate "Hix5hd2 high-speed I2C driver"
+ help
+ Say Y here to include support for high-speed I2C controller in the
+ Hisilicon based hix5hd2 SoCs. Specifically, the following versions
+ of the chipset are supported:
+ Hi3716CV200 (support six I2C module)
+ Hi3719CV100 (support six I2C module)
+ Hi3718CV100 (support six I2C module)
+ Hi3719MV100 (support two I2C module)
+ Hi3718MV100 (support two I2C module)
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-hix5hd2.
+
config I2C_I801
tristate "Intel 82801 (ICH/PCH)"
depends on PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 49bf07e..9739938 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
+obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
obj-$(CONFIG_I2C_IMX) += i2c-imx.o
obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
diff --git a/drivers/i2c/busses/i2c-hix5hd2.c b/drivers/i2c/busses/i2c-hix5hd2.c
new file mode 100644
index 0000000..2f6b87c
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hix5hd2.c
@@ -0,0 +1,573 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ * Now only support 7 bit address.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+/* Register Map */
+#define HIX5I2C_CTRL 0x00
+#define HIX5I2C_COM 0x04
+#define HIX5I2C_ICR 0x08
+#define HIX5I2C_SR 0x0c
+#define HIX5I2C_SCL_H 0x10
+#define HIX5I2C_SCL_L 0x14
+#define HIX5I2C_TXR 0x18
+#define HIX5I2C_RXR 0x1c
+
+/* I2C_CTRL_REG */
+#define I2C_ENABLE BIT(8)
+#define I2C_UNMASK_TOTAL BIT(7)
+#define I2C_UNMASK_START BIT(6)
+#define I2C_UNMASK_END BIT(5)
+#define I2C_UNMASK_SEND BIT(4)
+#define I2C_UNMASK_RECEIVE BIT(3)
+#define I2C_UNMASK_ACK BIT(2)
+#define I2C_UNMASK_ARBITRATE BIT(1)
+#define I2C_UNMASK_OVER BIT(0)
+#define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
+
+/* I2C_COM_REG */
+#define I2C_NO_ACK BIT(4)
+#define I2C_START BIT(3)
+#define I2C_READ BIT(2)
+#define I2C_WRITE BIT(1)
+#define I2C_STOP BIT(0)
+
+/* I2C_ICR_REG */
+#define I2C_CLEAR_START BIT(6)
+#define I2C_CLEAR_END BIT(5)
+#define I2C_CLEAR_SEND BIT(4)
+#define I2C_CLEAR_RECEIVE BIT(3)
+#define I2C_CLEAR_ACK BIT(2)
+#define I2C_CLEAR_ARBITRATE BIT(1)
+#define I2C_CLEAR_OVER BIT(0)
+#define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \
+ I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
+ I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
+ I2C_CLEAR_OVER)
+
+/* I2C_SR_REG */
+#define I2C_BUSY BIT(7)
+#define I2C_START_INTR BIT(6)
+#define I2C_END_INTR BIT(5)
+#define I2C_SEND_INTR BIT(4)
+#define I2C_RECEIVE_INTR BIT(3)
+#define I2C_ACK_INTR BIT(2)
+#define I2C_ARBITRATE_INTR BIT(1)
+#define I2C_OVER_INTR BIT(0)
+
+/*
+ * Controller operating frequency, timing values for operation
+ * are calculated against this frequency
+ */
+#define HIX5I2C_NS_TX_CLOCK 100000 /* 100k */
+#define HIX5I2C_HS_TX_CLOCK 400000 /* 400k */
+
+#define HIX5I2C_READ_OPERATION 0x01
+#define HIX5I2C_WRITE_OPERATION 0xfe
+
+enum hix5hd2_i2c_state {
+ HIX5I2C_STAT_RW_ERR = -1,
+ HIX5I2C_STAT_INIT,
+ HIX5I2C_STAT_RW,
+ HIX5I2C_STAT_SND_STOP,
+ HIX5I2C_STAT_RW_SUCCESS,
+};
+
+enum hix5hd2_i2c_speed {
+ HIX5I2C_NORMAL_SPD, /* Fast speed upto 1Mbps */
+ HIX5I2C_HIG_SPD, /* High speed upto 3.4Mbps */
+};
+
+struct hix5hd2_i2c {
+ struct i2c_adapter adap;
+ struct i2c_msg *msg;
+ unsigned int msg_ptr; /* msg index */
+ unsigned int len; /* msg length */
+ int stop;
+ struct completion msg_complete;
+
+ unsigned int irq;
+ void __iomem *regs;
+ struct clk *clk;
+ struct device *dev;
+ spinlock_t lock; /* IRQ synchronization */
+
+ int err;
+ enum hix5hd2_i2c_state state;
+ enum hix5hd2_i2c_speed speed_mode;
+
+ /* Controller frequency */
+ unsigned int s_clock;
+};
+
+static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c *i2c)
+{
+ u32 val = readl_relaxed(i2c->regs + HIX5I2C_SR);
+
+ writel_relaxed(val, i2c->regs + HIX5I2C_ICR);
+
+ return val;
+}
+
+static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c *i2c)
+{
+ writel_relaxed(I2C_CLEAR_ALL, i2c->regs + HIX5I2C_ICR);
+}
+
+static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c *i2c)
+{
+ writel_relaxed(0, i2c->regs + HIX5I2C_CTRL);
+}
+
+static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c *i2c)
+{
+ writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL,
+ i2c->regs + HIX5I2C_CTRL);
+}
+
+static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c *i2c)
+{
+ u32 rate, val;
+ u32 sclh, scll, sysclock;
+
+ /* close all i2c interrupt */
+ val = readl_relaxed(i2c->regs + HIX5I2C_CTRL);
+ writel_relaxed(val & (~I2C_UNMASK_TOTAL), i2c->regs + HIX5I2C_CTRL);
+
+ rate = i2c->s_clock;
+ sysclock = clk_get_rate(i2c->clk);
+ sclh = (sysclock / (rate * 2)) / 2 - 1;
+ writel_relaxed(sclh, i2c->regs + HIX5I2C_SCL_H);
+ scll = (sysclock / (rate * 2)) / 2 - 1;
+ writel_relaxed(scll, i2c->regs + HIX5I2C_SCL_L);
+
+ /* restore original interrupt*/
+ writel_relaxed(val, i2c->regs + HIX5I2C_CTRL);
+
+ dev_dbg(i2c->dev, "%s: sysclock=%d, rate=%d, sclh=%d, scll=%d\n",
+ __func__, sysclock, rate, sclh, scll);
+}
+
+static void hix5hd2_i2c_init(struct hix5hd2_i2c *i2c)
+{
+ hix5hd2_i2c_disable_irq(i2c);
+ hix5hd2_i2c_drv_setrate(i2c);
+ hix5hd2_i2c_clr_all_irq(i2c);
+ hix5hd2_i2c_enable_irq(i2c);
+}
+
+static void hix5hd2_i2c_reset(struct hix5hd2_i2c *i2c)
+{
+ clk_disable_unprepare(i2c->clk);
+ msleep(20);
+ clk_prepare_enable(i2c->clk);
+ hix5hd2_i2c_init(i2c);
+}
+
+static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c *i2c)
+{
+ unsigned long stop_time;
+ u32 int_status;
+
+ /* wait for 100 milli seconds for the bus to be idle */
+ stop_time = jiffies + msecs_to_jiffies(100);
+ do {
+ int_status = hix5hd2_i2c_clr_pend_irq(i2c);
+ if (!(int_status & I2C_BUSY))
+ return 0;
+
+ usleep_range(50, 200);
+ } while (time_before(jiffies, stop_time));
+
+ return -EBUSY;
+}
+
+static void hix5hd2_rw_over(struct hix5hd2_i2c *i2c)
+{
+ if (HIX5I2C_STAT_SND_STOP == i2c->state)
+ dev_dbg(i2c->dev, "%s: rw and send stop over\n", __func__);
+ else
+ dev_dbg(i2c->dev, "%s: have not data to send\n", __func__);
+
+ i2c->state = HIX5I2C_STAT_RW_SUCCESS;
+ i2c->err = 0;
+}
+
+static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c *i2c)
+{
+ if (i2c->stop) {
+ i2c->state = HIX5I2C_STAT_SND_STOP;
+ writel_relaxed(I2C_STOP, i2c->regs + HIX5I2C_COM);
+ } else {
+ hix5hd2_rw_over(i2c);
+ }
+}
+
+static void hix5hd2_read_handle(struct hix5hd2_i2c *i2c)
+{
+ if (1 == i2c->len) {
+ /* the last byte don't need send ACK */
+ writel_relaxed(I2C_READ | I2C_NO_ACK, i2c->regs + HIX5I2C_COM);
+ } else if (i2c->len > 1) {
+ /* if i2c master receive data will send ACK */
+ writel_relaxed(I2C_READ, i2c->regs + HIX5I2C_COM);
+ } else {
+ hix5hd2_rw_handle_stop(i2c);
+ }
+}
+
+static void hix5hd2_write_handle(struct hix5hd2_i2c *i2c)
+{
+ u8 data;
+
+ if (i2c->len > 0) {
+ data = i2c->msg->buf[i2c->msg_ptr++];
+ writel_relaxed(data, i2c->regs + HIX5I2C_TXR);
+ writel_relaxed(I2C_WRITE, i2c->regs + HIX5I2C_COM);
+ } else {
+ hix5hd2_rw_handle_stop(i2c);
+ }
+}
+
+static int hix5hd2_rw_preprocess(struct hix5hd2_i2c *i2c)
+{
+ u8 data;
+
+ if (HIX5I2C_STAT_INIT == i2c->state) {
+ i2c->state = HIX5I2C_STAT_RW;
+ } else if (HIX5I2C_STAT_RW == i2c->state) {
+ if (i2c->msg->flags & I2C_M_RD) {
+ data = readl_relaxed(i2c->regs + HIX5I2C_RXR);
+ i2c->msg->buf[i2c->msg_ptr++] = data;
+ }
+ i2c->len--;
+ } else {
+ dev_dbg(i2c->dev, "%s: error: i2c->state = %d, len = %d\n",
+ __func__, i2c->state, i2c->len);
+ return -EAGAIN;
+ }
+ return 0;
+}
+
+static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id)
+{
+ struct hix5hd2_i2c *i2c = dev_id;
+ u32 int_status;
+ int ret;
+
+ spin_lock(&i2c->lock);
+
+ int_status = hix5hd2_i2c_clr_pend_irq(i2c);
+
+ /* handle error */
+ if (int_status & I2C_ARBITRATE_INTR) {
+ /*Bus error */
+ dev_dbg(i2c->dev, "ARB bus loss\n");
+ i2c->err = -ENXIO;
+ i2c->state = HIX5I2C_STAT_RW_ERR;
+ goto stop;
+ } else if (int_status & I2C_ACK_INTR) {
+ /* ack error */
+ dev_dbg(i2c->dev, "No ACK from device\n");
+ i2c->err = -ENXIO;
+ i2c->state = HIX5I2C_STAT_RW_ERR;
+ goto stop;
+ }
+
+ if (int_status & I2C_OVER_INTR) {
+ if (i2c->len > 0) {
+ ret = hix5hd2_rw_preprocess(i2c);
+ if (ret) {
+ i2c->err = ret;
+ i2c->state = HIX5I2C_STAT_RW_ERR;
+ goto stop;
+ }
+ if (i2c->msg->flags & I2C_M_RD)
+ hix5hd2_read_handle(i2c);
+ else
+ hix5hd2_write_handle(i2c);
+ } else {
+ hix5hd2_rw_over(i2c);
+ }
+ }
+
+stop:
+ if ((HIX5I2C_STAT_RW_SUCCESS == i2c->state &&
+ i2c->msg->len == i2c->msg_ptr) ||
+ (HIX5I2C_STAT_RW_ERR == i2c->state)) {
+ hix5hd2_i2c_disable_irq(i2c);
+ hix5hd2_i2c_clr_pend_irq(i2c);
+ complete(&i2c->msg_complete);
+ }
+
+ spin_unlock(&i2c->lock);
+
+ return IRQ_HANDLED;
+}
+
+static void hix5hd2_i2c_message_start(struct hix5hd2_i2c *i2c, int stop)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&i2c->lock, flags);
+ hix5hd2_i2c_clr_all_irq(i2c);
+ hix5hd2_i2c_enable_irq(i2c);
+
+ if (i2c->msg->flags & I2C_M_RD)
+ writel_relaxed(i2c->msg->addr | HIX5I2C_READ_OPERATION,
+ i2c->regs + HIX5I2C_TXR);
+ else
+ writel_relaxed(i2c->msg->addr & HIX5I2C_WRITE_OPERATION,
+ i2c->regs + HIX5I2C_TXR);
+
+ writel_relaxed(I2C_WRITE | I2C_START, i2c->regs + HIX5I2C_COM);
+ spin_unlock_irqrestore(&i2c->lock, flags);
+}
+
+static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c *i2c,
+ struct i2c_msg *msgs, int stop)
+{
+ unsigned long timeout;
+ int ret;
+
+ i2c->msg = msgs;
+ i2c->msg_ptr = 0;
+ i2c->len = i2c->msg->len;
+ i2c->stop = stop;
+ i2c->err = 0;
+ i2c->state = HIX5I2C_STAT_INIT;
+
+ reinit_completion(&i2c->msg_complete);
+ hix5hd2_i2c_message_start(i2c, stop);
+
+ timeout = wait_for_completion_timeout(&i2c->msg_complete,
+ i2c->adap.timeout);
+ if (timeout == 0) {
+ i2c->state = HIX5I2C_STAT_RW_ERR;
+ i2c->err = -ETIMEDOUT;
+ dev_warn(i2c->dev, "%s timeout=%d\n",
+ msgs->flags & I2C_M_RD ? "rx" : "tx",
+ i2c->adap.timeout);
+ }
+ ret = i2c->state;
+
+ /*
+ * If this is the last message to be transfered (stop == 1)
+ * Then check if the bus can be brought back to idle.
+ */
+ if (i2c->state == HIX5I2C_STAT_RW_SUCCESS && stop)
+ ret = hix5hd2_i2c_wait_bus_idle(i2c);
+
+ if (ret < 0)
+ hix5hd2_i2c_reset(i2c);
+
+ return i2c->err;
+}
+
+static int hix5hd2_i2c_xfer(struct i2c_adapter *adap,
+ struct i2c_msg *msgs, int num)
+{
+ struct hix5hd2_i2c *i2c = i2c_get_adapdata(adap);
+ int i, ret, stop;
+
+ pm_runtime_get_sync(i2c->dev);
+
+ for (i = 0; i < num; i++, msgs++) {
+ stop = (i == num - 1);
+ ret = hix5hd2_i2c_xfer_msg(i2c, msgs, stop);
+ if (ret < 0)
+ goto out;
+ }
+
+ if (i == num) {
+ ret = num;
+ } else {
+ /* Only one message, cannot access the device */
+ if (i == 1)
+ ret = -EREMOTEIO;
+ else
+ ret = i;
+
+ dev_warn(i2c->dev, "xfer message failed\n");
+ }
+
+out:
+ pm_runtime_mark_last_busy(i2c->dev);
+ pm_runtime_put_autosuspend(i2c->dev);
+ return ret;
+}
+
+static u32 hix5hd2_i2c_func(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
+}
+
+static const struct i2c_algorithm hix5hd2_i2c_algorithm = {
+ .master_xfer = hix5hd2_i2c_xfer,
+ .functionality = hix5hd2_i2c_func,
+};
+
+static int hix5hd2_i2c_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct hix5hd2_i2c *i2c;
+ struct resource *mem;
+ unsigned int op_clock;
+ int ret;
+
+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct hix5hd2_i2c), GFP_KERNEL);
+ if (!i2c)
+ return -ENOMEM;
+
+ if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
+ /* use default value */
+ i2c->speed_mode = HIX5I2C_HIG_SPD;
+ i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
+ } else {
+ if (op_clock >= HIX5I2C_HS_TX_CLOCK) {
+ i2c->speed_mode = HIX5I2C_HIG_SPD;
+ i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
+ } else {
+ i2c->speed_mode = HIX5I2C_NORMAL_SPD;
+ i2c->s_clock = op_clock;
+ }
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(i2c->regs))
+ return PTR_ERR(i2c->regs);
+
+ i2c->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(i2c->clk)) {
+ dev_err(&pdev->dev, "cannot get clock\n");
+ return -ENOENT;
+ }
+ clk_prepare_enable(i2c->clk);
+
+ i2c->irq = platform_get_irq(pdev, 0);
+ if (i2c->irq <= 0) {
+ dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
+ ret = -EINVAL;
+ goto err_clk;
+ }
+
+ strlcpy(i2c->adap.name, "hix5hd2-i2c", sizeof(i2c->adap.name));
+ i2c->dev = &pdev->dev;
+ i2c->adap.owner = THIS_MODULE;
+ i2c->adap.algo = &hix5hd2_i2c_algorithm;
+ i2c->adap.retries = 3;
+ i2c->adap.dev.of_node = np;
+ i2c->adap.algo_data = i2c;
+ i2c->adap.dev.parent = &pdev->dev;
+ i2c_set_adapdata(&i2c->adap, i2c);
+ platform_set_drvdata(pdev, i2c);
+ spin_lock_init(&i2c->lock);
+ init_completion(&i2c->msg_complete);
+
+ hix5hd2_i2c_init(i2c);
+
+ ret = devm_request_irq(&pdev->dev, i2c->irq, hix5hd2_i2c_irq,
+ IRQF_NO_SUSPEND | IRQF_ONESHOT,
+ dev_name(&pdev->dev), i2c);
+ if (ret != 0) {
+ dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
+ goto err_clk;
+ }
+
+ ret = i2c_add_adapter(&i2c->adap);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to add bus to i2c core\n");
+ goto err_clk;
+ }
+
+ pm_suspend_ignore_children(&pdev->dev, true);
+ pm_runtime_set_autosuspend_delay(i2c->dev, MSEC_PER_SEC);
+ pm_runtime_use_autosuspend(i2c->dev);
+ pm_runtime_set_active(i2c->dev);
+ pm_runtime_enable(i2c->dev);
+
+ return ret;
+
+err_clk:
+ clk_disable_unprepare(i2c->clk);
+ return ret;
+}
+
+static int hix5hd2_i2c_remove(struct platform_device *pdev)
+{
+ struct hix5hd2_i2c *i2c = platform_get_drvdata(pdev);
+
+ i2c_del_adapter(&i2c->adap);
+ pm_runtime_disable(i2c->dev);
+ pm_runtime_set_suspended(i2c->dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int hix5hd2_i2c_runtime_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct hix5hd2_i2c *i2c = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(i2c->clk);
+
+ return 0;
+}
+
+static int hix5hd2_i2c_runtime_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct hix5hd2_i2c *i2c = platform_get_drvdata(pdev);
+
+ clk_prepare_enable(i2c->clk);
+ hix5hd2_i2c_init(i2c);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops hix5hd2_i2c_pm_ops = {
+ SET_PM_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend,
+ hix5hd2_i2c_runtime_resume,
+ NULL)
+};
+
+static const struct of_device_id hix5hd2_i2c_match[] = {
+ { .compatible = "hisilicon,hix5hd2-i2c" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match);
+
+static struct platform_driver hix5hd2_i2c_driver = {
+ .probe = hix5hd2_i2c_probe,
+ .remove = hix5hd2_i2c_remove,
+ .driver = {
+ .name = "hix5hd2-i2c",
+ .pm = &hix5hd2_i2c_pm_ops,
+ .of_match_table = hix5hd2_i2c_match,
+ },
+};
+
+module_platform_driver(hix5hd2_i2c_driver);
+
+MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver");
+MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:i2c-hix5hd2");
--
1.7.9.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH resend 0/2] i2c: hix5hd2: add i2c controller driver
2014-08-26 5:25 ` Zhangfei Gao
@ 2014-09-15 19:56 ` Zhangfei Gao
-1 siblings, 0 replies; 14+ messages in thread
From: Zhangfei Gao @ 2014-09-15 19:56 UTC (permalink / raw)
To: Wolfram Sang, Arnd Bergmann, Haifeng Yan, Jason Xue
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, Zhangfei Gao
On 26 August 2014 13:25, Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> Resend: verified on 3.17-rc1
>
> Wei Yan (2):
> i2c: hix5hd2: add devicetree documentation
> i2c: hix5hd2: add i2c controller driver
>
> .../devicetree/bindings/i2c/i2c-hix5hd2.txt | 31 ++
> drivers/i2c/busses/Kconfig | 16 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-hix5hd2.c | 576 ++++++++++++++++++++
> 4 files changed, 624 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
> create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c
>
Any comments, thanks a lot.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH resend 0/2] i2c: hix5hd2: add i2c controller driver
@ 2014-09-15 19:56 ` Zhangfei Gao
0 siblings, 0 replies; 14+ messages in thread
From: Zhangfei Gao @ 2014-09-15 19:56 UTC (permalink / raw)
To: linux-arm-kernel
On 26 August 2014 13:25, Zhangfei Gao <zhangfei.gao@linaro.org> wrote:
> Resend: verified on 3.17-rc1
>
> Wei Yan (2):
> i2c: hix5hd2: add devicetree documentation
> i2c: hix5hd2: add i2c controller driver
>
> .../devicetree/bindings/i2c/i2c-hix5hd2.txt | 31 ++
> drivers/i2c/busses/Kconfig | 16 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-hix5hd2.c | 576 ++++++++++++++++++++
> 4 files changed, 624 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
> create mode 100644 drivers/i2c/busses/i2c-hix5hd2.c
>
Any comments, thanks a lot.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH resend 2/2] i2c: hix5hd2: add i2c controller driver
2014-08-26 5:25 ` Zhangfei Gao
@ 2014-09-19 17:18 ` Wolfram Sang
-1 siblings, 0 replies; 14+ messages in thread
From: Wolfram Sang @ 2014-09-19 17:18 UTC (permalink / raw)
To: Zhangfei Gao
Cc: Arnd Bergmann, haifeng.yan-QSEj5FYQhm4dnm+yROfE0A,
jchxue-Re5JQEeQqe8AvxtiuMwx3w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, Wei Yan
Hi,
thanks for the submission.
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-hix5hd2.c
> @@ -0,0 +1,573 @@
> +/*
> + * Copyright (c) 2014 Linaro Ltd.
> + * Copyright (c) 2014 Hisilicon Limited.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
"publishhed"
> + *
> + * Now only support 7 bit address.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/i2c.h>
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
I think there should be at least of.h, too.
> +struct hix5hd2_i2c {
> + struct i2c_adapter adap;
> + struct i2c_msg *msg;
> + unsigned int msg_ptr; /* msg index */
Comment seems wrong. It looks to me as the msg buffer index. If so, the
variable name is also confusing.
> + unsigned int len; /* msg length */
> + int stop;
> + struct completion msg_complete;
> +
> + unsigned int irq;
That can be a local variable.
> + void __iomem *regs;
> + struct clk *clk;
> + struct device *dev;
> + spinlock_t lock; /* IRQ synchronization */
> +
> + int err;
> + enum hix5hd2_i2c_state state;
> + enum hix5hd2_i2c_speed speed_mode;
Where is this needed?
> +
> + /* Controller frequency */
> + unsigned int s_clock;
> +};
> +
> +static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c *i2c)
> +{
> + u32 rate, val;
> + u32 sclh, scll, sysclock;
> +
> + /* close all i2c interrupt */
> + val = readl_relaxed(i2c->regs + HIX5I2C_CTRL);
> + writel_relaxed(val & (~I2C_UNMASK_TOTAL), i2c->regs + HIX5I2C_CTRL);
> +
> + rate = i2c->s_clock;
> + sysclock = clk_get_rate(i2c->clk);
> + sclh = (sysclock / (rate * 2)) / 2 - 1;
> + writel_relaxed(sclh, i2c->regs + HIX5I2C_SCL_H);
> + scll = (sysclock / (rate * 2)) / 2 - 1;
scll and sclh use the same formula? Have you measured the setup
frequency with a scope?
> + writel_relaxed(scll, i2c->regs + HIX5I2C_SCL_L);
> +
> + /* restore original interrupt*/
> + writel_relaxed(val, i2c->regs + HIX5I2C_CTRL);
> +
> + dev_dbg(i2c->dev, "%s: sysclock=%d, rate=%d, sclh=%d, scll=%d\n",
> + __func__, sysclock, rate, sclh, scll);
> +}
> +
> +static void hix5hd2_rw_over(struct hix5hd2_i2c *i2c)
> +{
> + if (HIX5I2C_STAT_SND_STOP == i2c->state)
To be honest, I don't like having the constant on the left side. It
is far easier to read if they are on the right side. Plus, we have gcc
warnings to prevent the "=" and "==" mistake. Please switch them around
in this driver.
> + dev_dbg(i2c->dev, "%s: rw and send stop over\n", __func__);
> + else
> + dev_dbg(i2c->dev, "%s: have not data to send\n", __func__);
> +
> + i2c->state = HIX5I2C_STAT_RW_SUCCESS;
> + i2c->err = 0;
> +}
> +
...
> + /* handle error */
> + if (int_status & I2C_ARBITRATE_INTR) {
> + /*Bus error */
Space missing in front of "Bus". If this is an arbitration lost error,
then please use -EAGAIN. Check Documentation/i2c/fault-codes for the
convention.
> + dev_dbg(i2c->dev, "ARB bus loss\n");
> + i2c->err = -ENXIO;
> + i2c->state = HIX5I2C_STAT_RW_ERR;
> + goto stop;
> + } else if (int_status & I2C_ACK_INTR) {
> + /* ack error */
> + dev_dbg(i2c->dev, "No ACK from device\n");
> + i2c->err = -ENXIO;
> + i2c->state = HIX5I2C_STAT_RW_ERR;
> + goto stop;
> + }
> +
> +static void hix5hd2_i2c_message_start(struct hix5hd2_i2c *i2c, int stop)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&i2c->lock, flags);
> + hix5hd2_i2c_clr_all_irq(i2c);
> + hix5hd2_i2c_enable_irq(i2c);
> +
> + if (i2c->msg->flags & I2C_M_RD)
> + writel_relaxed(i2c->msg->addr | HIX5I2C_READ_OPERATION,
> + i2c->regs + HIX5I2C_TXR);
> + else
> + writel_relaxed(i2c->msg->addr & HIX5I2C_WRITE_OPERATION,
> + i2c->regs + HIX5I2C_TXR);
??? Does this really work? i2c->msg->addr should be left shifted by 1?
> +
> + writel_relaxed(I2C_WRITE | I2C_START, i2c->regs + HIX5I2C_COM);
> + spin_unlock_irqrestore(&i2c->lock, flags);
> +}
> +
> +static int hix5hd2_i2c_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct hix5hd2_i2c *i2c;
> + struct resource *mem;
> + unsigned int op_clock;
> + int ret;
> +
> + i2c = devm_kzalloc(&pdev->dev, sizeof(struct hix5hd2_i2c), GFP_KERNEL);
> + if (!i2c)
> + return -ENOMEM;
> +
> + if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
> + /* use default value */
> + i2c->speed_mode = HIX5I2C_HIG_SPD;
> + i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
Please use 100kHz as the default. This is the speed devices should
support. 400kHz is optional. And I think 100000 is easier to read than a
define.
> + } else {
> + if (op_clock >= HIX5I2C_HS_TX_CLOCK) {
> + i2c->speed_mode = HIX5I2C_HIG_SPD;
> + i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
So, if the speed is bigger than 400kHz, it will be capped down to
400kHz? Is that true? Then, the user should be informed about that.
> + } else {
> + i2c->speed_mode = HIX5I2C_NORMAL_SPD;
> + i2c->s_clock = op_clock;
> + }
> + }
> +
...
> + i2c->adap.owner = THIS_MODULE;
> + i2c->adap.algo = &hix5hd2_i2c_algorithm;
Single space as indentation.
Thanks,
Wolfram
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH resend 2/2] i2c: hix5hd2: add i2c controller driver
@ 2014-09-19 17:18 ` Wolfram Sang
0 siblings, 0 replies; 14+ messages in thread
From: Wolfram Sang @ 2014-09-19 17:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
thanks for the submission.
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-hix5hd2.c
> @@ -0,0 +1,573 @@
> +/*
> + * Copyright (c) 2014 Linaro Ltd.
> + * Copyright (c) 2014 Hisilicon Limited.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
"publishhed"
> + *
> + * Now only support 7 bit address.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/i2c.h>
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
I think there should be at least of.h, too.
> +struct hix5hd2_i2c {
> + struct i2c_adapter adap;
> + struct i2c_msg *msg;
> + unsigned int msg_ptr; /* msg index */
Comment seems wrong. It looks to me as the msg buffer index. If so, the
variable name is also confusing.
> + unsigned int len; /* msg length */
> + int stop;
> + struct completion msg_complete;
> +
> + unsigned int irq;
That can be a local variable.
> + void __iomem *regs;
> + struct clk *clk;
> + struct device *dev;
> + spinlock_t lock; /* IRQ synchronization */
> +
> + int err;
> + enum hix5hd2_i2c_state state;
> + enum hix5hd2_i2c_speed speed_mode;
Where is this needed?
> +
> + /* Controller frequency */
> + unsigned int s_clock;
> +};
> +
> +static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c *i2c)
> +{
> + u32 rate, val;
> + u32 sclh, scll, sysclock;
> +
> + /* close all i2c interrupt */
> + val = readl_relaxed(i2c->regs + HIX5I2C_CTRL);
> + writel_relaxed(val & (~I2C_UNMASK_TOTAL), i2c->regs + HIX5I2C_CTRL);
> +
> + rate = i2c->s_clock;
> + sysclock = clk_get_rate(i2c->clk);
> + sclh = (sysclock / (rate * 2)) / 2 - 1;
> + writel_relaxed(sclh, i2c->regs + HIX5I2C_SCL_H);
> + scll = (sysclock / (rate * 2)) / 2 - 1;
scll and sclh use the same formula? Have you measured the setup
frequency with a scope?
> + writel_relaxed(scll, i2c->regs + HIX5I2C_SCL_L);
> +
> + /* restore original interrupt*/
> + writel_relaxed(val, i2c->regs + HIX5I2C_CTRL);
> +
> + dev_dbg(i2c->dev, "%s: sysclock=%d, rate=%d, sclh=%d, scll=%d\n",
> + __func__, sysclock, rate, sclh, scll);
> +}
> +
> +static void hix5hd2_rw_over(struct hix5hd2_i2c *i2c)
> +{
> + if (HIX5I2C_STAT_SND_STOP == i2c->state)
To be honest, I don't like having the constant on the left side. It
is far easier to read if they are on the right side. Plus, we have gcc
warnings to prevent the "=" and "==" mistake. Please switch them around
in this driver.
> + dev_dbg(i2c->dev, "%s: rw and send stop over\n", __func__);
> + else
> + dev_dbg(i2c->dev, "%s: have not data to send\n", __func__);
> +
> + i2c->state = HIX5I2C_STAT_RW_SUCCESS;
> + i2c->err = 0;
> +}
> +
...
> + /* handle error */
> + if (int_status & I2C_ARBITRATE_INTR) {
> + /*Bus error */
Space missing in front of "Bus". If this is an arbitration lost error,
then please use -EAGAIN. Check Documentation/i2c/fault-codes for the
convention.
> + dev_dbg(i2c->dev, "ARB bus loss\n");
> + i2c->err = -ENXIO;
> + i2c->state = HIX5I2C_STAT_RW_ERR;
> + goto stop;
> + } else if (int_status & I2C_ACK_INTR) {
> + /* ack error */
> + dev_dbg(i2c->dev, "No ACK from device\n");
> + i2c->err = -ENXIO;
> + i2c->state = HIX5I2C_STAT_RW_ERR;
> + goto stop;
> + }
> +
> +static void hix5hd2_i2c_message_start(struct hix5hd2_i2c *i2c, int stop)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&i2c->lock, flags);
> + hix5hd2_i2c_clr_all_irq(i2c);
> + hix5hd2_i2c_enable_irq(i2c);
> +
> + if (i2c->msg->flags & I2C_M_RD)
> + writel_relaxed(i2c->msg->addr | HIX5I2C_READ_OPERATION,
> + i2c->regs + HIX5I2C_TXR);
> + else
> + writel_relaxed(i2c->msg->addr & HIX5I2C_WRITE_OPERATION,
> + i2c->regs + HIX5I2C_TXR);
??? Does this really work? i2c->msg->addr should be left shifted by 1?
> +
> + writel_relaxed(I2C_WRITE | I2C_START, i2c->regs + HIX5I2C_COM);
> + spin_unlock_irqrestore(&i2c->lock, flags);
> +}
> +
> +static int hix5hd2_i2c_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct hix5hd2_i2c *i2c;
> + struct resource *mem;
> + unsigned int op_clock;
> + int ret;
> +
> + i2c = devm_kzalloc(&pdev->dev, sizeof(struct hix5hd2_i2c), GFP_KERNEL);
> + if (!i2c)
> + return -ENOMEM;
> +
> + if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
> + /* use default value */
> + i2c->speed_mode = HIX5I2C_HIG_SPD;
> + i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
Please use 100kHz as the default. This is the speed devices should
support. 400kHz is optional. And I think 100000 is easier to read than a
define.
> + } else {
> + if (op_clock >= HIX5I2C_HS_TX_CLOCK) {
> + i2c->speed_mode = HIX5I2C_HIG_SPD;
> + i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
So, if the speed is bigger than 400kHz, it will be capped down to
400kHz? Is that true? Then, the user should be informed about that.
> + } else {
> + i2c->speed_mode = HIX5I2C_NORMAL_SPD;
> + i2c->s_clock = op_clock;
> + }
> + }
> +
...
> + i2c->adap.owner = THIS_MODULE;
> + i2c->adap.algo = &hix5hd2_i2c_algorithm;
Single space as indentation.
Thanks,
Wolfram
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH resend 2/2] i2c: hix5hd2: add i2c controller driver
2014-09-19 17:18 ` Wolfram Sang
@ 2014-09-26 3:30 ` zhangfei
-1 siblings, 0 replies; 14+ messages in thread
From: zhangfei @ 2014-09-26 3:30 UTC (permalink / raw)
To: Wolfram Sang
Cc: Arnd Bergmann, haifeng.yan-QSEj5FYQhm4dnm+yROfE0A,
jchxue-Re5JQEeQqe8AvxtiuMwx3w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, Wei Yan
Thanks Wolfram for the careful review
On 09/20/2014 01:18 AM, Wolfram Sang wrote:
> Hi,
>
> thanks for the submission.
>
>> --- /dev/null
>> +++ b/drivers/i2c/busses/i2c-hix5hd2.c
>> @@ -0,0 +1,573 @@
>> +/*
>> + * Copyright (c) 2014 Linaro Ltd.
>> + * Copyright (c) 2014 Hisilicon Limited.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * publishhed by the Free Software Foundation.
>
> "publishhed"
OK.
>
>> + *
>> + * Now only support 7 bit address.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/i2c.h>
>> +#include <linux/io.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_runtime.h>
>
> I think there should be at least of.h, too.
The of.h is already in i2c.h
include/linux/i2c.h:33:#include <linux/of.h>
>
>> +struct hix5hd2_i2c {
>> + struct i2c_adapter adap;
>> + struct i2c_msg *msg;
>> + unsigned int msg_ptr; /* msg index */
>
> Comment seems wrong. It looks to me as the msg buffer index. If so, the
> variable name is also confusing.
Change to msg_idx & msg_len.
>
>> + unsigned int len; /* msg length */
>> + int stop;
>> + struct completion msg_complete;
>> +
>> + unsigned int irq;
>
> That can be a local variable.
Yes
>
>> + void __iomem *regs;
>> + struct clk *clk;
>> + struct device *dev;
>> + spinlock_t lock; /* IRQ synchronization */
>> +
>> + int err;
>> + enum hix5hd2_i2c_state state;
>> + enum hix5hd2_i2c_speed speed_mode;
>
> Where is this needed?
will remove
>
>> +
>> + /* Controller frequency */
>> + unsigned int s_clock;
>> +};
>> +
>> +static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c *i2c)
>> +{
>> + u32 rate, val;
>> + u32 sclh, scll, sysclock;
>> +
>> + /* close all i2c interrupt */
>> + val = readl_relaxed(i2c->regs + HIX5I2C_CTRL);
>> + writel_relaxed(val & (~I2C_UNMASK_TOTAL), i2c->regs + HIX5I2C_CTRL);
>> +
>> + rate = i2c->s_clock;
>> + sysclock = clk_get_rate(i2c->clk);
>> + sclh = (sysclock / (rate * 2)) / 2 - 1;
>> + writel_relaxed(sclh, i2c->regs + HIX5I2C_SCL_H);
>> + scll = (sysclock / (rate * 2)) / 2 - 1;
>
> scll and sclh use the same formula? Have you measured the setup
> frequency with a scope?
Yes, it is confusing, will use the same vector scl instead.
The value is same means sclk high voltage and low voltage keep same time.
>
>> + writel_relaxed(scll, i2c->regs + HIX5I2C_SCL_L);
>> +
>> + /* restore original interrupt*/
>> + writel_relaxed(val, i2c->regs + HIX5I2C_CTRL);
>> +
>> + dev_dbg(i2c->dev, "%s: sysclock=%d, rate=%d, sclh=%d, scll=%d\n",
>> + __func__, sysclock, rate, sclh, scll);
>> +}
>> +
>> +static void hix5hd2_rw_over(struct hix5hd2_i2c *i2c)
>> +{
>> + if (HIX5I2C_STAT_SND_STOP == i2c->state)
>
> To be honest, I don't like having the constant on the left side. It
> is far easier to read if they are on the right side. Plus, we have gcc
> warnings to prevent the "=" and "==" mistake. Please switch them around
> in this driver.
Got it.
>
>> + dev_dbg(i2c->dev, "%s: rw and send stop over\n", __func__);
>> + else
>> + dev_dbg(i2c->dev, "%s: have not data to send\n", __func__);
>> +
>> + i2c->state = HIX5I2C_STAT_RW_SUCCESS;
>> + i2c->err = 0;
>> +}
>> +
>
> ...
>
>> + /* handle error */
>> + if (int_status & I2C_ARBITRATE_INTR) {
>> + /*Bus error */
>
> Space missing in front of "Bus". If this is an arbitration lost error,
> then please use -EAGAIN. Check Documentation/i2c/fault-codes for the
> convention.
OK.
>
>> + dev_dbg(i2c->dev, "ARB bus loss\n");
>> + i2c->err = -ENXIO;
>> + i2c->state = HIX5I2C_STAT_RW_ERR;
>> + goto stop;
>> + } else if (int_status & I2C_ACK_INTR) {
>> + /* ack error */
>> + dev_dbg(i2c->dev, "No ACK from device\n");
>> + i2c->err = -ENXIO;
>> + i2c->state = HIX5I2C_STAT_RW_ERR;
>> + goto stop;
>> + }
>> +
>> +static void hix5hd2_i2c_message_start(struct hix5hd2_i2c *i2c, int stop)
>> +{
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&i2c->lock, flags);
>> + hix5hd2_i2c_clr_all_irq(i2c);
>> + hix5hd2_i2c_enable_irq(i2c);
>> +
>> + if (i2c->msg->flags & I2C_M_RD)
>> + writel_relaxed(i2c->msg->addr | HIX5I2C_READ_OPERATION,
>> + i2c->regs + HIX5I2C_TXR);
>> + else
>> + writel_relaxed(i2c->msg->addr & HIX5I2C_WRITE_OPERATION,
>> + i2c->regs + HIX5I2C_TXR);
>
> ??? Does this really work? i2c->msg->addr should be left shifted by 1?
Double checked, it is because the test applictaion do the left shift.
Yes, will do the left shift by 1.
>
>> +
>> + writel_relaxed(I2C_WRITE | I2C_START, i2c->regs + HIX5I2C_COM);
>> + spin_unlock_irqrestore(&i2c->lock, flags);
>> +}
>> +
>> +static int hix5hd2_i2c_probe(struct platform_device *pdev)
>> +{
>> + struct device_node *np = pdev->dev.of_node;
>> + struct hix5hd2_i2c *i2c;
>> + struct resource *mem;
>> + unsigned int op_clock;
>> + int ret;
>> +
>> + i2c = devm_kzalloc(&pdev->dev, sizeof(struct hix5hd2_i2c), GFP_KERNEL);
>> + if (!i2c)
>> + return -ENOMEM;
>> +
>> + if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
>> + /* use default value */
>> + i2c->speed_mode = HIX5I2C_HIG_SPD;
>> + i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
>
> Please use 100kHz as the default. This is the speed devices should
> support. 400kHz is optional. And I think 100000 is easier to read than a
> define.
OK.
>
>> + } else {
>> + if (op_clock >= HIX5I2C_HS_TX_CLOCK) {
>> + i2c->speed_mode = HIX5I2C_HIG_SPD;
>> + i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
>
> So, if the speed is bigger than 400kHz, it will be capped down to
> 400kHz? Is that true? Then, the user should be informed about that.
Will add dev_warn to notify.
>
>> + } else {
>> + i2c->speed_mode = HIX5I2C_NORMAL_SPD;
>> + i2c->s_clock = op_clock;
>> + }
>> + }
>> +
>
> ...
>
>> + i2c->adap.owner = THIS_MODULE;
>> + i2c->adap.algo = &hix5hd2_i2c_algorithm;
>
> Single space as indentation.
Got it.
Thanks
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH resend 2/2] i2c: hix5hd2: add i2c controller driver
@ 2014-09-26 3:30 ` zhangfei
0 siblings, 0 replies; 14+ messages in thread
From: zhangfei @ 2014-09-26 3:30 UTC (permalink / raw)
To: linux-arm-kernel
Thanks Wolfram for the careful review
On 09/20/2014 01:18 AM, Wolfram Sang wrote:
> Hi,
>
> thanks for the submission.
>
>> --- /dev/null
>> +++ b/drivers/i2c/busses/i2c-hix5hd2.c
>> @@ -0,0 +1,573 @@
>> +/*
>> + * Copyright (c) 2014 Linaro Ltd.
>> + * Copyright (c) 2014 Hisilicon Limited.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * publishhed by the Free Software Foundation.
>
> "publishhed"
OK.
>
>> + *
>> + * Now only support 7 bit address.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/i2c.h>
>> +#include <linux/io.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_runtime.h>
>
> I think there should be at least of.h, too.
The of.h is already in i2c.h
include/linux/i2c.h:33:#include <linux/of.h>
>
>> +struct hix5hd2_i2c {
>> + struct i2c_adapter adap;
>> + struct i2c_msg *msg;
>> + unsigned int msg_ptr; /* msg index */
>
> Comment seems wrong. It looks to me as the msg buffer index. If so, the
> variable name is also confusing.
Change to msg_idx & msg_len.
>
>> + unsigned int len; /* msg length */
>> + int stop;
>> + struct completion msg_complete;
>> +
>> + unsigned int irq;
>
> That can be a local variable.
Yes
>
>> + void __iomem *regs;
>> + struct clk *clk;
>> + struct device *dev;
>> + spinlock_t lock; /* IRQ synchronization */
>> +
>> + int err;
>> + enum hix5hd2_i2c_state state;
>> + enum hix5hd2_i2c_speed speed_mode;
>
> Where is this needed?
will remove
>
>> +
>> + /* Controller frequency */
>> + unsigned int s_clock;
>> +};
>> +
>> +static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c *i2c)
>> +{
>> + u32 rate, val;
>> + u32 sclh, scll, sysclock;
>> +
>> + /* close all i2c interrupt */
>> + val = readl_relaxed(i2c->regs + HIX5I2C_CTRL);
>> + writel_relaxed(val & (~I2C_UNMASK_TOTAL), i2c->regs + HIX5I2C_CTRL);
>> +
>> + rate = i2c->s_clock;
>> + sysclock = clk_get_rate(i2c->clk);
>> + sclh = (sysclock / (rate * 2)) / 2 - 1;
>> + writel_relaxed(sclh, i2c->regs + HIX5I2C_SCL_H);
>> + scll = (sysclock / (rate * 2)) / 2 - 1;
>
> scll and sclh use the same formula? Have you measured the setup
> frequency with a scope?
Yes, it is confusing, will use the same vector scl instead.
The value is same means sclk high voltage and low voltage keep same time.
>
>> + writel_relaxed(scll, i2c->regs + HIX5I2C_SCL_L);
>> +
>> + /* restore original interrupt*/
>> + writel_relaxed(val, i2c->regs + HIX5I2C_CTRL);
>> +
>> + dev_dbg(i2c->dev, "%s: sysclock=%d, rate=%d, sclh=%d, scll=%d\n",
>> + __func__, sysclock, rate, sclh, scll);
>> +}
>> +
>> +static void hix5hd2_rw_over(struct hix5hd2_i2c *i2c)
>> +{
>> + if (HIX5I2C_STAT_SND_STOP == i2c->state)
>
> To be honest, I don't like having the constant on the left side. It
> is far easier to read if they are on the right side. Plus, we have gcc
> warnings to prevent the "=" and "==" mistake. Please switch them around
> in this driver.
Got it.
>
>> + dev_dbg(i2c->dev, "%s: rw and send stop over\n", __func__);
>> + else
>> + dev_dbg(i2c->dev, "%s: have not data to send\n", __func__);
>> +
>> + i2c->state = HIX5I2C_STAT_RW_SUCCESS;
>> + i2c->err = 0;
>> +}
>> +
>
> ...
>
>> + /* handle error */
>> + if (int_status & I2C_ARBITRATE_INTR) {
>> + /*Bus error */
>
> Space missing in front of "Bus". If this is an arbitration lost error,
> then please use -EAGAIN. Check Documentation/i2c/fault-codes for the
> convention.
OK.
>
>> + dev_dbg(i2c->dev, "ARB bus loss\n");
>> + i2c->err = -ENXIO;
>> + i2c->state = HIX5I2C_STAT_RW_ERR;
>> + goto stop;
>> + } else if (int_status & I2C_ACK_INTR) {
>> + /* ack error */
>> + dev_dbg(i2c->dev, "No ACK from device\n");
>> + i2c->err = -ENXIO;
>> + i2c->state = HIX5I2C_STAT_RW_ERR;
>> + goto stop;
>> + }
>> +
>> +static void hix5hd2_i2c_message_start(struct hix5hd2_i2c *i2c, int stop)
>> +{
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&i2c->lock, flags);
>> + hix5hd2_i2c_clr_all_irq(i2c);
>> + hix5hd2_i2c_enable_irq(i2c);
>> +
>> + if (i2c->msg->flags & I2C_M_RD)
>> + writel_relaxed(i2c->msg->addr | HIX5I2C_READ_OPERATION,
>> + i2c->regs + HIX5I2C_TXR);
>> + else
>> + writel_relaxed(i2c->msg->addr & HIX5I2C_WRITE_OPERATION,
>> + i2c->regs + HIX5I2C_TXR);
>
> ??? Does this really work? i2c->msg->addr should be left shifted by 1?
Double checked, it is because the test applictaion do the left shift.
Yes, will do the left shift by 1.
>
>> +
>> + writel_relaxed(I2C_WRITE | I2C_START, i2c->regs + HIX5I2C_COM);
>> + spin_unlock_irqrestore(&i2c->lock, flags);
>> +}
>> +
>> +static int hix5hd2_i2c_probe(struct platform_device *pdev)
>> +{
>> + struct device_node *np = pdev->dev.of_node;
>> + struct hix5hd2_i2c *i2c;
>> + struct resource *mem;
>> + unsigned int op_clock;
>> + int ret;
>> +
>> + i2c = devm_kzalloc(&pdev->dev, sizeof(struct hix5hd2_i2c), GFP_KERNEL);
>> + if (!i2c)
>> + return -ENOMEM;
>> +
>> + if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
>> + /* use default value */
>> + i2c->speed_mode = HIX5I2C_HIG_SPD;
>> + i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
>
> Please use 100kHz as the default. This is the speed devices should
> support. 400kHz is optional. And I think 100000 is easier to read than a
> define.
OK.
>
>> + } else {
>> + if (op_clock >= HIX5I2C_HS_TX_CLOCK) {
>> + i2c->speed_mode = HIX5I2C_HIG_SPD;
>> + i2c->s_clock = HIX5I2C_HS_TX_CLOCK;
>
> So, if the speed is bigger than 400kHz, it will be capped down to
> 400kHz? Is that true? Then, the user should be informed about that.
Will add dev_warn to notify.
>
>> + } else {
>> + i2c->speed_mode = HIX5I2C_NORMAL_SPD;
>> + i2c->s_clock = op_clock;
>> + }
>> + }
>> +
>
> ...
>
>> + i2c->adap.owner = THIS_MODULE;
>> + i2c->adap.algo = &hix5hd2_i2c_algorithm;
>
> Single space as indentation.
Got it.
Thanks
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH resend 2/2] i2c: hix5hd2: add i2c controller driver
2014-09-26 3:30 ` zhangfei
@ 2014-09-26 6:55 ` Wolfram Sang
-1 siblings, 0 replies; 14+ messages in thread
From: Wolfram Sang @ 2014-09-26 6:55 UTC (permalink / raw)
To: zhangfei
Cc: Arnd Bergmann, haifeng.yan-QSEj5FYQhm4dnm+yROfE0A,
jchxue-Re5JQEeQqe8AvxtiuMwx3w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, Wei Yan
[-- Attachment #1: Type: text/plain, Size: 970 bytes --]
> >>+#include <linux/clk.h>
> >>+#include <linux/delay.h>
> >>+#include <linux/i2c.h>
> >>+#include <linux/io.h>
> >>+#include <linux/interrupt.h>
> >>+#include <linux/module.h>
> >>+#include <linux/platform_device.h>
> >>+#include <linux/pm_runtime.h>
> >
> >I think there should be at least of.h, too.
> The of.h is already in i2c.h
> include/linux/i2c.h:33:#include <linux/of.h>
Please add it nonetheless, because you use e.g. of_property_read_u32()
directly. That makes you independet of changes to i2c.h.
> >>+ rate = i2c->s_clock;
> >>+ sysclock = clk_get_rate(i2c->clk);
> >>+ sclh = (sysclock / (rate * 2)) / 2 - 1;
> >>+ writel_relaxed(sclh, i2c->regs + HIX5I2C_SCL_H);
> >>+ scll = (sysclock / (rate * 2)) / 2 - 1;
> >
> >scll and sclh use the same formula? Have you measured the setup
> >frequency with a scope?
> Yes, it is confusing, will use the same vector scl instead.
> The value is same means sclk high voltage and low voltage keep same time.
OK.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH resend 2/2] i2c: hix5hd2: add i2c controller driver
@ 2014-09-26 6:55 ` Wolfram Sang
0 siblings, 0 replies; 14+ messages in thread
From: Wolfram Sang @ 2014-09-26 6:55 UTC (permalink / raw)
To: linux-arm-kernel
> >>+#include <linux/clk.h>
> >>+#include <linux/delay.h>
> >>+#include <linux/i2c.h>
> >>+#include <linux/io.h>
> >>+#include <linux/interrupt.h>
> >>+#include <linux/module.h>
> >>+#include <linux/platform_device.h>
> >>+#include <linux/pm_runtime.h>
> >
> >I think there should be at least of.h, too.
> The of.h is already in i2c.h
> include/linux/i2c.h:33:#include <linux/of.h>
Please add it nonetheless, because you use e.g. of_property_read_u32()
directly. That makes you independet of changes to i2c.h.
> >>+ rate = i2c->s_clock;
> >>+ sysclock = clk_get_rate(i2c->clk);
> >>+ sclh = (sysclock / (rate * 2)) / 2 - 1;
> >>+ writel_relaxed(sclh, i2c->regs + HIX5I2C_SCL_H);
> >>+ scll = (sysclock / (rate * 2)) / 2 - 1;
> >
> >scll and sclh use the same formula? Have you measured the setup
> >frequency with a scope?
> Yes, it is confusing, will use the same vector scl instead.
> The value is same means sclk high voltage and low voltage keep same time.
OK.
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^ permalink raw reply [flat|nested] 14+ messages in thread
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2014-08-26 5:25 [PATCH resend 0/2] i2c: hix5hd2: add i2c controller driver Zhangfei Gao
2014-08-26 5:25 ` Zhangfei Gao
[not found] ` <1409030722-30709-1-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-08-26 5:25 ` [PATCH resend 1/2] i2c: hix5hd2: add devicetree documentation Zhangfei Gao
2014-08-26 5:25 ` Zhangfei Gao
2014-08-26 5:25 ` [PATCH resend 2/2] i2c: hix5hd2: add i2c controller driver Zhangfei Gao
2014-08-26 5:25 ` Zhangfei Gao
[not found] ` <1409030722-30709-3-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-09-19 17:18 ` Wolfram Sang
2014-09-19 17:18 ` Wolfram Sang
2014-09-26 3:30 ` zhangfei
2014-09-26 3:30 ` zhangfei
[not found] ` <5424DDD5.1020706-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-09-26 6:55 ` Wolfram Sang
2014-09-26 6:55 ` Wolfram Sang
2014-09-15 19:56 ` [PATCH resend 0/2] " Zhangfei Gao
2014-09-15 19:56 ` Zhangfei Gao
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