All of lore.kernel.org
 help / color / mirror / Atom feed
* limiting modes on 4k monitors on Haswell ULT
@ 2014-10-02  3:30 Dave Airlie
  2014-10-02  8:00 ` Daniel Vetter
  0 siblings, 1 reply; 6+ messages in thread
From: Dave Airlie @ 2014-10-02  3:30 UTC (permalink / raw)
  To: intel-gfx

Hey guys,

so I have a haswell ULT laptop (lenovo t440s), and got access to a
Samsung single panel 4k monitor (no MST).

Now we detect the monitor fine, but unfortunately the ULT hsw can't
run it over DP, as it has clock limits in place. However we still
offer the 60hz mode and we pick it by default, ensuing black screens.

I've tested the same monitor with a haswell in a t540p and it works
fine due to having the higher limits in place.

Dave.

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: limiting modes on 4k monitors on Haswell ULT
  2014-10-02  3:30 limiting modes on 4k monitors on Haswell ULT Dave Airlie
@ 2014-10-02  8:00 ` Daniel Vetter
  2014-10-02  8:40   ` Ville Syrjälä
  2014-10-02 11:15   ` Damien Lespiau
  0 siblings, 2 replies; 6+ messages in thread
From: Daniel Vetter @ 2014-10-02  8:00 UTC (permalink / raw)
  To: Dave Airlie; +Cc: intel-gfx

On Thu, Oct 02, 2014 at 01:30:48PM +1000, Dave Airlie wrote:
> Hey guys,
> 
> so I have a haswell ULT laptop (lenovo t440s), and got access to a
> Samsung single panel 4k monitor (no MST).
> 
> Now we detect the monitor fine, but unfortunately the ULT hsw can't
> run it over DP, as it has clock limits in place. However we still
> offer the 60hz mode and we pick it by default, ensuing black screens.
> 
> I've tested the same monitor with a haswell in a t540p and it works
> fine due to having the higher limits in place.

We have the IS_HSW_ULX check in intel_dp_max_link_bw, and that's used by
both compute_config and mode_valid. So it should work, and from a quick
look I don't see any bugs. But obviously something is busted.

Can you please printk-augment intel_dp_mode_valid and check what's going
wrong there?

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: limiting modes on 4k monitors on Haswell ULT
  2014-10-02  8:00 ` Daniel Vetter
@ 2014-10-02  8:40   ` Ville Syrjälä
  2014-10-02 10:56     ` Dave Airlie
  2014-10-02 11:15   ` Damien Lespiau
  1 sibling, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2014-10-02  8:40 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: intel-gfx

On Thu, Oct 02, 2014 at 10:00:50AM +0200, Daniel Vetter wrote:
> On Thu, Oct 02, 2014 at 01:30:48PM +1000, Dave Airlie wrote:
> > Hey guys,
> > 
> > so I have a haswell ULT laptop (lenovo t440s), and got access to a
> > Samsung single panel 4k monitor (no MST).
> > 
> > Now we detect the monitor fine, but unfortunately the ULT hsw can't
> > run it over DP, as it has clock limits in place. However we still
> > offer the 60hz mode and we pick it by default, ensuing black screens.
> > 
> > I've tested the same monitor with a haswell in a t540p and it works
> > fine due to having the higher limits in place.
> 
> We have the IS_HSW_ULX check in intel_dp_max_link_bw, and that's used by
> both compute_config and mode_valid. So it should work, and from a quick
> look I don't see any bugs. But obviously something is busted.
> 
> Can you please printk-augment intel_dp_mode_valid and check what's going
> wrong there?

Or maybe this is about cdclk instead of link clock? I believe the max
cdclk ULT can support is 450MHz. I'm not sure if the default would be
450MHz or 337.5MHz. Also we still don't have support for changing that
during runtime even though I regularly try to trick people into
implementing it. What's the pixel clock of the mode that fails?

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: limiting modes on 4k monitors on Haswell ULT
  2014-10-02  8:40   ` Ville Syrjälä
@ 2014-10-02 10:56     ` Dave Airlie
  2014-10-07 13:07       ` Ville Syrjälä
  0 siblings, 1 reply; 6+ messages in thread
From: Dave Airlie @ 2014-10-02 10:56 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On 2 October 2014 18:40, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Oct 02, 2014 at 10:00:50AM +0200, Daniel Vetter wrote:
>> On Thu, Oct 02, 2014 at 01:30:48PM +1000, Dave Airlie wrote:
>> > Hey guys,
>> >
>> > so I have a haswell ULT laptop (lenovo t440s), and got access to a
>> > Samsung single panel 4k monitor (no MST).
>> >
>> > Now we detect the monitor fine, but unfortunately the ULT hsw can't
>> > run it over DP, as it has clock limits in place. However we still
>> > offer the 60hz mode and we pick it by default, ensuing black screens.
>> >
>> > I've tested the same monitor with a haswell in a t540p and it works
>> > fine due to having the higher limits in place.
>>
>> We have the IS_HSW_ULX check in intel_dp_max_link_bw, and that's used by
>> both compute_config and mode_valid. So it should work, and from a quick
>> look I don't see any bugs. But obviously something is busted.
>>
>> Can you please printk-augment intel_dp_mode_valid and check what's going
>> wrong there?
>
> Or maybe this is about cdclk instead of link clock? I believe the max
> cdclk ULT can support is 450MHz. I'm not sure if the default would be
> 450MHz or 337.5MHz. Also we still don't have support for changing that
> during runtime even though I regularly try to trick people into
> implementing it. What's the pixel clock of the mode that fails?

yup it appears to max cdclk, which is 450Mhz on the ULT and 540Mhz on
normal hsw.

Modeline "3840x2160R"  533.00  3840 3888 3920 4000  2160 2163 2168
2222 +hsync -vsync

cvt gives me that for reduced blank, so around that I guess, I can get
the exact mode line from logs tomorrow if required.

Dave.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: limiting modes on 4k monitors on Haswell ULT
  2014-10-02  8:00 ` Daniel Vetter
  2014-10-02  8:40   ` Ville Syrjälä
@ 2014-10-02 11:15   ` Damien Lespiau
  1 sibling, 0 replies; 6+ messages in thread
From: Damien Lespiau @ 2014-10-02 11:15 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: intel-gfx

On Thu, Oct 02, 2014 at 10:00:50AM +0200, Daniel Vetter wrote:
> On Thu, Oct 02, 2014 at 01:30:48PM +1000, Dave Airlie wrote:
> > Hey guys,
> > 
> > so I have a haswell ULT laptop (lenovo t440s), and got access to a
> > Samsung single panel 4k monitor (no MST).
> > 
> > Now we detect the monitor fine, but unfortunately the ULT hsw can't
> > run it over DP, as it has clock limits in place. However we still
> > offer the 60hz mode and we pick it by default, ensuing black screens.
> > 
> > I've tested the same monitor with a haswell in a t540p and it works
> > fine due to having the higher limits in place.
> 
> We have the IS_HSW_ULX check in intel_dp_max_link_bw, and that's used by
> both compute_config and mode_valid. So it should work, and from a quick
> look I don't see any bugs. But obviously something is busted.

Just to be a bit more specific:

ULT != ULX, the two SKUs have different limits. The test in
intel_dp_max_link_bw() is about eDP/DP max link rate: HBR2(ULT) Vs
HBR(ULX).

I'd go with Ville, that sounds like CDCLK is the limiting factor, and
we're missing these checks. From a cursory glance, it doesn't seem we
can do 4k on ULT.

-- 
Damien

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: limiting modes on 4k monitors on Haswell ULT
  2014-10-02 10:56     ` Dave Airlie
@ 2014-10-07 13:07       ` Ville Syrjälä
  0 siblings, 0 replies; 6+ messages in thread
From: Ville Syrjälä @ 2014-10-07 13:07 UTC (permalink / raw)
  To: Dave Airlie; +Cc: intel-gfx

On Thu, Oct 02, 2014 at 08:56:54PM +1000, Dave Airlie wrote:
> On 2 October 2014 18:40, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Oct 02, 2014 at 10:00:50AM +0200, Daniel Vetter wrote:
> >> On Thu, Oct 02, 2014 at 01:30:48PM +1000, Dave Airlie wrote:
> >> > Hey guys,
> >> >
> >> > so I have a haswell ULT laptop (lenovo t440s), and got access to a
> >> > Samsung single panel 4k monitor (no MST).
> >> >
> >> > Now we detect the monitor fine, but unfortunately the ULT hsw can't
> >> > run it over DP, as it has clock limits in place. However we still
> >> > offer the 60hz mode and we pick it by default, ensuing black screens.
> >> >
> >> > I've tested the same monitor with a haswell in a t540p and it works
> >> > fine due to having the higher limits in place.
> >>
> >> We have the IS_HSW_ULX check in intel_dp_max_link_bw, and that's used by
> >> both compute_config and mode_valid. So it should work, and from a quick
> >> look I don't see any bugs. But obviously something is busted.
> >>
> >> Can you please printk-augment intel_dp_mode_valid and check what's going
> >> wrong there?
> >
> > Or maybe this is about cdclk instead of link clock? I believe the max
> > cdclk ULT can support is 450MHz. I'm not sure if the default would be
> > 450MHz or 337.5MHz. Also we still don't have support for changing that
> > during runtime even though I regularly try to trick people into
> > implementing it. What's the pixel clock of the mode that fails?
> 
> yup it appears to max cdclk, which is 450Mhz on the ULT and 540Mhz on
> normal hsw.
> 
> Modeline "3840x2160R"  533.00  3840 3888 3920 4000  2160 2163 2168
> 2222 +hsync -vsync
> 
> cvt gives me that for reduced blank, so around that I guess, I can get
> the exact mode line from logs tomorrow if required.

Just FYI I went ahead and implemented something for dynamically
changing the cdclk frequency on HSW/BDW. But I only have a HSW-ULT
on me currently so I couldn't actually test it.

While doing that I added cdclk extraction support to all the
platforms for which I could find sane docs. For the rest I went with
a best guess, which means after my patches we can rely on
dev_priv->max_cdclk_freq on all platforms. That should make it
trivial to add some .mode_valid() checks based on the max cdclk,
but I didn't actually implemnt such checks yet.

Here's the code (includes a whole pile of cdclk related stuff)
for the brave:
git://gitorious.org/vsyrjala/linux.git cdclk_3

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-10-07 13:07 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-10-02  3:30 limiting modes on 4k monitors on Haswell ULT Dave Airlie
2014-10-02  8:00 ` Daniel Vetter
2014-10-02  8:40   ` Ville Syrjälä
2014-10-02 10:56     ` Dave Airlie
2014-10-07 13:07       ` Ville Syrjälä
2014-10-02 11:15   ` Damien Lespiau

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.