* [PATCH 0/5] sun6i: Add A31s (pinctrl) support
@ 2014-11-23 12:54 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard
Cc: Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Hi Maxime and Linus,
Here is a patch series for the A31s, a variant of the already supported
A31 with less pins.
As such this patch-set introduces pinctrl support for it + a dtsi + the
first board using it.
I'm not sure if sunxi pinctrl patches go through Maxime's tree or Linus' tree,
so I'll leave figuring out who takes what patches to you two.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 0/5] sun6i: Add A31s (pinctrl) support
@ 2014-11-23 12:54 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: linux-arm-kernel
Hi Maxime and Linus,
Here is a patch series for the A31s, a variant of the already supported
A31 with less pins.
As such this patch-set introduces pinctrl support for it + a dtsi + the
first board using it.
I'm not sure if sunxi pinctrl patches go through Maxime's tree or Linus' tree,
so I'll leave figuring out who takes what patches to you two.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-23 12:54 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard
Cc: Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Hans de Goede
While working on pinctrl for the A31s, I noticed that function 4 of
PA15 - PA18 was missing, add these.
I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
be PB4 & PB5, fix this as well.
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index a2b4b85..fb19e15 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
+ SUNXI_FUNCTION(0x4, "clk_a_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
+ SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
+ SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
+ SUNXI_FUNCTION(0x4, "clk_b_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
+ SUNXI_FUNCTION(0x4, "clk_c_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
- SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
- SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
@ 2014-11-23 12:54 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: linux-arm-kernel
While working on pinctrl for the A31s, I noticed that function 4 of
PA15 - PA18 was missing, add these.
I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
be PB4 & PB5, fix this as well.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index a2b4b85..fb19e15 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
+ SUNXI_FUNCTION(0x4, "clk_a_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
+ SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
+ SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
+ SUNXI_FUNCTION(0x4, "clk_b_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
+ SUNXI_FUNCTION(0x4, "clk_c_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
- SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
- SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 2/5] pinctrl: sun6i: Add A31s pinctrl support
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-23 12:54 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard
Cc: Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Hans de Goede
The A31s is a stripped down version of the A31, as such it is missing some
pins and some functions on some pins.
The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
with the missing pins and functions removed.
Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
prcm pins are identical between the A31 and the A31s.
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c | 814 +++++++++++++++++++++
4 files changed, 820 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 93ce12e..fdd8046 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -11,6 +11,7 @@ Required properties:
"allwinner,sun5i-a10s-pinctrl"
"allwinner,sun5i-a13-pinctrl"
"allwinner,sun6i-a31-pinctrl"
+ "allwinner,sun6i-a31s-pinctrl"
"allwinner,sun6i-a31-r-pinctrl"
"allwinner,sun7i-a20-pinctrl"
"allwinner,sun8i-a23-pinctrl"
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index a5e10f7..6cffe38 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
def_bool MACH_SUN6I
select PINCTRL_SUNXI_COMMON
+config PINCTRL_SUN6I_A31S
+ def_bool MACH_SUN6I
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN6I_A31_R
def_bool MACH_SUN6I
depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index e797efb..2f82290 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
+obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
new file mode 100644
index 0000000..42ee373
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
@@ -0,0 +1,814 @@
+/*
+ * Allwinner A31 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun6i_a31s_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RING */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
+ SUNXI_FUNCTION(0x4, "clk_a_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
+ SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
+ SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
+ SUNXI_FUNCTION(0x4, "clk_b_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
+ SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
+ SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
+ SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
+ SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* COL */
+ SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
+ SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
+ SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
+ SUNXI_FUNCTION(0x4, "clk_c_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* RE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
+ /* Hole in pin numbering ! */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
+ SUNXI_FUNCTION(0x3, "ts"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "ts"), /* ERR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D0 */
+ SUNXI_FUNCTION(0x3, "uart5"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D1 */
+ SUNXI_FUNCTION(0x3, "uart5"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D2 */
+ SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D4 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D5 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D6 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D7 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D8 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D4 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D9 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D5 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D10 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D6 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D11 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D7 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x4, "uart0")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x4, "uart0")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart4"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart4"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
+ /* Hole, note H starts at pin 9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
+ SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
+ SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
+ SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
+ SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
+ SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm0")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+};
+
+static const struct sunxi_pinctrl_desc sun6i_a31s_pinctrl_data = {
+ .pins = sun6i_a31s_pins,
+ .npins = ARRAY_SIZE(sun6i_a31s_pins),
+ .irq_banks = 4,
+};
+
+static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun6i_a31s_pinctrl_data);
+}
+
+static struct of_device_id sun6i_a31s_pinctrl_match[] = {
+ { .compatible = "allwinner,sun6i-a31s-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun6i_a31s_pinctrl_match);
+
+static struct platform_driver sun6i_a31s_pinctrl_driver = {
+ .probe = sun6i_a31s_pinctrl_probe,
+ .driver = {
+ .name = "sun6i-a31s-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = sun6i_a31s_pinctrl_match,
+ },
+};
+module_platform_driver(sun6i_a31s_pinctrl_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org");
+MODULE_DESCRIPTION("Allwinner A31 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 2/5] pinctrl: sun6i: Add A31s pinctrl support
@ 2014-11-23 12:54 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: linux-arm-kernel
The A31s is a stripped down version of the A31, as such it is missing some
pins and some functions on some pins.
The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
with the missing pins and functions removed.
Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
prcm pins are identical between the A31 and the A31s.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c | 814 +++++++++++++++++++++
4 files changed, 820 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 93ce12e..fdd8046 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -11,6 +11,7 @@ Required properties:
"allwinner,sun5i-a10s-pinctrl"
"allwinner,sun5i-a13-pinctrl"
"allwinner,sun6i-a31-pinctrl"
+ "allwinner,sun6i-a31s-pinctrl"
"allwinner,sun6i-a31-r-pinctrl"
"allwinner,sun7i-a20-pinctrl"
"allwinner,sun8i-a23-pinctrl"
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index a5e10f7..6cffe38 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
def_bool MACH_SUN6I
select PINCTRL_SUNXI_COMMON
+config PINCTRL_SUN6I_A31S
+ def_bool MACH_SUN6I
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN6I_A31_R
def_bool MACH_SUN6I
depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index e797efb..2f82290 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
+obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
new file mode 100644
index 0000000..42ee373
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
@@ -0,0 +1,814 @@
+/*
+ * Allwinner A31 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun6i_a31s_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RING */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
+ SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
+ SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
+ SUNXI_FUNCTION(0x4, "clk_a_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
+ SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
+ SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
+ SUNXI_FUNCTION(0x4, "clk_b_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
+ SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
+ SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
+ SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
+ SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* COL */
+ SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
+ SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
+ SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
+ SUNXI_FUNCTION(0x4, "clk_c_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* RE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
+ /* Hole in pin numbering ! */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
+ SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
+ SUNXI_FUNCTION(0x3, "ts"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "ts"), /* ERR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D0 */
+ SUNXI_FUNCTION(0x3, "uart5"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D1 */
+ SUNXI_FUNCTION(0x3, "uart5"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D2 */
+ SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D4 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D5 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D6 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D7 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D8 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D4 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D9 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D5 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D10 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D6 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D11 */
+ SUNXI_FUNCTION(0x3, "ts"), /* D7 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x4, "uart0")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x4, "uart0")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart4"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart4"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
+ /* Hole, note H starts at pin 9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
+ SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
+ SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
+ SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
+ SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
+ SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm0")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+};
+
+static const struct sunxi_pinctrl_desc sun6i_a31s_pinctrl_data = {
+ .pins = sun6i_a31s_pins,
+ .npins = ARRAY_SIZE(sun6i_a31s_pins),
+ .irq_banks = 4,
+};
+
+static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun6i_a31s_pinctrl_data);
+}
+
+static struct of_device_id sun6i_a31s_pinctrl_match[] = {
+ { .compatible = "allwinner,sun6i-a31s-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun6i_a31s_pinctrl_match);
+
+static struct platform_driver sun6i_a31s_pinctrl_driver = {
+ .probe = sun6i_a31s_pinctrl_probe,
+ .driver = {
+ .name = "sun6i-a31s-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = sun6i_a31s_pinctrl_match,
+ },
+};
+module_platform_driver(sun6i_a31s_pinctrl_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
+MODULE_DESCRIPTION("Allwinner A31 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 3/5] ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-23 12:54 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard
Cc: Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Hans de Goede
So fat the A31s is 100% compatible with the A31, still lets do the same
as what we've done for the A13 / A10s and give it its own compatible string,
in case need to differentiate later.
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
arch/arm/mach-sunxi/platsmp.c | 3 ++-
arch/arm/mach-sunxi/sunxi.c | 1 +
drivers/clk/sunxi/clk-sunxi.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index c53077b..8601491 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -120,4 +120,5 @@ struct smp_operations sun6i_smp_ops __initdata = {
.smp_prepare_cpus = sun6i_smp_prepare_cpus,
.smp_boot_secondary = sun6i_smp_boot_secondary,
};
-CPU_METHOD_OF_DECLARE(sun6i_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun6i_a31s_smp, "allwinner,sun6i-a31s", &sun6i_smp_ops);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index d7598ae..2d9ca5b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -29,6 +29,7 @@ MACHINE_END
static const char * const sun6i_board_dt_compat[] = {
"allwinner,sun6i-a31",
+ "allwinner,sun6i-a31s",
NULL,
};
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index f19e0f9..3577f4c 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1200,4 +1200,5 @@ static void __init sun6i_init_clocks(struct device_node *node)
ARRAY_SIZE(sun6i_critical_clocks));
}
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
+CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 3/5] ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi
@ 2014-11-23 12:54 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: linux-arm-kernel
So fat the A31s is 100% compatible with the A31, still lets do the same
as what we've done for the A13 / A10s and give it its own compatible string,
in case need to differentiate later.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/mach-sunxi/platsmp.c | 3 ++-
arch/arm/mach-sunxi/sunxi.c | 1 +
drivers/clk/sunxi/clk-sunxi.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index c53077b..8601491 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -120,4 +120,5 @@ struct smp_operations sun6i_smp_ops __initdata = {
.smp_prepare_cpus = sun6i_smp_prepare_cpus,
.smp_boot_secondary = sun6i_smp_boot_secondary,
};
-CPU_METHOD_OF_DECLARE(sun6i_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun6i_a31s_smp, "allwinner,sun6i-a31s", &sun6i_smp_ops);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index d7598ae..2d9ca5b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -29,6 +29,7 @@ MACHINE_END
static const char * const sun6i_board_dt_compat[] = {
"allwinner,sun6i-a31",
+ "allwinner,sun6i-a31s",
NULL,
};
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index f19e0f9..3577f4c 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1200,4 +1200,5 @@ static void __init sun6i_init_clocks(struct device_node *node)
ARRAY_SIZE(sun6i_critical_clocks));
}
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
+CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-23 12:54 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard
Cc: Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Hans de Goede
Add a dtsi file for A31s based boards. This is a copy of sun6i-a31.dtsi, with:
-The main pinctrl compatible changed to allwinner,sun6i-a31s.dtsi
-The ohci2 controller is present according to the data-sheet, but not routed
to the outside, so remove it from the dtsi as having an always disabled node
is not useful.
All the other nodes present in the original sun6i-a31.dtsi are present in
the A31s too, and are 100% compatible.
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/sun6i-a31s.dtsi | 925 ++++++++++++++++++++++++++++++++++++++
1 file changed, 925 insertions(+)
create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
new file mode 100644
index 0000000..b3b99a9
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
@@ -0,0 +1,925 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ ethernet0 = &gmac;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-hdmi";
+ clocks = <&pll6>;
+ status = "disabled";
+ };
+ };
+
+ cpus {
+ enable-method = "allwinner,sun6i-a31";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ interrupts = <0 120 4>,
+ <0 121 4>,
+ <0 122 4>,
+ <0 123 4>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ osc32k: clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6";
+ };
+
+ cpu: cpu@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+
+ /*
+ * PLL1 is listed twice here.
+ * While it looks suspicious, it's actually documented
+ * that way both in the datasheet and in the code from
+ * Allwinner.
+ */
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1_mux: ahb1_mux@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+ clock-output-names = "ahb1_mux";
+ };
+
+ ahb1: ahb1@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1_mux>;
+ clock-output-names = "ahb1";
+ };
+
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb1>;
+ clock-output-names = "ahb1_mipidsi", "ahb1_ss",
+ "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
+ "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
+ "ahb1_nand0", "ahb1_sdram",
+ "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
+ "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
+ "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
+ "ahb1_ehci1", "ahb1_ohci0",
+ "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
+ "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
+ "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
+ "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
+ "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
+ "ahb1_drc0", "ahb1_drc1";
+ };
+
+ apb1: apb1@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ apb1_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-apb1-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_codec", "apb1_digital_mic",
+ "apb1_pio", "apb1_daudio0",
+ "apb1_daudio1";
+ };
+
+ apb2_mux: apb2_mux@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+ clock-output-names = "apb2_mux";
+ };
+
+ apb2: apb2@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-apb2-div-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&apb2_mux>;
+ clock-output-names = "apb2";
+ };
+
+ apb2_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-apb2-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb2>;
+ clock-output-names = "apb2_i2c0", "apb2_i2c1",
+ "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
+ "apb2_uart1", "apb2_uart2", "apb2_uart3",
+ "apb2_uart4", "apb2_uart5";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc0";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc1";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc2";
+ };
+
+ mmc3_clk: clk@01c20094 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20094 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc3";
+ };
+
+ spi0_clk: clk@01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk@01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk@01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi2";
+ };
+
+ spi3_clk: clk@01c200ac {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200ac 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi3";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
+ "usb_ohci0", "usb_ohci1",
+ "usb_ohci2";
+ };
+
+ /*
+ * The following two are dummy clocks, placeholders used in the gmac_tx
+ * clock. The gmac driver will choose one parent depending on the PHY
+ * interface mode, using clk_set_rate auto-reparenting.
+ * The actual TX clock rate is not controlled by the gmac_tx clock.
+ */
+ mii_phy_tx_clk: clk@1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "mii_phy_tx";
+ };
+
+ gmac_int_tx_clk: clk@2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_int_tx";
+ };
+
+ gmac_tx_clk: clk@01c200d0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-gmac-clk";
+ reg = <0x01c200d0 0x4>;
+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+ clock-output-names = "gmac_tx";
+ };
+ };
+
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun6i-a31-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <0 50 4>;
+ clocks = <&ahb1_gates 6>;
+ resets = <&ahb1_rst 6>;
+ #dma-cells = <1>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb1_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mmc";
+ resets = <&ahb1_rst 8>;
+ reset-names = "ahb";
+ interrupts = <0 60 4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb1_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mmc";
+ resets = <&ahb1_rst 9>;
+ reset-names = "ahb";
+ interrupts = <0 61 4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb1_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mmc";
+ resets = <&ahb1_rst 10>;
+ reset-names = "ahb";
+ interrupts = <0 62 4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb1_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mmc";
+ resets = <&ahb1_rst 11>;
+ reset-names = "ahb";
+ interrupts = <0 63 4>;
+ status = "disabled";
+ };
+
+ usbphy: phy@01c19400 {
+ compatible = "allwinner,sun6i-a31-usb-phy";
+ reg = <0x01c19400 0x10>,
+ <0x01c1a800 0x4>,
+ <0x01c1b800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu1",
+ "pmu2";
+ clocks = <&usb_clk 8>,
+ <&usb_clk 9>,
+ <&usb_clk 10>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy";
+ resets = <&usb_clk 0>,
+ <&usb_clk 1>,
+ <&usb_clk 2>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <0 72 4>;
+ clocks = <&ahb1_gates 26>;
+ resets = <&ahb1_rst 26>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <0 73 4>;
+ clocks = <&ahb1_gates 29>, <&usb_clk 16>;
+ resets = <&ahb1_rst 29>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@01c1b000 {
+ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <0 74 4>;
+ clocks = <&ahb1_gates 27>;
+ resets = <&ahb1_rst 27>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1b400 {
+ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <0 75 4>;
+ clocks = <&ahb1_gates 30>, <&usb_clk 17>;
+ resets = <&ahb1_rst 30>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun6i-a31s-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <0 11 4>,
+ <0 15 4>,
+ <0 16 4>,
+ <0 17 4>;
+ clocks = <&apb1_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PH20", "PH21";
+ allwinner,function = "uart0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PH14", "PH15";
+ allwinner,function = "i2c0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PH16", "PH17";
+ allwinner,function = "i2c1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PH18", "PH19";
+ allwinner,function = "i2c2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_mii_a: gmac_mii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA8", "PA9", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA26", "PA27";
+ allwinner,function = "gmac";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_gmii_a: gmac_gmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA4", "PA5", "PA6", "PA7",
+ "PA8", "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA15",
+ "PA16", "PA17", "PA18", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA25", "PA26", "PA27";
+ allwinner,function = "gmac";
+ /*
+ * data lines in GMII mode run at 125MHz and
+ * might need a higher signal drive strength
+ */
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA25", "PA26", "PA27";
+ allwinner,function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ ahb1_rst: reset@01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset@01c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset@01c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <0 18 4>,
+ <0 19 4>,
+ <0 20 4>,
+ <0 21 4>,
+ <0 22 4>;
+ clocks = <&osc24M>;
+ };
+
+ wdt1: watchdog@01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <0 0 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 16>;
+ resets = <&apb2_rst 16>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <0 1 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 17>;
+ resets = <&apb2_rst 17>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <0 2 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 18>;
+ resets = <&apb2_rst 18>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <0 3 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 19>;
+ resets = <&apb2_rst 19>;
+ dmas = <&dma 9>, <&dma 9>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <0 4 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 20>;
+ resets = <&apb2_rst 20>;
+ dmas = <&dma 10>, <&dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@01c29400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29400 0x400>;
+ interrupts = <0 5 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 21>;
+ resets = <&apb2_rst 21>;
+ dmas = <&dma 22>, <&dma 22>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <0 6 4>;
+ clocks = <&apb2_gates 0>;
+ resets = <&apb2_rst 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <0 7 4>;
+ clocks = <&apb2_gates 1>;
+ resets = <&apb2_rst 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <0 8 4>;
+ clocks = <&apb2_gates 2>;
+ resets = <&apb2_rst 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@01c2b800 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b800 0x400>;
+ interrupts = <0 9 4>;
+ clocks = <&apb2_gates 3>;
+ resets = <&apb2_rst 3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac: ethernet@01c30000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x01c30000 0x1054>;
+ interrupts = <0 82 4>;
+ interrupt-names = "macirq";
+ clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ resets = <&ahb1_rst 17>;
+ reset-names = "stmmaceth";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer@01c60000 {
+ compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 51 4>,
+ <0 52 4>,
+ <0 53 4>,
+ <0 54 4>;
+ clocks = <&ahb1_gates 19>;
+ resets = <&ahb1_rst 19>;
+ };
+
+ spi0: spi@01c68000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <0 65 4>;
+ clocks = <&ahb1_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 20>;
+ status = "disabled";
+ };
+
+ spi1: spi@01c69000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <0 66 4>;
+ clocks = <&ahb1_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 21>;
+ status = "disabled";
+ };
+
+ spi2: spi@01c6a000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c6a000 0x1000>;
+ interrupts = <0 67 4>;
+ clocks = <&ahb1_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 25>, <&dma 25>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 22>;
+ status = "disabled";
+ };
+
+ spi3: spi@01c6b000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c6b000 0x1000>;
+ interrupts = <0 68 4>;
+ clocks = <&ahb1_gates 23>, <&spi3_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 26>, <&dma 26>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 23>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ rtc: rtc@01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <0 40 4>, <0 41 4>;
+ };
+
+ nmi_intc: interrupt-controller@01f00c0c {
+ compatible = "allwinner,sun6i-a31-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c0c 0x38>;
+ interrupts = <0 32 4>;
+ };
+
+ prcm@01f01400 {
+ compatible = "allwinner,sun6i-a31-prcm";
+ reg = <0x01f01400 0x200>;
+
+ ar100: ar100_clk {
+ compatible = "allwinner,sun6i-a31-ar100-clk";
+ #clock-cells = <0>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+ clock-output-names = "ar100";
+ };
+
+ ahb0: ahb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&ar100>;
+ clock-output-names = "ahb0";
+ };
+
+ apb0: apb0_clk {
+ compatible = "allwinner,sun6i-a31-apb0-clk";
+ #clock-cells = <0>;
+ clocks = <&ahb0>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: apb0_gates_clk {
+ compatible = "allwinner,sun6i-a31-apb0-gates-clk";
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_pio", "apb0_ir",
+ "apb0_timer", "apb0_p2wi",
+ "apb0_uart", "apb0_1wire",
+ "apb0_i2c";
+ };
+
+ ir_clk: ir_clk {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ir-clk";
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "ir";
+ };
+
+ apb0_rst: apb0_rst {
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ cpucfg@01f01c00 {
+ compatible = "allwinner,sun6i-a31-cpuconfig";
+ reg = <0x01f01c00 0x300>;
+ };
+
+ ir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <&apb0_gates 1>, <&ir_clk>;
+ clock-names = "apb", "ir";
+ resets = <&apb0_rst 1>;
+ interrupts = <0 37 4>;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun6i-a31-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <0 45 4>,
+ <0 46 4>;
+ clocks = <&apb0_gates 0>;
+ resets = <&apb0_rst 0>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ ir_pins_a: ir@0 {
+ allwinner,pins = "PL4";
+ allwinner,function = "s_ir";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+ };
+};
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
@ 2014-11-23 12:54 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: linux-arm-kernel
Add a dtsi file for A31s based boards. This is a copy of sun6i-a31.dtsi, with:
-The main pinctrl compatible changed to allwinner,sun6i-a31s.dtsi
-The ohci2 controller is present according to the data-sheet, but not routed
to the outside, so remove it from the dtsi as having an always disabled node
is not useful.
All the other nodes present in the original sun6i-a31.dtsi are present in
the A31s too, and are 100% compatible.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/sun6i-a31s.dtsi | 925 ++++++++++++++++++++++++++++++++++++++
1 file changed, 925 insertions(+)
create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
new file mode 100644
index 0000000..b3b99a9
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
@@ -0,0 +1,925 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ ethernet0 = &gmac;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer at 0 {
+ compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-hdmi";
+ clocks = <&pll6>;
+ status = "disabled";
+ };
+ };
+
+ cpus {
+ enable-method = "allwinner,sun6i-a31";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu at 1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu at 2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu at 3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ interrupts = <0 120 4>,
+ <0 121 4>,
+ <0 122 4>,
+ <0 123 4>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ osc32k: clk at 0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk at 01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll6: clk at 01c20028 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6";
+ };
+
+ cpu: cpu at 01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+
+ /*
+ * PLL1 is listed twice here.
+ * While it looks suspicious, it's actually documented
+ * that way both in the datasheet and in the code from
+ * Allwinner.
+ */
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi at 01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1_mux: ahb1_mux at 01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+ clock-output-names = "ahb1_mux";
+ };
+
+ ahb1: ahb1 at 01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1_mux>;
+ clock-output-names = "ahb1";
+ };
+
+ ahb1_gates: clk at 01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb1>;
+ clock-output-names = "ahb1_mipidsi", "ahb1_ss",
+ "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
+ "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
+ "ahb1_nand0", "ahb1_sdram",
+ "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
+ "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
+ "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
+ "ahb1_ehci1", "ahb1_ohci0",
+ "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
+ "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
+ "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
+ "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
+ "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
+ "ahb1_drc0", "ahb1_drc1";
+ };
+
+ apb1: apb1 at 01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ apb1_gates: clk at 01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-apb1-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_codec", "apb1_digital_mic",
+ "apb1_pio", "apb1_daudio0",
+ "apb1_daudio1";
+ };
+
+ apb2_mux: apb2_mux at 01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+ clock-output-names = "apb2_mux";
+ };
+
+ apb2: apb2 at 01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-apb2-div-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&apb2_mux>;
+ clock-output-names = "apb2";
+ };
+
+ apb2_gates: clk at 01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-apb2-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb2>;
+ clock-output-names = "apb2_i2c0", "apb2_i2c1",
+ "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
+ "apb2_uart1", "apb2_uart2", "apb2_uart3",
+ "apb2_uart4", "apb2_uart5";
+ };
+
+ mmc0_clk: clk at 01c20088 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc0";
+ };
+
+ mmc1_clk: clk at 01c2008c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc1";
+ };
+
+ mmc2_clk: clk at 01c20090 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc2";
+ };
+
+ mmc3_clk: clk at 01c20094 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20094 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "mmc3";
+ };
+
+ spi0_clk: clk at 01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk at 01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk at 01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi2";
+ };
+
+ spi3_clk: clk at 01c200ac {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200ac 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi3";
+ };
+
+ usb_clk: clk at 01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
+ "usb_ohci0", "usb_ohci1",
+ "usb_ohci2";
+ };
+
+ /*
+ * The following two are dummy clocks, placeholders used in the gmac_tx
+ * clock. The gmac driver will choose one parent depending on the PHY
+ * interface mode, using clk_set_rate auto-reparenting.
+ * The actual TX clock rate is not controlled by the gmac_tx clock.
+ */
+ mii_phy_tx_clk: clk at 1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "mii_phy_tx";
+ };
+
+ gmac_int_tx_clk: clk at 2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_int_tx";
+ };
+
+ gmac_tx_clk: clk at 01c200d0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-gmac-clk";
+ reg = <0x01c200d0 0x4>;
+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+ clock-output-names = "gmac_tx";
+ };
+ };
+
+ soc at 01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dma: dma-controller at 01c02000 {
+ compatible = "allwinner,sun6i-a31-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <0 50 4>;
+ clocks = <&ahb1_gates 6>;
+ resets = <&ahb1_rst 6>;
+ #dma-cells = <1>;
+ };
+
+ mmc0: mmc at 01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb1_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mmc";
+ resets = <&ahb1_rst 8>;
+ reset-names = "ahb";
+ interrupts = <0 60 4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc at 01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb1_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mmc";
+ resets = <&ahb1_rst 9>;
+ reset-names = "ahb";
+ interrupts = <0 61 4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc at 01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb1_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mmc";
+ resets = <&ahb1_rst 10>;
+ reset-names = "ahb";
+ interrupts = <0 62 4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc at 01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb1_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mmc";
+ resets = <&ahb1_rst 11>;
+ reset-names = "ahb";
+ interrupts = <0 63 4>;
+ status = "disabled";
+ };
+
+ usbphy: phy at 01c19400 {
+ compatible = "allwinner,sun6i-a31-usb-phy";
+ reg = <0x01c19400 0x10>,
+ <0x01c1a800 0x4>,
+ <0x01c1b800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu1",
+ "pmu2";
+ clocks = <&usb_clk 8>,
+ <&usb_clk 9>,
+ <&usb_clk 10>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy";
+ resets = <&usb_clk 0>,
+ <&usb_clk 1>,
+ <&usb_clk 2>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb at 01c1a000 {
+ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <0 72 4>;
+ clocks = <&ahb1_gates 26>;
+ resets = <&ahb1_rst 26>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb at 01c1a400 {
+ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <0 73 4>;
+ clocks = <&ahb1_gates 29>, <&usb_clk 16>;
+ resets = <&ahb1_rst 29>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb at 01c1b000 {
+ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <0 74 4>;
+ clocks = <&ahb1_gates 27>;
+ resets = <&ahb1_rst 27>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb at 01c1b400 {
+ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <0 75 4>;
+ clocks = <&ahb1_gates 30>, <&usb_clk 17>;
+ resets = <&ahb1_rst 30>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ pio: pinctrl at 01c20800 {
+ compatible = "allwinner,sun6i-a31s-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <0 11 4>,
+ <0 15 4>,
+ <0 16 4>,
+ <0 17 4>;
+ clocks = <&apb1_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ uart0_pins_a: uart0 at 0 {
+ allwinner,pins = "PH20", "PH21";
+ allwinner,function = "uart0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c0_pins_a: i2c0 at 0 {
+ allwinner,pins = "PH14", "PH15";
+ allwinner,function = "i2c0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c1_pins_a: i2c1 at 0 {
+ allwinner,pins = "PH16", "PH17";
+ allwinner,function = "i2c1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c2_pins_a: i2c2 at 0 {
+ allwinner,pins = "PH18", "PH19";
+ allwinner,function = "i2c2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_pins_a: mmc0 at 0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_mii_a: gmac_mii at 0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA8", "PA9", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA26", "PA27";
+ allwinner,function = "gmac";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_gmii_a: gmac_gmii at 0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA4", "PA5", "PA6", "PA7",
+ "PA8", "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA15",
+ "PA16", "PA17", "PA18", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA25", "PA26", "PA27";
+ allwinner,function = "gmac";
+ /*
+ * data lines in GMII mode run at 125MHz and
+ * might need a higher signal drive strength
+ */
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_rgmii_a: gmac_rgmii at 0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA25", "PA26", "PA27";
+ allwinner,function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ ahb1_rst: reset at 01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset at 01c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset at 01c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
+ };
+
+ timer at 01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <0 18 4>,
+ <0 19 4>,
+ <0 20 4>,
+ <0 21 4>,
+ <0 22 4>;
+ clocks = <&osc24M>;
+ };
+
+ wdt1: watchdog at 01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ };
+
+ uart0: serial at 01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <0 0 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 16>;
+ resets = <&apb2_rst 16>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial at 01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <0 1 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 17>;
+ resets = <&apb2_rst 17>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial at 01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <0 2 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 18>;
+ resets = <&apb2_rst 18>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial at 01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <0 3 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 19>;
+ resets = <&apb2_rst 19>;
+ dmas = <&dma 9>, <&dma 9>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial at 01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <0 4 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 20>;
+ resets = <&apb2_rst 20>;
+ dmas = <&dma 10>, <&dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial at 01c29400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29400 0x400>;
+ interrupts = <0 5 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 21>;
+ resets = <&apb2_rst 21>;
+ dmas = <&dma 22>, <&dma 22>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c0: i2c at 01c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <0 6 4>;
+ clocks = <&apb2_gates 0>;
+ resets = <&apb2_rst 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c at 01c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <0 7 4>;
+ clocks = <&apb2_gates 1>;
+ resets = <&apb2_rst 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c at 01c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <0 8 4>;
+ clocks = <&apb2_gates 2>;
+ resets = <&apb2_rst 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c at 01c2b800 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b800 0x400>;
+ interrupts = <0 9 4>;
+ clocks = <&apb2_gates 3>;
+ resets = <&apb2_rst 3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac: ethernet at 01c30000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x01c30000 0x1054>;
+ interrupts = <0 82 4>;
+ interrupt-names = "macirq";
+ clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ resets = <&ahb1_rst 17>;
+ reset-names = "stmmaceth";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer at 01c60000 {
+ compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 51 4>,
+ <0 52 4>,
+ <0 53 4>,
+ <0 54 4>;
+ clocks = <&ahb1_gates 19>;
+ resets = <&ahb1_rst 19>;
+ };
+
+ spi0: spi at 01c68000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <0 65 4>;
+ clocks = <&ahb1_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 20>;
+ status = "disabled";
+ };
+
+ spi1: spi at 01c69000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <0 66 4>;
+ clocks = <&ahb1_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 21>;
+ status = "disabled";
+ };
+
+ spi2: spi at 01c6a000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c6a000 0x1000>;
+ interrupts = <0 67 4>;
+ clocks = <&ahb1_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 25>, <&dma 25>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 22>;
+ status = "disabled";
+ };
+
+ spi3: spi at 01c6b000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c6b000 0x1000>;
+ interrupts = <0 68 4>;
+ clocks = <&ahb1_gates 23>, <&spi3_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 26>, <&dma 26>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 23>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller at 01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ rtc: rtc at 01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <0 40 4>, <0 41 4>;
+ };
+
+ nmi_intc: interrupt-controller at 01f00c0c {
+ compatible = "allwinner,sun6i-a31-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c0c 0x38>;
+ interrupts = <0 32 4>;
+ };
+
+ prcm at 01f01400 {
+ compatible = "allwinner,sun6i-a31-prcm";
+ reg = <0x01f01400 0x200>;
+
+ ar100: ar100_clk {
+ compatible = "allwinner,sun6i-a31-ar100-clk";
+ #clock-cells = <0>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+ clock-output-names = "ar100";
+ };
+
+ ahb0: ahb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&ar100>;
+ clock-output-names = "ahb0";
+ };
+
+ apb0: apb0_clk {
+ compatible = "allwinner,sun6i-a31-apb0-clk";
+ #clock-cells = <0>;
+ clocks = <&ahb0>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: apb0_gates_clk {
+ compatible = "allwinner,sun6i-a31-apb0-gates-clk";
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_pio", "apb0_ir",
+ "apb0_timer", "apb0_p2wi",
+ "apb0_uart", "apb0_1wire",
+ "apb0_i2c";
+ };
+
+ ir_clk: ir_clk {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ir-clk";
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "ir";
+ };
+
+ apb0_rst: apb0_rst {
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ cpucfg at 01f01c00 {
+ compatible = "allwinner,sun6i-a31-cpuconfig";
+ reg = <0x01f01c00 0x300>;
+ };
+
+ ir at 01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <&apb0_gates 1>, <&ir_clk>;
+ clock-names = "apb", "ir";
+ resets = <&apb0_rst 1>;
+ interrupts = <0 37 4>;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl at 01f02c00 {
+ compatible = "allwinner,sun6i-a31-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <0 45 4>,
+ <0 46 4>;
+ clocks = <&apb0_gates 0>;
+ resets = <&apb0_rst 0>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ ir_pins_a: ir at 0 {
+ allwinner,pins = "PL4";
+ allwinner,function = "s_ir";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+ };
+};
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-23 12:54 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: Linus Walleij, Maxime Ripard
Cc: Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Hans de Goede
The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html
Note it has no sdcard slot and therefore can only be fel booted.
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun6i-a31s-cs908.dts | 109 +++++++++++++++++++++++++++++++++
2 files changed, 111 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun6i-a31s-cs908.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8ebfa76..0c0201c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -434,7 +434,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
sun6i-a31-hummingbird.dtb \
- sun6i-a31-m9.dtb
+ sun6i-a31-m9.dtb \
+ sun6i-a31s-cs908.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-bananapi.dtb \
sun7i-a20-cubieboard2.dtb \
diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
new file mode 100644
index 0000000..48d3a70
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "sun6i-a31s.dtsi"
+
+/ {
+ model = "CSQ CS908 top set box";
+ compatible = "csq,cs908", "allwinner,sun6i-a31s";
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS0,115200";
+ };
+
+ soc@01c00000 {
+ usbphy: phy@01c19400 {
+ status = "okay";
+ };
+
+ ehci0: usb@01c1a000 {
+ status = "okay";
+ };
+
+ ehci1: usb@01c1b000 {
+ status = "okay";
+ };
+
+ ohci1: usb@01c1b400 {
+ status = "okay";
+ };
+
+ pio: pinctrl@01c20800 {
+ usb1_vbus_pin_csq908: usb1_vbus_pin@0 {
+ allwinner,pins = "PC27";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+ };
+
+ gmac: ethernet@01c30000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+
+ ir@01f02000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+ };
+ };
+};
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
@ 2014-11-23 12:54 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-23 12:54 UTC (permalink / raw)
To: linux-arm-kernel
The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html
Note it has no sdcard slot and therefore can only be fel booted.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun6i-a31s-cs908.dts | 109 +++++++++++++++++++++++++++++++++
2 files changed, 111 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun6i-a31s-cs908.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8ebfa76..0c0201c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -434,7 +434,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
sun6i-a31-hummingbird.dtb \
- sun6i-a31-m9.dtb
+ sun6i-a31-m9.dtb \
+ sun6i-a31s-cs908.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-bananapi.dtb \
sun7i-a20-cubieboard2.dtb \
diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
new file mode 100644
index 0000000..48d3a70
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "sun6i-a31s.dtsi"
+
+/ {
+ model = "CSQ CS908 top set box";
+ compatible = "csq,cs908", "allwinner,sun6i-a31s";
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS0,115200";
+ };
+
+ soc at 01c00000 {
+ usbphy: phy at 01c19400 {
+ status = "okay";
+ };
+
+ ehci0: usb at 01c1a000 {
+ status = "okay";
+ };
+
+ ehci1: usb at 01c1b000 {
+ status = "okay";
+ };
+
+ ohci1: usb at 01c1b400 {
+ status = "okay";
+ };
+
+ pio: pinctrl at 01c20800 {
+ usb1_vbus_pin_csq908: usb1_vbus_pin at 0 {
+ allwinner,pins = "PC27";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ uart0: serial at 01c28000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+ };
+
+ gmac: ethernet at 01c30000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ };
+
+ ir at 01f02000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+ };
+ };
+};
--
2.1.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-25 18:04 ` Maxime Ripard
-1 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:04 UTC (permalink / raw)
To: Hans de Goede
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 3698 bytes --]
Hi,
On Sun, Nov 23, 2014 at 01:54:39PM +0100, Hans de Goede wrote:
> While working on pinctrl for the A31s, I noticed that function 4 of
> PA15 - PA18 was missing, add these.
>
> I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
> be PB4 & PB5, fix this as well.
>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> index a2b4b85..fb19e15 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> @@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
> SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
> + SUNXI_FUNCTION(0x4, "clk_a_out"),
It's called clk_out_a on the A20, I'd rather stick with the same
scheme here.
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
> SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
> SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
> SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
> + SUNXI_FUNCTION(0x4, "clk_b_out"),
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
> SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
> + SUNXI_FUNCTION(0x4, "clk_c_out"),
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
> SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
> SUNXI_FUNCTION(0x3, "uart3"), /* TX */
> - SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
> SUNXI_FUNCTION(0x3, "uart3"), /* RX */
> - SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
Where did you get that info from? The datasheet still reports that
information.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
@ 2014-11-25 18:04 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:04 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Sun, Nov 23, 2014 at 01:54:39PM +0100, Hans de Goede wrote:
> While working on pinctrl for the A31s, I noticed that function 4 of
> PA15 - PA18 was missing, add these.
>
> I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
> be PB4 & PB5, fix this as well.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> index a2b4b85..fb19e15 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> @@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
> SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
> + SUNXI_FUNCTION(0x4, "clk_a_out"),
It's called clk_out_a on the A20, I'd rather stick with the same
scheme here.
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
> SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
> SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
> SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
> + SUNXI_FUNCTION(0x4, "clk_b_out"),
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
> SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
> + SUNXI_FUNCTION(0x4, "clk_c_out"),
> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
> SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
> SUNXI_FUNCTION(0x3, "uart3"), /* TX */
> - SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
> SUNXI_FUNCTION(0x3, "uart3"), /* RX */
> - SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
Where did you get that info from? The datasheet still reports that
information.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 2/5] pinctrl: sun6i: Add A31s pinctrl support
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-25 18:08 ` Maxime Ripard
-1 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:08 UTC (permalink / raw)
To: Hans de Goede
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 38092 bytes --]
On Sun, Nov 23, 2014 at 01:54:40PM +0100, Hans de Goede wrote:
> The A31s is a stripped down version of the A31, as such it is missing some
> pins and some functions on some pins.
>
> The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
> with the missing pins and functions removed.
>
> Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
> prcm pins are identical between the A31 and the A31s.
>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
> drivers/pinctrl/sunxi/Kconfig | 4 +
> drivers/pinctrl/sunxi/Makefile | 1 +
> drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c | 814 +++++++++++++++++++++
> 4 files changed, 820 insertions(+)
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index 93ce12e..fdd8046 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -11,6 +11,7 @@ Required properties:
> "allwinner,sun5i-a10s-pinctrl"
> "allwinner,sun5i-a13-pinctrl"
> "allwinner,sun6i-a31-pinctrl"
> + "allwinner,sun6i-a31s-pinctrl"
> "allwinner,sun6i-a31-r-pinctrl"
> "allwinner,sun7i-a20-pinctrl"
> "allwinner,sun8i-a23-pinctrl"
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index a5e10f7..6cffe38 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
> def_bool MACH_SUN6I
> select PINCTRL_SUNXI_COMMON
>
> +config PINCTRL_SUN6I_A31S
> + def_bool MACH_SUN6I
> + select PINCTRL_SUNXI_COMMON
> +
> config PINCTRL_SUN6I_A31_R
> def_bool MACH_SUN6I
> depends on RESET_CONTROLLER
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index e797efb..2f82290 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
> obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
> obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
> obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
> +obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
> obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
> obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
> obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> new file mode 100644
> index 0000000..42ee373
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> @@ -0,0 +1,814 @@
> +/*
> + * Allwinner A31 SoCs pinctrl driver.
^ A31s
> + *
> + * Copyright (C) 2014 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
And I guess your copyright would be more appropriate here.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun6i_a31s_pins[] = {
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* RING */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
> + SUNXI_FUNCTION(0x4, "clk_a_out"),
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
> + SUNXI_FUNCTION(0x4, "clk_b_out"),
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
> + SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
> + SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
> + SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
> + SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* COL */
> + SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
> + SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
> + SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
> + SUNXI_FUNCTION(0x4, "clk_c_out"),
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
> + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
> + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
> + SUNXI_FUNCTION(0x3, "uart3"), /* TX */
> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
> + SUNXI_FUNCTION(0x3, "uart3"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* RE */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
> + /* Hole in pin numbering ! */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
> + SUNXI_FUNCTION(0x3, "ts"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
> + SUNXI_FUNCTION(0x3, "ts"), /* ERR */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
> + SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
> + SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D0 */
> + SUNXI_FUNCTION(0x3, "uart5"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D1 */
> + SUNXI_FUNCTION(0x3, "uart5"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D2 */
> + SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D3 */
> + SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D4 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D5 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D1 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D6 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D2 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D7 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D3 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D8 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D4 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D9 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D5 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D10 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D6 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D11 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D7 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
> + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
> + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
> + SUNXI_FUNCTION(0x4, "uart0")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
> + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
> + SUNXI_FUNCTION(0x4, "uart0")), /* RX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
> + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart4"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart4"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
> + /* Hole, note H starts at pin 9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
> + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
> + SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
> + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
> + SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
> + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
> + SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
> + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
> + SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "pwm0")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart0")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart0")), /* RX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> +};
> +
> +static const struct sunxi_pinctrl_desc sun6i_a31s_pinctrl_data = {
> + .pins = sun6i_a31s_pins,
> + .npins = ARRAY_SIZE(sun6i_a31s_pins),
> + .irq_banks = 4,
> +};
> +
> +static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev)
> +{
> + return sunxi_pinctrl_init(pdev,
> + &sun6i_a31s_pinctrl_data);
> +}
> +
> +static struct of_device_id sun6i_a31s_pinctrl_match[] = {
> + { .compatible = "allwinner,sun6i-a31s-pinctrl", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, sun6i_a31s_pinctrl_match);
> +
> +static struct platform_driver sun6i_a31s_pinctrl_driver = {
> + .probe = sun6i_a31s_pinctrl_probe,
> + .driver = {
> + .name = "sun6i-a31s-pinctrl",
> + .owner = THIS_MODULE,
> + .of_match_table = sun6i_a31s_pinctrl_match,
> + },
> +};
> +module_platform_driver(sun6i_a31s_pinctrl_driver);
> +
> +MODULE_AUTHOR("Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org");
> +MODULE_DESCRIPTION("Allwinner A31 pinctrl driver");
s/A31/A31s/
It looks fine otherwise. Once these very minor issues fixed, you can
add my Acked-by.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 2/5] pinctrl: sun6i: Add A31s pinctrl support
@ 2014-11-25 18:08 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:08 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Nov 23, 2014 at 01:54:40PM +0100, Hans de Goede wrote:
> The A31s is a stripped down version of the A31, as such it is missing some
> pins and some functions on some pins.
>
> The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
> with the missing pins and functions removed.
>
> Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
> prcm pins are identical between the A31 and the A31s.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
> drivers/pinctrl/sunxi/Kconfig | 4 +
> drivers/pinctrl/sunxi/Makefile | 1 +
> drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c | 814 +++++++++++++++++++++
> 4 files changed, 820 insertions(+)
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index 93ce12e..fdd8046 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -11,6 +11,7 @@ Required properties:
> "allwinner,sun5i-a10s-pinctrl"
> "allwinner,sun5i-a13-pinctrl"
> "allwinner,sun6i-a31-pinctrl"
> + "allwinner,sun6i-a31s-pinctrl"
> "allwinner,sun6i-a31-r-pinctrl"
> "allwinner,sun7i-a20-pinctrl"
> "allwinner,sun8i-a23-pinctrl"
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index a5e10f7..6cffe38 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
> def_bool MACH_SUN6I
> select PINCTRL_SUNXI_COMMON
>
> +config PINCTRL_SUN6I_A31S
> + def_bool MACH_SUN6I
> + select PINCTRL_SUNXI_COMMON
> +
> config PINCTRL_SUN6I_A31_R
> def_bool MACH_SUN6I
> depends on RESET_CONTROLLER
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index e797efb..2f82290 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
> obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
> obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
> obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
> +obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
> obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
> obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
> obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> new file mode 100644
> index 0000000..42ee373
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> @@ -0,0 +1,814 @@
> +/*
> + * Allwinner A31 SoCs pinctrl driver.
^ A31s
> + *
> + * Copyright (C) 2014 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
And I guess your copyright would be more appropriate here.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun6i_a31s_pins[] = {
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* RING */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
> + SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
> + SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
> + SUNXI_FUNCTION(0x4, "clk_a_out"),
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
> + SUNXI_FUNCTION(0x4, "clk_b_out"),
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
> + SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
> + SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
> + SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
> + SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* COL */
> + SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
> + SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
> + SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
> + SUNXI_FUNCTION(0x4, "clk_c_out"),
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
> + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
> + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
> + SUNXI_FUNCTION(0x3, "uart3"), /* TX */
> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
> + SUNXI_FUNCTION(0x3, "uart3"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* RE */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
> + /* Hole in pin numbering ! */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
> + SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
> + SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
> + SUNXI_FUNCTION(0x3, "ts"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
> + SUNXI_FUNCTION(0x3, "ts"), /* ERR */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
> + SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
> + SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D0 */
> + SUNXI_FUNCTION(0x3, "uart5"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D1 */
> + SUNXI_FUNCTION(0x3, "uart5"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D2 */
> + SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D3 */
> + SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D4 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D5 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D1 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D6 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D2 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D7 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D3 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D8 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D4 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D9 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D5 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D10 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D6 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* D11 */
> + SUNXI_FUNCTION(0x3, "ts"), /* D7 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
> + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
> + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
> + SUNXI_FUNCTION(0x4, "uart0")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
> + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
> + SUNXI_FUNCTION(0x4, "uart0")), /* RX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
> + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
> + SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart4"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart4"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
> + /* Hole, note H starts at pin 9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
> + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
> + SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
> + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
> + SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
> + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
> + SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
> + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
> + SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "pwm0")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart0")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart0")), /* RX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> +};
> +
> +static const struct sunxi_pinctrl_desc sun6i_a31s_pinctrl_data = {
> + .pins = sun6i_a31s_pins,
> + .npins = ARRAY_SIZE(sun6i_a31s_pins),
> + .irq_banks = 4,
> +};
> +
> +static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev)
> +{
> + return sunxi_pinctrl_init(pdev,
> + &sun6i_a31s_pinctrl_data);
> +}
> +
> +static struct of_device_id sun6i_a31s_pinctrl_match[] = {
> + { .compatible = "allwinner,sun6i-a31s-pinctrl", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, sun6i_a31s_pinctrl_match);
> +
> +static struct platform_driver sun6i_a31s_pinctrl_driver = {
> + .probe = sun6i_a31s_pinctrl_probe,
> + .driver = {
> + .name = "sun6i-a31s-pinctrl",
> + .owner = THIS_MODULE,
> + .of_match_table = sun6i_a31s_pinctrl_match,
> + },
> +};
> +module_platform_driver(sun6i_a31s_pinctrl_driver);
> +
> +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
> +MODULE_DESCRIPTION("Allwinner A31 pinctrl driver");
s/A31/A31s/
It looks fine otherwise. Once these very minor issues fixed, you can
add my Acked-by.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-25 18:18 ` Maxime Ripard
-1 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:18 UTC (permalink / raw)
To: Hans de Goede
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 27730 bytes --]
Hi,
On Sun, Nov 23, 2014 at 01:54:42PM +0100, Hans de Goede wrote:
> Add a dtsi file for A31s based boards. This is a copy of sun6i-a31.dtsi, with:
>
> -The main pinctrl compatible changed to allwinner,sun6i-a31s.dtsi
> -The ohci2 controller is present according to the data-sheet, but not routed
> to the outside, so remove it from the dtsi as having an always disabled node
> is not useful.
>
> All the other nodes present in the original sun6i-a31.dtsi are present in
> the A31s too, and are 100% compatible.
Then maybe duplicating the DT isn't worth it then.
Creating a sun6i.dtsi and including that from both the A31 and A31s
seems more like an appropriate solution.
>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm/boot/dts/sun6i-a31s.dtsi | 925 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 925 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
>
> diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
> new file mode 100644
> index 0000000..b3b99a9
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
> @@ -0,0 +1,925 @@
> +/*
> + * Copyright 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
It should be your copyright here.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public
> + * License along with this library; if not, write to the Free
> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> + * MA 02110-1301 USA
There was an issue with the wording of the license, s/library/file/
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + ethernet0 = &gmac;
> + };
> +
> + chosen {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + framebuffer@0 {
> + compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
> + allwinner,pipeline = "de_be0-lcd0-hdmi";
> + clocks = <&pll6>;
pll6 uses an argument now
> + status = "disabled";
> + };
> + };
> +
> + cpus {
> + enable-method = "allwinner,sun6i-a31";
allwinner,sun6i-a31s I guess?
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <3>;
> + };
> + };
> +
> + memory {
> + reg = <0x40000000 0x80000000>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
> + interrupts = <0 120 4>,
> + <0 121 4>,
> + <0 122 4>,
> + <0 123 4>;
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + };
> +
> + osc32k: clk@0 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + pll1: clk@01c20000 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-pll1-clk";
> + reg = <0x01c20000 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll1";
> + };
> +
> + pll6: clk@01c20028 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-pll6-clk";
> + reg = <0x01c20028 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll6";
> + };
> +
> + cpu: cpu@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-cpu-clk";
> + reg = <0x01c20050 0x4>;
> +
> + /*
> + * PLL1 is listed twice here.
> + * While it looks suspicious, it's actually documented
> + * that way both in the datasheet and in the code from
> + * Allwinner.
> + */
> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> + clock-output-names = "cpu";
> + };
> +
> + axi: axi@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-axi-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&cpu>;
> + clock-output-names = "axi";
> + };
> +
> + ahb1_mux: ahb1_mux@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
> + clock-output-names = "ahb1_mux";
> + };
> +
> + ahb1: ahb1@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-ahb-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb1_mux>;
> + clock-output-names = "ahb1";
> + };
> +
> + ahb1_gates: clk@01c20060 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
> + reg = <0x01c20060 0x8>;
> + clocks = <&ahb1>;
> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
> + "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
> + "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
> + "ahb1_nand0", "ahb1_sdram",
> + "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
> + "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
> + "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
> + "ahb1_ehci1", "ahb1_ohci0",
> + "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
> + "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
> + "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
> + "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
> + "ahb1_drc0", "ahb1_drc1";
> + };
Are the gates really identical?
As in not even stripped down?
> + apb1: apb1@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb0-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb1>;
> + clock-output-names = "apb1";
> + };
> +
> + apb1_gates: clk@01c20068 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-apb1-gates-clk";
> + reg = <0x01c20068 0x4>;
> + clocks = <&apb1>;
> + clock-output-names = "apb1_codec", "apb1_digital_mic",
> + "apb1_pio", "apb1_daudio0",
> + "apb1_daudio1";
> + };
> +
> + apb2_mux: apb2_mux@01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
> + clock-output-names = "apb2_mux";
> + };
> +
> + apb2: apb2@01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-apb2-div-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&apb2_mux>;
> + clock-output-names = "apb2";
> + };
> +
> + apb2_gates: clk@01c2006c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-apb2-gates-clk";
> + reg = <0x01c2006c 0x4>;
> + clocks = <&apb2>;
> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
> + "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
> + "apb2_uart1", "apb2_uart2", "apb2_uart3",
> + "apb2_uart4", "apb2_uart5";
> + };
> +
> + mmc0_clk: clk@01c20088 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20088 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "mmc0";
> + };
> +
> + mmc1_clk: clk@01c2008c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c2008c 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "mmc1";
> + };
> +
> + mmc2_clk: clk@01c20090 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20090 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "mmc2";
> + };
> +
> + mmc3_clk: clk@01c20094 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20094 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "mmc3";
> + };
> +
> + spi0_clk: clk@01c200a0 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200a0 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "spi0";
> + };
> +
> + spi1_clk: clk@01c200a4 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200a4 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "spi1";
> + };
> +
> + spi2_clk: clk@01c200a8 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200a8 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "spi2";
> + };
> +
> + spi3_clk: clk@01c200ac {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200ac 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "spi3";
> + };
> +
> + usb_clk: clk@01c200cc {
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-usb-clk";
> + reg = <0x01c200cc 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
> + "usb_ohci0", "usb_ohci1",
> + "usb_ohci2";
> + };
> +
> + /*
> + * The following two are dummy clocks, placeholders used in the gmac_tx
> + * clock. The gmac driver will choose one parent depending on the PHY
> + * interface mode, using clk_set_rate auto-reparenting.
> + * The actual TX clock rate is not controlled by the gmac_tx clock.
> + */
> + mii_phy_tx_clk: clk@1 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <25000000>;
> + clock-output-names = "mii_phy_tx";
> + };
> +
> + gmac_int_tx_clk: clk@2 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + clock-output-names = "gmac_int_tx";
> + };
> +
> + gmac_tx_clk: clk@01c200d0 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun7i-a20-gmac-clk";
> + reg = <0x01c200d0 0x4>;
> + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
> + clock-output-names = "gmac_tx";
> + };
> + };
> +
> + soc@01c00000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + dma: dma-controller@01c02000 {
> + compatible = "allwinner,sun6i-a31-dma";
> + reg = <0x01c02000 0x1000>;
> + interrupts = <0 50 4>;
> + clocks = <&ahb1_gates 6>;
> + resets = <&ahb1_rst 6>;
> + #dma-cells = <1>;
> + };
> +
> + mmc0: mmc@01c0f000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ahb1_gates 8>, <&mmc0_clk>;
> + clock-names = "ahb", "mmc";
> + resets = <&ahb1_rst 8>;
> + reset-names = "ahb";
> + interrupts = <0 60 4>;
> + status = "disabled";
> + };
> +
> + mmc1: mmc@01c10000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ahb1_gates 9>, <&mmc1_clk>;
> + clock-names = "ahb", "mmc";
> + resets = <&ahb1_rst 9>;
> + reset-names = "ahb";
> + interrupts = <0 61 4>;
> + status = "disabled";
> + };
> +
> + mmc2: mmc@01c11000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&ahb1_gates 10>, <&mmc2_clk>;
> + clock-names = "ahb", "mmc";
> + resets = <&ahb1_rst 10>;
> + reset-names = "ahb";
> + interrupts = <0 62 4>;
> + status = "disabled";
> + };
> +
> + mmc3: mmc@01c12000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c12000 0x1000>;
> + clocks = <&ahb1_gates 11>, <&mmc3_clk>;
> + clock-names = "ahb", "mmc";
> + resets = <&ahb1_rst 11>;
> + reset-names = "ahb";
> + interrupts = <0 63 4>;
> + status = "disabled";
> + };
> +
> + usbphy: phy@01c19400 {
> + compatible = "allwinner,sun6i-a31-usb-phy";
> + reg = <0x01c19400 0x10>,
> + <0x01c1a800 0x4>,
> + <0x01c1b800 0x4>;
> + reg-names = "phy_ctrl",
> + "pmu1",
> + "pmu2";
> + clocks = <&usb_clk 8>,
> + <&usb_clk 9>,
> + <&usb_clk 10>;
> + clock-names = "usb0_phy",
> + "usb1_phy",
> + "usb2_phy";
> + resets = <&usb_clk 0>,
> + <&usb_clk 1>,
> + <&usb_clk 2>;
> + reset-names = "usb0_reset",
> + "usb1_reset",
> + "usb2_reset";
> + status = "disabled";
> + #phy-cells = <1>;
> + };
> +
> + ehci0: usb@01c1a000 {
> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
> + reg = <0x01c1a000 0x100>;
> + interrupts = <0 72 4>;
> + clocks = <&ahb1_gates 26>;
> + resets = <&ahb1_rst 26>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci0: usb@01c1a400 {
> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
> + reg = <0x01c1a400 0x100>;
> + interrupts = <0 73 4>;
> + clocks = <&ahb1_gates 29>, <&usb_clk 16>;
> + resets = <&ahb1_rst 29>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci1: usb@01c1b000 {
> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
> + reg = <0x01c1b000 0x100>;
> + interrupts = <0 74 4>;
> + clocks = <&ahb1_gates 27>;
> + resets = <&ahb1_rst 27>;
> + phys = <&usbphy 2>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci1: usb@01c1b400 {
> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
> + reg = <0x01c1b400 0x100>;
> + interrupts = <0 75 4>;
> + clocks = <&ahb1_gates 30>, <&usb_clk 17>;
> + resets = <&ahb1_rst 30>;
> + phys = <&usbphy 2>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + pio: pinctrl@01c20800 {
> + compatible = "allwinner,sun6i-a31s-pinctrl";
> + reg = <0x01c20800 0x400>;
> + interrupts = <0 11 4>,
> + <0 15 4>,
> + <0 16 4>,
> + <0 17 4>;
> + clocks = <&apb1_gates 5>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + #size-cells = <0>;
> + #gpio-cells = <3>;
> +
> + uart0_pins_a: uart0@0 {
> + allwinner,pins = "PH20", "PH21";
> + allwinner,function = "uart0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + i2c0_pins_a: i2c0@0 {
> + allwinner,pins = "PH14", "PH15";
> + allwinner,function = "i2c0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + i2c1_pins_a: i2c1@0 {
> + allwinner,pins = "PH16", "PH17";
> + allwinner,function = "i2c1";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + i2c2_pins_a: i2c2@0 {
> + allwinner,pins = "PH18", "PH19";
> + allwinner,function = "i2c2";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + mmc0_pins_a: mmc0@0 {
> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
Spaces after the comma, and I guess that would be better on two lines.
> + allwinner,function = "mmc0";
> + allwinner,drive = <2>;
> + allwinner,pull = <0>;
> + };
> +
> + gmac_pins_mii_a: gmac_mii@0 {
> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
> + "PA8", "PA9", "PA11",
> + "PA12", "PA13", "PA14", "PA19",
> + "PA20", "PA21", "PA22", "PA23",
> + "PA24", "PA26", "PA27";
> + allwinner,function = "gmac";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + gmac_pins_gmii_a: gmac_gmii@0 {
> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
> + "PA4", "PA5", "PA6", "PA7",
> + "PA8", "PA9", "PA10", "PA11",
> + "PA12", "PA13", "PA14", "PA15",
> + "PA16", "PA17", "PA18", "PA19",
> + "PA20", "PA21", "PA22", "PA23",
> + "PA24", "PA25", "PA26", "PA27";
> + allwinner,function = "gmac";
> + /*
> + * data lines in GMII mode run at 125MHz and
> + * might need a higher signal drive strength
> + */
> + allwinner,drive = <2>;
> + allwinner,pull = <0>;
> + };
> +
> + gmac_pins_rgmii_a: gmac_rgmii@0 {
> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
> + "PA9", "PA10", "PA11",
> + "PA12", "PA13", "PA14", "PA19",
> + "PA20", "PA25", "PA26", "PA27";
> + allwinner,function = "gmac";
> + /*
> + * data lines in RGMII mode use DDR mode
> + * and need a higher signal drive strength
> + */
> + allwinner,drive = <3>;
> + allwinner,pull = <0>;
> + };
> + };
> +
> + ahb1_rst: reset@01c202c0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-ahb1-reset";
> + reg = <0x01c202c0 0xc>;
> + };
> +
> + apb1_rst: reset@01c202d0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d0 0x4>;
> + };
> +
> + apb2_rst: reset@01c202d8 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d8 0x4>;
> + };
> +
> + timer@01c20c00 {
> + compatible = "allwinner,sun4i-a10-timer";
> + reg = <0x01c20c00 0xa0>;
> + interrupts = <0 18 4>,
> + <0 19 4>,
> + <0 20 4>,
> + <0 21 4>,
> + <0 22 4>;
> + clocks = <&osc24M>;
> + };
> +
> + wdt1: watchdog@01c20ca0 {
> + compatible = "allwinner,sun6i-a31-wdt";
> + reg = <0x01c20ca0 0x20>;
> + };
> +
> + uart0: serial@01c28000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28000 0x400>;
> + interrupts = <0 0 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 16>;
> + resets = <&apb2_rst 16>;
> + dmas = <&dma 6>, <&dma 6>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart1: serial@01c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <0 1 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 17>;
> + resets = <&apb2_rst 17>;
> + dmas = <&dma 7>, <&dma 7>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart2: serial@01c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <0 2 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 18>;
> + resets = <&apb2_rst 18>;
> + dmas = <&dma 8>, <&dma 8>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart3: serial@01c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <0 3 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 19>;
> + resets = <&apb2_rst 19>;
> + dmas = <&dma 9>, <&dma 9>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart4: serial@01c29000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29000 0x400>;
> + interrupts = <0 4 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 20>;
> + resets = <&apb2_rst 20>;
> + dmas = <&dma 10>, <&dma 10>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart5: serial@01c29400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29400 0x400>;
> + interrupts = <0 5 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 21>;
> + resets = <&apb2_rst 21>;
> + dmas = <&dma 22>, <&dma 22>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + i2c0: i2c@01c2ac00 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2ac00 0x400>;
> + interrupts = <0 6 4>;
> + clocks = <&apb2_gates 0>;
> + resets = <&apb2_rst 0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@01c2b000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = <0 7 4>;
> + clocks = <&apb2_gates 1>;
> + resets = <&apb2_rst 1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@01c2b400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = <0 8 4>;
> + clocks = <&apb2_gates 2>;
> + resets = <&apb2_rst 2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c@01c2b800 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b800 0x400>;
> + interrupts = <0 9 4>;
> + clocks = <&apb2_gates 3>;
> + resets = <&apb2_rst 3>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + gmac: ethernet@01c30000 {
> + compatible = "allwinner,sun7i-a20-gmac";
> + reg = <0x01c30000 0x1054>;
> + interrupts = <0 82 4>;
> + interrupt-names = "macirq";
> + clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
> + clock-names = "stmmaceth", "allwinner_gmac_tx";
> + resets = <&ahb1_rst 17>;
> + reset-names = "stmmaceth";
> + snps,pbl = <2>;
> + snps,fixed-burst;
> + snps,force_sf_dma_mode;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + timer@01c60000 {
> + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
> + reg = <0x01c60000 0x1000>;
> + interrupts = <0 51 4>,
> + <0 52 4>,
> + <0 53 4>,
> + <0 54 4>;
> + clocks = <&ahb1_gates 19>;
> + resets = <&ahb1_rst 19>;
> + };
> +
> + spi0: spi@01c68000 {
> + compatible = "allwinner,sun6i-a31-spi";
> + reg = <0x01c68000 0x1000>;
> + interrupts = <0 65 4>;
> + clocks = <&ahb1_gates 20>, <&spi0_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 23>, <&dma 23>;
> + dma-names = "rx", "tx";
> + resets = <&ahb1_rst 20>;
> + status = "disabled";
> + };
> +
> + spi1: spi@01c69000 {
> + compatible = "allwinner,sun6i-a31-spi";
> + reg = <0x01c69000 0x1000>;
> + interrupts = <0 66 4>;
> + clocks = <&ahb1_gates 21>, <&spi1_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 24>, <&dma 24>;
> + dma-names = "rx", "tx";
> + resets = <&ahb1_rst 21>;
> + status = "disabled";
> + };
> +
> + spi2: spi@01c6a000 {
> + compatible = "allwinner,sun6i-a31-spi";
> + reg = <0x01c6a000 0x1000>;
> + interrupts = <0 67 4>;
> + clocks = <&ahb1_gates 22>, <&spi2_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 25>, <&dma 25>;
> + dma-names = "rx", "tx";
> + resets = <&ahb1_rst 22>;
> + status = "disabled";
> + };
> +
> + spi3: spi@01c6b000 {
> + compatible = "allwinner,sun6i-a31-spi";
> + reg = <0x01c6b000 0x1000>;
> + interrupts = <0 68 4>;
> + clocks = <&ahb1_gates 23>, <&spi3_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 26>, <&dma 26>;
> + dma-names = "rx", "tx";
> + resets = <&ahb1_rst 23>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@01c81000 {
> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + reg = <0x01c81000 0x1000>,
> + <0x01c82000 0x1000>,
> + <0x01c84000 0x2000>,
> + <0x01c86000 0x2000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = <1 9 0xf04>;
> + };
> +
> + rtc: rtc@01f00000 {
> + compatible = "allwinner,sun6i-a31-rtc";
> + reg = <0x01f00000 0x54>;
> + interrupts = <0 40 4>, <0 41 4>;
> + };
> +
> + nmi_intc: interrupt-controller@01f00c0c {
> + compatible = "allwinner,sun6i-a31-sc-nmi";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + reg = <0x01f00c0c 0x38>;
> + interrupts = <0 32 4>;
> + };
> +
> + prcm@01f01400 {
> + compatible = "allwinner,sun6i-a31-prcm";
> + reg = <0x01f01400 0x200>;
> +
> + ar100: ar100_clk {
> + compatible = "allwinner,sun6i-a31-ar100-clk";
> + #clock-cells = <0>;
> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
> + clock-output-names = "ar100";
> + };
> +
> + ahb0: ahb0_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clocks = <&ar100>;
> + clock-output-names = "ahb0";
> + };
> +
> + apb0: apb0_clk {
> + compatible = "allwinner,sun6i-a31-apb0-clk";
> + #clock-cells = <0>;
> + clocks = <&ahb0>;
> + clock-output-names = "apb0";
> + };
> +
> + apb0_gates: apb0_gates_clk {
> + compatible = "allwinner,sun6i-a31-apb0-gates-clk";
> + #clock-cells = <1>;
> + clocks = <&apb0>;
> + clock-output-names = "apb0_pio", "apb0_ir",
> + "apb0_timer", "apb0_p2wi",
> + "apb0_uart", "apb0_1wire",
> + "apb0_i2c";
> + };
> +
> + ir_clk: ir_clk {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-ir-clk";
> + clocks = <&osc32k>, <&osc24M>;
> + clock-output-names = "ir";
> + };
This is yet to be agreed on....
> +
> + apb0_rst: apb0_rst {
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + #reset-cells = <1>;
> + };
> + };
> +
> + cpucfg@01f01c00 {
> + compatible = "allwinner,sun6i-a31-cpuconfig";
> + reg = <0x01f01c00 0x300>;
> + };
> +
> + ir@01f02000 {
> + compatible = "allwinner,sun5i-a13-ir";
> + clocks = <&apb0_gates 1>, <&ir_clk>;
> + clock-names = "apb", "ir";
> + resets = <&apb0_rst 1>;
> + interrupts = <0 37 4>;
> + reg = <0x01f02000 0x40>;
> + status = "disabled";
> + };
> +
> + r_pio: pinctrl@01f02c00 {
> + compatible = "allwinner,sun6i-a31-r-pinctrl";
> + reg = <0x01f02c00 0x400>;
> + interrupts = <0 45 4>,
> + <0 46 4>;
> + clocks = <&apb0_gates 0>;
> + resets = <&apb0_rst 0>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + #size-cells = <0>;
> + #gpio-cells = <3>;
> +
> + ir_pins_a: ir@0 {
> + allwinner,pins = "PL4";
> + allwinner,function = "s_ir";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> + };
> + };
> +};
> --
> 2.1.0
>
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
@ 2014-11-25 18:18 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Sun, Nov 23, 2014 at 01:54:42PM +0100, Hans de Goede wrote:
> Add a dtsi file for A31s based boards. This is a copy of sun6i-a31.dtsi, with:
>
> -The main pinctrl compatible changed to allwinner,sun6i-a31s.dtsi
> -The ohci2 controller is present according to the data-sheet, but not routed
> to the outside, so remove it from the dtsi as having an always disabled node
> is not useful.
>
> All the other nodes present in the original sun6i-a31.dtsi are present in
> the A31s too, and are 100% compatible.
Then maybe duplicating the DT isn't worth it then.
Creating a sun6i.dtsi and including that from both the A31 and A31s
seems more like an appropriate solution.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> arch/arm/boot/dts/sun6i-a31s.dtsi | 925 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 925 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
>
> diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
> new file mode 100644
> index 0000000..b3b99a9
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
> @@ -0,0 +1,925 @@
> +/*
> + * Copyright 2013 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
It should be your copyright here.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public
> + * License along with this library; if not, write to the Free
> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> + * MA 02110-1301 USA
There was an issue with the wording of the license, s/library/file/
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + ethernet0 = &gmac;
> + };
> +
> + chosen {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + framebuffer at 0 {
> + compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
> + allwinner,pipeline = "de_be0-lcd0-hdmi";
> + clocks = <&pll6>;
pll6 uses an argument now
> + status = "disabled";
> + };
> + };
> +
> + cpus {
> + enable-method = "allwinner,sun6i-a31";
allwinner,sun6i-a31s I guess?
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + };
> +
> + cpu at 1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + };
> +
> + cpu at 2 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <2>;
> + };
> +
> + cpu at 3 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <3>;
> + };
> + };
> +
> + memory {
> + reg = <0x40000000 0x80000000>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
> + interrupts = <0 120 4>,
> + <0 121 4>,
> + <0 122 4>,
> + <0 123 4>;
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + };
> +
> + osc32k: clk at 0 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + pll1: clk at 01c20000 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-pll1-clk";
> + reg = <0x01c20000 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll1";
> + };
> +
> + pll6: clk at 01c20028 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-pll6-clk";
> + reg = <0x01c20028 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll6";
> + };
> +
> + cpu: cpu at 01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-cpu-clk";
> + reg = <0x01c20050 0x4>;
> +
> + /*
> + * PLL1 is listed twice here.
> + * While it looks suspicious, it's actually documented
> + * that way both in the datasheet and in the code from
> + * Allwinner.
> + */
> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> + clock-output-names = "cpu";
> + };
> +
> + axi: axi at 01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-axi-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&cpu>;
> + clock-output-names = "axi";
> + };
> +
> + ahb1_mux: ahb1_mux at 01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
> + clock-output-names = "ahb1_mux";
> + };
> +
> + ahb1: ahb1 at 01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-ahb-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb1_mux>;
> + clock-output-names = "ahb1";
> + };
> +
> + ahb1_gates: clk at 01c20060 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
> + reg = <0x01c20060 0x8>;
> + clocks = <&ahb1>;
> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
> + "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
> + "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
> + "ahb1_nand0", "ahb1_sdram",
> + "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
> + "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
> + "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
> + "ahb1_ehci1", "ahb1_ohci0",
> + "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
> + "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
> + "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
> + "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
> + "ahb1_drc0", "ahb1_drc1";
> + };
Are the gates really identical?
As in not even stripped down?
> + apb1: apb1 at 01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb0-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb1>;
> + clock-output-names = "apb1";
> + };
> +
> + apb1_gates: clk at 01c20068 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-apb1-gates-clk";
> + reg = <0x01c20068 0x4>;
> + clocks = <&apb1>;
> + clock-output-names = "apb1_codec", "apb1_digital_mic",
> + "apb1_pio", "apb1_daudio0",
> + "apb1_daudio1";
> + };
> +
> + apb2_mux: apb2_mux at 01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
> + clock-output-names = "apb2_mux";
> + };
> +
> + apb2: apb2 at 01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-apb2-div-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&apb2_mux>;
> + clock-output-names = "apb2";
> + };
> +
> + apb2_gates: clk at 01c2006c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-apb2-gates-clk";
> + reg = <0x01c2006c 0x4>;
> + clocks = <&apb2>;
> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
> + "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
> + "apb2_uart1", "apb2_uart2", "apb2_uart3",
> + "apb2_uart4", "apb2_uart5";
> + };
> +
> + mmc0_clk: clk at 01c20088 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20088 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "mmc0";
> + };
> +
> + mmc1_clk: clk at 01c2008c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c2008c 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "mmc1";
> + };
> +
> + mmc2_clk: clk at 01c20090 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20090 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "mmc2";
> + };
> +
> + mmc3_clk: clk at 01c20094 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20094 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "mmc3";
> + };
> +
> + spi0_clk: clk at 01c200a0 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200a0 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "spi0";
> + };
> +
> + spi1_clk: clk at 01c200a4 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200a4 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "spi1";
> + };
> +
> + spi2_clk: clk at 01c200a8 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200a8 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "spi2";
> + };
> +
> + spi3_clk: clk at 01c200ac {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200ac 0x4>;
> + clocks = <&osc24M>, <&pll6>;
> + clock-output-names = "spi3";
> + };
> +
> + usb_clk: clk at 01c200cc {
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-usb-clk";
> + reg = <0x01c200cc 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
> + "usb_ohci0", "usb_ohci1",
> + "usb_ohci2";
> + };
> +
> + /*
> + * The following two are dummy clocks, placeholders used in the gmac_tx
> + * clock. The gmac driver will choose one parent depending on the PHY
> + * interface mode, using clk_set_rate auto-reparenting.
> + * The actual TX clock rate is not controlled by the gmac_tx clock.
> + */
> + mii_phy_tx_clk: clk at 1 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <25000000>;
> + clock-output-names = "mii_phy_tx";
> + };
> +
> + gmac_int_tx_clk: clk at 2 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + clock-output-names = "gmac_int_tx";
> + };
> +
> + gmac_tx_clk: clk at 01c200d0 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun7i-a20-gmac-clk";
> + reg = <0x01c200d0 0x4>;
> + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
> + clock-output-names = "gmac_tx";
> + };
> + };
> +
> + soc at 01c00000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + dma: dma-controller at 01c02000 {
> + compatible = "allwinner,sun6i-a31-dma";
> + reg = <0x01c02000 0x1000>;
> + interrupts = <0 50 4>;
> + clocks = <&ahb1_gates 6>;
> + resets = <&ahb1_rst 6>;
> + #dma-cells = <1>;
> + };
> +
> + mmc0: mmc at 01c0f000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ahb1_gates 8>, <&mmc0_clk>;
> + clock-names = "ahb", "mmc";
> + resets = <&ahb1_rst 8>;
> + reset-names = "ahb";
> + interrupts = <0 60 4>;
> + status = "disabled";
> + };
> +
> + mmc1: mmc at 01c10000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ahb1_gates 9>, <&mmc1_clk>;
> + clock-names = "ahb", "mmc";
> + resets = <&ahb1_rst 9>;
> + reset-names = "ahb";
> + interrupts = <0 61 4>;
> + status = "disabled";
> + };
> +
> + mmc2: mmc at 01c11000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&ahb1_gates 10>, <&mmc2_clk>;
> + clock-names = "ahb", "mmc";
> + resets = <&ahb1_rst 10>;
> + reset-names = "ahb";
> + interrupts = <0 62 4>;
> + status = "disabled";
> + };
> +
> + mmc3: mmc at 01c12000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c12000 0x1000>;
> + clocks = <&ahb1_gates 11>, <&mmc3_clk>;
> + clock-names = "ahb", "mmc";
> + resets = <&ahb1_rst 11>;
> + reset-names = "ahb";
> + interrupts = <0 63 4>;
> + status = "disabled";
> + };
> +
> + usbphy: phy at 01c19400 {
> + compatible = "allwinner,sun6i-a31-usb-phy";
> + reg = <0x01c19400 0x10>,
> + <0x01c1a800 0x4>,
> + <0x01c1b800 0x4>;
> + reg-names = "phy_ctrl",
> + "pmu1",
> + "pmu2";
> + clocks = <&usb_clk 8>,
> + <&usb_clk 9>,
> + <&usb_clk 10>;
> + clock-names = "usb0_phy",
> + "usb1_phy",
> + "usb2_phy";
> + resets = <&usb_clk 0>,
> + <&usb_clk 1>,
> + <&usb_clk 2>;
> + reset-names = "usb0_reset",
> + "usb1_reset",
> + "usb2_reset";
> + status = "disabled";
> + #phy-cells = <1>;
> + };
> +
> + ehci0: usb at 01c1a000 {
> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
> + reg = <0x01c1a000 0x100>;
> + interrupts = <0 72 4>;
> + clocks = <&ahb1_gates 26>;
> + resets = <&ahb1_rst 26>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci0: usb at 01c1a400 {
> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
> + reg = <0x01c1a400 0x100>;
> + interrupts = <0 73 4>;
> + clocks = <&ahb1_gates 29>, <&usb_clk 16>;
> + resets = <&ahb1_rst 29>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci1: usb at 01c1b000 {
> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
> + reg = <0x01c1b000 0x100>;
> + interrupts = <0 74 4>;
> + clocks = <&ahb1_gates 27>;
> + resets = <&ahb1_rst 27>;
> + phys = <&usbphy 2>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci1: usb at 01c1b400 {
> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
> + reg = <0x01c1b400 0x100>;
> + interrupts = <0 75 4>;
> + clocks = <&ahb1_gates 30>, <&usb_clk 17>;
> + resets = <&ahb1_rst 30>;
> + phys = <&usbphy 2>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + pio: pinctrl at 01c20800 {
> + compatible = "allwinner,sun6i-a31s-pinctrl";
> + reg = <0x01c20800 0x400>;
> + interrupts = <0 11 4>,
> + <0 15 4>,
> + <0 16 4>,
> + <0 17 4>;
> + clocks = <&apb1_gates 5>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + #size-cells = <0>;
> + #gpio-cells = <3>;
> +
> + uart0_pins_a: uart0 at 0 {
> + allwinner,pins = "PH20", "PH21";
> + allwinner,function = "uart0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + i2c0_pins_a: i2c0 at 0 {
> + allwinner,pins = "PH14", "PH15";
> + allwinner,function = "i2c0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + i2c1_pins_a: i2c1 at 0 {
> + allwinner,pins = "PH16", "PH17";
> + allwinner,function = "i2c1";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + i2c2_pins_a: i2c2 at 0 {
> + allwinner,pins = "PH18", "PH19";
> + allwinner,function = "i2c2";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + mmc0_pins_a: mmc0 at 0 {
> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
Spaces after the comma, and I guess that would be better on two lines.
> + allwinner,function = "mmc0";
> + allwinner,drive = <2>;
> + allwinner,pull = <0>;
> + };
> +
> + gmac_pins_mii_a: gmac_mii at 0 {
> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
> + "PA8", "PA9", "PA11",
> + "PA12", "PA13", "PA14", "PA19",
> + "PA20", "PA21", "PA22", "PA23",
> + "PA24", "PA26", "PA27";
> + allwinner,function = "gmac";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + gmac_pins_gmii_a: gmac_gmii at 0 {
> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
> + "PA4", "PA5", "PA6", "PA7",
> + "PA8", "PA9", "PA10", "PA11",
> + "PA12", "PA13", "PA14", "PA15",
> + "PA16", "PA17", "PA18", "PA19",
> + "PA20", "PA21", "PA22", "PA23",
> + "PA24", "PA25", "PA26", "PA27";
> + allwinner,function = "gmac";
> + /*
> + * data lines in GMII mode run at 125MHz and
> + * might need a higher signal drive strength
> + */
> + allwinner,drive = <2>;
> + allwinner,pull = <0>;
> + };
> +
> + gmac_pins_rgmii_a: gmac_rgmii at 0 {
> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
> + "PA9", "PA10", "PA11",
> + "PA12", "PA13", "PA14", "PA19",
> + "PA20", "PA25", "PA26", "PA27";
> + allwinner,function = "gmac";
> + /*
> + * data lines in RGMII mode use DDR mode
> + * and need a higher signal drive strength
> + */
> + allwinner,drive = <3>;
> + allwinner,pull = <0>;
> + };
> + };
> +
> + ahb1_rst: reset at 01c202c0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-ahb1-reset";
> + reg = <0x01c202c0 0xc>;
> + };
> +
> + apb1_rst: reset at 01c202d0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d0 0x4>;
> + };
> +
> + apb2_rst: reset at 01c202d8 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d8 0x4>;
> + };
> +
> + timer at 01c20c00 {
> + compatible = "allwinner,sun4i-a10-timer";
> + reg = <0x01c20c00 0xa0>;
> + interrupts = <0 18 4>,
> + <0 19 4>,
> + <0 20 4>,
> + <0 21 4>,
> + <0 22 4>;
> + clocks = <&osc24M>;
> + };
> +
> + wdt1: watchdog at 01c20ca0 {
> + compatible = "allwinner,sun6i-a31-wdt";
> + reg = <0x01c20ca0 0x20>;
> + };
> +
> + uart0: serial at 01c28000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28000 0x400>;
> + interrupts = <0 0 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 16>;
> + resets = <&apb2_rst 16>;
> + dmas = <&dma 6>, <&dma 6>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart1: serial at 01c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <0 1 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 17>;
> + resets = <&apb2_rst 17>;
> + dmas = <&dma 7>, <&dma 7>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart2: serial at 01c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <0 2 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 18>;
> + resets = <&apb2_rst 18>;
> + dmas = <&dma 8>, <&dma 8>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart3: serial at 01c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <0 3 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 19>;
> + resets = <&apb2_rst 19>;
> + dmas = <&dma 9>, <&dma 9>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart4: serial at 01c29000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29000 0x400>;
> + interrupts = <0 4 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 20>;
> + resets = <&apb2_rst 20>;
> + dmas = <&dma 10>, <&dma 10>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart5: serial at 01c29400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29400 0x400>;
> + interrupts = <0 5 4>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 21>;
> + resets = <&apb2_rst 21>;
> + dmas = <&dma 22>, <&dma 22>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + i2c0: i2c at 01c2ac00 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2ac00 0x400>;
> + interrupts = <0 6 4>;
> + clocks = <&apb2_gates 0>;
> + resets = <&apb2_rst 0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c at 01c2b000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = <0 7 4>;
> + clocks = <&apb2_gates 1>;
> + resets = <&apb2_rst 1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c at 01c2b400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = <0 8 4>;
> + clocks = <&apb2_gates 2>;
> + resets = <&apb2_rst 2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c at 01c2b800 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b800 0x400>;
> + interrupts = <0 9 4>;
> + clocks = <&apb2_gates 3>;
> + resets = <&apb2_rst 3>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + gmac: ethernet at 01c30000 {
> + compatible = "allwinner,sun7i-a20-gmac";
> + reg = <0x01c30000 0x1054>;
> + interrupts = <0 82 4>;
> + interrupt-names = "macirq";
> + clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
> + clock-names = "stmmaceth", "allwinner_gmac_tx";
> + resets = <&ahb1_rst 17>;
> + reset-names = "stmmaceth";
> + snps,pbl = <2>;
> + snps,fixed-burst;
> + snps,force_sf_dma_mode;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + timer at 01c60000 {
> + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
> + reg = <0x01c60000 0x1000>;
> + interrupts = <0 51 4>,
> + <0 52 4>,
> + <0 53 4>,
> + <0 54 4>;
> + clocks = <&ahb1_gates 19>;
> + resets = <&ahb1_rst 19>;
> + };
> +
> + spi0: spi at 01c68000 {
> + compatible = "allwinner,sun6i-a31-spi";
> + reg = <0x01c68000 0x1000>;
> + interrupts = <0 65 4>;
> + clocks = <&ahb1_gates 20>, <&spi0_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 23>, <&dma 23>;
> + dma-names = "rx", "tx";
> + resets = <&ahb1_rst 20>;
> + status = "disabled";
> + };
> +
> + spi1: spi at 01c69000 {
> + compatible = "allwinner,sun6i-a31-spi";
> + reg = <0x01c69000 0x1000>;
> + interrupts = <0 66 4>;
> + clocks = <&ahb1_gates 21>, <&spi1_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 24>, <&dma 24>;
> + dma-names = "rx", "tx";
> + resets = <&ahb1_rst 21>;
> + status = "disabled";
> + };
> +
> + spi2: spi at 01c6a000 {
> + compatible = "allwinner,sun6i-a31-spi";
> + reg = <0x01c6a000 0x1000>;
> + interrupts = <0 67 4>;
> + clocks = <&ahb1_gates 22>, <&spi2_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 25>, <&dma 25>;
> + dma-names = "rx", "tx";
> + resets = <&ahb1_rst 22>;
> + status = "disabled";
> + };
> +
> + spi3: spi at 01c6b000 {
> + compatible = "allwinner,sun6i-a31-spi";
> + reg = <0x01c6b000 0x1000>;
> + interrupts = <0 68 4>;
> + clocks = <&ahb1_gates 23>, <&spi3_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 26>, <&dma 26>;
> + dma-names = "rx", "tx";
> + resets = <&ahb1_rst 23>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller at 01c81000 {
> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + reg = <0x01c81000 0x1000>,
> + <0x01c82000 0x1000>,
> + <0x01c84000 0x2000>,
> + <0x01c86000 0x2000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = <1 9 0xf04>;
> + };
> +
> + rtc: rtc at 01f00000 {
> + compatible = "allwinner,sun6i-a31-rtc";
> + reg = <0x01f00000 0x54>;
> + interrupts = <0 40 4>, <0 41 4>;
> + };
> +
> + nmi_intc: interrupt-controller at 01f00c0c {
> + compatible = "allwinner,sun6i-a31-sc-nmi";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + reg = <0x01f00c0c 0x38>;
> + interrupts = <0 32 4>;
> + };
> +
> + prcm at 01f01400 {
> + compatible = "allwinner,sun6i-a31-prcm";
> + reg = <0x01f01400 0x200>;
> +
> + ar100: ar100_clk {
> + compatible = "allwinner,sun6i-a31-ar100-clk";
> + #clock-cells = <0>;
> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
> + clock-output-names = "ar100";
> + };
> +
> + ahb0: ahb0_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clocks = <&ar100>;
> + clock-output-names = "ahb0";
> + };
> +
> + apb0: apb0_clk {
> + compatible = "allwinner,sun6i-a31-apb0-clk";
> + #clock-cells = <0>;
> + clocks = <&ahb0>;
> + clock-output-names = "apb0";
> + };
> +
> + apb0_gates: apb0_gates_clk {
> + compatible = "allwinner,sun6i-a31-apb0-gates-clk";
> + #clock-cells = <1>;
> + clocks = <&apb0>;
> + clock-output-names = "apb0_pio", "apb0_ir",
> + "apb0_timer", "apb0_p2wi",
> + "apb0_uart", "apb0_1wire",
> + "apb0_i2c";
> + };
> +
> + ir_clk: ir_clk {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-ir-clk";
> + clocks = <&osc32k>, <&osc24M>;
> + clock-output-names = "ir";
> + };
This is yet to be agreed on....
> +
> + apb0_rst: apb0_rst {
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + #reset-cells = <1>;
> + };
> + };
> +
> + cpucfg at 01f01c00 {
> + compatible = "allwinner,sun6i-a31-cpuconfig";
> + reg = <0x01f01c00 0x300>;
> + };
> +
> + ir at 01f02000 {
> + compatible = "allwinner,sun5i-a13-ir";
> + clocks = <&apb0_gates 1>, <&ir_clk>;
> + clock-names = "apb", "ir";
> + resets = <&apb0_rst 1>;
> + interrupts = <0 37 4>;
> + reg = <0x01f02000 0x40>;
> + status = "disabled";
> + };
> +
> + r_pio: pinctrl at 01f02c00 {
> + compatible = "allwinner,sun6i-a31-r-pinctrl";
> + reg = <0x01f02c00 0x400>;
> + interrupts = <0 45 4>,
> + <0 46 4>;
> + clocks = <&apb0_gates 0>;
> + resets = <&apb0_rst 0>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + #size-cells = <0>;
> + #gpio-cells = <3>;
> +
> + ir_pins_a: ir at 0 {
> + allwinner,pins = "PL4";
> + allwinner,function = "s_ir";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> + };
> + };
> +};
> --
> 2.1.0
>
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-25 18:21 ` Maxime Ripard
-1 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:21 UTC (permalink / raw)
To: Hans de Goede
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 5669 bytes --]
On Sun, Nov 23, 2014 at 01:54:43PM +0100, Hans de Goede wrote:
> The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
> rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
> controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
>
> http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html
>
> Note it has no sdcard slot and therefore can only be fel booted.
Thanks a lot for working on this!
I also bought another board with an A31s, but it ended up having
neither USB OTG or MMC, which rendered it pretty useless.
I wonder wether to put URL in the commit log is the right thing
though. It's most likely to be dead in a very near future. The cover
letter would be a better fit for that.
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/sun6i-a31s-cs908.dts | 109 +++++++++++++++++++++++++++++++++
> 2 files changed, 111 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/sun6i-a31s-cs908.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8ebfa76..0c0201c 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -434,7 +434,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
> sun6i-a31-app4-evb1.dtb \
> sun6i-a31-colombus.dtb \
> sun6i-a31-hummingbird.dtb \
> - sun6i-a31-m9.dtb
> + sun6i-a31-m9.dtb \
> + sun6i-a31s-cs908.dtb
> dtb-$(CONFIG_MACH_SUN7I) += \
> sun7i-a20-bananapi.dtb \
> sun7i-a20-cubieboard2.dtb \
> diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
> new file mode 100644
> index 0000000..48d3a70
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
> @@ -0,0 +1,109 @@
> +/*
> + * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public
> + * License along with this library; if not, write to the Free
> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> + * MA 02110-1301 USA
s/library/file/
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +/include/ "sun6i-a31s.dtsi"
> +
> +/ {
> + model = "CSQ CS908 top set box";
Shouldn't it be Set Top Box instead?
> + compatible = "csq,cs908", "allwinner,sun6i-a31s";
> +
> + chosen {
> + bootargs = "earlyprintk console=ttyS0,115200";
> + };
> +
> + soc@01c00000 {
> + usbphy: phy@01c19400 {
> + status = "okay";
> + };
> +
> + ehci0: usb@01c1a000 {
> + status = "okay";
> + };
> +
> + ehci1: usb@01c1b000 {
> + status = "okay";
> + };
> +
> + ohci1: usb@01c1b400 {
> + status = "okay";
> + };
> +
> + pio: pinctrl@01c20800 {
> + usb1_vbus_pin_csq908: usb1_vbus_pin@0 {
> + allwinner,pins = "PC27";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> + };
> +
> + uart0: serial@01c28000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> + };
> +
> + gmac: ethernet@01c30000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac_pins_mii_a>;
> + phy = <&phy1>;
> + phy-mode = "mii";
> + status = "okay";
> +
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> + };
> +
> + ir@01f02000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ir_pins_a>;
> + status = "okay";
> + };
> + };
> +};
> --
> 2.1.0
>
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
@ 2014-11-25 18:21 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:21 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Nov 23, 2014 at 01:54:43PM +0100, Hans de Goede wrote:
> The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
> rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
> controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
>
> http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html
>
> Note it has no sdcard slot and therefore can only be fel booted.
Thanks a lot for working on this!
I also bought another board with an A31s, but it ended up having
neither USB OTG or MMC, which rendered it pretty useless.
I wonder wether to put URL in the commit log is the right thing
though. It's most likely to be dead in a very near future. The cover
letter would be a better fit for that.
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/sun6i-a31s-cs908.dts | 109 +++++++++++++++++++++++++++++++++
> 2 files changed, 111 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/sun6i-a31s-cs908.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8ebfa76..0c0201c 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -434,7 +434,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
> sun6i-a31-app4-evb1.dtb \
> sun6i-a31-colombus.dtb \
> sun6i-a31-hummingbird.dtb \
> - sun6i-a31-m9.dtb
> + sun6i-a31-m9.dtb \
> + sun6i-a31s-cs908.dtb
> dtb-$(CONFIG_MACH_SUN7I) += \
> sun7i-a20-bananapi.dtb \
> sun7i-a20-cubieboard2.dtb \
> diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
> new file mode 100644
> index 0000000..48d3a70
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
> @@ -0,0 +1,109 @@
> +/*
> + * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public
> + * License along with this library; if not, write to the Free
> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> + * MA 02110-1301 USA
s/library/file/
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +/include/ "sun6i-a31s.dtsi"
> +
> +/ {
> + model = "CSQ CS908 top set box";
Shouldn't it be Set Top Box instead?
> + compatible = "csq,cs908", "allwinner,sun6i-a31s";
> +
> + chosen {
> + bootargs = "earlyprintk console=ttyS0,115200";
> + };
> +
> + soc at 01c00000 {
> + usbphy: phy at 01c19400 {
> + status = "okay";
> + };
> +
> + ehci0: usb at 01c1a000 {
> + status = "okay";
> + };
> +
> + ehci1: usb at 01c1b000 {
> + status = "okay";
> + };
> +
> + ohci1: usb at 01c1b400 {
> + status = "okay";
> + };
> +
> + pio: pinctrl at 01c20800 {
> + usb1_vbus_pin_csq908: usb1_vbus_pin at 0 {
> + allwinner,pins = "PC27";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> + };
> +
> + uart0: serial at 01c28000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> + };
> +
> + gmac: ethernet at 01c30000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac_pins_mii_a>;
> + phy = <&phy1>;
> + phy-mode = "mii";
> + status = "okay";
> +
> + phy1: ethernet-phy at 1 {
> + reg = <1>;
> + };
> + };
> +
> + ir at 01f02000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ir_pins_a>;
> + status = "okay";
> + };
> + };
> +};
> --
> 2.1.0
>
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 3/5] ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-25 18:24 ` Maxime Ripard
-1 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:24 UTC (permalink / raw)
To: Hans de Goede
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
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On Sun, Nov 23, 2014 at 01:54:41PM +0100, Hans de Goede wrote:
> So fat the A31s is 100% compatible with the A31, still lets do the same
> as what we've done for the A13 / A10s and give it its own compatible string,
> in case need to differentiate later.
>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
Thanks a lot for this. It's been a long awaited addition.
I don't have any comment on this patch, except that you should also
update Documentation/arm/sunxi/README to reflect this newly supported
SoC.
That can go through another patch though.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 3/5] ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi
@ 2014-11-25 18:24 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-25 18:24 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Nov 23, 2014 at 01:54:41PM +0100, Hans de Goede wrote:
> So fat the A31s is 100% compatible with the A31, still lets do the same
> as what we've done for the A13 / A10s and give it its own compatible string,
> in case need to differentiate later.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Thanks a lot for this. It's been a long awaited addition.
I don't have any comment on this patch, except that you should also
update Documentation/arm/sunxi/README to reflect this newly supported
SoC.
That can go through another patch though.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
2014-11-25 18:18 ` Maxime Ripard
@ 2014-11-25 23:45 ` Chen-Yu Tsai
-1 siblings, 0 replies; 52+ messages in thread
From: Chen-Yu Tsai @ 2014-11-25 23:45 UTC (permalink / raw)
To: Maxime Ripard
Cc: Hans de Goede, Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi
On Wed, Nov 26, 2014 at 2:18 AM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi,
>
> On Sun, Nov 23, 2014 at 01:54:42PM +0100, Hans de Goede wrote:
>> Add a dtsi file for A31s based boards. This is a copy of sun6i-a31.dtsi, with:
>>
>> -The main pinctrl compatible changed to allwinner,sun6i-a31s.dtsi
>> -The ohci2 controller is present according to the data-sheet, but not routed
>> to the outside, so remove it from the dtsi as having an always disabled node
>> is not useful.
>>
>> All the other nodes present in the original sun6i-a31.dtsi are present in
>> the A31s too, and are 100% compatible.
>
> Then maybe duplicating the DT isn't worth it then.
>
> Creating a sun6i.dtsi and including that from both the A31 and A31s
> seems more like an appropriate solution.
>
>>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>> arch/arm/boot/dts/sun6i-a31s.dtsi | 925 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 925 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> new file mode 100644
>> index 0000000..b3b99a9
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> @@ -0,0 +1,925 @@
>> +/*
>> + * Copyright 2013 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>
> It should be your copyright here.
>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public
>> + * License along with this library; if not, write to the Free
>> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>
> There was an issue with the wording of the license, s/library/file/
>
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &uart2;
>> + serial3 = &uart3;
>> + serial4 = &uart4;
>> + serial5 = &uart5;
>> + ethernet0 = &gmac;
>> + };
>> +
>> + chosen {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + framebuffer@0 {
>> + compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
>> + allwinner,pipeline = "de_be0-lcd0-hdmi";
>> + clocks = <&pll6>;
>
> pll6 uses an argument now
>
>> + status = "disabled";
>> + };
>> + };
>> +
>> + cpus {
>> + enable-method = "allwinner,sun6i-a31";
>
> allwinner,sun6i-a31s I guess?
>
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0>;
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <1>;
>> + };
>> +
>> + cpu@2 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <2>;
>> + };
>> +
>> + cpu@3 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <3>;
>> + };
>> + };
>> +
>> + memory {
>> + reg = <0x40000000 0x80000000>;
>> + };
>> +
>> + pmu {
>> + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
>> + interrupts = <0 120 4>,
>> + <0 121 4>,
>> + <0 122 4>,
>> + <0 123 4>;
>> + };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: osc24M {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + };
>> +
>> + osc32k: clk@0 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + pll1: clk@01c20000 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-pll1-clk";
>> + reg = <0x01c20000 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll1";
>> + };
>> +
>> + pll6: clk@01c20028 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>> + reg = <0x01c20028 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll6";
>> + };
>> +
>> + cpu: cpu@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>> + reg = <0x01c20050 0x4>;
>> +
>> + /*
>> + * PLL1 is listed twice here.
>> + * While it looks suspicious, it's actually documented
>> + * that way both in the datasheet and in the code from
>> + * Allwinner.
>> + */
>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> + clock-output-names = "cpu";
>> + };
>> +
>> + axi: axi@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-axi-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&cpu>;
>> + clock-output-names = "axi";
>> + };
>> +
>> + ahb1_mux: ahb1_mux@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
>> + clock-output-names = "ahb1_mux";
>> + };
>> +
>> + ahb1: ahb1@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-ahb-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1_mux>;
>> + clock-output-names = "ahb1";
>> + };
>> +
>> + ahb1_gates: clk@01c20060 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
>> + reg = <0x01c20060 0x8>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
>> + "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
>> + "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
>> + "ahb1_nand0", "ahb1_sdram",
>> + "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
>> + "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
>> + "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
>> + "ahb1_ehci1", "ahb1_ohci0",
>> + "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
>> + "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
>> + "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
>> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
>> + "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
>> + "ahb1_drc0", "ahb1_drc1";
>> + };
>
> Are the gates really identical?
>
> As in not even stripped down?
According to the user manuals, the AHB1 gates on the A31s don't have
GMAC (or EMAC in the manual) and MIPI DSI listed. Though it seems
a lot of A31s hardware out there actually use GMAC.
The APB1 and APB2 gates are the same.
>> + apb1: apb1@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "apb1";
>> + };
>> +
>> + apb1_gates: clk@01c20068 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-apb1-gates-clk";
>> + reg = <0x01c20068 0x4>;
>> + clocks = <&apb1>;
>> + clock-output-names = "apb1_codec", "apb1_digital_mic",
>> + "apb1_pio", "apb1_daudio0",
>> + "apb1_daudio1";
>> + };
>> +
>> + apb2_mux: apb2_mux@01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
>> + clock-output-names = "apb2_mux";
>> + };
>> +
>> + apb2: apb2@01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-apb2-div-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&apb2_mux>;
>> + clock-output-names = "apb2";
>> + };
>> +
>> + apb2_gates: clk@01c2006c {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-apb2-gates-clk";
>> + reg = <0x01c2006c 0x4>;
>> + clocks = <&apb2>;
>> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
>> + "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
>> + "apb2_uart1", "apb2_uart2", "apb2_uart3",
>> + "apb2_uart4", "apb2_uart5";
>> + };
>> +
>> + mmc0_clk: clk@01c20088 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20088 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc0";
>> + };
>> +
>> + mmc1_clk: clk@01c2008c {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c2008c 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc1";
>> + };
>> +
>> + mmc2_clk: clk@01c20090 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20090 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc2";
>> + };
>> +
>> + mmc3_clk: clk@01c20094 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20094 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc3";
>> + };
>> +
>> + spi0_clk: clk@01c200a0 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a0 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi0";
>> + };
>> +
>> + spi1_clk: clk@01c200a4 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a4 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi1";
>> + };
>> +
>> + spi2_clk: clk@01c200a8 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a8 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi2";
>> + };
>> +
>> + spi3_clk: clk@01c200ac {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200ac 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi3";
>> + };
>> +
>> + usb_clk: clk@01c200cc {
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-usb-clk";
>> + reg = <0x01c200cc 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
>> + "usb_ohci0", "usb_ohci1",
>> + "usb_ohci2";
>> + };
>> +
>> + /*
>> + * The following two are dummy clocks, placeholders used in the gmac_tx
>> + * clock. The gmac driver will choose one parent depending on the PHY
>> + * interface mode, using clk_set_rate auto-reparenting.
>> + * The actual TX clock rate is not controlled by the gmac_tx clock.
>> + */
>> + mii_phy_tx_clk: clk@1 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <25000000>;
>> + clock-output-names = "mii_phy_tx";
>> + };
>> +
>> + gmac_int_tx_clk: clk@2 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <125000000>;
>> + clock-output-names = "gmac_int_tx";
>> + };
>> +
>> + gmac_tx_clk: clk@01c200d0 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun7i-a20-gmac-clk";
>> + reg = <0x01c200d0 0x4>;
>> + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
>> + clock-output-names = "gmac_tx";
>> + };
>> + };
>> +
>> + soc@01c00000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + dma: dma-controller@01c02000 {
>> + compatible = "allwinner,sun6i-a31-dma";
>> + reg = <0x01c02000 0x1000>;
>> + interrupts = <0 50 4>;
>> + clocks = <&ahb1_gates 6>;
>> + resets = <&ahb1_rst 6>;
>> + #dma-cells = <1>;
>> + };
>> +
>> + mmc0: mmc@01c0f000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ahb1_gates 8>, <&mmc0_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 8>;
>> + reset-names = "ahb";
>> + interrupts = <0 60 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc@01c10000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&ahb1_gates 9>, <&mmc1_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 9>;
>> + reset-names = "ahb";
>> + interrupts = <0 61 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc2: mmc@01c11000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&ahb1_gates 10>, <&mmc2_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 10>;
>> + reset-names = "ahb";
>> + interrupts = <0 62 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc3: mmc@01c12000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c12000 0x1000>;
>> + clocks = <&ahb1_gates 11>, <&mmc3_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 11>;
>> + reset-names = "ahb";
>> + interrupts = <0 63 4>;
>> + status = "disabled";
>> + };
>> +
>> + usbphy: phy@01c19400 {
>> + compatible = "allwinner,sun6i-a31-usb-phy";
>> + reg = <0x01c19400 0x10>,
>> + <0x01c1a800 0x4>,
>> + <0x01c1b800 0x4>;
>> + reg-names = "phy_ctrl",
>> + "pmu1",
>> + "pmu2";
>> + clocks = <&usb_clk 8>,
>> + <&usb_clk 9>,
>> + <&usb_clk 10>;
>> + clock-names = "usb0_phy",
>> + "usb1_phy",
>> + "usb2_phy";
>> + resets = <&usb_clk 0>,
>> + <&usb_clk 1>,
>> + <&usb_clk 2>;
>> + reset-names = "usb0_reset",
>> + "usb1_reset",
>> + "usb2_reset";
>> + status = "disabled";
>> + #phy-cells = <1>;
>> + };
>> +
>> + ehci0: usb@01c1a000 {
>> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
>> + reg = <0x01c1a000 0x100>;
>> + interrupts = <0 72 4>;
>> + clocks = <&ahb1_gates 26>;
>> + resets = <&ahb1_rst 26>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci0: usb@01c1a400 {
>> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
>> + reg = <0x01c1a400 0x100>;
>> + interrupts = <0 73 4>;
>> + clocks = <&ahb1_gates 29>, <&usb_clk 16>;
>> + resets = <&ahb1_rst 29>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ehci1: usb@01c1b000 {
>> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
>> + reg = <0x01c1b000 0x100>;
>> + interrupts = <0 74 4>;
>> + clocks = <&ahb1_gates 27>;
>> + resets = <&ahb1_rst 27>;
>> + phys = <&usbphy 2>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci1: usb@01c1b400 {
>> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
>> + reg = <0x01c1b400 0x100>;
>> + interrupts = <0 75 4>;
>> + clocks = <&ahb1_gates 30>, <&usb_clk 17>;
>> + resets = <&ahb1_rst 30>;
>> + phys = <&usbphy 2>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + pio: pinctrl@01c20800 {
>> + compatible = "allwinner,sun6i-a31s-pinctrl";
>> + reg = <0x01c20800 0x400>;
>> + interrupts = <0 11 4>,
>> + <0 15 4>,
>> + <0 16 4>,
>> + <0 17 4>;
>> + clocks = <&apb1_gates 5>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + uart0_pins_a: uart0@0 {
>> + allwinner,pins = "PH20", "PH21";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c0_pins_a: i2c0@0 {
>> + allwinner,pins = "PH14", "PH15";
>> + allwinner,function = "i2c0";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c1_pins_a: i2c1@0 {
>> + allwinner,pins = "PH16", "PH17";
>> + allwinner,function = "i2c1";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c2_pins_a: i2c2@0 {
>> + allwinner,pins = "PH18", "PH19";
>> + allwinner,function = "i2c2";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + mmc0_pins_a: mmc0@0 {
>> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
>
> Spaces after the comma, and I guess that would be better on two lines.
This is in the other dtsi. We should probably fix the styling there as well.
>> + allwinner,function = "mmc0";
>> + allwinner,drive = <2>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_mii_a: gmac_mii@0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA8", "PA9", "PA11",
>> + "PA12", "PA13", "PA14", "PA19",
>> + "PA20", "PA21", "PA22", "PA23",
>> + "PA24", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_gmii_a: gmac_gmii@0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA4", "PA5", "PA6", "PA7",
>> + "PA8", "PA9", "PA10", "PA11",
>> + "PA12", "PA13", "PA14", "PA15",
>> + "PA16", "PA17", "PA18", "PA19",
>> + "PA20", "PA21", "PA22", "PA23",
>> + "PA24", "PA25", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + /*
>> + * data lines in GMII mode run at 125MHz and
>> + * might need a higher signal drive strength
>> + */
>> + allwinner,drive = <2>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_rgmii_a: gmac_rgmii@0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA9", "PA10", "PA11",
>> + "PA12", "PA13", "PA14", "PA19",
>> + "PA20", "PA25", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + /*
>> + * data lines in RGMII mode use DDR mode
>> + * and need a higher signal drive strength
>> + */
>> + allwinner,drive = <3>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> +
>> + ahb1_rst: reset@01c202c0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-reset";
>> + reg = <0x01c202c0 0xc>;
>> + };
>> +
>> + apb1_rst: reset@01c202d0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d0 0x4>;
>> + };
>> +
>> + apb2_rst: reset@01c202d8 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d8 0x4>;
>> + };
>> +
>> + timer@01c20c00 {
>> + compatible = "allwinner,sun4i-a10-timer";
>> + reg = <0x01c20c00 0xa0>;
>> + interrupts = <0 18 4>,
>> + <0 19 4>,
>> + <0 20 4>,
>> + <0 21 4>,
>> + <0 22 4>;
>> + clocks = <&osc24M>;
>> + };
>> +
>> + wdt1: watchdog@01c20ca0 {
>> + compatible = "allwinner,sun6i-a31-wdt";
>> + reg = <0x01c20ca0 0x20>;
>> + };
>> +
>> + uart0: serial@01c28000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28000 0x400>;
>> + interrupts = <0 0 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 16>;
>> + resets = <&apb2_rst 16>;
>> + dmas = <&dma 6>, <&dma 6>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@01c28400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28400 0x400>;
>> + interrupts = <0 1 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 17>;
>> + resets = <&apb2_rst 17>;
>> + dmas = <&dma 7>, <&dma 7>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@01c28800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28800 0x400>;
>> + interrupts = <0 2 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 18>;
>> + resets = <&apb2_rst 18>;
>> + dmas = <&dma 8>, <&dma 8>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@01c28c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28c00 0x400>;
>> + interrupts = <0 3 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 19>;
>> + resets = <&apb2_rst 19>;
>> + dmas = <&dma 9>, <&dma 9>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@01c29000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29000 0x400>;
>> + interrupts = <0 4 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 20>;
>> + resets = <&apb2_rst 20>;
>> + dmas = <&dma 10>, <&dma 10>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart5: serial@01c29400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29400 0x400>;
>> + interrupts = <0 5 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 21>;
>> + resets = <&apb2_rst 21>;
>> + dmas = <&dma 22>, <&dma 22>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + i2c0: i2c@01c2ac00 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2ac00 0x400>;
>> + interrupts = <0 6 4>;
>> + clocks = <&apb2_gates 0>;
>> + resets = <&apb2_rst 0>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c1: i2c@01c2b000 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b000 0x400>;
>> + interrupts = <0 7 4>;
>> + clocks = <&apb2_gates 1>;
>> + resets = <&apb2_rst 1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c2: i2c@01c2b400 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b400 0x400>;
>> + interrupts = <0 8 4>;
>> + clocks = <&apb2_gates 2>;
>> + resets = <&apb2_rst 2>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c3: i2c@01c2b800 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b800 0x400>;
>> + interrupts = <0 9 4>;
>> + clocks = <&apb2_gates 3>;
>> + resets = <&apb2_rst 3>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + gmac: ethernet@01c30000 {
>> + compatible = "allwinner,sun7i-a20-gmac";
>> + reg = <0x01c30000 0x1054>;
>> + interrupts = <0 82 4>;
>> + interrupt-names = "macirq";
>> + clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
>> + clock-names = "stmmaceth", "allwinner_gmac_tx";
>> + resets = <&ahb1_rst 17>;
>> + reset-names = "stmmaceth";
>> + snps,pbl = <2>;
>> + snps,fixed-burst;
>> + snps,force_sf_dma_mode;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + timer@01c60000 {
>> + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
>> + reg = <0x01c60000 0x1000>;
>> + interrupts = <0 51 4>,
>> + <0 52 4>,
>> + <0 53 4>,
>> + <0 54 4>;
>> + clocks = <&ahb1_gates 19>;
>> + resets = <&ahb1_rst 19>;
>> + };
>> +
>> + spi0: spi@01c68000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c68000 0x1000>;
>> + interrupts = <0 65 4>;
>> + clocks = <&ahb1_gates 20>, <&spi0_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 23>, <&dma 23>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 20>;
>> + status = "disabled";
>> + };
>> +
>> + spi1: spi@01c69000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c69000 0x1000>;
>> + interrupts = <0 66 4>;
>> + clocks = <&ahb1_gates 21>, <&spi1_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 24>, <&dma 24>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 21>;
>> + status = "disabled";
>> + };
>> +
>> + spi2: spi@01c6a000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c6a000 0x1000>;
>> + interrupts = <0 67 4>;
>> + clocks = <&ahb1_gates 22>, <&spi2_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 25>, <&dma 25>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 22>;
>> + status = "disabled";
>> + };
>> +
>> + spi3: spi@01c6b000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c6b000 0x1000>;
>> + interrupts = <0 68 4>;
>> + clocks = <&ahb1_gates 23>, <&spi3_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 26>, <&dma 26>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 23>;
>> + status = "disabled";
>> + };
>> +
>> + gic: interrupt-controller@01c81000 {
>> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
>> + reg = <0x01c81000 0x1000>,
>> + <0x01c82000 0x1000>,
>> + <0x01c84000 0x2000>,
>> + <0x01c86000 0x2000>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + interrupts = <1 9 0xf04>;
>> + };
>> +
>> + rtc: rtc@01f00000 {
>> + compatible = "allwinner,sun6i-a31-rtc";
>> + reg = <0x01f00000 0x54>;
>> + interrupts = <0 40 4>, <0 41 4>;
>> + };
>> +
>> + nmi_intc: interrupt-controller@01f00c0c {
>> + compatible = "allwinner,sun6i-a31-sc-nmi";
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + reg = <0x01f00c0c 0x38>;
>> + interrupts = <0 32 4>;
>> + };
>> +
>> + prcm@01f01400 {
>> + compatible = "allwinner,sun6i-a31-prcm";
>> + reg = <0x01f01400 0x200>;
>> +
>> + ar100: ar100_clk {
>> + compatible = "allwinner,sun6i-a31-ar100-clk";
>> + #clock-cells = <0>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
>> + clock-output-names = "ar100";
>> + };
>> +
>> + ahb0: ahb0_clk {
>> + compatible = "fixed-factor-clock";
>> + #clock-cells = <0>;
>> + clock-div = <1>;
>> + clock-mult = <1>;
>> + clocks = <&ar100>;
>> + clock-output-names = "ahb0";
>> + };
>> +
>> + apb0: apb0_clk {
>> + compatible = "allwinner,sun6i-a31-apb0-clk";
>> + #clock-cells = <0>;
>> + clocks = <&ahb0>;
>> + clock-output-names = "apb0";
>> + };
>> +
>> + apb0_gates: apb0_gates_clk {
>> + compatible = "allwinner,sun6i-a31-apb0-gates-clk";
>> + #clock-cells = <1>;
>> + clocks = <&apb0>;
>> + clock-output-names = "apb0_pio", "apb0_ir",
>> + "apb0_timer", "apb0_p2wi",
>> + "apb0_uart", "apb0_1wire",
>> + "apb0_i2c";
>> + };
>> +
>> + ir_clk: ir_clk {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ir-clk";
>> + clocks = <&osc32k>, <&osc24M>;
>> + clock-output-names = "ir";
>> + };
>
> This is yet to be agreed on....
>
>> +
>> + apb0_rst: apb0_rst {
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + #reset-cells = <1>;
>> + };
>> + };
>> +
>> + cpucfg@01f01c00 {
>> + compatible = "allwinner,sun6i-a31-cpuconfig";
>> + reg = <0x01f01c00 0x300>;
>> + };
>> +
>> + ir@01f02000 {
>> + compatible = "allwinner,sun5i-a13-ir";
>> + clocks = <&apb0_gates 1>, <&ir_clk>;
>> + clock-names = "apb", "ir";
>> + resets = <&apb0_rst 1>;
>> + interrupts = <0 37 4>;
>> + reg = <0x01f02000 0x40>;
>> + status = "disabled";
>> + };
>> +
>> + r_pio: pinctrl@01f02c00 {
>> + compatible = "allwinner,sun6i-a31-r-pinctrl";
>> + reg = <0x01f02c00 0x400>;
>> + interrupts = <0 45 4>,
>> + <0 46 4>;
>> + clocks = <&apb0_gates 0>;
>> + resets = <&apb0_rst 0>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + ir_pins_a: ir@0 {
>> + allwinner,pins = "PL4";
>> + allwinner,function = "s_ir";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> + };
>> +};
>> --
>> 2.1.0
>>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
@ 2014-11-25 23:45 ` Chen-Yu Tsai
0 siblings, 0 replies; 52+ messages in thread
From: Chen-Yu Tsai @ 2014-11-25 23:45 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Nov 26, 2014 at 2:18 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sun, Nov 23, 2014 at 01:54:42PM +0100, Hans de Goede wrote:
>> Add a dtsi file for A31s based boards. This is a copy of sun6i-a31.dtsi, with:
>>
>> -The main pinctrl compatible changed to allwinner,sun6i-a31s.dtsi
>> -The ohci2 controller is present according to the data-sheet, but not routed
>> to the outside, so remove it from the dtsi as having an always disabled node
>> is not useful.
>>
>> All the other nodes present in the original sun6i-a31.dtsi are present in
>> the A31s too, and are 100% compatible.
>
> Then maybe duplicating the DT isn't worth it then.
>
> Creating a sun6i.dtsi and including that from both the A31 and A31s
> seems more like an appropriate solution.
>
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> arch/arm/boot/dts/sun6i-a31s.dtsi | 925 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 925 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> new file mode 100644
>> index 0000000..b3b99a9
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> @@ -0,0 +1,925 @@
>> +/*
>> + * Copyright 2013 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>
> It should be your copyright here.
>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public
>> + * License along with this library; if not, write to the Free
>> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>
> There was an issue with the wording of the license, s/library/file/
>
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &uart2;
>> + serial3 = &uart3;
>> + serial4 = &uart4;
>> + serial5 = &uart5;
>> + ethernet0 = &gmac;
>> + };
>> +
>> + chosen {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + framebuffer at 0 {
>> + compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
>> + allwinner,pipeline = "de_be0-lcd0-hdmi";
>> + clocks = <&pll6>;
>
> pll6 uses an argument now
>
>> + status = "disabled";
>> + };
>> + };
>> +
>> + cpus {
>> + enable-method = "allwinner,sun6i-a31";
>
> allwinner,sun6i-a31s I guess?
>
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu at 0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0>;
>> + };
>> +
>> + cpu at 1 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <1>;
>> + };
>> +
>> + cpu at 2 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <2>;
>> + };
>> +
>> + cpu at 3 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <3>;
>> + };
>> + };
>> +
>> + memory {
>> + reg = <0x40000000 0x80000000>;
>> + };
>> +
>> + pmu {
>> + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
>> + interrupts = <0 120 4>,
>> + <0 121 4>,
>> + <0 122 4>,
>> + <0 123 4>;
>> + };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: osc24M {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + };
>> +
>> + osc32k: clk at 0 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + pll1: clk at 01c20000 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-pll1-clk";
>> + reg = <0x01c20000 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll1";
>> + };
>> +
>> + pll6: clk at 01c20028 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>> + reg = <0x01c20028 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll6";
>> + };
>> +
>> + cpu: cpu at 01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>> + reg = <0x01c20050 0x4>;
>> +
>> + /*
>> + * PLL1 is listed twice here.
>> + * While it looks suspicious, it's actually documented
>> + * that way both in the datasheet and in the code from
>> + * Allwinner.
>> + */
>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> + clock-output-names = "cpu";
>> + };
>> +
>> + axi: axi at 01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-axi-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&cpu>;
>> + clock-output-names = "axi";
>> + };
>> +
>> + ahb1_mux: ahb1_mux at 01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
>> + clock-output-names = "ahb1_mux";
>> + };
>> +
>> + ahb1: ahb1 at 01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-ahb-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1_mux>;
>> + clock-output-names = "ahb1";
>> + };
>> +
>> + ahb1_gates: clk at 01c20060 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
>> + reg = <0x01c20060 0x8>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
>> + "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
>> + "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
>> + "ahb1_nand0", "ahb1_sdram",
>> + "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
>> + "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
>> + "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
>> + "ahb1_ehci1", "ahb1_ohci0",
>> + "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
>> + "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
>> + "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
>> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
>> + "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
>> + "ahb1_drc0", "ahb1_drc1";
>> + };
>
> Are the gates really identical?
>
> As in not even stripped down?
According to the user manuals, the AHB1 gates on the A31s don't have
GMAC (or EMAC in the manual) and MIPI DSI listed. Though it seems
a lot of A31s hardware out there actually use GMAC.
The APB1 and APB2 gates are the same.
>> + apb1: apb1 at 01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "apb1";
>> + };
>> +
>> + apb1_gates: clk at 01c20068 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-apb1-gates-clk";
>> + reg = <0x01c20068 0x4>;
>> + clocks = <&apb1>;
>> + clock-output-names = "apb1_codec", "apb1_digital_mic",
>> + "apb1_pio", "apb1_daudio0",
>> + "apb1_daudio1";
>> + };
>> +
>> + apb2_mux: apb2_mux at 01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
>> + clock-output-names = "apb2_mux";
>> + };
>> +
>> + apb2: apb2 at 01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-apb2-div-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&apb2_mux>;
>> + clock-output-names = "apb2";
>> + };
>> +
>> + apb2_gates: clk at 01c2006c {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-apb2-gates-clk";
>> + reg = <0x01c2006c 0x4>;
>> + clocks = <&apb2>;
>> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
>> + "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
>> + "apb2_uart1", "apb2_uart2", "apb2_uart3",
>> + "apb2_uart4", "apb2_uart5";
>> + };
>> +
>> + mmc0_clk: clk at 01c20088 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20088 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc0";
>> + };
>> +
>> + mmc1_clk: clk at 01c2008c {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c2008c 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc1";
>> + };
>> +
>> + mmc2_clk: clk at 01c20090 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20090 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc2";
>> + };
>> +
>> + mmc3_clk: clk at 01c20094 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20094 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc3";
>> + };
>> +
>> + spi0_clk: clk at 01c200a0 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a0 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi0";
>> + };
>> +
>> + spi1_clk: clk at 01c200a4 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a4 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi1";
>> + };
>> +
>> + spi2_clk: clk at 01c200a8 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a8 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi2";
>> + };
>> +
>> + spi3_clk: clk at 01c200ac {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200ac 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi3";
>> + };
>> +
>> + usb_clk: clk at 01c200cc {
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-usb-clk";
>> + reg = <0x01c200cc 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
>> + "usb_ohci0", "usb_ohci1",
>> + "usb_ohci2";
>> + };
>> +
>> + /*
>> + * The following two are dummy clocks, placeholders used in the gmac_tx
>> + * clock. The gmac driver will choose one parent depending on the PHY
>> + * interface mode, using clk_set_rate auto-reparenting.
>> + * The actual TX clock rate is not controlled by the gmac_tx clock.
>> + */
>> + mii_phy_tx_clk: clk at 1 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <25000000>;
>> + clock-output-names = "mii_phy_tx";
>> + };
>> +
>> + gmac_int_tx_clk: clk at 2 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <125000000>;
>> + clock-output-names = "gmac_int_tx";
>> + };
>> +
>> + gmac_tx_clk: clk at 01c200d0 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun7i-a20-gmac-clk";
>> + reg = <0x01c200d0 0x4>;
>> + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
>> + clock-output-names = "gmac_tx";
>> + };
>> + };
>> +
>> + soc at 01c00000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + dma: dma-controller at 01c02000 {
>> + compatible = "allwinner,sun6i-a31-dma";
>> + reg = <0x01c02000 0x1000>;
>> + interrupts = <0 50 4>;
>> + clocks = <&ahb1_gates 6>;
>> + resets = <&ahb1_rst 6>;
>> + #dma-cells = <1>;
>> + };
>> +
>> + mmc0: mmc at 01c0f000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ahb1_gates 8>, <&mmc0_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 8>;
>> + reset-names = "ahb";
>> + interrupts = <0 60 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc at 01c10000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&ahb1_gates 9>, <&mmc1_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 9>;
>> + reset-names = "ahb";
>> + interrupts = <0 61 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc2: mmc at 01c11000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&ahb1_gates 10>, <&mmc2_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 10>;
>> + reset-names = "ahb";
>> + interrupts = <0 62 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc3: mmc at 01c12000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c12000 0x1000>;
>> + clocks = <&ahb1_gates 11>, <&mmc3_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 11>;
>> + reset-names = "ahb";
>> + interrupts = <0 63 4>;
>> + status = "disabled";
>> + };
>> +
>> + usbphy: phy at 01c19400 {
>> + compatible = "allwinner,sun6i-a31-usb-phy";
>> + reg = <0x01c19400 0x10>,
>> + <0x01c1a800 0x4>,
>> + <0x01c1b800 0x4>;
>> + reg-names = "phy_ctrl",
>> + "pmu1",
>> + "pmu2";
>> + clocks = <&usb_clk 8>,
>> + <&usb_clk 9>,
>> + <&usb_clk 10>;
>> + clock-names = "usb0_phy",
>> + "usb1_phy",
>> + "usb2_phy";
>> + resets = <&usb_clk 0>,
>> + <&usb_clk 1>,
>> + <&usb_clk 2>;
>> + reset-names = "usb0_reset",
>> + "usb1_reset",
>> + "usb2_reset";
>> + status = "disabled";
>> + #phy-cells = <1>;
>> + };
>> +
>> + ehci0: usb at 01c1a000 {
>> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
>> + reg = <0x01c1a000 0x100>;
>> + interrupts = <0 72 4>;
>> + clocks = <&ahb1_gates 26>;
>> + resets = <&ahb1_rst 26>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci0: usb at 01c1a400 {
>> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
>> + reg = <0x01c1a400 0x100>;
>> + interrupts = <0 73 4>;
>> + clocks = <&ahb1_gates 29>, <&usb_clk 16>;
>> + resets = <&ahb1_rst 29>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ehci1: usb at 01c1b000 {
>> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
>> + reg = <0x01c1b000 0x100>;
>> + interrupts = <0 74 4>;
>> + clocks = <&ahb1_gates 27>;
>> + resets = <&ahb1_rst 27>;
>> + phys = <&usbphy 2>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci1: usb at 01c1b400 {
>> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
>> + reg = <0x01c1b400 0x100>;
>> + interrupts = <0 75 4>;
>> + clocks = <&ahb1_gates 30>, <&usb_clk 17>;
>> + resets = <&ahb1_rst 30>;
>> + phys = <&usbphy 2>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + pio: pinctrl at 01c20800 {
>> + compatible = "allwinner,sun6i-a31s-pinctrl";
>> + reg = <0x01c20800 0x400>;
>> + interrupts = <0 11 4>,
>> + <0 15 4>,
>> + <0 16 4>,
>> + <0 17 4>;
>> + clocks = <&apb1_gates 5>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + uart0_pins_a: uart0 at 0 {
>> + allwinner,pins = "PH20", "PH21";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c0_pins_a: i2c0 at 0 {
>> + allwinner,pins = "PH14", "PH15";
>> + allwinner,function = "i2c0";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c1_pins_a: i2c1 at 0 {
>> + allwinner,pins = "PH16", "PH17";
>> + allwinner,function = "i2c1";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c2_pins_a: i2c2 at 0 {
>> + allwinner,pins = "PH18", "PH19";
>> + allwinner,function = "i2c2";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + mmc0_pins_a: mmc0 at 0 {
>> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
>
> Spaces after the comma, and I guess that would be better on two lines.
This is in the other dtsi. We should probably fix the styling there as well.
>> + allwinner,function = "mmc0";
>> + allwinner,drive = <2>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_mii_a: gmac_mii at 0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA8", "PA9", "PA11",
>> + "PA12", "PA13", "PA14", "PA19",
>> + "PA20", "PA21", "PA22", "PA23",
>> + "PA24", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_gmii_a: gmac_gmii at 0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA4", "PA5", "PA6", "PA7",
>> + "PA8", "PA9", "PA10", "PA11",
>> + "PA12", "PA13", "PA14", "PA15",
>> + "PA16", "PA17", "PA18", "PA19",
>> + "PA20", "PA21", "PA22", "PA23",
>> + "PA24", "PA25", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + /*
>> + * data lines in GMII mode run at 125MHz and
>> + * might need a higher signal drive strength
>> + */
>> + allwinner,drive = <2>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_rgmii_a: gmac_rgmii at 0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA9", "PA10", "PA11",
>> + "PA12", "PA13", "PA14", "PA19",
>> + "PA20", "PA25", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + /*
>> + * data lines in RGMII mode use DDR mode
>> + * and need a higher signal drive strength
>> + */
>> + allwinner,drive = <3>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> +
>> + ahb1_rst: reset at 01c202c0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-reset";
>> + reg = <0x01c202c0 0xc>;
>> + };
>> +
>> + apb1_rst: reset at 01c202d0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d0 0x4>;
>> + };
>> +
>> + apb2_rst: reset at 01c202d8 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d8 0x4>;
>> + };
>> +
>> + timer at 01c20c00 {
>> + compatible = "allwinner,sun4i-a10-timer";
>> + reg = <0x01c20c00 0xa0>;
>> + interrupts = <0 18 4>,
>> + <0 19 4>,
>> + <0 20 4>,
>> + <0 21 4>,
>> + <0 22 4>;
>> + clocks = <&osc24M>;
>> + };
>> +
>> + wdt1: watchdog at 01c20ca0 {
>> + compatible = "allwinner,sun6i-a31-wdt";
>> + reg = <0x01c20ca0 0x20>;
>> + };
>> +
>> + uart0: serial at 01c28000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28000 0x400>;
>> + interrupts = <0 0 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 16>;
>> + resets = <&apb2_rst 16>;
>> + dmas = <&dma 6>, <&dma 6>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial at 01c28400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28400 0x400>;
>> + interrupts = <0 1 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 17>;
>> + resets = <&apb2_rst 17>;
>> + dmas = <&dma 7>, <&dma 7>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial at 01c28800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28800 0x400>;
>> + interrupts = <0 2 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 18>;
>> + resets = <&apb2_rst 18>;
>> + dmas = <&dma 8>, <&dma 8>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial at 01c28c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28c00 0x400>;
>> + interrupts = <0 3 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 19>;
>> + resets = <&apb2_rst 19>;
>> + dmas = <&dma 9>, <&dma 9>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial at 01c29000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29000 0x400>;
>> + interrupts = <0 4 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 20>;
>> + resets = <&apb2_rst 20>;
>> + dmas = <&dma 10>, <&dma 10>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart5: serial at 01c29400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29400 0x400>;
>> + interrupts = <0 5 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 21>;
>> + resets = <&apb2_rst 21>;
>> + dmas = <&dma 22>, <&dma 22>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + i2c0: i2c at 01c2ac00 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2ac00 0x400>;
>> + interrupts = <0 6 4>;
>> + clocks = <&apb2_gates 0>;
>> + resets = <&apb2_rst 0>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c1: i2c at 01c2b000 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b000 0x400>;
>> + interrupts = <0 7 4>;
>> + clocks = <&apb2_gates 1>;
>> + resets = <&apb2_rst 1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c2: i2c at 01c2b400 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b400 0x400>;
>> + interrupts = <0 8 4>;
>> + clocks = <&apb2_gates 2>;
>> + resets = <&apb2_rst 2>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c3: i2c at 01c2b800 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b800 0x400>;
>> + interrupts = <0 9 4>;
>> + clocks = <&apb2_gates 3>;
>> + resets = <&apb2_rst 3>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + gmac: ethernet at 01c30000 {
>> + compatible = "allwinner,sun7i-a20-gmac";
>> + reg = <0x01c30000 0x1054>;
>> + interrupts = <0 82 4>;
>> + interrupt-names = "macirq";
>> + clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
>> + clock-names = "stmmaceth", "allwinner_gmac_tx";
>> + resets = <&ahb1_rst 17>;
>> + reset-names = "stmmaceth";
>> + snps,pbl = <2>;
>> + snps,fixed-burst;
>> + snps,force_sf_dma_mode;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + timer at 01c60000 {
>> + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
>> + reg = <0x01c60000 0x1000>;
>> + interrupts = <0 51 4>,
>> + <0 52 4>,
>> + <0 53 4>,
>> + <0 54 4>;
>> + clocks = <&ahb1_gates 19>;
>> + resets = <&ahb1_rst 19>;
>> + };
>> +
>> + spi0: spi at 01c68000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c68000 0x1000>;
>> + interrupts = <0 65 4>;
>> + clocks = <&ahb1_gates 20>, <&spi0_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 23>, <&dma 23>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 20>;
>> + status = "disabled";
>> + };
>> +
>> + spi1: spi at 01c69000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c69000 0x1000>;
>> + interrupts = <0 66 4>;
>> + clocks = <&ahb1_gates 21>, <&spi1_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 24>, <&dma 24>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 21>;
>> + status = "disabled";
>> + };
>> +
>> + spi2: spi at 01c6a000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c6a000 0x1000>;
>> + interrupts = <0 67 4>;
>> + clocks = <&ahb1_gates 22>, <&spi2_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 25>, <&dma 25>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 22>;
>> + status = "disabled";
>> + };
>> +
>> + spi3: spi at 01c6b000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c6b000 0x1000>;
>> + interrupts = <0 68 4>;
>> + clocks = <&ahb1_gates 23>, <&spi3_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 26>, <&dma 26>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 23>;
>> + status = "disabled";
>> + };
>> +
>> + gic: interrupt-controller at 01c81000 {
>> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
>> + reg = <0x01c81000 0x1000>,
>> + <0x01c82000 0x1000>,
>> + <0x01c84000 0x2000>,
>> + <0x01c86000 0x2000>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + interrupts = <1 9 0xf04>;
>> + };
>> +
>> + rtc: rtc at 01f00000 {
>> + compatible = "allwinner,sun6i-a31-rtc";
>> + reg = <0x01f00000 0x54>;
>> + interrupts = <0 40 4>, <0 41 4>;
>> + };
>> +
>> + nmi_intc: interrupt-controller at 01f00c0c {
>> + compatible = "allwinner,sun6i-a31-sc-nmi";
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + reg = <0x01f00c0c 0x38>;
>> + interrupts = <0 32 4>;
>> + };
>> +
>> + prcm at 01f01400 {
>> + compatible = "allwinner,sun6i-a31-prcm";
>> + reg = <0x01f01400 0x200>;
>> +
>> + ar100: ar100_clk {
>> + compatible = "allwinner,sun6i-a31-ar100-clk";
>> + #clock-cells = <0>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
>> + clock-output-names = "ar100";
>> + };
>> +
>> + ahb0: ahb0_clk {
>> + compatible = "fixed-factor-clock";
>> + #clock-cells = <0>;
>> + clock-div = <1>;
>> + clock-mult = <1>;
>> + clocks = <&ar100>;
>> + clock-output-names = "ahb0";
>> + };
>> +
>> + apb0: apb0_clk {
>> + compatible = "allwinner,sun6i-a31-apb0-clk";
>> + #clock-cells = <0>;
>> + clocks = <&ahb0>;
>> + clock-output-names = "apb0";
>> + };
>> +
>> + apb0_gates: apb0_gates_clk {
>> + compatible = "allwinner,sun6i-a31-apb0-gates-clk";
>> + #clock-cells = <1>;
>> + clocks = <&apb0>;
>> + clock-output-names = "apb0_pio", "apb0_ir",
>> + "apb0_timer", "apb0_p2wi",
>> + "apb0_uart", "apb0_1wire",
>> + "apb0_i2c";
>> + };
>> +
>> + ir_clk: ir_clk {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ir-clk";
>> + clocks = <&osc32k>, <&osc24M>;
>> + clock-output-names = "ir";
>> + };
>
> This is yet to be agreed on....
>
>> +
>> + apb0_rst: apb0_rst {
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + #reset-cells = <1>;
>> + };
>> + };
>> +
>> + cpucfg at 01f01c00 {
>> + compatible = "allwinner,sun6i-a31-cpuconfig";
>> + reg = <0x01f01c00 0x300>;
>> + };
>> +
>> + ir at 01f02000 {
>> + compatible = "allwinner,sun5i-a13-ir";
>> + clocks = <&apb0_gates 1>, <&ir_clk>;
>> + clock-names = "apb", "ir";
>> + resets = <&apb0_rst 1>;
>> + interrupts = <0 37 4>;
>> + reg = <0x01f02000 0x40>;
>> + status = "disabled";
>> + };
>> +
>> + r_pio: pinctrl at 01f02c00 {
>> + compatible = "allwinner,sun6i-a31-r-pinctrl";
>> + reg = <0x01f02c00 0x400>;
>> + interrupts = <0 45 4>,
>> + <0 46 4>;
>> + clocks = <&apb0_gates 0>;
>> + resets = <&apb0_rst 0>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + ir_pins_a: ir at 0 {
>> + allwinner,pins = "PL4";
>> + allwinner,function = "s_ir";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> + };
>> +};
>> --
>> 2.1.0
>>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 2/5] pinctrl: sun6i: Add A31s pinctrl support
2014-11-25 18:08 ` Maxime Ripard
@ 2014-11-26 8:11 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 8:11 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Hi,
On 11/25/2014 07:08 PM, Maxime Ripard wrote:
> On Sun, Nov 23, 2014 at 01:54:40PM +0100, Hans de Goede wrote:
>> The A31s is a stripped down version of the A31, as such it is missing some
>> pins and some functions on some pins.
>>
>> The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
>> with the missing pins and functions removed.
>>
>> Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
>> prcm pins are identical between the A31 and the A31s.
>>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
>> drivers/pinctrl/sunxi/Kconfig | 4 +
>> drivers/pinctrl/sunxi/Makefile | 1 +
>> drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c | 814 +++++++++++++++++++++
>> 4 files changed, 820 insertions(+)
>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> index 93ce12e..fdd8046 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> @@ -11,6 +11,7 @@ Required properties:
>> "allwinner,sun5i-a10s-pinctrl"
>> "allwinner,sun5i-a13-pinctrl"
>> "allwinner,sun6i-a31-pinctrl"
>> + "allwinner,sun6i-a31s-pinctrl"
>> "allwinner,sun6i-a31-r-pinctrl"
>> "allwinner,sun7i-a20-pinctrl"
>> "allwinner,sun8i-a23-pinctrl"
>> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>> index a5e10f7..6cffe38 100644
>> --- a/drivers/pinctrl/sunxi/Kconfig
>> +++ b/drivers/pinctrl/sunxi/Kconfig
>> @@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
>> def_bool MACH_SUN6I
>> select PINCTRL_SUNXI_COMMON
>>
>> +config PINCTRL_SUN6I_A31S
>> + def_bool MACH_SUN6I
>> + select PINCTRL_SUNXI_COMMON
>> +
>> config PINCTRL_SUN6I_A31_R
>> def_bool MACH_SUN6I
>> depends on RESET_CONTROLLER
>> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
>> index e797efb..2f82290 100644
>> --- a/drivers/pinctrl/sunxi/Makefile
>> +++ b/drivers/pinctrl/sunxi/Makefile
>> @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
>> obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
>> obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
>> obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
>> +obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
>> obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
>> obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
>> obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
>> new file mode 100644
>> index 0000000..42ee373
>> --- /dev/null
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
>> @@ -0,0 +1,814 @@
>> +/*
>> + * Allwinner A31 SoCs pinctrl driver.
>
> ^ A31s
>
Good one.
>> + *
>> + * Copyright (C) 2014 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>
> And I guess your copyright would be more appropriate here.
It is a copy of a file you authored, with some lines removed, so I deliberately left
this as is.
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pinctrl/pinctrl.h>
>> +
>> +#include "pinctrl-sunxi.h"
>> +
>> +static const struct sunxi_desc_pin sun6i_a31s_pins[] = {
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* RING */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
>> + SUNXI_FUNCTION(0x4, "clk_a_out"),
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
>> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
>> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
>> + SUNXI_FUNCTION(0x4, "clk_b_out"),
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
>> + SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
>> + SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* COL */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
>> + SUNXI_FUNCTION(0x4, "clk_c_out"),
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
>> + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
>> + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
>> + SUNXI_FUNCTION(0x3, "uart3"), /* TX */
>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
>> + SUNXI_FUNCTION(0x3, "uart3"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* RE */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
>> + /* Hole in pin numbering ! */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
>> + SUNXI_FUNCTION(0x3, "ts"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
>> + SUNXI_FUNCTION(0x3, "ts"), /* ERR */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
>> + SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
>> + SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D0 */
>> + SUNXI_FUNCTION(0x3, "uart5"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D1 */
>> + SUNXI_FUNCTION(0x3, "uart5"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D2 */
>> + SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D3 */
>> + SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D4 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D5 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D1 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D6 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D2 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D7 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D3 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D8 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D4 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D9 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D5 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D10 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D6 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D11 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D7 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
>> + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
>> + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
>> + SUNXI_FUNCTION(0x4, "uart0")), /* TX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
>> + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
>> + SUNXI_FUNCTION(0x4, "uart0")), /* RX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
>> + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart4"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart4"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
>> + /* Hole, note H starts at pin 9 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
>> + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
>> + SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
>> + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
>> + SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
>> + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
>> + SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
>> + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
>> + SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "pwm0")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart0")), /* TX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart0")), /* RX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> +};
>> +
>> +static const struct sunxi_pinctrl_desc sun6i_a31s_pinctrl_data = {
>> + .pins = sun6i_a31s_pins,
>> + .npins = ARRAY_SIZE(sun6i_a31s_pins),
>> + .irq_banks = 4,
>> +};
>> +
>> +static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev)
>> +{
>> + return sunxi_pinctrl_init(pdev,
>> + &sun6i_a31s_pinctrl_data);
>> +}
>> +
>> +static struct of_device_id sun6i_a31s_pinctrl_match[] = {
>> + { .compatible = "allwinner,sun6i-a31s-pinctrl", },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, sun6i_a31s_pinctrl_match);
>> +
>> +static struct platform_driver sun6i_a31s_pinctrl_driver = {
>> + .probe = sun6i_a31s_pinctrl_probe,
>> + .driver = {
>> + .name = "sun6i-a31s-pinctrl",
>> + .owner = THIS_MODULE,
>> + .of_match_table = sun6i_a31s_pinctrl_match,
>> + },
>> +};
>> +module_platform_driver(sun6i_a31s_pinctrl_driver);
>> +
>> +MODULE_AUTHOR("Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org");
>> +MODULE_DESCRIPTION("Allwinner A31 pinctrl driver");
>
> s/A31/A31s/
Will fix.
> It looks fine otherwise. Once these very minor issues fixed, you can
> add my Acked-by.
Ok, let me know what you want to do about the copyright header and I'll fix the
other 2 issues.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 2/5] pinctrl: sun6i: Add A31s pinctrl support
@ 2014-11-26 8:11 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 8:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 11/25/2014 07:08 PM, Maxime Ripard wrote:
> On Sun, Nov 23, 2014 at 01:54:40PM +0100, Hans de Goede wrote:
>> The A31s is a stripped down version of the A31, as such it is missing some
>> pins and some functions on some pins.
>>
>> The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
>> with the missing pins and functions removed.
>>
>> Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
>> prcm pins are identical between the A31 and the A31s.
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
>> drivers/pinctrl/sunxi/Kconfig | 4 +
>> drivers/pinctrl/sunxi/Makefile | 1 +
>> drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c | 814 +++++++++++++++++++++
>> 4 files changed, 820 insertions(+)
>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> index 93ce12e..fdd8046 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> @@ -11,6 +11,7 @@ Required properties:
>> "allwinner,sun5i-a10s-pinctrl"
>> "allwinner,sun5i-a13-pinctrl"
>> "allwinner,sun6i-a31-pinctrl"
>> + "allwinner,sun6i-a31s-pinctrl"
>> "allwinner,sun6i-a31-r-pinctrl"
>> "allwinner,sun7i-a20-pinctrl"
>> "allwinner,sun8i-a23-pinctrl"
>> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>> index a5e10f7..6cffe38 100644
>> --- a/drivers/pinctrl/sunxi/Kconfig
>> +++ b/drivers/pinctrl/sunxi/Kconfig
>> @@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
>> def_bool MACH_SUN6I
>> select PINCTRL_SUNXI_COMMON
>>
>> +config PINCTRL_SUN6I_A31S
>> + def_bool MACH_SUN6I
>> + select PINCTRL_SUNXI_COMMON
>> +
>> config PINCTRL_SUN6I_A31_R
>> def_bool MACH_SUN6I
>> depends on RESET_CONTROLLER
>> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
>> index e797efb..2f82290 100644
>> --- a/drivers/pinctrl/sunxi/Makefile
>> +++ b/drivers/pinctrl/sunxi/Makefile
>> @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
>> obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
>> obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
>> obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
>> +obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
>> obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
>> obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
>> obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
>> new file mode 100644
>> index 0000000..42ee373
>> --- /dev/null
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
>> @@ -0,0 +1,814 @@
>> +/*
>> + * Allwinner A31 SoCs pinctrl driver.
>
> ^ A31s
>
Good one.
>> + *
>> + * Copyright (C) 2014 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>
> And I guess your copyright would be more appropriate here.
It is a copy of a file you authored, with some lines removed, so I deliberately left
this as is.
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pinctrl/pinctrl.h>
>> +
>> +#include "pinctrl-sunxi.h"
>> +
>> +static const struct sunxi_desc_pin sun6i_a31s_pins[] = {
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* RING */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
>> + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
>> + SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
>> + SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
>> + SUNXI_FUNCTION(0x4, "clk_a_out"),
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
>> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
>> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
>> + SUNXI_FUNCTION(0x4, "clk_b_out"),
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
>> + SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
>> + SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* COL */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
>> + SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
>> + SUNXI_FUNCTION(0x4, "clk_c_out"),
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
>> + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
>> + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
>> + SUNXI_FUNCTION(0x3, "uart3"), /* TX */
>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
>> + SUNXI_FUNCTION(0x3, "uart3"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* RE */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
>> + /* Hole in pin numbering ! */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
>> + SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
>> + SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
>> + SUNXI_FUNCTION(0x3, "ts"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
>> + SUNXI_FUNCTION(0x3, "ts"), /* ERR */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
>> + SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
>> + SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D0 */
>> + SUNXI_FUNCTION(0x3, "uart5"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D1 */
>> + SUNXI_FUNCTION(0x3, "uart5"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D2 */
>> + SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D3 */
>> + SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D4 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D5 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D1 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D6 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D2 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D7 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D3 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D8 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D4 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D9 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D5 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D10 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D6 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* D11 */
>> + SUNXI_FUNCTION(0x3, "ts"), /* D7 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
>> + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
>> + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
>> + SUNXI_FUNCTION(0x4, "uart0")), /* TX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
>> + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
>> + SUNXI_FUNCTION(0x4, "uart0")), /* RX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
>> + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
>> + SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart4"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart4"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
>> + /* Hole, note H starts at pin 9 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
>> + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
>> + SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
>> + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
>> + SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
>> + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
>> + SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
>> + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
>> + SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "pwm0")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart0")), /* TX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart0")), /* RX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> +};
>> +
>> +static const struct sunxi_pinctrl_desc sun6i_a31s_pinctrl_data = {
>> + .pins = sun6i_a31s_pins,
>> + .npins = ARRAY_SIZE(sun6i_a31s_pins),
>> + .irq_banks = 4,
>> +};
>> +
>> +static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev)
>> +{
>> + return sunxi_pinctrl_init(pdev,
>> + &sun6i_a31s_pinctrl_data);
>> +}
>> +
>> +static struct of_device_id sun6i_a31s_pinctrl_match[] = {
>> + { .compatible = "allwinner,sun6i-a31s-pinctrl", },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, sun6i_a31s_pinctrl_match);
>> +
>> +static struct platform_driver sun6i_a31s_pinctrl_driver = {
>> + .probe = sun6i_a31s_pinctrl_probe,
>> + .driver = {
>> + .name = "sun6i-a31s-pinctrl",
>> + .owner = THIS_MODULE,
>> + .of_match_table = sun6i_a31s_pinctrl_match,
>> + },
>> +};
>> +module_platform_driver(sun6i_a31s_pinctrl_driver);
>> +
>> +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
>> +MODULE_DESCRIPTION("Allwinner A31 pinctrl driver");
>
> s/A31/A31s/
Will fix.
> It looks fine otherwise. Once these very minor issues fixed, you can
> add my Acked-by.
Ok, let me know what you want to do about the copyright header and I'll fix the
other 2 issues.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
2014-11-25 18:04 ` Maxime Ripard
@ 2014-11-26 8:30 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 8:30 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Hi,
On 11/25/2014 07:04 PM, Maxime Ripard wrote:
> Hi,
>
> On Sun, Nov 23, 2014 at 01:54:39PM +0100, Hans de Goede wrote:
>> While working on pinctrl for the A31s, I noticed that function 4 of
>> PA15 - PA18 was missing, add these.
>>
>> I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
>> be PB4 & PB5, fix this as well.
>>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>> drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>> index a2b4b85..fb19e15 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>> @@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
>> + SUNXI_FUNCTION(0x4, "clk_a_out"),
>
> It's called clk_out_a on the A20, I'd rather stick with the same
> scheme here.
Will fix.
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
>> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
>> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
>> + SUNXI_FUNCTION(0x4, "clk_b_out"),
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> @@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
>> + SUNXI_FUNCTION(0x4, "clk_c_out"),
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> @@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
>> SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
>> SUNXI_FUNCTION(0x3, "uart3"), /* TX */
>> - SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
>> SUNXI_FUNCTION(0x3, "uart3"), /* RX */
>> - SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>
> Where did you get that info from? The datasheet still reports that
> information.
I assume with the datasheet you mean "A31 User Manual V1.20.pdf", which
was last updated on September 20, 2013. I did not check that one, now I
see where the original pinctrl code from.
So I've done some more digging:
"A31 Datasheet - v1.00 (2012-12-24).pdf" also has twi3 sck / sda on pin
PB5 / PB6 like the current pinctrl code.
But "A31 Datasheet V1.40.pdf" which has the following in its revision log:
"1.4 Dec 10,2013 Modify Pin Description"
Moves them to PB4 / PB5 and that is where I got this from (and was the only
place I initially looked), I think that this is an intentional change, and
that PB4 / PB5 are the correct pins.
I will ask Allwinner which is correct, so that we know for sure.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
@ 2014-11-26 8:30 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 8:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 11/25/2014 07:04 PM, Maxime Ripard wrote:
> Hi,
>
> On Sun, Nov 23, 2014 at 01:54:39PM +0100, Hans de Goede wrote:
>> While working on pinctrl for the A31s, I noticed that function 4 of
>> PA15 - PA18 was missing, add these.
>>
>> I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
>> be PB4 & PB5, fix this as well.
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>> index a2b4b85..fb19e15 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>> @@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
>> + SUNXI_FUNCTION(0x4, "clk_a_out"),
>
> It's called clk_out_a on the A20, I'd rather stick with the same
> scheme here.
Will fix.
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
>> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
>> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
>> + SUNXI_FUNCTION(0x4, "clk_b_out"),
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> @@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
>> SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
>> + SUNXI_FUNCTION(0x4, "clk_c_out"),
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> @@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
>> SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
>> SUNXI_FUNCTION(0x3, "uart3"), /* TX */
>> - SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
>> SUNXI_FUNCTION(0x0, "gpio_in"),
>> SUNXI_FUNCTION(0x1, "gpio_out"),
>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
>> SUNXI_FUNCTION(0x3, "uart3"), /* RX */
>> - SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>
> Where did you get that info from? The datasheet still reports that
> information.
I assume with the datasheet you mean "A31 User Manual V1.20.pdf", which
was last updated on September 20, 2013. I did not check that one, now I
see where the original pinctrl code from.
So I've done some more digging:
"A31 Datasheet - v1.00 (2012-12-24).pdf" also has twi3 sck / sda on pin
PB5 / PB6 like the current pinctrl code.
But "A31 Datasheet V1.40.pdf" which has the following in its revision log:
"1.4 Dec 10,2013 Modify Pin Description"
Moves them to PB4 / PB5 and that is where I got this from (and was the only
place I initially looked), I think that this is an intentional change, and
that PB4 / PB5 are the correct pins.
I will ask Allwinner which is correct, so that we know for sure.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: Re: [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
2014-11-25 18:18 ` Maxime Ripard
@ 2014-11-26 8:44 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 8:44 UTC (permalink / raw)
To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi,
On 11/25/2014 07:18 PM, Maxime Ripard wrote:
> Hi,
>
> On Sun, Nov 23, 2014 at 01:54:42PM +0100, Hans de Goede wrote:
>> Add a dtsi file for A31s based boards. This is a copy of sun6i-a31.dtsi, with:
>>
>> -The main pinctrl compatible changed to allwinner,sun6i-a31s.dtsi
>> -The ohci2 controller is present according to the data-sheet, but not routed
>> to the outside, so remove it from the dtsi as having an always disabled node
>> is not useful.
>>
>> All the other nodes present in the original sun6i-a31.dtsi are present in
>> the A31s too, and are 100% compatible.
>
> Then maybe duplicating the DT isn't worth it then.
>
> Creating a sun6i.dtsi and including that from both the A31 and A31s
> seems more like an appropriate solution.
So to be clear, we would get:
sun6i.dtsi, which has everything which is currently in sun6i-a31.dtsi, minus
the compatible for the main pinctrl node.
sun6i-a31.dtsi, which includes sun6i.dtsi, and sets the compatible for the main
pinctrl node.
sun6i-a31s.dtsi, idem.
BTW as for the 100% compatible thing, I've gotten confirmation from Allwinner
that the A31 and A31s are the same die in a different package.
This also explains why when working on DRAM controller support for the A31s I noticed
that the auto-detect code for the A31 worked fine, and figured out there was only one
channel without any issues, the second channel actually is there, it is just not routed
to the outside.
Which brings us to the question should we differentiate between them at all ? I think
that from a pinctrl pov it makes sense to differentiate, and that for the rest we should
try not to needlessly differentiate.
>
>>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>> arch/arm/boot/dts/sun6i-a31s.dtsi | 925 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 925 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> new file mode 100644
>> index 0000000..b3b99a9
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> @@ -0,0 +1,925 @@
>> +/*
>> + * Copyright 2013 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>
> It should be your copyright here.
Same discussion as before, if I copy a file you authored it still is yours _copy_right
wise :)
>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public
>> + * License along with this library; if not, write to the Free
>> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>
> There was an issue with the wording of the license, s/library/file/
Ok. Is this already fixed in dts-for-3.19 ? Currently this patch-set is based on
3.18 + some cherry picked patches from dts-for-3.19, if this is fixed there, I
guess I need to cherry pick some more to avoid conflicts.
>
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &uart2;
>> + serial3 = &uart3;
>> + serial4 = &uart4;
>> + serial5 = &uart5;
>> + ethernet0 = &gmac;
>> + };
>> +
>> + chosen {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + framebuffer@0 {
>> + compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
>> + allwinner,pipeline = "de_be0-lcd0-hdmi";
>> + clocks = <&pll6>;
>
> pll6 uses an argument now
>
>> + status = "disabled";
>> + };
>> + };
>> +
>> + cpus {
>> + enable-method = "allwinner,sun6i-a31";
>
> allwinner,sun6i-a31s I guess?
Although this is not a "compatible" I would like to treat it as such
and just keep this as "allwinner,sun6i-a31", as it is 100% compatible.
>
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0>;
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <1>;
>> + };
>> +
>> + cpu@2 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <2>;
>> + };
>> +
>> + cpu@3 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <3>;
>> + };
>> + };
>> +
>> + memory {
>> + reg = <0x40000000 0x80000000>;
>> + };
>> +
>> + pmu {
>> + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
>> + interrupts = <0 120 4>,
>> + <0 121 4>,
>> + <0 122 4>,
>> + <0 123 4>;
>> + };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: osc24M {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + };
>> +
>> + osc32k: clk@0 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + pll1: clk@01c20000 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-pll1-clk";
>> + reg = <0x01c20000 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll1";
>> + };
>> +
>> + pll6: clk@01c20028 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>> + reg = <0x01c20028 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll6";
>> + };
>> +
>> + cpu: cpu@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>> + reg = <0x01c20050 0x4>;
>> +
>> + /*
>> + * PLL1 is listed twice here.
>> + * While it looks suspicious, it's actually documented
>> + * that way both in the datasheet and in the code from
>> + * Allwinner.
>> + */
>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> + clock-output-names = "cpu";
>> + };
>> +
>> + axi: axi@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-axi-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&cpu>;
>> + clock-output-names = "axi";
>> + };
>> +
>> + ahb1_mux: ahb1_mux@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
>> + clock-output-names = "ahb1_mux";
>> + };
>> +
>> + ahb1: ahb1@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-ahb-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1_mux>;
>> + clock-output-names = "ahb1";
>> + };
>> +
>> + ahb1_gates: clk@01c20060 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
>> + reg = <0x01c20060 0x8>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
>> + "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
>> + "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
>> + "ahb1_nand0", "ahb1_sdram",
>> + "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
>> + "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
>> + "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
>> + "ahb1_ehci1", "ahb1_ohci0",
>> + "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
>> + "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
>> + "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
>> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
>> + "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
>> + "ahb1_drc0", "ahb1_drc1";
>> + };
>
> Are the gates really identical?
According to the user manual, yes.
> As in not even stripped down?
Yep, it is the same die.
>
>> + apb1: apb1@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "apb1";
>> + };
>> +
>> + apb1_gates: clk@01c20068 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-apb1-gates-clk";
>> + reg = <0x01c20068 0x4>;
>> + clocks = <&apb1>;
>> + clock-output-names = "apb1_codec", "apb1_digital_mic",
>> + "apb1_pio", "apb1_daudio0",
>> + "apb1_daudio1";
>> + };
>> +
>> + apb2_mux: apb2_mux@01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
>> + clock-output-names = "apb2_mux";
>> + };
>> +
>> + apb2: apb2@01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-apb2-div-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&apb2_mux>;
>> + clock-output-names = "apb2";
>> + };
>> +
>> + apb2_gates: clk@01c2006c {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-apb2-gates-clk";
>> + reg = <0x01c2006c 0x4>;
>> + clocks = <&apb2>;
>> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
>> + "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
>> + "apb2_uart1", "apb2_uart2", "apb2_uart3",
>> + "apb2_uart4", "apb2_uart5";
>> + };
>> +
>> + mmc0_clk: clk@01c20088 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20088 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc0";
>> + };
>> +
>> + mmc1_clk: clk@01c2008c {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c2008c 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc1";
>> + };
>> +
>> + mmc2_clk: clk@01c20090 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20090 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc2";
>> + };
>> +
>> + mmc3_clk: clk@01c20094 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20094 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc3";
>> + };
>> +
>> + spi0_clk: clk@01c200a0 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a0 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi0";
>> + };
>> +
>> + spi1_clk: clk@01c200a4 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a4 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi1";
>> + };
>> +
>> + spi2_clk: clk@01c200a8 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a8 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi2";
>> + };
>> +
>> + spi3_clk: clk@01c200ac {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200ac 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi3";
>> + };
>> +
>> + usb_clk: clk@01c200cc {
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-usb-clk";
>> + reg = <0x01c200cc 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
>> + "usb_ohci0", "usb_ohci1",
>> + "usb_ohci2";
>> + };
>> +
>> + /*
>> + * The following two are dummy clocks, placeholders used in the gmac_tx
>> + * clock. The gmac driver will choose one parent depending on the PHY
>> + * interface mode, using clk_set_rate auto-reparenting.
>> + * The actual TX clock rate is not controlled by the gmac_tx clock.
>> + */
>> + mii_phy_tx_clk: clk@1 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <25000000>;
>> + clock-output-names = "mii_phy_tx";
>> + };
>> +
>> + gmac_int_tx_clk: clk@2 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <125000000>;
>> + clock-output-names = "gmac_int_tx";
>> + };
>> +
>> + gmac_tx_clk: clk@01c200d0 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun7i-a20-gmac-clk";
>> + reg = <0x01c200d0 0x4>;
>> + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
>> + clock-output-names = "gmac_tx";
>> + };
>> + };
>> +
>> + soc@01c00000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + dma: dma-controller@01c02000 {
>> + compatible = "allwinner,sun6i-a31-dma";
>> + reg = <0x01c02000 0x1000>;
>> + interrupts = <0 50 4>;
>> + clocks = <&ahb1_gates 6>;
>> + resets = <&ahb1_rst 6>;
>> + #dma-cells = <1>;
>> + };
>> +
>> + mmc0: mmc@01c0f000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ahb1_gates 8>, <&mmc0_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 8>;
>> + reset-names = "ahb";
>> + interrupts = <0 60 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc@01c10000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&ahb1_gates 9>, <&mmc1_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 9>;
>> + reset-names = "ahb";
>> + interrupts = <0 61 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc2: mmc@01c11000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&ahb1_gates 10>, <&mmc2_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 10>;
>> + reset-names = "ahb";
>> + interrupts = <0 62 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc3: mmc@01c12000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c12000 0x1000>;
>> + clocks = <&ahb1_gates 11>, <&mmc3_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 11>;
>> + reset-names = "ahb";
>> + interrupts = <0 63 4>;
>> + status = "disabled";
>> + };
>> +
>> + usbphy: phy@01c19400 {
>> + compatible = "allwinner,sun6i-a31-usb-phy";
>> + reg = <0x01c19400 0x10>,
>> + <0x01c1a800 0x4>,
>> + <0x01c1b800 0x4>;
>> + reg-names = "phy_ctrl",
>> + "pmu1",
>> + "pmu2";
>> + clocks = <&usb_clk 8>,
>> + <&usb_clk 9>,
>> + <&usb_clk 10>;
>> + clock-names = "usb0_phy",
>> + "usb1_phy",
>> + "usb2_phy";
>> + resets = <&usb_clk 0>,
>> + <&usb_clk 1>,
>> + <&usb_clk 2>;
>> + reset-names = "usb0_reset",
>> + "usb1_reset",
>> + "usb2_reset";
>> + status = "disabled";
>> + #phy-cells = <1>;
>> + };
>> +
>> + ehci0: usb@01c1a000 {
>> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
>> + reg = <0x01c1a000 0x100>;
>> + interrupts = <0 72 4>;
>> + clocks = <&ahb1_gates 26>;
>> + resets = <&ahb1_rst 26>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci0: usb@01c1a400 {
>> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
>> + reg = <0x01c1a400 0x100>;
>> + interrupts = <0 73 4>;
>> + clocks = <&ahb1_gates 29>, <&usb_clk 16>;
>> + resets = <&ahb1_rst 29>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ehci1: usb@01c1b000 {
>> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
>> + reg = <0x01c1b000 0x100>;
>> + interrupts = <0 74 4>;
>> + clocks = <&ahb1_gates 27>;
>> + resets = <&ahb1_rst 27>;
>> + phys = <&usbphy 2>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci1: usb@01c1b400 {
>> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
>> + reg = <0x01c1b400 0x100>;
>> + interrupts = <0 75 4>;
>> + clocks = <&ahb1_gates 30>, <&usb_clk 17>;
>> + resets = <&ahb1_rst 30>;
>> + phys = <&usbphy 2>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + pio: pinctrl@01c20800 {
>> + compatible = "allwinner,sun6i-a31s-pinctrl";
>> + reg = <0x01c20800 0x400>;
>> + interrupts = <0 11 4>,
>> + <0 15 4>,
>> + <0 16 4>,
>> + <0 17 4>;
>> + clocks = <&apb1_gates 5>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + uart0_pins_a: uart0@0 {
>> + allwinner,pins = "PH20", "PH21";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c0_pins_a: i2c0@0 {
>> + allwinner,pins = "PH14", "PH15";
>> + allwinner,function = "i2c0";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c1_pins_a: i2c1@0 {
>> + allwinner,pins = "PH16", "PH17";
>> + allwinner,function = "i2c1";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c2_pins_a: i2c2@0 {
>> + allwinner,pins = "PH18", "PH19";
>> + allwinner,function = "i2c2";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + mmc0_pins_a: mmc0@0 {
>> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
>
> Spaces after the comma, and I guess that would be better on two lines.
Erm, as said in the commit message this is a copy, with all the shortcomings of the
orginal. Anyways this become mute if we just rename sun6i-a31.dtsi to sun6i.dtsi
as discussed, then we avoid the whole having 2 copies dance.
>
>> + allwinner,function = "mmc0";
>> + allwinner,drive = <2>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_mii_a: gmac_mii@0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA8", "PA9", "PA11",
>> + "PA12", "PA13", "PA14", "PA19",
>> + "PA20", "PA21", "PA22", "PA23",
>> + "PA24", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_gmii_a: gmac_gmii@0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA4", "PA5", "PA6", "PA7",
>> + "PA8", "PA9", "PA10", "PA11",
>> + "PA12", "PA13", "PA14", "PA15",
>> + "PA16", "PA17", "PA18", "PA19",
>> + "PA20", "PA21", "PA22", "PA23",
>> + "PA24", "PA25", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + /*
>> + * data lines in GMII mode run at 125MHz and
>> + * might need a higher signal drive strength
>> + */
>> + allwinner,drive = <2>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_rgmii_a: gmac_rgmii@0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA9", "PA10", "PA11",
>> + "PA12", "PA13", "PA14", "PA19",
>> + "PA20", "PA25", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + /*
>> + * data lines in RGMII mode use DDR mode
>> + * and need a higher signal drive strength
>> + */
>> + allwinner,drive = <3>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> +
>> + ahb1_rst: reset@01c202c0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-reset";
>> + reg = <0x01c202c0 0xc>;
>> + };
>> +
>> + apb1_rst: reset@01c202d0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d0 0x4>;
>> + };
>> +
>> + apb2_rst: reset@01c202d8 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d8 0x4>;
>> + };
>> +
>> + timer@01c20c00 {
>> + compatible = "allwinner,sun4i-a10-timer";
>> + reg = <0x01c20c00 0xa0>;
>> + interrupts = <0 18 4>,
>> + <0 19 4>,
>> + <0 20 4>,
>> + <0 21 4>,
>> + <0 22 4>;
>> + clocks = <&osc24M>;
>> + };
>> +
>> + wdt1: watchdog@01c20ca0 {
>> + compatible = "allwinner,sun6i-a31-wdt";
>> + reg = <0x01c20ca0 0x20>;
>> + };
>> +
>> + uart0: serial@01c28000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28000 0x400>;
>> + interrupts = <0 0 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 16>;
>> + resets = <&apb2_rst 16>;
>> + dmas = <&dma 6>, <&dma 6>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@01c28400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28400 0x400>;
>> + interrupts = <0 1 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 17>;
>> + resets = <&apb2_rst 17>;
>> + dmas = <&dma 7>, <&dma 7>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@01c28800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28800 0x400>;
>> + interrupts = <0 2 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 18>;
>> + resets = <&apb2_rst 18>;
>> + dmas = <&dma 8>, <&dma 8>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@01c28c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28c00 0x400>;
>> + interrupts = <0 3 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 19>;
>> + resets = <&apb2_rst 19>;
>> + dmas = <&dma 9>, <&dma 9>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@01c29000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29000 0x400>;
>> + interrupts = <0 4 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 20>;
>> + resets = <&apb2_rst 20>;
>> + dmas = <&dma 10>, <&dma 10>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart5: serial@01c29400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29400 0x400>;
>> + interrupts = <0 5 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 21>;
>> + resets = <&apb2_rst 21>;
>> + dmas = <&dma 22>, <&dma 22>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + i2c0: i2c@01c2ac00 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2ac00 0x400>;
>> + interrupts = <0 6 4>;
>> + clocks = <&apb2_gates 0>;
>> + resets = <&apb2_rst 0>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c1: i2c@01c2b000 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b000 0x400>;
>> + interrupts = <0 7 4>;
>> + clocks = <&apb2_gates 1>;
>> + resets = <&apb2_rst 1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c2: i2c@01c2b400 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b400 0x400>;
>> + interrupts = <0 8 4>;
>> + clocks = <&apb2_gates 2>;
>> + resets = <&apb2_rst 2>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c3: i2c@01c2b800 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b800 0x400>;
>> + interrupts = <0 9 4>;
>> + clocks = <&apb2_gates 3>;
>> + resets = <&apb2_rst 3>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + gmac: ethernet@01c30000 {
>> + compatible = "allwinner,sun7i-a20-gmac";
>> + reg = <0x01c30000 0x1054>;
>> + interrupts = <0 82 4>;
>> + interrupt-names = "macirq";
>> + clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
>> + clock-names = "stmmaceth", "allwinner_gmac_tx";
>> + resets = <&ahb1_rst 17>;
>> + reset-names = "stmmaceth";
>> + snps,pbl = <2>;
>> + snps,fixed-burst;
>> + snps,force_sf_dma_mode;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + timer@01c60000 {
>> + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
>> + reg = <0x01c60000 0x1000>;
>> + interrupts = <0 51 4>,
>> + <0 52 4>,
>> + <0 53 4>,
>> + <0 54 4>;
>> + clocks = <&ahb1_gates 19>;
>> + resets = <&ahb1_rst 19>;
>> + };
>> +
>> + spi0: spi@01c68000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c68000 0x1000>;
>> + interrupts = <0 65 4>;
>> + clocks = <&ahb1_gates 20>, <&spi0_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 23>, <&dma 23>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 20>;
>> + status = "disabled";
>> + };
>> +
>> + spi1: spi@01c69000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c69000 0x1000>;
>> + interrupts = <0 66 4>;
>> + clocks = <&ahb1_gates 21>, <&spi1_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 24>, <&dma 24>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 21>;
>> + status = "disabled";
>> + };
>> +
>> + spi2: spi@01c6a000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c6a000 0x1000>;
>> + interrupts = <0 67 4>;
>> + clocks = <&ahb1_gates 22>, <&spi2_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 25>, <&dma 25>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 22>;
>> + status = "disabled";
>> + };
>> +
>> + spi3: spi@01c6b000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c6b000 0x1000>;
>> + interrupts = <0 68 4>;
>> + clocks = <&ahb1_gates 23>, <&spi3_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 26>, <&dma 26>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 23>;
>> + status = "disabled";
>> + };
>> +
>> + gic: interrupt-controller@01c81000 {
>> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
>> + reg = <0x01c81000 0x1000>,
>> + <0x01c82000 0x1000>,
>> + <0x01c84000 0x2000>,
>> + <0x01c86000 0x2000>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + interrupts = <1 9 0xf04>;
>> + };
>> +
>> + rtc: rtc@01f00000 {
>> + compatible = "allwinner,sun6i-a31-rtc";
>> + reg = <0x01f00000 0x54>;
>> + interrupts = <0 40 4>, <0 41 4>;
>> + };
>> +
>> + nmi_intc: interrupt-controller@01f00c0c {
>> + compatible = "allwinner,sun6i-a31-sc-nmi";
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + reg = <0x01f00c0c 0x38>;
>> + interrupts = <0 32 4>;
>> + };
>> +
>> + prcm@01f01400 {
>> + compatible = "allwinner,sun6i-a31-prcm";
>> + reg = <0x01f01400 0x200>;
>> +
>> + ar100: ar100_clk {
>> + compatible = "allwinner,sun6i-a31-ar100-clk";
>> + #clock-cells = <0>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
>> + clock-output-names = "ar100";
>> + };
>> +
>> + ahb0: ahb0_clk {
>> + compatible = "fixed-factor-clock";
>> + #clock-cells = <0>;
>> + clock-div = <1>;
>> + clock-mult = <1>;
>> + clocks = <&ar100>;
>> + clock-output-names = "ahb0";
>> + };
>> +
>> + apb0: apb0_clk {
>> + compatible = "allwinner,sun6i-a31-apb0-clk";
>> + #clock-cells = <0>;
>> + clocks = <&ahb0>;
>> + clock-output-names = "apb0";
>> + };
>> +
>> + apb0_gates: apb0_gates_clk {
>> + compatible = "allwinner,sun6i-a31-apb0-gates-clk";
>> + #clock-cells = <1>;
>> + clocks = <&apb0>;
>> + clock-output-names = "apb0_pio", "apb0_ir",
>> + "apb0_timer", "apb0_p2wi",
>> + "apb0_uart", "apb0_1wire",
>> + "apb0_i2c";
>> + };
>> +
>> + ir_clk: ir_clk {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ir-clk";
>> + clocks = <&osc32k>, <&osc24M>;
>> + clock-output-names = "ir";
>> + };
>
> This is yet to be agreed on....
Ack, copy / paste error, will drop.
>
>> +
>> + apb0_rst: apb0_rst {
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + #reset-cells = <1>;
>> + };
>> + };
>> +
>> + cpucfg@01f01c00 {
>> + compatible = "allwinner,sun6i-a31-cpuconfig";
>> + reg = <0x01f01c00 0x300>;
>> + };
>> +
>> + ir@01f02000 {
>> + compatible = "allwinner,sun5i-a13-ir";
>> + clocks = <&apb0_gates 1>, <&ir_clk>;
>> + clock-names = "apb", "ir";
>> + resets = <&apb0_rst 1>;
>> + interrupts = <0 37 4>;
>> + reg = <0x01f02000 0x40>;
>> + status = "disabled";
>> + };
>> +
>> + r_pio: pinctrl@01f02c00 {
>> + compatible = "allwinner,sun6i-a31-r-pinctrl";
>> + reg = <0x01f02c00 0x400>;
>> + interrupts = <0 45 4>,
>> + <0 46 4>;
>> + clocks = <&apb0_gates 0>;
>> + resets = <&apb0_rst 0>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + ir_pins_a: ir@0 {
>> + allwinner,pins = "PL4";
>> + allwinner,function = "s_ir";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> + };
>> +};
>> --
>> 2.1.0
>>
>
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* [linux-sunxi] Re: [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
@ 2014-11-26 8:44 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 8:44 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 11/25/2014 07:18 PM, Maxime Ripard wrote:
> Hi,
>
> On Sun, Nov 23, 2014 at 01:54:42PM +0100, Hans de Goede wrote:
>> Add a dtsi file for A31s based boards. This is a copy of sun6i-a31.dtsi, with:
>>
>> -The main pinctrl compatible changed to allwinner,sun6i-a31s.dtsi
>> -The ohci2 controller is present according to the data-sheet, but not routed
>> to the outside, so remove it from the dtsi as having an always disabled node
>> is not useful.
>>
>> All the other nodes present in the original sun6i-a31.dtsi are present in
>> the A31s too, and are 100% compatible.
>
> Then maybe duplicating the DT isn't worth it then.
>
> Creating a sun6i.dtsi and including that from both the A31 and A31s
> seems more like an appropriate solution.
So to be clear, we would get:
sun6i.dtsi, which has everything which is currently in sun6i-a31.dtsi, minus
the compatible for the main pinctrl node.
sun6i-a31.dtsi, which includes sun6i.dtsi, and sets the compatible for the main
pinctrl node.
sun6i-a31s.dtsi, idem.
BTW as for the 100% compatible thing, I've gotten confirmation from Allwinner
that the A31 and A31s are the same die in a different package.
This also explains why when working on DRAM controller support for the A31s I noticed
that the auto-detect code for the A31 worked fine, and figured out there was only one
channel without any issues, the second channel actually is there, it is just not routed
to the outside.
Which brings us to the question should we differentiate between them at all ? I think
that from a pinctrl pov it makes sense to differentiate, and that for the rest we should
try not to needlessly differentiate.
>
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> arch/arm/boot/dts/sun6i-a31s.dtsi | 925 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 925 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> new file mode 100644
>> index 0000000..b3b99a9
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
>> @@ -0,0 +1,925 @@
>> +/*
>> + * Copyright 2013 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>
> It should be your copyright here.
Same discussion as before, if I copy a file you authored it still is yours _copy_right
wise :)
>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public
>> + * License along with this library; if not, write to the Free
>> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>
> There was an issue with the wording of the license, s/library/file/
Ok. Is this already fixed in dts-for-3.19 ? Currently this patch-set is based on
3.18 + some cherry picked patches from dts-for-3.19, if this is fixed there, I
guess I need to cherry pick some more to avoid conflicts.
>
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &uart2;
>> + serial3 = &uart3;
>> + serial4 = &uart4;
>> + serial5 = &uart5;
>> + ethernet0 = &gmac;
>> + };
>> +
>> + chosen {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + framebuffer at 0 {
>> + compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
>> + allwinner,pipeline = "de_be0-lcd0-hdmi";
>> + clocks = <&pll6>;
>
> pll6 uses an argument now
>
>> + status = "disabled";
>> + };
>> + };
>> +
>> + cpus {
>> + enable-method = "allwinner,sun6i-a31";
>
> allwinner,sun6i-a31s I guess?
Although this is not a "compatible" I would like to treat it as such
and just keep this as "allwinner,sun6i-a31", as it is 100% compatible.
>
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu at 0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0>;
>> + };
>> +
>> + cpu at 1 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <1>;
>> + };
>> +
>> + cpu at 2 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <2>;
>> + };
>> +
>> + cpu at 3 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <3>;
>> + };
>> + };
>> +
>> + memory {
>> + reg = <0x40000000 0x80000000>;
>> + };
>> +
>> + pmu {
>> + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
>> + interrupts = <0 120 4>,
>> + <0 121 4>,
>> + <0 122 4>,
>> + <0 123 4>;
>> + };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: osc24M {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + };
>> +
>> + osc32k: clk at 0 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + pll1: clk at 01c20000 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-pll1-clk";
>> + reg = <0x01c20000 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll1";
>> + };
>> +
>> + pll6: clk at 01c20028 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>> + reg = <0x01c20028 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll6";
>> + };
>> +
>> + cpu: cpu at 01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>> + reg = <0x01c20050 0x4>;
>> +
>> + /*
>> + * PLL1 is listed twice here.
>> + * While it looks suspicious, it's actually documented
>> + * that way both in the datasheet and in the code from
>> + * Allwinner.
>> + */
>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> + clock-output-names = "cpu";
>> + };
>> +
>> + axi: axi at 01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-axi-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&cpu>;
>> + clock-output-names = "axi";
>> + };
>> +
>> + ahb1_mux: ahb1_mux at 01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
>> + clock-output-names = "ahb1_mux";
>> + };
>> +
>> + ahb1: ahb1 at 01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-ahb-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1_mux>;
>> + clock-output-names = "ahb1";
>> + };
>> +
>> + ahb1_gates: clk at 01c20060 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
>> + reg = <0x01c20060 0x8>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
>> + "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
>> + "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
>> + "ahb1_nand0", "ahb1_sdram",
>> + "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
>> + "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
>> + "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
>> + "ahb1_ehci1", "ahb1_ohci0",
>> + "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
>> + "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
>> + "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
>> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
>> + "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
>> + "ahb1_drc0", "ahb1_drc1";
>> + };
>
> Are the gates really identical?
According to the user manual, yes.
> As in not even stripped down?
Yep, it is the same die.
>
>> + apb1: apb1 at 01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "apb1";
>> + };
>> +
>> + apb1_gates: clk at 01c20068 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-apb1-gates-clk";
>> + reg = <0x01c20068 0x4>;
>> + clocks = <&apb1>;
>> + clock-output-names = "apb1_codec", "apb1_digital_mic",
>> + "apb1_pio", "apb1_daudio0",
>> + "apb1_daudio1";
>> + };
>> +
>> + apb2_mux: apb2_mux at 01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
>> + clock-output-names = "apb2_mux";
>> + };
>> +
>> + apb2: apb2 at 01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-apb2-div-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&apb2_mux>;
>> + clock-output-names = "apb2";
>> + };
>> +
>> + apb2_gates: clk at 01c2006c {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-apb2-gates-clk";
>> + reg = <0x01c2006c 0x4>;
>> + clocks = <&apb2>;
>> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
>> + "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
>> + "apb2_uart1", "apb2_uart2", "apb2_uart3",
>> + "apb2_uart4", "apb2_uart5";
>> + };
>> +
>> + mmc0_clk: clk at 01c20088 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20088 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc0";
>> + };
>> +
>> + mmc1_clk: clk at 01c2008c {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c2008c 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc1";
>> + };
>> +
>> + mmc2_clk: clk at 01c20090 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20090 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc2";
>> + };
>> +
>> + mmc3_clk: clk at 01c20094 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c20094 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "mmc3";
>> + };
>> +
>> + spi0_clk: clk at 01c200a0 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a0 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi0";
>> + };
>> +
>> + spi1_clk: clk at 01c200a4 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a4 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi1";
>> + };
>> +
>> + spi2_clk: clk at 01c200a8 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200a8 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi2";
>> + };
>> +
>> + spi3_clk: clk at 01c200ac {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-mod0-clk";
>> + reg = <0x01c200ac 0x4>;
>> + clocks = <&osc24M>, <&pll6>;
>> + clock-output-names = "spi3";
>> + };
>> +
>> + usb_clk: clk at 01c200cc {
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-usb-clk";
>> + reg = <0x01c200cc 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
>> + "usb_ohci0", "usb_ohci1",
>> + "usb_ohci2";
>> + };
>> +
>> + /*
>> + * The following two are dummy clocks, placeholders used in the gmac_tx
>> + * clock. The gmac driver will choose one parent depending on the PHY
>> + * interface mode, using clk_set_rate auto-reparenting.
>> + * The actual TX clock rate is not controlled by the gmac_tx clock.
>> + */
>> + mii_phy_tx_clk: clk at 1 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <25000000>;
>> + clock-output-names = "mii_phy_tx";
>> + };
>> +
>> + gmac_int_tx_clk: clk at 2 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <125000000>;
>> + clock-output-names = "gmac_int_tx";
>> + };
>> +
>> + gmac_tx_clk: clk at 01c200d0 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun7i-a20-gmac-clk";
>> + reg = <0x01c200d0 0x4>;
>> + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
>> + clock-output-names = "gmac_tx";
>> + };
>> + };
>> +
>> + soc at 01c00000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + dma: dma-controller at 01c02000 {
>> + compatible = "allwinner,sun6i-a31-dma";
>> + reg = <0x01c02000 0x1000>;
>> + interrupts = <0 50 4>;
>> + clocks = <&ahb1_gates 6>;
>> + resets = <&ahb1_rst 6>;
>> + #dma-cells = <1>;
>> + };
>> +
>> + mmc0: mmc at 01c0f000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ahb1_gates 8>, <&mmc0_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 8>;
>> + reset-names = "ahb";
>> + interrupts = <0 60 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc at 01c10000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&ahb1_gates 9>, <&mmc1_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 9>;
>> + reset-names = "ahb";
>> + interrupts = <0 61 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc2: mmc at 01c11000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&ahb1_gates 10>, <&mmc2_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 10>;
>> + reset-names = "ahb";
>> + interrupts = <0 62 4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc3: mmc at 01c12000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c12000 0x1000>;
>> + clocks = <&ahb1_gates 11>, <&mmc3_clk>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ahb1_rst 11>;
>> + reset-names = "ahb";
>> + interrupts = <0 63 4>;
>> + status = "disabled";
>> + };
>> +
>> + usbphy: phy at 01c19400 {
>> + compatible = "allwinner,sun6i-a31-usb-phy";
>> + reg = <0x01c19400 0x10>,
>> + <0x01c1a800 0x4>,
>> + <0x01c1b800 0x4>;
>> + reg-names = "phy_ctrl",
>> + "pmu1",
>> + "pmu2";
>> + clocks = <&usb_clk 8>,
>> + <&usb_clk 9>,
>> + <&usb_clk 10>;
>> + clock-names = "usb0_phy",
>> + "usb1_phy",
>> + "usb2_phy";
>> + resets = <&usb_clk 0>,
>> + <&usb_clk 1>,
>> + <&usb_clk 2>;
>> + reset-names = "usb0_reset",
>> + "usb1_reset",
>> + "usb2_reset";
>> + status = "disabled";
>> + #phy-cells = <1>;
>> + };
>> +
>> + ehci0: usb at 01c1a000 {
>> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
>> + reg = <0x01c1a000 0x100>;
>> + interrupts = <0 72 4>;
>> + clocks = <&ahb1_gates 26>;
>> + resets = <&ahb1_rst 26>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci0: usb at 01c1a400 {
>> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
>> + reg = <0x01c1a400 0x100>;
>> + interrupts = <0 73 4>;
>> + clocks = <&ahb1_gates 29>, <&usb_clk 16>;
>> + resets = <&ahb1_rst 29>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ehci1: usb at 01c1b000 {
>> + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
>> + reg = <0x01c1b000 0x100>;
>> + interrupts = <0 74 4>;
>> + clocks = <&ahb1_gates 27>;
>> + resets = <&ahb1_rst 27>;
>> + phys = <&usbphy 2>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci1: usb at 01c1b400 {
>> + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
>> + reg = <0x01c1b400 0x100>;
>> + interrupts = <0 75 4>;
>> + clocks = <&ahb1_gates 30>, <&usb_clk 17>;
>> + resets = <&ahb1_rst 30>;
>> + phys = <&usbphy 2>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + pio: pinctrl at 01c20800 {
>> + compatible = "allwinner,sun6i-a31s-pinctrl";
>> + reg = <0x01c20800 0x400>;
>> + interrupts = <0 11 4>,
>> + <0 15 4>,
>> + <0 16 4>,
>> + <0 17 4>;
>> + clocks = <&apb1_gates 5>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + uart0_pins_a: uart0 at 0 {
>> + allwinner,pins = "PH20", "PH21";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c0_pins_a: i2c0 at 0 {
>> + allwinner,pins = "PH14", "PH15";
>> + allwinner,function = "i2c0";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c1_pins_a: i2c1 at 0 {
>> + allwinner,pins = "PH16", "PH17";
>> + allwinner,function = "i2c1";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + i2c2_pins_a: i2c2 at 0 {
>> + allwinner,pins = "PH18", "PH19";
>> + allwinner,function = "i2c2";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + mmc0_pins_a: mmc0 at 0 {
>> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
>
> Spaces after the comma, and I guess that would be better on two lines.
Erm, as said in the commit message this is a copy, with all the shortcomings of the
orginal. Anyways this become mute if we just rename sun6i-a31.dtsi to sun6i.dtsi
as discussed, then we avoid the whole having 2 copies dance.
>
>> + allwinner,function = "mmc0";
>> + allwinner,drive = <2>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_mii_a: gmac_mii at 0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA8", "PA9", "PA11",
>> + "PA12", "PA13", "PA14", "PA19",
>> + "PA20", "PA21", "PA22", "PA23",
>> + "PA24", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_gmii_a: gmac_gmii at 0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA4", "PA5", "PA6", "PA7",
>> + "PA8", "PA9", "PA10", "PA11",
>> + "PA12", "PA13", "PA14", "PA15",
>> + "PA16", "PA17", "PA18", "PA19",
>> + "PA20", "PA21", "PA22", "PA23",
>> + "PA24", "PA25", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + /*
>> + * data lines in GMII mode run at 125MHz and
>> + * might need a higher signal drive strength
>> + */
>> + allwinner,drive = <2>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + gmac_pins_rgmii_a: gmac_rgmii at 0 {
>> + allwinner,pins = "PA0", "PA1", "PA2", "PA3",
>> + "PA9", "PA10", "PA11",
>> + "PA12", "PA13", "PA14", "PA19",
>> + "PA20", "PA25", "PA26", "PA27";
>> + allwinner,function = "gmac";
>> + /*
>> + * data lines in RGMII mode use DDR mode
>> + * and need a higher signal drive strength
>> + */
>> + allwinner,drive = <3>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> +
>> + ahb1_rst: reset at 01c202c0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-reset";
>> + reg = <0x01c202c0 0xc>;
>> + };
>> +
>> + apb1_rst: reset at 01c202d0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d0 0x4>;
>> + };
>> +
>> + apb2_rst: reset at 01c202d8 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d8 0x4>;
>> + };
>> +
>> + timer at 01c20c00 {
>> + compatible = "allwinner,sun4i-a10-timer";
>> + reg = <0x01c20c00 0xa0>;
>> + interrupts = <0 18 4>,
>> + <0 19 4>,
>> + <0 20 4>,
>> + <0 21 4>,
>> + <0 22 4>;
>> + clocks = <&osc24M>;
>> + };
>> +
>> + wdt1: watchdog at 01c20ca0 {
>> + compatible = "allwinner,sun6i-a31-wdt";
>> + reg = <0x01c20ca0 0x20>;
>> + };
>> +
>> + uart0: serial at 01c28000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28000 0x400>;
>> + interrupts = <0 0 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 16>;
>> + resets = <&apb2_rst 16>;
>> + dmas = <&dma 6>, <&dma 6>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial at 01c28400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28400 0x400>;
>> + interrupts = <0 1 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 17>;
>> + resets = <&apb2_rst 17>;
>> + dmas = <&dma 7>, <&dma 7>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial at 01c28800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28800 0x400>;
>> + interrupts = <0 2 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 18>;
>> + resets = <&apb2_rst 18>;
>> + dmas = <&dma 8>, <&dma 8>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial at 01c28c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28c00 0x400>;
>> + interrupts = <0 3 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 19>;
>> + resets = <&apb2_rst 19>;
>> + dmas = <&dma 9>, <&dma 9>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial at 01c29000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29000 0x400>;
>> + interrupts = <0 4 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 20>;
>> + resets = <&apb2_rst 20>;
>> + dmas = <&dma 10>, <&dma 10>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart5: serial at 01c29400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29400 0x400>;
>> + interrupts = <0 5 4>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 21>;
>> + resets = <&apb2_rst 21>;
>> + dmas = <&dma 22>, <&dma 22>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + i2c0: i2c at 01c2ac00 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2ac00 0x400>;
>> + interrupts = <0 6 4>;
>> + clocks = <&apb2_gates 0>;
>> + resets = <&apb2_rst 0>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c1: i2c at 01c2b000 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b000 0x400>;
>> + interrupts = <0 7 4>;
>> + clocks = <&apb2_gates 1>;
>> + resets = <&apb2_rst 1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c2: i2c at 01c2b400 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b400 0x400>;
>> + interrupts = <0 8 4>;
>> + clocks = <&apb2_gates 2>;
>> + resets = <&apb2_rst 2>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c3: i2c at 01c2b800 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b800 0x400>;
>> + interrupts = <0 9 4>;
>> + clocks = <&apb2_gates 3>;
>> + resets = <&apb2_rst 3>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + gmac: ethernet at 01c30000 {
>> + compatible = "allwinner,sun7i-a20-gmac";
>> + reg = <0x01c30000 0x1054>;
>> + interrupts = <0 82 4>;
>> + interrupt-names = "macirq";
>> + clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
>> + clock-names = "stmmaceth", "allwinner_gmac_tx";
>> + resets = <&ahb1_rst 17>;
>> + reset-names = "stmmaceth";
>> + snps,pbl = <2>;
>> + snps,fixed-burst;
>> + snps,force_sf_dma_mode;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + timer at 01c60000 {
>> + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
>> + reg = <0x01c60000 0x1000>;
>> + interrupts = <0 51 4>,
>> + <0 52 4>,
>> + <0 53 4>,
>> + <0 54 4>;
>> + clocks = <&ahb1_gates 19>;
>> + resets = <&ahb1_rst 19>;
>> + };
>> +
>> + spi0: spi at 01c68000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c68000 0x1000>;
>> + interrupts = <0 65 4>;
>> + clocks = <&ahb1_gates 20>, <&spi0_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 23>, <&dma 23>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 20>;
>> + status = "disabled";
>> + };
>> +
>> + spi1: spi at 01c69000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c69000 0x1000>;
>> + interrupts = <0 66 4>;
>> + clocks = <&ahb1_gates 21>, <&spi1_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 24>, <&dma 24>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 21>;
>> + status = "disabled";
>> + };
>> +
>> + spi2: spi at 01c6a000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c6a000 0x1000>;
>> + interrupts = <0 67 4>;
>> + clocks = <&ahb1_gates 22>, <&spi2_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 25>, <&dma 25>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 22>;
>> + status = "disabled";
>> + };
>> +
>> + spi3: spi at 01c6b000 {
>> + compatible = "allwinner,sun6i-a31-spi";
>> + reg = <0x01c6b000 0x1000>;
>> + interrupts = <0 68 4>;
>> + clocks = <&ahb1_gates 23>, <&spi3_clk>;
>> + clock-names = "ahb", "mod";
>> + dmas = <&dma 26>, <&dma 26>;
>> + dma-names = "rx", "tx";
>> + resets = <&ahb1_rst 23>;
>> + status = "disabled";
>> + };
>> +
>> + gic: interrupt-controller at 01c81000 {
>> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
>> + reg = <0x01c81000 0x1000>,
>> + <0x01c82000 0x1000>,
>> + <0x01c84000 0x2000>,
>> + <0x01c86000 0x2000>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + interrupts = <1 9 0xf04>;
>> + };
>> +
>> + rtc: rtc at 01f00000 {
>> + compatible = "allwinner,sun6i-a31-rtc";
>> + reg = <0x01f00000 0x54>;
>> + interrupts = <0 40 4>, <0 41 4>;
>> + };
>> +
>> + nmi_intc: interrupt-controller at 01f00c0c {
>> + compatible = "allwinner,sun6i-a31-sc-nmi";
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + reg = <0x01f00c0c 0x38>;
>> + interrupts = <0 32 4>;
>> + };
>> +
>> + prcm at 01f01400 {
>> + compatible = "allwinner,sun6i-a31-prcm";
>> + reg = <0x01f01400 0x200>;
>> +
>> + ar100: ar100_clk {
>> + compatible = "allwinner,sun6i-a31-ar100-clk";
>> + #clock-cells = <0>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
>> + clock-output-names = "ar100";
>> + };
>> +
>> + ahb0: ahb0_clk {
>> + compatible = "fixed-factor-clock";
>> + #clock-cells = <0>;
>> + clock-div = <1>;
>> + clock-mult = <1>;
>> + clocks = <&ar100>;
>> + clock-output-names = "ahb0";
>> + };
>> +
>> + apb0: apb0_clk {
>> + compatible = "allwinner,sun6i-a31-apb0-clk";
>> + #clock-cells = <0>;
>> + clocks = <&ahb0>;
>> + clock-output-names = "apb0";
>> + };
>> +
>> + apb0_gates: apb0_gates_clk {
>> + compatible = "allwinner,sun6i-a31-apb0-gates-clk";
>> + #clock-cells = <1>;
>> + clocks = <&apb0>;
>> + clock-output-names = "apb0_pio", "apb0_ir",
>> + "apb0_timer", "apb0_p2wi",
>> + "apb0_uart", "apb0_1wire",
>> + "apb0_i2c";
>> + };
>> +
>> + ir_clk: ir_clk {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ir-clk";
>> + clocks = <&osc32k>, <&osc24M>;
>> + clock-output-names = "ir";
>> + };
>
> This is yet to be agreed on....
Ack, copy / paste error, will drop.
>
>> +
>> + apb0_rst: apb0_rst {
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + #reset-cells = <1>;
>> + };
>> + };
>> +
>> + cpucfg at 01f01c00 {
>> + compatible = "allwinner,sun6i-a31-cpuconfig";
>> + reg = <0x01f01c00 0x300>;
>> + };
>> +
>> + ir at 01f02000 {
>> + compatible = "allwinner,sun5i-a13-ir";
>> + clocks = <&apb0_gates 1>, <&ir_clk>;
>> + clock-names = "apb", "ir";
>> + resets = <&apb0_rst 1>;
>> + interrupts = <0 37 4>;
>> + reg = <0x01f02000 0x40>;
>> + status = "disabled";
>> + };
>> +
>> + r_pio: pinctrl at 01f02c00 {
>> + compatible = "allwinner,sun6i-a31-r-pinctrl";
>> + reg = <0x01f02c00 0x400>;
>> + interrupts = <0 45 4>,
>> + <0 46 4>;
>> + clocks = <&apb0_gates 0>;
>> + resets = <&apb0_rst 0>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + ir_pins_a: ir at 0 {
>> + allwinner,pins = "PL4";
>> + allwinner,function = "s_ir";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> + };
>> +};
>> --
>> 2.1.0
>>
>
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
2014-11-25 18:21 ` Maxime Ripard
@ 2014-11-26 8:58 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 8:58 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Hi,
On 11/25/2014 07:21 PM, Maxime Ripard wrote:
> On Sun, Nov 23, 2014 at 01:54:43PM +0100, Hans de Goede wrote:
>> The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
>> rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
>> controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
>>
>> http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html
>>
>> Note it has no sdcard slot and therefore can only be fel booted.
>
> Thanks a lot for working on this!
>
> I also bought another board with an A31s, but it ended up having
> neither USB OTG or MMC, which rendered it pretty useless.
Are you sure ? The cs908 also does not have an otg connector,
as said it has 2 usb-a receptacles, with the following usb "routing":
usb0 (otg): usb-a receptacle 1 (labeled 1 on the box, 0 on the print)
usb1 (ehci): routed to internal wifi
usb2 (ehci): usb-a receptacle 2 (labeled 2 on both the box and the print)
I'm using fel mode with an usb-a <-> usb-a cable connected to usb0 on
the cs908. The cs908 has no fel button, so I've hooked up the serial console,
and then keep 2 pressed on the serial console while inserting the usb-a into
the PC (which will also power the board). boot0 from the nand will then jump
into fel mode when it sees the 2 keypress.
This was an interesting exercise to confirm that everything on the A31s just
works with A31 code, but now that is confirms A31s devices are not all that
interesting anymore :)
> I wonder wether to put URL in the commit log is the right thing
> though. It's most likely to be dead in a very near future. The cover
> letter would be a better fit for that.
Ok, I'll drop it from the commit message.
Regards,
Hans
>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>> arch/arm/boot/dts/Makefile | 3 +-
>> arch/arm/boot/dts/sun6i-a31s-cs908.dts | 109 +++++++++++++++++++++++++++++++++
>> 2 files changed, 111 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/boot/dts/sun6i-a31s-cs908.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 8ebfa76..0c0201c 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -434,7 +434,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
>> sun6i-a31-app4-evb1.dtb \
>> sun6i-a31-colombus.dtb \
>> sun6i-a31-hummingbird.dtb \
>> - sun6i-a31-m9.dtb
>> + sun6i-a31-m9.dtb \
>> + sun6i-a31s-cs908.dtb
>> dtb-$(CONFIG_MACH_SUN7I) += \
>> sun7i-a20-bananapi.dtb \
>> sun7i-a20-cubieboard2.dtb \
>> diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
>> new file mode 100644
>> index 0000000..48d3a70
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
>> @@ -0,0 +1,109 @@
>> +/*
>> + * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public
>> + * License along with this library; if not, write to the Free
>> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>
> s/library/file/
>
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +/include/ "sun6i-a31s.dtsi"
>> +
>> +/ {
>> + model = "CSQ CS908 top set box";
>
> Shouldn't it be Set Top Box instead?
>
>> + compatible = "csq,cs908", "allwinner,sun6i-a31s";
>> +
>> + chosen {
>> + bootargs = "earlyprintk console=ttyS0,115200";
>> + };
>> +
>> + soc@01c00000 {
>> + usbphy: phy@01c19400 {
>> + status = "okay";
>> + };
>> +
>> + ehci0: usb@01c1a000 {
>> + status = "okay";
>> + };
>> +
>> + ehci1: usb@01c1b000 {
>> + status = "okay";
>> + };
>> +
>> + ohci1: usb@01c1b400 {
>> + status = "okay";
>> + };
>> +
>> + pio: pinctrl@01c20800 {
>> + usb1_vbus_pin_csq908: usb1_vbus_pin@0 {
>> + allwinner,pins = "PC27";
>> + allwinner,function = "gpio_out";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> +
>> + uart0: serial@01c28000 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart0_pins_a>;
>> + status = "okay";
>> + };
>> +
>> + gmac: ethernet@01c30000 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gmac_pins_mii_a>;
>> + phy = <&phy1>;
>> + phy-mode = "mii";
>> + status = "okay";
>> +
>> + phy1: ethernet-phy@1 {
>> + reg = <1>;
>> + };
>> + };
>> +
>> + ir@01f02000 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&ir_pins_a>;
>> + status = "okay";
>> + };
>> + };
>> +};
>> --
>> 2.1.0
>>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
@ 2014-11-26 8:58 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 8:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 11/25/2014 07:21 PM, Maxime Ripard wrote:
> On Sun, Nov 23, 2014 at 01:54:43PM +0100, Hans de Goede wrote:
>> The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
>> rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
>> controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
>>
>> http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html
>>
>> Note it has no sdcard slot and therefore can only be fel booted.
>
> Thanks a lot for working on this!
>
> I also bought another board with an A31s, but it ended up having
> neither USB OTG or MMC, which rendered it pretty useless.
Are you sure ? The cs908 also does not have an otg connector,
as said it has 2 usb-a receptacles, with the following usb "routing":
usb0 (otg): usb-a receptacle 1 (labeled 1 on the box, 0 on the print)
usb1 (ehci): routed to internal wifi
usb2 (ehci): usb-a receptacle 2 (labeled 2 on both the box and the print)
I'm using fel mode with an usb-a <-> usb-a cable connected to usb0 on
the cs908. The cs908 has no fel button, so I've hooked up the serial console,
and then keep 2 pressed on the serial console while inserting the usb-a into
the PC (which will also power the board). boot0 from the nand will then jump
into fel mode when it sees the 2 keypress.
This was an interesting exercise to confirm that everything on the A31s just
works with A31 code, but now that is confirms A31s devices are not all that
interesting anymore :)
> I wonder wether to put URL in the commit log is the right thing
> though. It's most likely to be dead in a very near future. The cover
> letter would be a better fit for that.
Ok, I'll drop it from the commit message.
Regards,
Hans
>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> arch/arm/boot/dts/Makefile | 3 +-
>> arch/arm/boot/dts/sun6i-a31s-cs908.dts | 109 +++++++++++++++++++++++++++++++++
>> 2 files changed, 111 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/boot/dts/sun6i-a31s-cs908.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 8ebfa76..0c0201c 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -434,7 +434,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
>> sun6i-a31-app4-evb1.dtb \
>> sun6i-a31-colombus.dtb \
>> sun6i-a31-hummingbird.dtb \
>> - sun6i-a31-m9.dtb
>> + sun6i-a31-m9.dtb \
>> + sun6i-a31s-cs908.dtb
>> dtb-$(CONFIG_MACH_SUN7I) += \
>> sun7i-a20-bananapi.dtb \
>> sun7i-a20-cubieboard2.dtb \
>> diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
>> new file mode 100644
>> index 0000000..48d3a70
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
>> @@ -0,0 +1,109 @@
>> +/*
>> + * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public
>> + * License along with this library; if not, write to the Free
>> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>
> s/library/file/
>
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +/include/ "sun6i-a31s.dtsi"
>> +
>> +/ {
>> + model = "CSQ CS908 top set box";
>
> Shouldn't it be Set Top Box instead?
>
>> + compatible = "csq,cs908", "allwinner,sun6i-a31s";
>> +
>> + chosen {
>> + bootargs = "earlyprintk console=ttyS0,115200";
>> + };
>> +
>> + soc at 01c00000 {
>> + usbphy: phy at 01c19400 {
>> + status = "okay";
>> + };
>> +
>> + ehci0: usb at 01c1a000 {
>> + status = "okay";
>> + };
>> +
>> + ehci1: usb at 01c1b000 {
>> + status = "okay";
>> + };
>> +
>> + ohci1: usb at 01c1b400 {
>> + status = "okay";
>> + };
>> +
>> + pio: pinctrl at 01c20800 {
>> + usb1_vbus_pin_csq908: usb1_vbus_pin at 0 {
>> + allwinner,pins = "PC27";
>> + allwinner,function = "gpio_out";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <0>;
>> + };
>> + };
>> +
>> + uart0: serial at 01c28000 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart0_pins_a>;
>> + status = "okay";
>> + };
>> +
>> + gmac: ethernet at 01c30000 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gmac_pins_mii_a>;
>> + phy = <&phy1>;
>> + phy-mode = "mii";
>> + status = "okay";
>> +
>> + phy1: ethernet-phy at 1 {
>> + reg = <1>;
>> + };
>> + };
>> +
>> + ir at 01f02000 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&ir_pins_a>;
>> + status = "okay";
>> + };
>> + };
>> +};
>> --
>> 2.1.0
>>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
2014-11-25 23:45 ` Chen-Yu Tsai
@ 2014-11-26 9:05 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 9:05 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi
Hi,
On 11/26/2014 12:45 AM, Chen-Yu Tsai wrote:
> On Wed, Nov 26, 2014 at 2:18 AM, Maxime Ripard
<snip>
>>> + ahb1_gates: clk@01c20060 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
>>> + reg = <0x01c20060 0x8>;
>>> + clocks = <&ahb1>;
>>> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
>>> + "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
>>> + "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
>>> + "ahb1_nand0", "ahb1_sdram",
>>> + "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
>>> + "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
>>> + "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
>>> + "ahb1_ehci1", "ahb1_ohci0",
>>> + "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
>>> + "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
>>> + "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
>>> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
>>> + "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
>>> + "ahb1_drc0", "ahb1_drc1";
>>> + };
>>
>> Are the gates really identical?
>>
>> As in not even stripped down?
>
> According to the user manuals, the AHB1 gates on the A31s don't have
> GMAC (or EMAC in the manual) and MIPI DSI listed. Though it seems
> a lot of A31s hardware out there actually use GMAC.
Hmm, interesting I was focussing on the ohci2 gate when comparing them as
the ohci2 is not listed in the pinmux.
The GMAC clock gate definitely actually is there, as I've an A31s based board
with a working GMAC.
Also Allwinner has confirmed to me that the A31 and A31s are the same die, so
there is no reason to differentiate between the 2 at this level. Either we do
no differentiation at all, or only at the pinmux level to reflect that certain
pins are simply just not there.
My vote goes to differentiating at the pinmux level.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
@ 2014-11-26 9:05 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-26 9:05 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 11/26/2014 12:45 AM, Chen-Yu Tsai wrote:
> On Wed, Nov 26, 2014 at 2:18 AM, Maxime Ripard
<snip>
>>> + ahb1_gates: clk at 01c20060 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
>>> + reg = <0x01c20060 0x8>;
>>> + clocks = <&ahb1>;
>>> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
>>> + "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
>>> + "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
>>> + "ahb1_nand0", "ahb1_sdram",
>>> + "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
>>> + "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
>>> + "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
>>> + "ahb1_ehci1", "ahb1_ohci0",
>>> + "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
>>> + "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
>>> + "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
>>> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
>>> + "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
>>> + "ahb1_drc0", "ahb1_drc1";
>>> + };
>>
>> Are the gates really identical?
>>
>> As in not even stripped down?
>
> According to the user manuals, the AHB1 gates on the A31s don't have
> GMAC (or EMAC in the manual) and MIPI DSI listed. Though it seems
> a lot of A31s hardware out there actually use GMAC.
Hmm, interesting I was focussing on the ohci2 gate when comparing them as
the ohci2 is not listed in the pinmux.
The GMAC clock gate definitely actually is there, as I've an A31s based board
with a working GMAC.
Also Allwinner has confirmed to me that the A31 and A31s are the same die, so
there is no reason to differentiate between the 2 at this level. Either we do
no differentiation at all, or only at the pinmux level to reflect that certain
pins are simply just not there.
My vote goes to differentiating at the pinmux level.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
2014-11-26 9:05 ` Hans de Goede
@ 2014-11-26 9:39 ` Chen-Yu Tsai
-1 siblings, 0 replies; 52+ messages in thread
From: Chen-Yu Tsai @ 2014-11-26 9:39 UTC (permalink / raw)
To: Hans de Goede
Cc: Maxime Ripard, Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi
Hi,
On Wed, Nov 26, 2014 at 5:05 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
> Hi,
>
> On 11/26/2014 12:45 AM, Chen-Yu Tsai wrote:
>>
>> On Wed, Nov 26, 2014 at 2:18 AM, Maxime Ripard
>
>
> <snip>
>
>
>>>> + ahb1_gates: clk@01c20060 {
>>>> + #clock-cells = <1>;
>>>> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
>>>> + reg = <0x01c20060 0x8>;
>>>> + clocks = <&ahb1>;
>>>> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
>>>> + "ahb1_dma", "ahb1_mmc0",
>>>> "ahb1_mmc1",
>>>> + "ahb1_mmc2", "ahb1_mmc3",
>>>> "ahb1_nand1",
>>>> + "ahb1_nand0", "ahb1_sdram",
>>>> + "ahb1_gmac", "ahb1_ts",
>>>> "ahb1_hstimer",
>>>> + "ahb1_spi0", "ahb1_spi1",
>>>> "ahb1_spi2",
>>>> + "ahb1_spi3", "ahb1_otg",
>>>> "ahb1_ehci0",
>>>> + "ahb1_ehci1", "ahb1_ohci0",
>>>> + "ahb1_ohci1", "ahb1_ohci2",
>>>> "ahb1_ve",
>>>> + "ahb1_lcd0", "ahb1_lcd1",
>>>> "ahb1_csi",
>>>> + "ahb1_hdmi", "ahb1_de0",
>>>> "ahb1_de1",
>>>> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
>>>> + "ahb1_gpu", "ahb1_deu0",
>>>> "ahb1_deu1",
>>>> + "ahb1_drc0", "ahb1_drc1";
>>>> + };
>>>
>>>
>>> Are the gates really identical?
>>>
>>> As in not even stripped down?
>>
>>
>> According to the user manuals, the AHB1 gates on the A31s don't have
>> GMAC (or EMAC in the manual) and MIPI DSI listed. Though it seems
>> a lot of A31s hardware out there actually use GMAC.
>
>
> Hmm, interesting I was focussing on the ohci2 gate when comparing them as
> the ohci2 is not listed in the pinmux.
>
> The GMAC clock gate definitely actually is there, as I've an A31s based
> board
> with a working GMAC.
>
> Also Allwinner has confirmed to me that the A31 and A31s are the same die,
> so
> there is no reason to differentiate between the 2 at this level. Either we
> do
> no differentiation at all, or only at the pinmux level to reflect that
> certain
> pins are simply just not there.
>
> My vote goes to differentiating at the pinmux level.
I agree. Since it is confirmed the dies are the same, the hardware
description should be the same as well, except for the external
differences (pinmux). Only downside is a slightly bloated DTB
containing nodes we will never use on the a31s.
IIRC, Allwinner's kernel treats them as the same as well.
ChenYu
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
@ 2014-11-26 9:39 ` Chen-Yu Tsai
0 siblings, 0 replies; 52+ messages in thread
From: Chen-Yu Tsai @ 2014-11-26 9:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Wed, Nov 26, 2014 at 5:05 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 11/26/2014 12:45 AM, Chen-Yu Tsai wrote:
>>
>> On Wed, Nov 26, 2014 at 2:18 AM, Maxime Ripard
>
>
> <snip>
>
>
>>>> + ahb1_gates: clk at 01c20060 {
>>>> + #clock-cells = <1>;
>>>> + compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
>>>> + reg = <0x01c20060 0x8>;
>>>> + clocks = <&ahb1>;
>>>> + clock-output-names = "ahb1_mipidsi", "ahb1_ss",
>>>> + "ahb1_dma", "ahb1_mmc0",
>>>> "ahb1_mmc1",
>>>> + "ahb1_mmc2", "ahb1_mmc3",
>>>> "ahb1_nand1",
>>>> + "ahb1_nand0", "ahb1_sdram",
>>>> + "ahb1_gmac", "ahb1_ts",
>>>> "ahb1_hstimer",
>>>> + "ahb1_spi0", "ahb1_spi1",
>>>> "ahb1_spi2",
>>>> + "ahb1_spi3", "ahb1_otg",
>>>> "ahb1_ehci0",
>>>> + "ahb1_ehci1", "ahb1_ohci0",
>>>> + "ahb1_ohci1", "ahb1_ohci2",
>>>> "ahb1_ve",
>>>> + "ahb1_lcd0", "ahb1_lcd1",
>>>> "ahb1_csi",
>>>> + "ahb1_hdmi", "ahb1_de0",
>>>> "ahb1_de1",
>>>> + "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
>>>> + "ahb1_gpu", "ahb1_deu0",
>>>> "ahb1_deu1",
>>>> + "ahb1_drc0", "ahb1_drc1";
>>>> + };
>>>
>>>
>>> Are the gates really identical?
>>>
>>> As in not even stripped down?
>>
>>
>> According to the user manuals, the AHB1 gates on the A31s don't have
>> GMAC (or EMAC in the manual) and MIPI DSI listed. Though it seems
>> a lot of A31s hardware out there actually use GMAC.
>
>
> Hmm, interesting I was focussing on the ohci2 gate when comparing them as
> the ohci2 is not listed in the pinmux.
>
> The GMAC clock gate definitely actually is there, as I've an A31s based
> board
> with a working GMAC.
>
> Also Allwinner has confirmed to me that the A31 and A31s are the same die,
> so
> there is no reason to differentiate between the 2 at this level. Either we
> do
> no differentiation at all, or only at the pinmux level to reflect that
> certain
> pins are simply just not there.
>
> My vote goes to differentiating at the pinmux level.
I agree. Since it is confirmed the dies are the same, the hardware
description should be the same as well, except for the external
differences (pinmux). Only downside is a slightly bloated DTB
containing nodes we will never use on the a31s.
IIRC, Allwinner's kernel treats them as the same as well.
ChenYu
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 2/5] pinctrl: sun6i: Add A31s pinctrl support
2014-11-26 8:11 ` Hans de Goede
@ 2014-11-26 18:37 ` Maxime Ripard
-1 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-26 18:37 UTC (permalink / raw)
To: Hans de Goede
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 3880 bytes --]
On Wed, Nov 26, 2014 at 09:11:21AM +0100, Hans de Goede wrote:
> Hi,
>
> On 11/25/2014 07:08 PM, Maxime Ripard wrote:
> >On Sun, Nov 23, 2014 at 01:54:40PM +0100, Hans de Goede wrote:
> >>The A31s is a stripped down version of the A31, as such it is missing some
> >>pins and some functions on some pins.
> >>
> >>The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
> >>with the missing pins and functions removed.
> >>
> >>Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
> >>prcm pins are identical between the A31 and the A31s.
> >>
> >>Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >>---
> >> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
> >> drivers/pinctrl/sunxi/Kconfig | 4 +
> >> drivers/pinctrl/sunxi/Makefile | 1 +
> >> drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c | 814 +++++++++++++++++++++
> >> 4 files changed, 820 insertions(+)
> >> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> >>
> >>diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >>index 93ce12e..fdd8046 100644
> >>--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >>+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >>@@ -11,6 +11,7 @@ Required properties:
> >> "allwinner,sun5i-a10s-pinctrl"
> >> "allwinner,sun5i-a13-pinctrl"
> >> "allwinner,sun6i-a31-pinctrl"
> >>+ "allwinner,sun6i-a31s-pinctrl"
> >> "allwinner,sun6i-a31-r-pinctrl"
> >> "allwinner,sun7i-a20-pinctrl"
> >> "allwinner,sun8i-a23-pinctrl"
> >>diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> >>index a5e10f7..6cffe38 100644
> >>--- a/drivers/pinctrl/sunxi/Kconfig
> >>+++ b/drivers/pinctrl/sunxi/Kconfig
> >>@@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
> >> def_bool MACH_SUN6I
> >> select PINCTRL_SUNXI_COMMON
> >>
> >>+config PINCTRL_SUN6I_A31S
> >>+ def_bool MACH_SUN6I
> >>+ select PINCTRL_SUNXI_COMMON
> >>+
> >> config PINCTRL_SUN6I_A31_R
> >> def_bool MACH_SUN6I
> >> depends on RESET_CONTROLLER
> >>diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> >>index e797efb..2f82290 100644
> >>--- a/drivers/pinctrl/sunxi/Makefile
> >>+++ b/drivers/pinctrl/sunxi/Makefile
> >>@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
> >> obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
> >> obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
> >> obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
> >>+obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
> >> obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
> >> obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
> >> obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
> >>diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> >>new file mode 100644
> >>index 0000000..42ee373
> >>--- /dev/null
> >>+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> >>@@ -0,0 +1,814 @@
> >>+/*
> >>+ * Allwinner A31 SoCs pinctrl driver.
> >
> > ^ A31s
> >
>
> Good one.
>
> >>+ *
> >>+ * Copyright (C) 2014 Maxime Ripard
> >>+ *
> >>+ * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> >
> >And I guess your copyright would be more appropriate here.
>
> It is a copy of a file you authored, with some lines removed, so I deliberately left
> this as is.
I'd feel more confortable with at least listing you as the author and
copyright owner, you did more work than I on this one, but it's your
call.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 2/5] pinctrl: sun6i: Add A31s pinctrl support
@ 2014-11-26 18:37 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-26 18:37 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Nov 26, 2014 at 09:11:21AM +0100, Hans de Goede wrote:
> Hi,
>
> On 11/25/2014 07:08 PM, Maxime Ripard wrote:
> >On Sun, Nov 23, 2014 at 01:54:40PM +0100, Hans de Goede wrote:
> >>The A31s is a stripped down version of the A31, as such it is missing some
> >>pins and some functions on some pins.
> >>
> >>The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
> >>with the missing pins and functions removed.
> >>
> >>Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
> >>prcm pins are identical between the A31 and the A31s.
> >>
> >>Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> >>---
> >> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
> >> drivers/pinctrl/sunxi/Kconfig | 4 +
> >> drivers/pinctrl/sunxi/Makefile | 1 +
> >> drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c | 814 +++++++++++++++++++++
> >> 4 files changed, 820 insertions(+)
> >> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> >>
> >>diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >>index 93ce12e..fdd8046 100644
> >>--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >>+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >>@@ -11,6 +11,7 @@ Required properties:
> >> "allwinner,sun5i-a10s-pinctrl"
> >> "allwinner,sun5i-a13-pinctrl"
> >> "allwinner,sun6i-a31-pinctrl"
> >>+ "allwinner,sun6i-a31s-pinctrl"
> >> "allwinner,sun6i-a31-r-pinctrl"
> >> "allwinner,sun7i-a20-pinctrl"
> >> "allwinner,sun8i-a23-pinctrl"
> >>diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> >>index a5e10f7..6cffe38 100644
> >>--- a/drivers/pinctrl/sunxi/Kconfig
> >>+++ b/drivers/pinctrl/sunxi/Kconfig
> >>@@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
> >> def_bool MACH_SUN6I
> >> select PINCTRL_SUNXI_COMMON
> >>
> >>+config PINCTRL_SUN6I_A31S
> >>+ def_bool MACH_SUN6I
> >>+ select PINCTRL_SUNXI_COMMON
> >>+
> >> config PINCTRL_SUN6I_A31_R
> >> def_bool MACH_SUN6I
> >> depends on RESET_CONTROLLER
> >>diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> >>index e797efb..2f82290 100644
> >>--- a/drivers/pinctrl/sunxi/Makefile
> >>+++ b/drivers/pinctrl/sunxi/Makefile
> >>@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
> >> obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
> >> obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
> >> obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
> >>+obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
> >> obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
> >> obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
> >> obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
> >>diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> >>new file mode 100644
> >>index 0000000..42ee373
> >>--- /dev/null
> >>+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
> >>@@ -0,0 +1,814 @@
> >>+/*
> >>+ * Allwinner A31 SoCs pinctrl driver.
> >
> > ^ A31s
> >
>
> Good one.
>
> >>+ *
> >>+ * Copyright (C) 2014 Maxime Ripard
> >>+ *
> >>+ * Maxime Ripard <maxime.ripard@free-electrons.com>
> >
> >And I guess your copyright would be more appropriate here.
>
> It is a copy of a file you authored, with some lines removed, so I deliberately left
> this as is.
I'd feel more confortable with at least listing you as the author and
copyright owner, you did more work than I on this one, but it's your
call.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
2014-11-26 8:30 ` Hans de Goede
@ 2014-11-26 18:44 ` Maxime Ripard
-1 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-26 18:44 UTC (permalink / raw)
To: Hans de Goede
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 5124 bytes --]
On Wed, Nov 26, 2014 at 09:30:40AM +0100, Hans de Goede wrote:
> Hi,
>
> On 11/25/2014 07:04 PM, Maxime Ripard wrote:
> >Hi,
> >
> >On Sun, Nov 23, 2014 at 01:54:39PM +0100, Hans de Goede wrote:
> >>While working on pinctrl for the A31s, I noticed that function 4 of
> >>PA15 - PA18 was missing, add these.
> >>
> >>I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
> >>be PB4 & PB5, fix this as well.
> >>
> >>Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >>---
> >> drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
> >> 1 file changed, 7 insertions(+), 2 deletions(-)
> >>
> >>diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> >>index a2b4b85..fb19e15 100644
> >>--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> >>+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> >>@@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
> >>+ SUNXI_FUNCTION(0x4, "clk_a_out"),
> >
> >It's called clk_out_a on the A20, I'd rather stick with the same
> >scheme here.
>
> Will fix.
>
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
> >>+ SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
> >>+ SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
> >>+ SUNXI_FUNCTION(0x4, "clk_b_out"),
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >>@@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
> >>+ SUNXI_FUNCTION(0x4, "clk_c_out"),
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >>@@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
> >> SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
> >>+ SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
> >> SUNXI_FUNCTION(0x3, "uart3"), /* TX */
> >>- SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> >>+ SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
> >> SUNXI_FUNCTION(0x3, "uart3"), /* RX */
> >>- SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
> >
> >Where did you get that info from? The datasheet still reports that
> >information.
>
> I assume with the datasheet you mean "A31 User Manual V1.20.pdf", which
> was last updated on September 20, 2013. I did not check that one, now I
> see where the original pinctrl code from.
>
> So I've done some more digging:
>
> "A31 Datasheet - v1.00 (2012-12-24).pdf" also has twi3 sck / sda on pin
> PB5 / PB6 like the current pinctrl code.
>
> But "A31 Datasheet V1.40.pdf" which has the following in its revision log:
> "1.4 Dec 10,2013 Modify Pin Description"
>
> Moves them to PB4 / PB5 and that is where I got this from (and was the only
> place I initially looked), I think that this is an intentional change, and
> that PB4 / PB5 are the correct pins.
Funny, I was looking at the A31 datasheet v1.4 from 10/12/2013 that is
in the allwinner's repo, and that's where I got this from (or some
earlier version of it)
https://github.com/allwinner-zh/documents/blob/master/A31/A31%20datasheet%20V1.4%2020131210.pdf
Something's weird here :)
> I will ask Allwinner which is correct, so that we know for sure.
Yep, I saw that, thanks for clearing that up.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
@ 2014-11-26 18:44 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-11-26 18:44 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Nov 26, 2014 at 09:30:40AM +0100, Hans de Goede wrote:
> Hi,
>
> On 11/25/2014 07:04 PM, Maxime Ripard wrote:
> >Hi,
> >
> >On Sun, Nov 23, 2014 at 01:54:39PM +0100, Hans de Goede wrote:
> >>While working on pinctrl for the A31s, I noticed that function 4 of
> >>PA15 - PA18 was missing, add these.
> >>
> >>I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
> >>be PB4 & PB5, fix this as well.
> >>
> >>Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> >>---
> >> drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
> >> 1 file changed, 7 insertions(+), 2 deletions(-)
> >>
> >>diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> >>index a2b4b85..fb19e15 100644
> >>--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> >>+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
> >>@@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
> >>+ SUNXI_FUNCTION(0x4, "clk_a_out"),
> >
> >It's called clk_out_a on the A20, I'd rather stick with the same
> >scheme here.
>
> Will fix.
>
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
> >>+ SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
> >>+ SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
> >>+ SUNXI_FUNCTION(0x4, "clk_b_out"),
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >>@@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
> >> SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
> >>+ SUNXI_FUNCTION(0x4, "clk_c_out"),
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >>@@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
> >> SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
> >>+ SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
> >> SUNXI_FUNCTION(0x3, "uart3"), /* TX */
> >>- SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
> >>+ SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
> >> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
> >> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> >> SUNXI_FUNCTION(0x0, "gpio_in"),
> >> SUNXI_FUNCTION(0x1, "gpio_out"),
> >> SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
> >> SUNXI_FUNCTION(0x3, "uart3"), /* RX */
> >>- SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
> >
> >Where did you get that info from? The datasheet still reports that
> >information.
>
> I assume with the datasheet you mean "A31 User Manual V1.20.pdf", which
> was last updated on September 20, 2013. I did not check that one, now I
> see where the original pinctrl code from.
>
> So I've done some more digging:
>
> "A31 Datasheet - v1.00 (2012-12-24).pdf" also has twi3 sck / sda on pin
> PB5 / PB6 like the current pinctrl code.
>
> But "A31 Datasheet V1.40.pdf" which has the following in its revision log:
> "1.4 Dec 10,2013 Modify Pin Description"
>
> Moves them to PB4 / PB5 and that is where I got this from (and was the only
> place I initially looked), I think that this is an intentional change, and
> that PB4 / PB5 are the correct pins.
Funny, I was looking at the A31 datasheet v1.4 from 10/12/2013 that is
in the allwinner's repo, and that's where I got this from (or some
earlier version of it)
https://github.com/allwinner-zh/documents/blob/master/A31/A31%20datasheet%20V1.4%2020131210.pdf
Something's weird here :)
> I will ask Allwinner which is correct, so that we know for sure.
Yep, I saw that, thanks for clearing that up.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
2014-11-26 18:44 ` Maxime Ripard
@ 2014-11-27 8:28 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-27 8:28 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Hi,
On 11/26/2014 07:44 PM, Maxime Ripard wrote:
> On Wed, Nov 26, 2014 at 09:30:40AM +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 11/25/2014 07:04 PM, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Sun, Nov 23, 2014 at 01:54:39PM +0100, Hans de Goede wrote:
>>>> While working on pinctrl for the A31s, I noticed that function 4 of
>>>> PA15 - PA18 was missing, add these.
>>>>
>>>> I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
>>>> be PB4 & PB5, fix this as well.
>>>>
>>>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>> ---
>>>> drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
>>>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>>>> index a2b4b85..fb19e15 100644
>>>> --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>>>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>>>> @@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
>>>> + SUNXI_FUNCTION(0x4, "clk_a_out"),
>>>
>>> It's called clk_out_a on the A20, I'd rather stick with the same
>>> scheme here.
>>
>> Will fix.
>>
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
>>>> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
>>>> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
>>>> + SUNXI_FUNCTION(0x4, "clk_b_out"),
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> @@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
>>>> + SUNXI_FUNCTION(0x4, "clk_c_out"),
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> @@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
>>>> SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
>>>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
>>>> SUNXI_FUNCTION(0x3, "uart3"), /* TX */
>>>> - SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>>>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
>>>> SUNXI_FUNCTION(0x3, "uart3"), /* RX */
>>>> - SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>>>
>>> Where did you get that info from? The datasheet still reports that
>>> information.
>>
>> I assume with the datasheet you mean "A31 User Manual V1.20.pdf", which
>> was last updated on September 20, 2013. I did not check that one, now I
>> see where the original pinctrl code from.
>>
>> So I've done some more digging:
>>
>> "A31 Datasheet - v1.00 (2012-12-24).pdf" also has twi3 sck / sda on pin
>> PB5 / PB6 like the current pinctrl code.
>>
>> But "A31 Datasheet V1.40.pdf" which has the following in its revision log:
>> "1.4 Dec 10,2013 Modify Pin Description"
>>
>> Moves them to PB4 / PB5 and that is where I got this from (and was the only
>> place I initially looked), I think that this is an intentional change, and
>> that PB4 / PB5 are the correct pins.
>
> Funny, I was looking at the A31 datasheet v1.4 from 10/12/2013 that is
> in the allwinner's repo, and that's where I got this from (or some
> earlier version of it)
>
> https://github.com/allwinner-zh/documents/blob/master/A31/A31%20datasheet%20V1.4%2020131210.pdf
>
> Something's weird here :)
Oh, on double checking my "A31 Datasheet V1.40.pdf" also has the ins at PB5/6, only the
A31s data sheet V1.4 has them at PB4/5.
>> I will ask Allwinner which is correct, so that we know for sure.
>
> Yep, I saw that, thanks for clearing that up.
So lets wait for their answer.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing
@ 2014-11-27 8:28 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-27 8:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 11/26/2014 07:44 PM, Maxime Ripard wrote:
> On Wed, Nov 26, 2014 at 09:30:40AM +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 11/25/2014 07:04 PM, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Sun, Nov 23, 2014 at 01:54:39PM +0100, Hans de Goede wrote:
>>>> While working on pinctrl for the A31s, I noticed that function 4 of
>>>> PA15 - PA18 was missing, add these.
>>>>
>>>> I also noticed that i2c3 sck / sda got assigned to PB5 & PB6, this should
>>>> be PB4 & PB5, fix this as well.
>>>>
>>>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>>>> ---
>>>> drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 9 +++++++--
>>>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>>>> index a2b4b85..fb19e15 100644
>>>> --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>>>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
>>>> @@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
>>>> + SUNXI_FUNCTION(0x4, "clk_a_out"),
>>>
>>> It's called clk_out_a on the A20, I'd rather stick with the same
>>> scheme here.
>>
>> Will fix.
>>
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
>>>> + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
>>>> + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
>>>> + SUNXI_FUNCTION(0x4, "clk_b_out"),
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> @@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
>>>> SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
>>>> + SUNXI_FUNCTION(0x4, "clk_c_out"),
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> @@ -242,20 +247,20 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
>>>> SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
>>>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
>>>> SUNXI_FUNCTION(0x3, "uart3"), /* TX */
>>>> - SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
>>>> + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>>>> SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
>>>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
>>>> SUNXI_FUNCTION(0x0, "gpio_in"),
>>>> SUNXI_FUNCTION(0x1, "gpio_out"),
>>>> SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
>>>> SUNXI_FUNCTION(0x3, "uart3"), /* RX */
>>>> - SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
>>>
>>> Where did you get that info from? The datasheet still reports that
>>> information.
>>
>> I assume with the datasheet you mean "A31 User Manual V1.20.pdf", which
>> was last updated on September 20, 2013. I did not check that one, now I
>> see where the original pinctrl code from.
>>
>> So I've done some more digging:
>>
>> "A31 Datasheet - v1.00 (2012-12-24).pdf" also has twi3 sck / sda on pin
>> PB5 / PB6 like the current pinctrl code.
>>
>> But "A31 Datasheet V1.40.pdf" which has the following in its revision log:
>> "1.4 Dec 10,2013 Modify Pin Description"
>>
>> Moves them to PB4 / PB5 and that is where I got this from (and was the only
>> place I initially looked), I think that this is an intentional change, and
>> that PB4 / PB5 are the correct pins.
>
> Funny, I was looking at the A31 datasheet v1.4 from 10/12/2013 that is
> in the allwinner's repo, and that's where I got this from (or some
> earlier version of it)
>
> https://github.com/allwinner-zh/documents/blob/master/A31/A31%20datasheet%20V1.4%2020131210.pdf
>
> Something's weird here :)
Oh, on double checking my "A31 Datasheet V1.40.pdf" also has the ins at PB5/6, only the
A31s data sheet V1.4 has them at PB4/5.
>> I will ask Allwinner which is correct, so that we know for sure.
>
> Yep, I saw that, thanks for clearing that up.
So lets wait for their answer.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 0/5] sun6i: Add A31s (pinctrl) support
2014-11-23 12:54 ` Hans de Goede
@ 2014-11-28 12:01 ` Linus Walleij
-1 siblings, 0 replies; 52+ messages in thread
From: Linus Walleij @ 2014-11-28 12:01 UTC (permalink / raw)
To: Hans de Goede
Cc: Maxime Ripard, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-sunxi
On Sun, Nov 23, 2014 at 1:54 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
> I'm not sure if sunxi pinctrl patches go through Maxime's tree or Linus' tree,
> so I'll leave figuring out who takes what patches to you two.
The changes in drivers/pinctrl and arch/* are usually orthogonal
(just Kconfig symbols and DTS changes, no cross calls or header
files that break compilation etc) and then they can be
applied orthogonally. I just put the pinctrl patch in my tree and
the rest in the platform tree.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 0/5] sun6i: Add A31s (pinctrl) support
@ 2014-11-28 12:01 ` Linus Walleij
0 siblings, 0 replies; 52+ messages in thread
From: Linus Walleij @ 2014-11-28 12:01 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Nov 23, 2014 at 1:54 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> I'm not sure if sunxi pinctrl patches go through Maxime's tree or Linus' tree,
> so I'll leave figuring out who takes what patches to you two.
The changes in drivers/pinctrl and arch/* are usually orthogonal
(just Kconfig symbols and DTS changes, no cross calls or header
files that break compilation etc) and then they can be
applied orthogonally. I just put the pinctrl patch in my tree and
the rest in the platform tree.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 0/5] sun6i: Add A31s (pinctrl) support
2014-11-28 12:01 ` Linus Walleij
@ 2014-11-28 12:59 ` Hans de Goede
-1 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-28 12:59 UTC (permalink / raw)
To: Linus Walleij
Cc: Maxime Ripard, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-sunxi
Hi,
On 11/28/2014 01:01 PM, Linus Walleij wrote:
> On Sun, Nov 23, 2014 at 1:54 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
>
>> I'm not sure if sunxi pinctrl patches go through Maxime's tree or Linus' tree,
>> so I'll leave figuring out who takes what patches to you two.
>
> The changes in drivers/pinctrl and arch/* are usually orthogonal
> (just Kconfig symbols and DTS changes, no cross calls or header
> files that break compilation etc) and then they can be
> applied orthogonally. I just put the pinctrl patch in my tree and
> the rest in the platform tree.
Ok, note in case it was not clear there will be a v2, so please do not merge v1.
Thanks,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 0/5] sun6i: Add A31s (pinctrl) support
@ 2014-11-28 12:59 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-11-28 12:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 11/28/2014 01:01 PM, Linus Walleij wrote:
> On Sun, Nov 23, 2014 at 1:54 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>
>> I'm not sure if sunxi pinctrl patches go through Maxime's tree or Linus' tree,
>> so I'll leave figuring out who takes what patches to you two.
>
> The changes in drivers/pinctrl and arch/* are usually orthogonal
> (just Kconfig symbols and DTS changes, no cross calls or header
> files that break compilation etc) and then they can be
> applied orthogonally. I just put the pinctrl patch in my tree and
> the rest in the platform tree.
Ok, note in case it was not clear there will be a v2, so please do not merge v1.
Thanks,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
2014-11-26 9:39 ` Chen-Yu Tsai
@ 2014-12-04 14:13 ` Maxime Ripard
-1 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-12-04 14:13 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Hans de Goede, Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 1580 bytes --]
On Wed, Nov 26, 2014 at 05:39:31PM +0800, Chen-Yu Tsai wrote:
> >>> Are the gates really identical?
> >>>
> >>> As in not even stripped down?
> >>
> >>
> >> According to the user manuals, the AHB1 gates on the A31s don't have
> >> GMAC (or EMAC in the manual) and MIPI DSI listed. Though it seems
> >> a lot of A31s hardware out there actually use GMAC.
> >
> >
> > Hmm, interesting I was focussing on the ohci2 gate when comparing them as
> > the ohci2 is not listed in the pinmux.
> >
> > The GMAC clock gate definitely actually is there, as I've an A31s based
> > board
> > with a working GMAC.
> >
> > Also Allwinner has confirmed to me that the A31 and A31s are the same die,
> > so
> > there is no reason to differentiate between the 2 at this level. Either we
> > do
> > no differentiation at all, or only at the pinmux level to reflect that
> > certain
> > pins are simply just not there.
> >
> > My vote goes to differentiating at the pinmux level.
>
> I agree. Since it is confirmed the dies are the same, the hardware
> description should be the same as well, except for the external
> differences (pinmux). Only downside is a slightly bloated DTB
> containing nodes we will never use on the a31s.
Or we can have a sun6i.dtsi that lists all the hardware, and have the
sun6i-a31.dtsi and sun6i-a31s.dtsi that only define the various
pinmuxes.
That way we would avoid duplication, especially if they are identical,
while reducing the useless bloat too.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi
@ 2014-12-04 14:13 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-12-04 14:13 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Nov 26, 2014 at 05:39:31PM +0800, Chen-Yu Tsai wrote:
> >>> Are the gates really identical?
> >>>
> >>> As in not even stripped down?
> >>
> >>
> >> According to the user manuals, the AHB1 gates on the A31s don't have
> >> GMAC (or EMAC in the manual) and MIPI DSI listed. Though it seems
> >> a lot of A31s hardware out there actually use GMAC.
> >
> >
> > Hmm, interesting I was focussing on the ohci2 gate when comparing them as
> > the ohci2 is not listed in the pinmux.
> >
> > The GMAC clock gate definitely actually is there, as I've an A31s based
> > board
> > with a working GMAC.
> >
> > Also Allwinner has confirmed to me that the A31 and A31s are the same die,
> > so
> > there is no reason to differentiate between the 2 at this level. Either we
> > do
> > no differentiation at all, or only at the pinmux level to reflect that
> > certain
> > pins are simply just not there.
> >
> > My vote goes to differentiating at the pinmux level.
>
> I agree. Since it is confirmed the dies are the same, the hardware
> description should be the same as well, except for the external
> differences (pinmux). Only downside is a slightly bloated DTB
> containing nodes we will never use on the a31s.
Or we can have a sun6i.dtsi that lists all the hardware, and have the
sun6i-a31.dtsi and sun6i-a31s.dtsi that only define the various
pinmuxes.
That way we would avoid duplication, especially if they are identical,
while reducing the useless bloat too.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
2014-11-26 8:58 ` Hans de Goede
@ 2014-12-04 16:33 ` Maxime Ripard
-1 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-12-04 16:33 UTC (permalink / raw)
To: Hans de Goede
Cc: Linus Walleij, Chen-Yu Tsai, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 1926 bytes --]
Hi,
On Wed, Nov 26, 2014 at 09:58:18AM +0100, Hans de Goede wrote:
> Hi,
>
> On 11/25/2014 07:21 PM, Maxime Ripard wrote:
> >On Sun, Nov 23, 2014 at 01:54:43PM +0100, Hans de Goede wrote:
> >>The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
> >>rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
> >>controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
> >>
> >>http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html
> >>
> >>Note it has no sdcard slot and therefore can only be fel booted.
> >
> >Thanks a lot for working on this!
> >
> >I also bought another board with an A31s, but it ended up having
> >neither USB OTG or MMC, which rendered it pretty useless.
>
> Are you sure ? The cs908 also does not have an otg connector,
> as said it has 2 usb-a receptacles, with the following usb "routing":
>
> usb0 (otg): usb-a receptacle 1 (labeled 1 on the box, 0 on the print)
> usb1 (ehci): routed to internal wifi
> usb2 (ehci): usb-a receptacle 2 (labeled 2 on both the box and the print)
>
> I'm using fel mode with an usb-a <-> usb-a cable connected to usb0 on
> the cs908. The cs908 has no fel button, so I've hooked up the serial console,
> and then keep 2 pressed on the serial console while inserting the usb-a into
> the PC (which will also power the board). boot0 from the nand will then jump
> into fel mode when it sees the 2 keypress.
>
> This was an interesting exercise to confirm that everything on the A31s just
> works with A31 code, but now that is confirms A31s devices are not all that
> interesting anymore :)
Ah, that's very interesting... I'll dig this board out then, and try
both USB-A connector. It might very well be just that.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
@ 2014-12-04 16:33 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2014-12-04 16:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Wed, Nov 26, 2014 at 09:58:18AM +0100, Hans de Goede wrote:
> Hi,
>
> On 11/25/2014 07:21 PM, Maxime Ripard wrote:
> >On Sun, Nov 23, 2014 at 01:54:43PM +0100, Hans de Goede wrote:
> >>The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
> >>rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
> >>controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
> >>
> >>http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html
> >>
> >>Note it has no sdcard slot and therefore can only be fel booted.
> >
> >Thanks a lot for working on this!
> >
> >I also bought another board with an A31s, but it ended up having
> >neither USB OTG or MMC, which rendered it pretty useless.
>
> Are you sure ? The cs908 also does not have an otg connector,
> as said it has 2 usb-a receptacles, with the following usb "routing":
>
> usb0 (otg): usb-a receptacle 1 (labeled 1 on the box, 0 on the print)
> usb1 (ehci): routed to internal wifi
> usb2 (ehci): usb-a receptacle 2 (labeled 2 on both the box and the print)
>
> I'm using fel mode with an usb-a <-> usb-a cable connected to usb0 on
> the cs908. The cs908 has no fel button, so I've hooked up the serial console,
> and then keep 2 pressed on the serial console while inserting the usb-a into
> the PC (which will also power the board). boot0 from the nand will then jump
> into fel mode when it sees the 2 keypress.
>
> This was an interesting exercise to confirm that everything on the A31s just
> works with A31 code, but now that is confirms A31s devices are not all that
> interesting anymore :)
Ah, that's very interesting... I'll dig this board out then, and try
both USB-A connector. It might very well be just that.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: Re: [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
[not found] ` <5475962A.4090508-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-12-04 16:33 ` Maxime Ripard
@ 2014-12-15 10:21 ` Code Kipper
[not found] ` <CAEKpxBnm2w9pcuf_T1HaO8ACz+94U9G3MeYKNhtzph+9fPtPWg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
1 sibling, 1 reply; 52+ messages in thread
From: Code Kipper @ 2014-12-15 10:21 UTC (permalink / raw)
To: linux-sunxi, Hans de Goede; +Cc: Maxime Ripard, Chen-Yu Tsai, devicetree
[-- Attachment #1: Type: text/plain, Size: 1672 bytes --]
>
> usb0 (otg): usb-a receptacle 1 (labeled 1 on the box, 0 on the print)
> usb1 (ehci): routed to internal wifi
> usb2 (ehci): usb-a receptacle 2 (labeled 2 on both the box and the print)
>
> I'm using fel mode with an usb-a <-> usb-a cable connected to usb0 on
> the cs908. The cs908 has no fel button, so I've hooked up the serial
> console,
> and then keep 2 pressed on the serial console while inserting the usb-a
> into
> the PC (which will also power the board). boot0 from the nand will then
> jump
> into fel mode when it sees the 2 keypress.
>
Hi Hans,
I'm looking to try this on my vidon box which like the cs908 doesn't have
OTG
or a fel button. Just would like to confirm the wiring on the usb-a 2 usb-a
male
cable. Are they connected one to one i.e. 5v <-> 5v, D+ <-> D+ etc or are
the
data lines twisted. i.e. D+ <-> D- and vice versa?.
Good work with the A31 and A23 deliveries.
Thanks,
CK
>
> This was an interesting exercise to confirm that everything on the A31s
> just
> works with A31 code, but now that is confirms A31s devices are not all that
> interesting anymore :)
>
> I wonder wether to put URL in the commit log is the right thing
>> though. It's most likely to be dead in a very near future. The cover
>> letter would be a better fit for that.
>>
>
> Ok, I'll drop it from the commit message.
>
> Regards,
>
> Hans
>
>
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: Re: [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board
[not found] ` <CAEKpxBnm2w9pcuf_T1HaO8ACz+94U9G3MeYKNhtzph+9fPtPWg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2014-12-15 11:38 ` Hans de Goede
0 siblings, 0 replies; 52+ messages in thread
From: Hans de Goede @ 2014-12-15 11:38 UTC (permalink / raw)
To: Code Kipper, linux-sunxi; +Cc: Maxime Ripard, Chen-Yu Tsai, devicetree
Hi,
On 15-12-14 11:21, Code Kipper wrote:
>>
>> usb0 (otg): usb-a receptacle 1 (labeled 1 on the box, 0 on the print)
>> usb1 (ehci): routed to internal wifi
>> usb2 (ehci): usb-a receptacle 2 (labeled 2 on both the box and the print)
>>
>> I'm using fel mode with an usb-a <-> usb-a cable connected to usb0 on
>> the cs908. The cs908 has no fel button, so I've hooked up the serial
>> console,
>> and then keep 2 pressed on the serial console while inserting the usb-a
>> into
>> the PC (which will also power the board). boot0 from the nand will then
>> jump
>> into fel mode when it sees the 2 keypress.
>>
>
> Hi Hans,
>
> I'm looking to try this on my vidon box which like the cs908 doesn't have
> OTG
> or a fel button. Just would like to confirm the wiring on the usb-a 2 usb-a
> male
> cable. Are they connected one to one i.e. 5v <-> 5v, D+ <-> D+ etc or are
> the
> data lines twisted. i.e. D+ <-> D- and vice versa?.
I don't know, I just picked a A <-> A cable out of my box with usb cables
(some regular usb devices actually ship with an A receptacle instead of a B)
used that and things just worked. So I would say whatever standard A <-> A
cables are using.
Regards,
Hans
^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2014-12-15 11:38 UTC | newest]
Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-11-23 12:54 [PATCH 0/5] sun6i: Add A31s (pinctrl) support Hans de Goede
2014-11-23 12:54 ` Hans de Goede
[not found] ` <1416747283-13489-1-git-send-email-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-11-23 12:54 ` [PATCH 1/5] pinctrl: sun6i: Add some missing functions, fix i2c3 muxing Hans de Goede
2014-11-23 12:54 ` Hans de Goede
[not found] ` <1416747283-13489-2-git-send-email-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-11-25 18:04 ` Maxime Ripard
2014-11-25 18:04 ` Maxime Ripard
2014-11-26 8:30 ` Hans de Goede
2014-11-26 8:30 ` Hans de Goede
[not found] ` <54758FB0.4010503-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-11-26 18:44 ` Maxime Ripard
2014-11-26 18:44 ` Maxime Ripard
2014-11-27 8:28 ` Hans de Goede
2014-11-27 8:28 ` Hans de Goede
2014-11-23 12:54 ` [PATCH 2/5] pinctrl: sun6i: Add A31s pinctrl support Hans de Goede
2014-11-23 12:54 ` Hans de Goede
[not found] ` <1416747283-13489-3-git-send-email-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-11-25 18:08 ` Maxime Ripard
2014-11-25 18:08 ` Maxime Ripard
2014-11-26 8:11 ` Hans de Goede
2014-11-26 8:11 ` Hans de Goede
[not found] ` <54758B29.7040203-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-11-26 18:37 ` Maxime Ripard
2014-11-26 18:37 ` Maxime Ripard
2014-11-23 12:54 ` [PATCH 3/5] ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi Hans de Goede
2014-11-23 12:54 ` Hans de Goede
[not found] ` <1416747283-13489-4-git-send-email-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-11-25 18:24 ` Maxime Ripard
2014-11-25 18:24 ` Maxime Ripard
2014-11-23 12:54 ` [PATCH 4/5] ARM: dts: sun6i: Add sun6i-a31s.dtsi Hans de Goede
2014-11-23 12:54 ` Hans de Goede
[not found] ` <1416747283-13489-5-git-send-email-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-11-25 18:18 ` Maxime Ripard
2014-11-25 18:18 ` Maxime Ripard
2014-11-25 23:45 ` Chen-Yu Tsai
2014-11-25 23:45 ` Chen-Yu Tsai
[not found] ` <CAGb2v64=M37i0WVBbjOOWCrfP5tcHMr6yE+C6rPiy-sV7__qFQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-11-26 9:05 ` Hans de Goede
2014-11-26 9:05 ` Hans de Goede
[not found] ` <547597C7.5070005-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-11-26 9:39 ` Chen-Yu Tsai
2014-11-26 9:39 ` Chen-Yu Tsai
[not found] ` <CAGb2v66kHvChJw=5jBXGSfGbqnr=hmC1YOyzR-N7EN=AVookLA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-12-04 14:13 ` Maxime Ripard
2014-12-04 14:13 ` Maxime Ripard
2014-11-26 8:44 ` Hans de Goede
2014-11-26 8:44 ` [linux-sunxi] " Hans de Goede
2014-11-23 12:54 ` [PATCH 5/5] ARM: dts: sun6i: Add dts file for CSQ CS908 board Hans de Goede
2014-11-23 12:54 ` Hans de Goede
[not found] ` <1416747283-13489-6-git-send-email-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-11-25 18:21 ` Maxime Ripard
2014-11-25 18:21 ` Maxime Ripard
2014-11-26 8:58 ` Hans de Goede
2014-11-26 8:58 ` Hans de Goede
[not found] ` <5475962A.4090508-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2014-12-04 16:33 ` Maxime Ripard
2014-12-04 16:33 ` Maxime Ripard
2014-12-15 10:21 ` Code Kipper
[not found] ` <CAEKpxBnm2w9pcuf_T1HaO8ACz+94U9G3MeYKNhtzph+9fPtPWg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-12-15 11:38 ` Hans de Goede
2014-11-28 12:01 ` [PATCH 0/5] sun6i: Add A31s (pinctrl) support Linus Walleij
2014-11-28 12:01 ` Linus Walleij
[not found] ` <CACRpkdb3P+KM+ANqe6fKqJcRnBp6zvJhWUFZDap8qFDWdY1JNQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-11-28 12:59 ` Hans de Goede
2014-11-28 12:59 ` Hans de Goede
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