[PATCH v2 1/2] spi: dw-mid: fix FIFO size

[PATCH v2 1/2] spi: dw-mid: fix FIFO size

[Andy Shevchenko]

The FIFO size is 40 accordingly to the specifications, but this means 0x40,
i.e. 64 bytes. This patch fixes the typo and enables FIFO size autodetection
for Intel MID devices.

Fixes: 7063c0d942a1 (spi/dw_spi: add DMA support)
Cc: stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/spi/spi-dw-mid.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 7281316..a67d37c 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -271,7 +271,6 @@ int dw_spi_mid_init(struct dw_spi *dws)
 	iounmap(clk_reg);
 
 	dws->num_cs = 16;
-	dws->fifo_len = 40;	/* FIFO has 40 words buffer */
 
 #ifdef CONFIG_SPI_DW_MID_DMA
 	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
-- 
2.1.3

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[PATCH v2 2/2] spi: dw-mid: fix number of CS lines

[Andy Shevchenko]

According to specification the SPI1 has 5 bits for chip selects. The current
code limits it to 4 bits. The patch fixes that constant.

Fixes: 7063c0d942a1 (spi/dw_spi: add DMA support)
Cc: stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/spi/spi-dw-mid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index a67d37c..bd72ec6 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -270,7 +270,7 @@ int dw_spi_mid_init(struct dw_spi *dws)
 	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
 	iounmap(clk_reg);
 
-	dws->num_cs = 16;
+	dws->num_cs = 32;
 
 #ifdef CONFIG_SPI_DW_MID_DMA
 	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
-- 
2.1.3

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Re: [PATCH v2 2/2] spi: dw-mid: fix number of CS lines

[Mark Brown]

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On Fri, Jan 02, 2015 at 05:48:52PM +0200, Andy Shevchenko wrote:
> According to specification the SPI1 has 5 bits for chip selects. The current
> code limits it to 4 bits. The patch fixes that constant.
> 
> Fixes: 7063c0d942a1 (spi/dw_spi: add DMA support)
> Cc: stable@vger.kernel.org
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

I'm not seeing this as an obvious candidate for stable, it seems more
like a new feature really in terms of impact, and that doesn't look like
the commit that's being fixed - it's the last one that refactored things
but that's not the same thing.

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Re: [PATCH v2 1/2] spi: dw-mid: fix FIFO size

[Mark Brown]

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On Fri, Jan 02, 2015 at 05:48:51PM +0200, Andy Shevchenko wrote:
> The FIFO size is 40 accordingly to the specifications, but this means 0x40,
> i.e. 64 bytes. This patch fixes the typo and enables FIFO size autodetection
> for Intel MID devices.

Applied, thanks.

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