* [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports
@ 2015-01-09 12:21 ville.syrjala
2015-01-09 12:21 ` [PATCH 1/7] drm/i915: Make hpd arrays big enough to avoid out of bounds access ville.syrjala
` (7 more replies)
0 siblings, 8 replies; 19+ messages in thread
From: ville.syrjala @ 2015-01-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Egbert Eich
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
My BSW has a nasty problem where it generates tons of spurious hpd interrupts
when the eDP display is disabled. The best solution seems to be to disable hpd
for eDP ports when the port is disabled since we don't care about long hpds
anyway and short hpds are only relevant while the link is up and running.
This series tries to implement that, and I've included a few random
fixes/refactorings to the hpd code as well.
Ville Syrjälä (7):
drm/i915: Make hpd arrays big enough to avoid out of bounds access
drm/i915: Remove I915_HAS_HOTPLUG() check from i915_hpd_irq_setup()
drm/i915: Don't register HDMI connectors for eDP ports on VLV/CHV
drm/i915: Don't pretend SDVO hotplug works on 915
drm/i915: Set intel_connector->polled to DRM_CONNECTOR_POLL_HPD when
appropriate
drm/i915: Unify hpd setup between init and hpd storm handling
drm/i915: Disable HPD for disabled eDP ports
drivers/gpu/drm/i915/i915_irq.c | 172 ++++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_crt.c | 4 +-
drivers/gpu/drm/i915/intel_display.c | 6 +-
drivers/gpu/drm/i915/intel_dp.c | 18 ++++
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +
drivers/gpu/drm/i915/intel_drv.h | 3 +
drivers/gpu/drm/i915/intel_hdmi.c | 2 +
drivers/gpu/drm/i915/intel_sdvo.c | 4 +
8 files changed, 136 insertions(+), 75 deletions(-)
--
2.0.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/7] drm/i915: Make hpd arrays big enough to avoid out of bounds access
2015-01-09 12:21 [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports ville.syrjala
@ 2015-01-09 12:21 ` ville.syrjala
2015-01-09 14:41 ` [Intel-gfx] " Jani Nikula
2015-01-09 12:21 ` [PATCH 2/7] drm/i915: Remove I915_HAS_HOTPLUG() check from i915_hpd_irq_setup() ville.syrjala
` (6 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: ville.syrjala @ 2015-01-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Egbert Eich, stable
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_hpd_irq_handler() walks the passed in hpd[] array assuming it
contains HPD_NUM_PINS elements. Currently that's not true as we don't
specify an explicit size for the arrays when initializing them. Avoid
the out of bounds accesses by specifying the size for the arrays.
Cc: stable@vger.kernel.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 818ab4e..1d52ae9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -45,7 +45,7 @@
* and related files, but that will be described in separate chapters.
*/
-static const u32 hpd_ibx[] = {
+static const u32 hpd_ibx[HPD_NUM_PINS] = {
[HPD_CRT] = SDE_CRT_HOTPLUG,
[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
@@ -53,7 +53,7 @@ static const u32 hpd_ibx[] = {
[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};
-static const u32 hpd_cpt[] = {
+static const u32 hpd_cpt[HPD_NUM_PINS] = {
[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
@@ -61,7 +61,7 @@ static const u32 hpd_cpt[] = {
[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};
-static const u32 hpd_mask_i915[] = {
+static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
[HPD_CRT] = CRT_HOTPLUG_INT_EN,
[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
@@ -70,7 +70,7 @@ static const u32 hpd_mask_i915[] = {
[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};
-static const u32 hpd_status_g4x[] = {
+static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
@@ -79,7 +79,7 @@ static const u32 hpd_status_g4x[] = {
[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};
-static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
+static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */
[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
@@ -1522,7 +1522,7 @@ static inline enum port get_port_from_pin(enum hpd_pin pin)
static inline void intel_hpd_irq_handler(struct drm_device *dev,
u32 hotplug_trigger,
u32 dig_hotplug_reg,
- const u32 *hpd)
+ const u32 hpd[HPD_NUM_PINS])
{
struct drm_i915_private *dev_priv = dev->dev_private;
int i;
--
2.0.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/7] drm/i915: Remove I915_HAS_HOTPLUG() check from i915_hpd_irq_setup()
2015-01-09 12:21 [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports ville.syrjala
2015-01-09 12:21 ` [PATCH 1/7] drm/i915: Make hpd arrays big enough to avoid out of bounds access ville.syrjala
@ 2015-01-09 12:21 ` ville.syrjala
2015-01-09 14:52 ` Jani Nikula
2015-01-09 12:21 ` [PATCH 3/7] drm/i915: Don't register HDMI connectors for eDP ports on VLV/CHV ville.syrjala
` (5 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: ville.syrjala @ 2015-01-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Egbert Eich
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The dev_priv->display.hpd_irq_setup hook is optional, so we can move the
I915_HAS_HOTPLUG() check out of i915_hpd_irq_setup() and only set up the
hook when hotplug support is present.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 42 ++++++++++++++++++++---------------------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1d52ae9..8fe5a87 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4145,26 +4145,24 @@ static void i915_hpd_irq_setup(struct drm_device *dev)
assert_spin_locked(&dev_priv->irq_lock);
- if (I915_HAS_HOTPLUG(dev)) {
- hotplug_en = I915_READ(PORT_HOTPLUG_EN);
- hotplug_en &= ~HOTPLUG_INT_EN_MASK;
- /* Note HDMI and DP share hotplug bits */
- /* enable bits are the same for all generations */
- for_each_intel_encoder(dev, intel_encoder)
- if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
- hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
- /* Programming the CRT detection parameters tends
- to generate a spurious hotplug event about three
- seconds later. So just do it once.
- */
- if (IS_G4X(dev))
- hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
- hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
- hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
-
- /* Ignore TV since it's buggy */
- I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
- }
+ hotplug_en = I915_READ(PORT_HOTPLUG_EN);
+ hotplug_en &= ~HOTPLUG_INT_EN_MASK;
+ /* Note HDMI and DP share hotplug bits */
+ /* enable bits are the same for all generations */
+ for_each_intel_encoder(dev, intel_encoder)
+ if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
+ hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
+ /* Programming the CRT detection parameters tends
+ to generate a spurious hotplug event about three
+ seconds later. So just do it once.
+ */
+ if (IS_G4X(dev))
+ hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
+ hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
+ hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
+
+ /* Ignore TV since it's buggy */
+ I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
}
static irqreturn_t i965_irq_handler(int irq, void *arg)
@@ -4428,14 +4426,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->irq_postinstall = i915_irq_postinstall;
dev->driver->irq_uninstall = i915_irq_uninstall;
dev->driver->irq_handler = i915_irq_handler;
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else {
dev->driver->irq_preinstall = i965_irq_preinstall;
dev->driver->irq_postinstall = i965_irq_postinstall;
dev->driver->irq_uninstall = i965_irq_uninstall;
dev->driver->irq_handler = i965_irq_handler;
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
}
+ if (I915_HAS_HOTPLUG(dev_priv))
+ dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
dev->driver->enable_vblank = i915_enable_vblank;
dev->driver->disable_vblank = i915_disable_vblank;
}
--
2.0.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 3/7] drm/i915: Don't register HDMI connectors for eDP ports on VLV/CHV
2015-01-09 12:21 [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports ville.syrjala
2015-01-09 12:21 ` [PATCH 1/7] drm/i915: Make hpd arrays big enough to avoid out of bounds access ville.syrjala
2015-01-09 12:21 ` [PATCH 2/7] drm/i915: Remove I915_HAS_HOTPLUG() check from i915_hpd_irq_setup() ville.syrjala
@ 2015-01-09 12:21 ` ville.syrjala
2015-01-09 15:02 ` Jani Nikula
2015-01-09 12:21 ` [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915 ville.syrjala
` (4 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: ville.syrjala @ 2015-01-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Egbert Eich
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
If we determine that a specific port is eDP, don't register the HDMI
connector/encoder for it. The reason being that we want to disable
HPD interrupts for eDP ports when the display is off, but the presence
of the extra HDMI connector would demand the HPD interrupt to remain
enabled all the time.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d1a4de8..2b1f220 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12390,14 +12390,16 @@ static void intel_setup_outputs(struct drm_device *dev)
* eDP ports. Consult the VBT as well as DP_DETECTED to
* detect eDP ports.
*/
- if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
+ if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
+ !intel_dp_is_edp(dev, PORT_B))
intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
PORT_B);
if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
intel_dp_is_edp(dev, PORT_B))
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
- if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
+ if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
+ !intel_dp_is_edp(dev, PORT_C))
intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
PORT_C);
if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
--
2.0.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915
2015-01-09 12:21 [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports ville.syrjala
` (2 preceding siblings ...)
2015-01-09 12:21 ` [PATCH 3/7] drm/i915: Don't register HDMI connectors for eDP ports on VLV/CHV ville.syrjala
@ 2015-01-09 12:21 ` ville.syrjala
2015-01-09 15:04 ` Jani Nikula
2015-01-12 23:48 ` Daniel Vetter
2015-01-09 12:21 ` [PATCH 5/7] drm/i915: Set intel_connector->polled to DRM_CONNECTOR_POLL_HPD when appropriate ville.syrjala
` (3 subsequent siblings)
7 siblings, 2 replies; 19+ messages in thread
From: ville.syrjala @ 2015-01-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Egbert Eich
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
915 doens't support hotplug at all, so we shouldn't try to pretend
otherwise in the SDVO code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_sdvo.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 6d7a277..4e3d362 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1617,6 +1617,9 @@ static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
struct drm_device *dev = intel_sdvo->base.base.dev;
uint16_t hotplug;
+ if (!I915_HAS_HOTPLUG(dev))
+ return 0;
+
/* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
* on the line. */
if (IS_I945G(dev) || IS_I945GM(dev))
--
2.0.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 5/7] drm/i915: Set intel_connector->polled to DRM_CONNECTOR_POLL_HPD when appropriate
2015-01-09 12:21 [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports ville.syrjala
` (3 preceding siblings ...)
2015-01-09 12:21 ` [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915 ville.syrjala
@ 2015-01-09 12:21 ` ville.syrjala
2015-01-09 12:21 ` [PATCH 6/7] drm/i915: Unify hpd setup between init and hpd storm handling ville.syrjala
` (2 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: ville.syrjala @ 2015-01-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Egbert Eich
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to toggle hpd support on/off per-connector during runtime, we
need to track the desired hpd state for each connector. Currently we're
being lazy and only setting up intel_connector->polled when we wish to
use polling instead of hpd, so a value of 0 can mean both "use hpd" and
"no hpd/polling whatsoever". Change things so that 0 actually means only
the latter, and a value of DRM_CONNECTOR_POLL_HPD will indicate that
we wish to use the hpd interrupt.
To do that we need to initiialize intel_connector->polled to
DRM_CONNECTOR_POLL_HPD for all hpd capable connectors.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_crt.c | 4 +++-
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_dp_mst.c | 2 ++
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
drivers/gpu/drm/i915/intel_sdvo.c | 1 +
5 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index a9af9a4..a42d059 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -902,7 +902,9 @@ void intel_crt_init(struct drm_device *dev)
drm_connector_register(connector);
- if (!I915_HAS_HOTPLUG(dev))
+ if (I915_HAS_HOTPLUG(dev))
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
+ else
intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
/*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 88d81a8..4d6af4c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5072,6 +5072,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
BUG();
}
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
+
if (is_edp(intel_dp)) {
pps_lock(intel_dp);
intel_dp_init_panel_power_timestamps(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 7f8c6a6..831a2d9 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -407,6 +407,8 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_connector->mst_port = intel_dp;
intel_connector->port = port;
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
+
for (i = PIPE_A; i <= PIPE_C; i++) {
drm_mode_connector_attach_encoder(&intel_connector->base,
&intel_dp->mst_encoders[i]->base.base);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 3abc200..e59bc95 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1687,6 +1687,8 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
BUG();
}
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
+
if (IS_VALLEYVIEW(dev)) {
intel_hdmi->write_infoframe = vlv_write_infoframe;
intel_hdmi->set_infoframes = vlv_set_infoframes;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4e3d362..0ee0af7 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2455,6 +2455,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
*/
intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
intel_sdvo_enable_hotplug(intel_encoder);
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
} else {
intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
}
--
2.0.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 6/7] drm/i915: Unify hpd setup between init and hpd storm handling
2015-01-09 12:21 [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports ville.syrjala
` (4 preceding siblings ...)
2015-01-09 12:21 ` [PATCH 5/7] drm/i915: Set intel_connector->polled to DRM_CONNECTOR_POLL_HPD when appropriate ville.syrjala
@ 2015-01-09 12:21 ` ville.syrjala
2015-01-09 12:21 ` [PATCH 7/7] drm/i915: Disable HPD for disabled eDP ports ville.syrjala
2015-01-13 0:46 ` [PATCH 0/7] drm/i915: Disable hpd " Sean V Kelley
7 siblings, 0 replies; 19+ messages in thread
From: ville.syrjala @ 2015-01-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Egbert Eich
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Handle things the same way when initializing hpd support and re-enabling
hpd interrupts after recovering from an interrupt storm. Later on we'll
share the same code also when togglind hpd on/off for inidividual eDP
connectors.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 93 +++++++++++++++++++++--------------------
1 file changed, 48 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8fe5a87..c482903 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4165,6 +4165,46 @@ static void i915_hpd_irq_setup(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
}
+static void intel_hpd_irq_setup(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct drm_connector *connector;
+ int hpd_pin;
+
+ assert_spin_locked(&dev_priv->irq_lock);
+
+ for (hpd_pin = 1; hpd_pin < HPD_NUM_PINS; hpd_pin++)
+ dev_priv->hpd_stats[hpd_pin].hpd_mark = HPD_DISABLED;
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ uint8_t polled;
+
+ /* mst connector */
+ if (!intel_connector->encoder)
+ continue;
+
+ hpd_pin = intel_connector->encoder->hpd_pin;
+ if (hpd_pin == HPD_NONE)
+ continue;
+
+ polled = intel_connector->polled;
+
+ if (connector->polled != polled)
+ DRM_DEBUG_KMS("%sabling HPD on connector %s (pin %d)\n",
+ polled == DRM_CONNECTOR_POLL_HPD ? "en" : "dis",
+ connector->name, hpd_pin);
+ connector->polled = polled;
+
+ if (connector->polled == DRM_CONNECTOR_POLL_HPD)
+ dev_priv->hpd_stats[hpd_pin].hpd_mark = HPD_ENABLED;
+ }
+
+ if (dev_priv->display.hpd_irq_setup)
+ dev_priv->display.hpd_irq_setup(dev);
+}
+
static irqreturn_t i965_irq_handler(int irq, void *arg)
{
struct drm_device *dev = arg;
@@ -4293,35 +4333,11 @@ static void intel_hpd_irq_reenable_work(struct work_struct *work)
container_of(work, typeof(*dev_priv),
hotplug_reenable_work.work);
struct drm_device *dev = dev_priv->dev;
- struct drm_mode_config *mode_config = &dev->mode_config;
- int i;
intel_runtime_pm_get(dev_priv);
spin_lock_irq(&dev_priv->irq_lock);
- for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
- struct drm_connector *connector;
-
- if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
- continue;
-
- dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
-
- list_for_each_entry(connector, &mode_config->connector_list, head) {
- struct intel_connector *intel_connector = to_intel_connector(connector);
-
- if (intel_connector->encoder->hpd_pin == i) {
- if (connector->polled != intel_connector->polled)
- DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
- connector->name);
- connector->polled = intel_connector->polled;
- if (!connector->polled)
- connector->polled = DRM_CONNECTOR_POLL_HPD;
- }
- }
- }
- if (dev_priv->display.hpd_irq_setup)
- dev_priv->display.hpd_irq_setup(dev);
+ intel_hpd_irq_setup(dev);
spin_unlock_irq(&dev_priv->irq_lock);
intel_runtime_pm_put(dev_priv);
@@ -4454,28 +4470,15 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
void intel_hpd_init(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
- struct drm_mode_config *mode_config = &dev->mode_config;
- struct drm_connector *connector;
- int i;
+ int hpd_pin;
- for (i = 1; i < HPD_NUM_PINS; i++) {
- dev_priv->hpd_stats[i].hpd_cnt = 0;
- dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
- }
- list_for_each_entry(connector, &mode_config->connector_list, head) {
- struct intel_connector *intel_connector = to_intel_connector(connector);
- connector->polled = intel_connector->polled;
- if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
- connector->polled = DRM_CONNECTOR_POLL_HPD;
- if (intel_connector->mst_port)
- connector->polled = DRM_CONNECTOR_POLL_HPD;
- }
-
- /* Interrupt setup is already guaranteed to be single-threaded, this is
- * just to make the assert_spin_locked checks happy. */
spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->display.hpd_irq_setup)
- dev_priv->display.hpd_irq_setup(dev);
+
+ for (hpd_pin = 1; hpd_pin < HPD_NUM_PINS; hpd_pin++)
+ dev_priv->hpd_stats[hpd_pin].hpd_cnt = 0;
+
+ intel_hpd_irq_setup(dev);
+
spin_unlock_irq(&dev_priv->irq_lock);
}
--
2.0.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 7/7] drm/i915: Disable HPD for disabled eDP ports
2015-01-09 12:21 [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports ville.syrjala
` (5 preceding siblings ...)
2015-01-09 12:21 ` [PATCH 6/7] drm/i915: Unify hpd setup between init and hpd storm handling ville.syrjala
@ 2015-01-09 12:21 ` ville.syrjala
2015-01-09 17:47 ` shuang.he
2015-01-13 0:46 ` [PATCH 0/7] drm/i915: Disable hpd " Sean V Kelley
7 siblings, 1 reply; 19+ messages in thread
From: ville.syrjala @ 2015-01-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Egbert Eich
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
My BSW likes to generate tons of HPD interrupts while the eDP port is
disabled. I guess it leaves the HPD like floating and then stuff like
CPU activity can cause noise on the line leading to tons of spurious
interrupts.
To combat this, disable the relevant HPD interrupt whenever the port is
disabled. We don't need need HPDs on disabled eDP ports anyway since the
display can't physically disappear.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 38 ++++++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_dp.c | 18 +++++++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c482903..6041d82 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4165,7 +4165,8 @@ static void i915_hpd_irq_setup(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
}
-static void intel_hpd_irq_setup(struct drm_device *dev)
+static void intel_hpd_irq_setup(struct drm_device *dev,
+ bool force)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_mode_config *mode_config = &dev->mode_config;
@@ -4189,7 +4190,15 @@ static void intel_hpd_irq_setup(struct drm_device *dev)
if (hpd_pin == HPD_NONE)
continue;
- polled = intel_connector->polled;
+ /*
+ * If hpd storm detection switched to
+ * polling don't change back unless forced.
+ */
+ if (!force && connector->polled & (DRM_CONNECTOR_POLL_CONNECT |
+ DRM_CONNECTOR_POLL_DISCONNECT))
+ polled = connector->polled;
+ else
+ polled = intel_connector->polled;
if (connector->polled != polled)
DRM_DEBUG_KMS("%sabling HPD on connector %s (pin %d)\n",
@@ -4205,6 +4214,27 @@ static void intel_hpd_irq_setup(struct drm_device *dev)
dev_priv->display.hpd_irq_setup(dev);
}
+void intel_connector_hpd_enable(struct intel_connector *intel_connector,
+ bool enable)
+{
+ struct drm_device *dev = intel_connector->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ spin_lock_irq(&dev_priv->irq_lock);
+
+ if (enable && intel_connector->polled == 0)
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
+ else if (!enable && intel_connector->polled == DRM_CONNECTOR_POLL_HPD)
+ intel_connector->polled = 0;
+ else
+ goto out;
+
+ intel_hpd_irq_setup(dev, false);
+
+ out:
+ spin_unlock_irq(&dev_priv->irq_lock);
+}
+
static irqreturn_t i965_irq_handler(int irq, void *arg)
{
struct drm_device *dev = arg;
@@ -4337,7 +4367,7 @@ static void intel_hpd_irq_reenable_work(struct work_struct *work)
intel_runtime_pm_get(dev_priv);
spin_lock_irq(&dev_priv->irq_lock);
- intel_hpd_irq_setup(dev);
+ intel_hpd_irq_setup(dev, true);
spin_unlock_irq(&dev_priv->irq_lock);
intel_runtime_pm_put(dev_priv);
@@ -4477,7 +4507,7 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
for (hpd_pin = 1; hpd_pin < HPD_NUM_PINS; hpd_pin++)
dev_priv->hpd_stats[hpd_pin].hpd_cnt = 0;
- intel_hpd_irq_setup(dev);
+ intel_hpd_irq_setup(dev, true);
spin_unlock_irq(&dev_priv->irq_lock);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4d6af4c..b53a6f0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2102,6 +2102,10 @@ static void intel_disable_dp(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+ if (is_edp(intel_dp))
+ intel_connector_hpd_enable(intel_dp->attached_connector,
+ false);
+
if (crtc->config.has_audio)
intel_audio_codec_disable(encoder);
@@ -2307,6 +2311,10 @@ static void intel_enable_dp(struct intel_encoder *encoder)
if (IS_VALLEYVIEW(dev))
vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
+ if (is_edp(intel_dp))
+ intel_connector_hpd_enable(intel_dp->attached_connector,
+ true);
+
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
intel_dp_complete_link_train(intel_dp);
@@ -4373,6 +4381,7 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->dev);
struct intel_dp *intel_dp;
if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
@@ -4392,6 +4401,11 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
intel_edp_panel_vdd_sanitize(intel_dp);
pps_unlock(intel_dp);
+
+ /* enable HPD for eDP only if the port is currently enabled */
+ if (I915_READ(intel_dp->output_reg) & DP_PORT_EN)
+ intel_dp->attached_connector->polled = DRM_CONNECTOR_POLL_HPD;
+
}
static const struct drm_connector_funcs intel_dp_connector_funcs = {
@@ -5072,7 +5086,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
BUG();
}
- intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
+ /* enable HPD for eDP only if the port is currently enabled */
+ if (!is_edp(intel_dp) || intel_dp->DP & DP_PORT_EN)
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
if (is_edp(intel_dp)) {
pps_lock(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bb871f3..bb72c46 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -809,6 +809,9 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
int intel_get_crtc_scanline(struct intel_crtc *crtc);
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
+void intel_connector_hpd_enable(struct intel_connector *intel_connector,
+ bool enable);
+
/* intel_crt.c */
void intel_crt_init(struct drm_device *dev);
--
2.0.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915: Make hpd arrays big enough to avoid out of bounds access
2015-01-09 12:21 ` [PATCH 1/7] drm/i915: Make hpd arrays big enough to avoid out of bounds access ville.syrjala
@ 2015-01-09 14:41 ` Jani Nikula
2015-01-09 15:27 ` Ville Syrjälä
0 siblings, 1 reply; 19+ messages in thread
From: Jani Nikula @ 2015-01-09 14:41 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Egbert Eich, stable
On Fri, 09 Jan 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_hpd_irq_handler() walks the passed in hpd[] array assuming it
> contains HPD_NUM_PINS elements. Currently that's not true as we don't
> specify an explicit size for the arrays when initializing them. Avoid
> the out of bounds accesses by specifying the size for the arrays.
My first impression was wowowow, this must fix some of those obscure hpd
bugs we seem to have. But no, all of the arrays have HPD_PORT_D which
means we don't go out of bounds. This patch doesn't change the sizes of
the arrays.
> Cc: stable@vger.kernel.org
I'm not sure if that's appropriate in light of the above ("It must fix a
real bug that bothers people").
But we should do this *before* it becomes a bug.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 818ab4e..1d52ae9 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -45,7 +45,7 @@
> * and related files, but that will be described in separate chapters.
> */
>
> -static const u32 hpd_ibx[] = {
> +static const u32 hpd_ibx[HPD_NUM_PINS] = {
> [HPD_CRT] = SDE_CRT_HOTPLUG,
> [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
> [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
> @@ -53,7 +53,7 @@ static const u32 hpd_ibx[] = {
> [HPD_PORT_D] = SDE_PORTD_HOTPLUG
> };
>
> -static const u32 hpd_cpt[] = {
> +static const u32 hpd_cpt[HPD_NUM_PINS] = {
> [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
> [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
> [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
> @@ -61,7 +61,7 @@ static const u32 hpd_cpt[] = {
> [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
> };
>
> -static const u32 hpd_mask_i915[] = {
> +static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
> [HPD_CRT] = CRT_HOTPLUG_INT_EN,
> [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
> [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
> @@ -70,7 +70,7 @@ static const u32 hpd_mask_i915[] = {
> [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
> };
>
> -static const u32 hpd_status_g4x[] = {
> +static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
> [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
> [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
> [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
> @@ -79,7 +79,7 @@ static const u32 hpd_status_g4x[] = {
> [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
> };
>
> -static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
> +static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */
> [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
> [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
> [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
> @@ -1522,7 +1522,7 @@ static inline enum port get_port_from_pin(enum hpd_pin pin)
> static inline void intel_hpd_irq_handler(struct drm_device *dev,
> u32 hotplug_trigger,
> u32 dig_hotplug_reg,
> - const u32 *hpd)
> + const u32 hpd[HPD_NUM_PINS])
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> int i;
> --
> 2.0.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/7] drm/i915: Remove I915_HAS_HOTPLUG() check from i915_hpd_irq_setup()
2015-01-09 12:21 ` [PATCH 2/7] drm/i915: Remove I915_HAS_HOTPLUG() check from i915_hpd_irq_setup() ville.syrjala
@ 2015-01-09 14:52 ` Jani Nikula
0 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2015-01-09 14:52 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Egbert Eich
On Fri, 09 Jan 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The dev_priv->display.hpd_irq_setup hook is optional, so we can move the
> I915_HAS_HOTPLUG() check out of i915_hpd_irq_setup() and only set up the
> hook when hotplug support is present.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 42 ++++++++++++++++++++---------------------
> 1 file changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 1d52ae9..8fe5a87 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4145,26 +4145,24 @@ static void i915_hpd_irq_setup(struct drm_device *dev)
>
> assert_spin_locked(&dev_priv->irq_lock);
>
> - if (I915_HAS_HOTPLUG(dev)) {
> - hotplug_en = I915_READ(PORT_HOTPLUG_EN);
> - hotplug_en &= ~HOTPLUG_INT_EN_MASK;
> - /* Note HDMI and DP share hotplug bits */
> - /* enable bits are the same for all generations */
> - for_each_intel_encoder(dev, intel_encoder)
> - if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
> - hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
> - /* Programming the CRT detection parameters tends
> - to generate a spurious hotplug event about three
> - seconds later. So just do it once.
> - */
> - if (IS_G4X(dev))
> - hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
> - hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
> - hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
> -
> - /* Ignore TV since it's buggy */
> - I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
> - }
> + hotplug_en = I915_READ(PORT_HOTPLUG_EN);
> + hotplug_en &= ~HOTPLUG_INT_EN_MASK;
> + /* Note HDMI and DP share hotplug bits */
> + /* enable bits are the same for all generations */
> + for_each_intel_encoder(dev, intel_encoder)
> + if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
> + hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
> + /* Programming the CRT detection parameters tends
> + to generate a spurious hotplug event about three
> + seconds later. So just do it once.
> + */
> + if (IS_G4X(dev))
> + hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
> + hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
> + hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
> +
> + /* Ignore TV since it's buggy */
> + I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
> }
>
> static irqreturn_t i965_irq_handler(int irq, void *arg)
> @@ -4428,14 +4426,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->irq_postinstall = i915_irq_postinstall;
> dev->driver->irq_uninstall = i915_irq_uninstall;
> dev->driver->irq_handler = i915_irq_handler;
> - dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> } else {
> dev->driver->irq_preinstall = i965_irq_preinstall;
> dev->driver->irq_postinstall = i965_irq_postinstall;
> dev->driver->irq_uninstall = i965_irq_uninstall;
> dev->driver->irq_handler = i965_irq_handler;
> - dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> }
> + if (I915_HAS_HOTPLUG(dev_priv))
> + dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> dev->driver->enable_vblank = i915_enable_vblank;
> dev->driver->disable_vblank = i915_disable_vblank;
> }
> --
> 2.0.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/7] drm/i915: Don't register HDMI connectors for eDP ports on VLV/CHV
2015-01-09 12:21 ` [PATCH 3/7] drm/i915: Don't register HDMI connectors for eDP ports on VLV/CHV ville.syrjala
@ 2015-01-09 15:02 ` Jani Nikula
2015-01-12 23:48 ` Daniel Vetter
0 siblings, 1 reply; 19+ messages in thread
From: Jani Nikula @ 2015-01-09 15:02 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Egbert Eich
On Fri, 09 Jan 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> If we determine that a specific port is eDP, don't register the HDMI
> connector/encoder for it. The reason being that we want to disable
> HPD interrupts for eDP ports when the display is off, but the presence
> of the extra HDMI connector would demand the HPD interrupt to remain
> enabled all the time.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d1a4de8..2b1f220 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12390,14 +12390,16 @@ static void intel_setup_outputs(struct drm_device *dev)
> * eDP ports. Consult the VBT as well as DP_DETECTED to
> * detect eDP ports.
> */
> - if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
> + if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
> + !intel_dp_is_edp(dev, PORT_B))
> intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
> PORT_B);
> if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
> intel_dp_is_edp(dev, PORT_B))
> intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
I wonder if these would read better with
if (intel_dp_is_edp(dev, PORT_B)) {
...
} else {
if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
...
if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
...
}
Dunno. Either way,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> - if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
> + if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
> + !intel_dp_is_edp(dev, PORT_C))
> intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
> PORT_C);
> if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
> --
> 2.0.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915
2015-01-09 12:21 ` [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915 ville.syrjala
@ 2015-01-09 15:04 ` Jani Nikula
2015-01-12 23:48 ` Daniel Vetter
1 sibling, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2015-01-09 15:04 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Egbert Eich
On Fri, 09 Jan 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> 915 doens't support hotplug at all, so we shouldn't try to pretend
> otherwise in the SDVO code.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_sdvo.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 6d7a277..4e3d362 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1617,6 +1617,9 @@ static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
> struct drm_device *dev = intel_sdvo->base.base.dev;
> uint16_t hotplug;
>
> + if (!I915_HAS_HOTPLUG(dev))
> + return 0;
> +
> /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
> * on the line. */
> if (IS_I945G(dev) || IS_I945GM(dev))
> --
> 2.0.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915: Make hpd arrays big enough to avoid out of bounds access
2015-01-09 14:41 ` [Intel-gfx] " Jani Nikula
@ 2015-01-09 15:27 ` Ville Syrjälä
0 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjälä @ 2015-01-09 15:27 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Egbert Eich, stable
On Fri, Jan 09, 2015 at 04:41:33PM +0200, Jani Nikula wrote:
> On Fri, 09 Jan 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > intel_hpd_irq_handler() walks the passed in hpd[] array assuming it
> > contains HPD_NUM_PINS elements. Currently that's not true as we don't
> > specify an explicit size for the arrays when initializing them. Avoid
> > the out of bounds accesses by specifying the size for the arrays.
>
> My first impression was wowowow, this must fix some of those obscure hpd
> bugs we seem to have. But no, all of the arrays have HPD_PORT_D which
> means we don't go out of bounds. This patch doesn't change the sizes of
> the arrays.
Hmm, I somehow convinced myself that PORT_D wasn't in all of them.
I suppose I was thinking that port D isn't around on all platforms
and then thought the same will hold for the arrays without actually
checking. That does make the patch a bit less interesting.
>
> > Cc: stable@vger.kernel.org
>
> I'm not sure if that's appropriate in light of the above ("It must fix a
> real bug that bothers people").
>
Yeah I guess we can drop the stable then.
> But we should do this *before* it becomes a bug.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 818ab4e..1d52ae9 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -45,7 +45,7 @@
> > * and related files, but that will be described in separate chapters.
> > */
> >
> > -static const u32 hpd_ibx[] = {
> > +static const u32 hpd_ibx[HPD_NUM_PINS] = {
> > [HPD_CRT] = SDE_CRT_HOTPLUG,
> > [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
> > [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
> > @@ -53,7 +53,7 @@ static const u32 hpd_ibx[] = {
> > [HPD_PORT_D] = SDE_PORTD_HOTPLUG
> > };
> >
> > -static const u32 hpd_cpt[] = {
> > +static const u32 hpd_cpt[HPD_NUM_PINS] = {
> > [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
> > [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
> > [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
> > @@ -61,7 +61,7 @@ static const u32 hpd_cpt[] = {
> > [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
> > };
> >
> > -static const u32 hpd_mask_i915[] = {
> > +static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
> > [HPD_CRT] = CRT_HOTPLUG_INT_EN,
> > [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
> > [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
> > @@ -70,7 +70,7 @@ static const u32 hpd_mask_i915[] = {
> > [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
> > };
> >
> > -static const u32 hpd_status_g4x[] = {
> > +static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
> > [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
> > [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
> > [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
> > @@ -79,7 +79,7 @@ static const u32 hpd_status_g4x[] = {
> > [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
> > };
> >
> > -static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
> > +static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */
> > [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
> > [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
> > [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
> > @@ -1522,7 +1522,7 @@ static inline enum port get_port_from_pin(enum hpd_pin pin)
> > static inline void intel_hpd_irq_handler(struct drm_device *dev,
> > u32 hotplug_trigger,
> > u32 dig_hotplug_reg,
> > - const u32 *hpd)
> > + const u32 hpd[HPD_NUM_PINS])
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > int i;
> > --
> > 2.0.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 7/7] drm/i915: Disable HPD for disabled eDP ports
2015-01-09 12:21 ` [PATCH 7/7] drm/i915: Disable HPD for disabled eDP ports ville.syrjala
@ 2015-01-09 17:47 ` shuang.he
0 siblings, 0 replies; 19+ messages in thread
From: shuang.he @ 2015-01-09 17:47 UTC (permalink / raw)
To: shuang.he, intel-gfx, ville.syrjala
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -31 363/364 332/364
ILK -38 364/365 326/365
SNB +4-65 443/450 382/450
IVB -44 496/498 452/498
BYT -8 288/289 280/289
HSW +19-69 542/564 492/564
BDW -25 406/407 381/407
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-bcs-overwrite-source NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-rcs-early-read NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-rcs-overwrite-source NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-bcs-early-read NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-bcs-overwrite-source NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-rcs-early-read NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-rcs-overwrite-source NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible NSPT(7, M23M25)PASS(1, M25) NSPT(1, M25)
PNV igt_gem_pread_after_blit_interruptible NRUN(2, M23M25)PASS(1, M25) NRUN(1, M25)
PNV igt_gem_pread_after_blit_interruptible-display NRUN(2, M23M25)PASS(1, M25) NRUN(1, M25)
PNV igt_gem_pread_after_blit_interruptible-snoop NRUN(2, M23M25)PASS(1, M25) NRUN(1, M25)
PNV igt_gem_pread_after_blit_interruptible-uncached NRUN(2, M23M25)PASS(1, M25) NRUN(1, M25)
PNV igt_gem_pread_after_blit_normal NRUN(2, M23M25)PASS(1, M25) NRUN(1, M25)
PNV igt_gem_pread_after_blit_normal-display NRUN(2, M23M25)PASS(1, M25) NRUN(1, M25)
PNV igt_gem_pread_after_blit_normal-snoop NRUN(2, M23M25)PASS(1, M25) NRUN(1, M25)
PNV igt_gem_pread_after_blit_normal-uncached NRUN(2, M23M25)PASS(1, M25) NRUN(1, M25)
ILK igt_gem_concurrent_blit_gpu-bcs-early-read NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpu-bcs-overwrite-source NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpuX-bcs-early-read NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpuX-bcs-overwrite-source NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible NSPT(7, M26M37)PASS(1, M37) NSPT(1, M26)
ILK igt_gem_pread_after_blit_interruptible NRUN(2, M26M37)PASS(1, M37) NRUN(1, M26)
ILK igt_gem_pread_after_blit_interruptible-display NRUN(2, M26M37)PASS(1, M37) NRUN(1, M26)
ILK igt_gem_pread_after_blit_interruptible-snoop NRUN(2, M26M37)PASS(1, M37) NRUN(1, M26)
ILK igt_gem_pread_after_blit_interruptible-uncached NRUN(2, M26M37)PASS(1, M37) NRUN(1, M26)
ILK igt_gem_pread_after_blit_normal NRUN(2, M26M37)PASS(1, M37) NRUN(1, M26)
ILK igt_gem_pread_after_blit_normal-display NRUN(2, M26M37)PASS(1, M37) NRUN(1, M26)
ILK igt_gem_pread_after_blit_normal-snoop NRUN(2, M26M37)PASS(1, M37) NRUN(1, M26)
ILK igt_gem_pread_after_blit_normal-uncached NRUN(2, M26M37)PASS(1, M37) NRUN(1, M26)
ILK igt_kms_flip_nonexisting-fb DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_render_direct-render DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_bcs-flip-vs-modeset-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_blocking-absolute-wf_vblank-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_busy-flip-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_flip-vs-dpms-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_flip-vs-panning DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_flip-vs-rmfb-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_plain-flip-fb-recreate-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_plain-flip-ts-check-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_rcs-flip-vs-dpms DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_rcs-flip-vs-modeset DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_rcs-flip-vs-panning DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_rcs-flip-vs-panning-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_vblank-vs-hang DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_wf_vblank-ts-check DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
ILK igt_kms_flip_wf_vblank-vs-modeset-interruptible DMESG_WARN(4, M26)PASS(1, M37) DMESG_WARN(1, M26)
SNB igt_gem_concurrent_blit_gpu-bcs-early-read NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-bcs-early-read-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-bcs-overwrite-source NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-rcs-early-read NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-rcs-overwrite-source NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-bcs-early-read NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-bcs-early-read-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-bcs-overwrite-source NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-rcs-early-read NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-rcs-early-read-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-rcs-overwrite-source NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible NSPT(7, M22M35)PASS(1, M35) NSPT(1, M22)
SNB igt_gem_pread_after_blit_interruptible NRUN(3, M22M35)PASS(1, M35) NRUN(1, M22)
SNB igt_gem_pread_after_blit_interruptible-display NRUN(3, M22M35)PASS(1, M35) NRUN(1, M22)
SNB igt_gem_pread_after_blit_interruptible-snoop NRUN(3, M22M35)PASS(1, M35) NRUN(1, M22)
SNB igt_gem_pread_after_blit_interruptible-uncached NRUN(3, M22M35)PASS(1, M35) NRUN(1, M22)
SNB igt_gem_pread_after_blit_normal NRUN(3, M22M35)PASS(1, M35) NRUN(1, M22)
SNB igt_gem_pread_after_blit_normal-display NRUN(3, M22M35)PASS(1, M35) NRUN(1, M22)
SNB igt_gem_pread_after_blit_normal-snoop NRUN(3, M22M35)PASS(1, M35) NRUN(1, M22)
SNB igt_gem_pread_after_blit_normal-uncached NRUN(3, M22M35)PASS(1, M35) NRUN(1, M22)
SNB igt_kms_cursor_crc_cursor-size-change NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_kms_flip_dpms-vs-vblank-race DMESG_WARN(3, M35M22)PASS(6, M35M22) PASS(1, M22)
SNB igt_kms_flip_dpms-vs-vblank-race-interruptible DMESG_WARN(2, M35M22)PASS(7, M35M22) PASS(1, M22)
SNB igt_kms_flip_event_leak NSPT(5, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_kms_flip_modeset-vs-vblank-race DMESG_WARN(4, M35M22)PASS(6, M35M22) PASS(1, M22)
SNB igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_kms_plane_plane-position-hole-pipe-B-plane-1 DMESG_WARN(1, M35)PASS(10, M35M22) PASS(1, M22)
SNB igt_kms_rotation_crc_primary-rotation NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_kms_rotation_crc_sprite-rotation NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_cursor NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_cursor-dpms NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_dpms-non-lpsp NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_drm-resources-equal NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_fences NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_fences-dpms NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_gem-execbuf NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_gem-mmap-cpu NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_gem-mmap-gtt NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_gem-pread NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_i2c NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_modeset-non-lpsp NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_pci-d3-state NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
SNB igt_pm_rpm_rte NSPT(6, M35M22)PASS(1, M35) NSPT(1, M22)
*SNB igt_gem_concurrent_blit_gtt-rcs-overwrite-source-forked PASS(1, M35) DMESG_WARN(1, M22)
IVB igt_gem_concurrent_blit_gpu-bcs-early-read NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-bcs-early-read-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-bcs-overwrite-source NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-rcs-early-read NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-rcs-early-read-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-rcs-overwrite-source NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-bcs-early-read NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-bcs-early-read-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-bcs-overwrite-source NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-rcs-early-read NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-rcs-early-read-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-rcs-overwrite-source NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible NSPT(7, M21M34M4)PASS(1, M34) NSPT(1, M4)
IVB igt_gem_pread_after_blit_interruptible NRUN(2, M21M4)PASS(1, M34) NRUN(1, M4)
IVB igt_gem_pread_after_blit_interruptible-display NRUN(2, M21M4)PASS(1, M34) NRUN(1, M4)
IVB igt_gem_pread_after_blit_interruptible-snoop NRUN(2, M21M4)PASS(1, M34) NRUN(1, M4)
IVB igt_gem_pread_after_blit_interruptible-uncached NRUN(2, M21M4)PASS(1, M34) NRUN(1, M4)
IVB igt_gem_pread_after_blit_normal NRUN(2, M21M4)PASS(1, M34) NRUN(1, M4)
IVB igt_gem_pread_after_blit_normal-display NRUN(2, M21M4)PASS(1, M34) NRUN(1, M4)
IVB igt_gem_pread_after_blit_normal-snoop NRUN(2, M21M4)PASS(1, M34) NRUN(1, M4)
IVB igt_gem_pread_after_blit_normal-uncached NRUN(2, M21M4)PASS(1, M34) NRUN(1, M4)
*BYT igt_gem_pread_after_blit_interruptible NRUN(2, M51)PASS(1, M48) NRUN(1, M50)
*BYT igt_gem_pread_after_blit_interruptible-display NRUN(2, M51)PASS(1, M48) NRUN(1, M50)
*BYT igt_gem_pread_after_blit_interruptible-snoop NRUN(2, M51)PASS(1, M48) NRUN(1, M50)
*BYT igt_gem_pread_after_blit_interruptible-uncached NRUN(2, M51)PASS(1, M48) NRUN(1, M50)
*BYT igt_gem_pread_after_blit_normal NRUN(2, M51)PASS(1, M48) NRUN(1, M50)
*BYT igt_gem_pread_after_blit_normal-display NRUN(2, M51)PASS(1, M48) NRUN(1, M50)
*BYT igt_gem_pread_after_blit_normal-snoop NRUN(2, M51)PASS(1, M48) NRUN(1, M50)
*BYT igt_gem_pread_after_blit_normal-uncached NRUN(2, M51)PASS(1, M48) NRUN(1, M50)
HSW igt_gem_concurrent_blit_gpu-bcs-early-read NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-bcs-early-read-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-bcs-overwrite-source NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-rcs-early-read NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-rcs-early-read-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-rcs-overwrite-source NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-bcs-early-read NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-bcs-early-read-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-bcs-overwrite-source NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-rcs-early-read NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-rcs-early-read-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-rcs-overwrite-source NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible NSPT(7, M19M20M40)PASS(1, M40) NSPT(1, M19)
HSW igt_gem_pread_after_blit_interruptible NRUN(2, M19)PASS(1, M40) NRUN(1, M19)
HSW igt_gem_pread_after_blit_interruptible-display NRUN(2, M19)PASS(1, M40) NRUN(1, M19)
HSW igt_gem_pread_after_blit_interruptible-snoop NRUN(2, M19)PASS(1, M40) NRUN(1, M19)
HSW igt_gem_pread_after_blit_interruptible-uncached NRUN(2, M19)PASS(1, M40) NRUN(1, M19)
HSW igt_gem_pread_after_blit_normal NRUN(2, M19)PASS(1, M40) NRUN(1, M19)
HSW igt_gem_pread_after_blit_normal-display NRUN(2, M19)PASS(1, M40) NRUN(1, M19)
HSW igt_gem_pread_after_blit_normal-snoop NRUN(2, M19)PASS(1, M40) NRUN(1, M19)
HSW igt_gem_pread_after_blit_normal-uncached NRUN(2, M19)PASS(1, M40) NRUN(1, M19)
HSW igt_kms_cursor_crc_cursor-size-change NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_kms_fence_pin_leak NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_kms_flip_dpms-vs-vblank-race DMESG_WARN(1, M40)PASS(5, M19M20) PASS(1, M19)
HSW igt_kms_flip_dpms-vs-vblank-race-interruptible DMESG_WARN(2, M40)PASS(5, M19M20) PASS(1, M19)
HSW igt_kms_flip_event_leak NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_kms_flip_flip-vs-dpms-off-vs-modeset DMESG_WARN(1, M40)PASS(5, M19M20) PASS(1, M19)
HSW igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(2, M40M19)PASS(5, M19M20) PASS(1, M19)
HSW igt_kms_flip_modeset-vs-vblank-race DMESG_WARN(1, M40)PASS(5, M19M20) PASS(1, M19)
HSW igt_kms_flip_modeset-vs-vblank-race-interruptible DMESG_WARN(1, M40)PASS(5, M19M20) PASS(1, M19)
HSW igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(2, M40)PASS(6, M19M20) PASS(1, M19)
HSW igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_kms_pipe_crc_basic_read-crc-pipe-B TIMEOUT(1, M40)PASS(3, M19) PASS(1, M19)
HSW igt_kms_pipe_crc_basic_read-crc-pipe-B-frame-sequence TIMEOUT(1, M40)PASS(3, M19) PASS(1, M19)
HSW igt_kms_pipe_crc_basic_read-crc-pipe-C TIMEOUT(1, M40)PASS(3, M19) PASS(1, M19)
HSW igt_kms_pipe_crc_basic_read-crc-pipe-C-frame-sequence TIMEOUT(1, M40)PASS(3, M19) PASS(1, M19)
HSW igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-1 TIMEOUT(1, M40)PASS(3, M19) PASS(1, M19)
HSW igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-2 TIMEOUT(1, M40)PASS(3, M19) PASS(1, M19)
HSW igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-1 TIMEOUT(1, M40)PASS(4, M19M20) PASS(1, M19)
HSW igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2 TIMEOUT(1, M40)PASS(4, M19M20) PASS(1, M19)
HSW igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-1 TIMEOUT(3, M40)PASS(7, M19M40M20) PASS(1, M19)
HSW igt_kms_setmode_invalid-clone-exclusive-crtc DMESG_WARN(1, M40)PASS(3, M19) PASS(1, M19)
HSW igt_pm_lpsp_non-edp NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_cursor NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_cursor-dpms NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_dpms-non-lpsp NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_drm-resources-equal NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_fences NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_fences-dpms NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_gem-execbuf NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_gem-mmap-cpu NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_gem-mmap-gtt NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_gem-pread NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_i2c NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_modeset-non-lpsp NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(4, M19)DMESG_WARN(1, M40)PASS(5, M40M20) NSPT(1, M19)
HSW igt_pm_rpm_pci-d3-state NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
HSW igt_pm_rpm_rte NSPT(3, M19)PASS(1, M40) NSPT(1, M19)
*HSW igt_gem_concurrent_blit_gtt-bcs-early-read-forked PASS(2, M40M19) DMESG_WARN(1, M19)
*HSW igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-forked PASS(1, M40) DMESG_WARN(1, M19)
*HSW igt_gem_concurrent_blit_gtt-rcs-early-read-forked PASS(1, M40) DMESG_WARN(1, M19)
*HSW igt_gem_concurrent_blit_gttX-bcs-overwrite-source-forked PASS(1, M40) DMESG_WARN(1, M19)
HSW igt_kms_flip_flip-vs-rmfb DMESG_WARN(1, M40)PASS(4, M19) PASS(1, M19)
HSW igt_kms_flip_flip-vs-rmfb-interruptible DMESG_WARN(1, M40)PASS(3, M19) PASS(1, M19)
BDW igt_gem_concurrent_blit_gpu-bcs-early-read NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-bcs-overwrite-source NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-rcs-early-read NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-rcs-overwrite-source NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-bcs-early-read NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-bcs-overwrite-source NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-rcs-early-read NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-rcs-overwrite-source NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
BDW igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible NSPT(7, M28M30)PASS(1, M30) NSPT(1, M28)
*BDW igt_gem_concurrent_blit_gtt-bcs-early-read-interruptible PASS(2, M30M28) DMESG_WARN(1, M28)
Note: You need to pay more attention to line start with '*'
_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/7] drm/i915: Don't register HDMI connectors for eDP ports on VLV/CHV
2015-01-09 15:02 ` Jani Nikula
@ 2015-01-12 23:48 ` Daniel Vetter
0 siblings, 0 replies; 19+ messages in thread
From: Daniel Vetter @ 2015-01-12 23:48 UTC (permalink / raw)
To: Jani Nikula; +Cc: Egbert Eich, intel-gfx
On Fri, Jan 09, 2015 at 05:02:40PM +0200, Jani Nikula wrote:
> On Fri, 09 Jan 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > If we determine that a specific port is eDP, don't register the HDMI
> > connector/encoder for it. The reason being that we want to disable
> > HPD interrupts for eDP ports when the display is off, but the presence
> > of the extra HDMI connector would demand the HPD interrupt to remain
> > enabled all the time.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index d1a4de8..2b1f220 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -12390,14 +12390,16 @@ static void intel_setup_outputs(struct drm_device *dev)
> > * eDP ports. Consult the VBT as well as DP_DETECTED to
> > * detect eDP ports.
> > */
> > - if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
> > + if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
> > + !intel_dp_is_edp(dev, PORT_B))
> > intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
> > PORT_B);
> > if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
> > intel_dp_is_edp(dev, PORT_B))
> > intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
>
> I wonder if these would read better with
>
> if (intel_dp_is_edp(dev, PORT_B)) {
> ...
> } else {
> if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
> ...
> if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
> ...
> }
>
> Dunno. Either way,
Imo if we want to polish the turd here I think it might be beter to push
checks down into the various intel_<encoder>_init functions, and just have
the logic for deciding which ports a platform has at most here (and at
which reg offsets). Atm we have a crazy mix of checks both here and there.
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Anyway, merged, thanks for patch and review.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915
2015-01-09 12:21 ` [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915 ville.syrjala
2015-01-09 15:04 ` Jani Nikula
@ 2015-01-12 23:48 ` Daniel Vetter
2015-01-16 10:57 ` Ville Syrjälä
1 sibling, 1 reply; 19+ messages in thread
From: Daniel Vetter @ 2015-01-12 23:48 UTC (permalink / raw)
To: Syrjala, Ville; +Cc: Egbert Eich, intel-gfx
On Fri, Jan 09, 2015 at 02:21:15PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> 915 doens't support hotplug at all, so we shouldn't try to pretend
> otherwise in the SDVO code.
It actually has a hpd pin, but since it's just one for all ports we
haven't ever used it. Probably would't work well when facing an irq storm.
I'll augment the commit message jus to clarify.
-Daniel
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_sdvo.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 6d7a277..4e3d362 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1617,6 +1617,9 @@ static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
> struct drm_device *dev = intel_sdvo->base.base.dev;
> uint16_t hotplug;
>
> + if (!I915_HAS_HOTPLUG(dev))
> + return 0;
> +
> /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
> * on the line. */
> if (IS_I945G(dev) || IS_I945GM(dev))
> --
> 2.0.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports
2015-01-09 12:21 [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports ville.syrjala
` (6 preceding siblings ...)
2015-01-09 12:21 ` [PATCH 7/7] drm/i915: Disable HPD for disabled eDP ports ville.syrjala
@ 2015-01-13 0:46 ` Sean V Kelley
2015-01-13 9:36 ` Ville Syrjälä
7 siblings, 1 reply; 19+ messages in thread
From: Sean V Kelley @ 2015-01-13 0:46 UTC (permalink / raw)
To: intel-gfx
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 01/09/2015 04:21 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> My BSW has a nasty problem where it generates tons of spurious hpd
> interrupts when the eDP display is disabled. The best solution
> seems to be to disable hpd for eDP ports when the port is disabled
> since we don't care about long hpds anyway and short hpds are only
> relevant while the link is up and running.
>
How did these spurious interrupts affect your system? Did you see
this on both B and C Stepping?
Sean
> This series tries to implement that, and I've included a few
> random fixes/refactorings to the hpd code as well.
>
> Ville Syrjälä (7): drm/i915: Make hpd arrays big enough to avoid
> out of bounds access drm/i915: Remove I915_HAS_HOTPLUG() check from
> i915_hpd_irq_setup() drm/i915: Don't register HDMI connectors for
> eDP ports on VLV/CHV drm/i915: Don't pretend SDVO hotplug works on
> 915 drm/i915: Set intel_connector->polled to DRM_CONNECTOR_POLL_HPD
> when appropriate drm/i915: Unify hpd setup between init and hpd
> storm handling drm/i915: Disable HPD for disabled eDP ports
>
> drivers/gpu/drm/i915/i915_irq.c | 172
> ++++++++++++++++++++---------------
> drivers/gpu/drm/i915/intel_crt.c | 4 +-
> drivers/gpu/drm/i915/intel_display.c | 6 +-
> drivers/gpu/drm/i915/intel_dp.c | 18 ++++
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +
> drivers/gpu/drm/i915/intel_drv.h | 3 +
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +
> drivers/gpu/drm/i915/intel_sdvo.c | 4 + 8 files changed, 136
> insertions(+), 75 deletions(-)
>
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports
2015-01-13 0:46 ` [PATCH 0/7] drm/i915: Disable hpd " Sean V Kelley
@ 2015-01-13 9:36 ` Ville Syrjälä
0 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjälä @ 2015-01-13 9:36 UTC (permalink / raw)
To: Sean V Kelley; +Cc: intel-gfx
On Mon, Jan 12, 2015 at 04:46:12PM -0800, Sean V Kelley wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>
>
> On 01/09/2015 04:21 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > My BSW has a nasty problem where it generates tons of spurious hpd
> > interrupts when the eDP display is disabled. The best solution
> > seems to be to disable hpd for eDP ports when the port is disabled
> > since we don't care about long hpds anyway and short hpds are only
> > relevant while the link is up and running.
> >
>
> How did these spurious interrupts affect your system?
You get tons of debug spew from the kernel. In fact occasionally so much
that there's a feedback loop where the debug prints cause more noise on
the hpd line to generate more spurious interrupts. It could become bad
enoguh that the machine was pretty much dead, just constantly printing
hpd debug messages.
> Did you see this on both B and C Stepping?
Yep. It's probably more or a board issue.
>
> Sean
>
>
>
> > This series tries to implement that, and I've included a few
> > random fixes/refactorings to the hpd code as well.
> >
> > Ville Syrjälä (7): drm/i915: Make hpd arrays big enough to avoid
> > out of bounds access drm/i915: Remove I915_HAS_HOTPLUG() check from
> > i915_hpd_irq_setup() drm/i915: Don't register HDMI connectors for
> > eDP ports on VLV/CHV drm/i915: Don't pretend SDVO hotplug works on
> > 915 drm/i915: Set intel_connector->polled to DRM_CONNECTOR_POLL_HPD
> > when appropriate drm/i915: Unify hpd setup between init and hpd
> > storm handling drm/i915: Disable HPD for disabled eDP ports
> >
> > drivers/gpu/drm/i915/i915_irq.c | 172
> > ++++++++++++++++++++---------------
> > drivers/gpu/drm/i915/intel_crt.c | 4 +-
> > drivers/gpu/drm/i915/intel_display.c | 6 +-
> > drivers/gpu/drm/i915/intel_dp.c | 18 ++++
> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +
> > drivers/gpu/drm/i915/intel_drv.h | 3 +
> > drivers/gpu/drm/i915/intel_hdmi.c | 2 +
> > drivers/gpu/drm/i915/intel_sdvo.c | 4 + 8 files changed, 136
> > insertions(+), 75 deletions(-)
> >
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> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915
2015-01-12 23:48 ` Daniel Vetter
@ 2015-01-16 10:57 ` Ville Syrjälä
0 siblings, 0 replies; 19+ messages in thread
From: Ville Syrjälä @ 2015-01-16 10:57 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Egbert Eich, intel-gfx
On Tue, Jan 13, 2015 at 12:48:47AM +0100, Daniel Vetter wrote:
> On Fri, Jan 09, 2015 at 02:21:15PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > 915 doens't support hotplug at all, so we shouldn't try to pretend
> > otherwise in the SDVO code.
>
> It actually has a hpd pin, but since it's just one for all ports we
> haven't ever used it.
You learn something new every day.
> Probably would't work well when facing an irq storm.
irq storm handling is already pretty hosed for DP++ ports for the same
reason.
>
> I'll augment the commit message jus to clarify.
> -Daniel
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_sdvo.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> > index 6d7a277..4e3d362 100644
> > --- a/drivers/gpu/drm/i915/intel_sdvo.c
> > +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> > @@ -1617,6 +1617,9 @@ static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
> > struct drm_device *dev = intel_sdvo->base.base.dev;
> > uint16_t hotplug;
> >
> > + if (!I915_HAS_HOTPLUG(dev))
> > + return 0;
> > +
> > /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
> > * on the line. */
> > if (IS_I945G(dev) || IS_I945GM(dev))
> > --
> > 2.0.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2015-01-16 10:57 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-09 12:21 [PATCH 0/7] drm/i915: Disable hpd for disabled eDP ports ville.syrjala
2015-01-09 12:21 ` [PATCH 1/7] drm/i915: Make hpd arrays big enough to avoid out of bounds access ville.syrjala
2015-01-09 14:41 ` [Intel-gfx] " Jani Nikula
2015-01-09 15:27 ` Ville Syrjälä
2015-01-09 12:21 ` [PATCH 2/7] drm/i915: Remove I915_HAS_HOTPLUG() check from i915_hpd_irq_setup() ville.syrjala
2015-01-09 14:52 ` Jani Nikula
2015-01-09 12:21 ` [PATCH 3/7] drm/i915: Don't register HDMI connectors for eDP ports on VLV/CHV ville.syrjala
2015-01-09 15:02 ` Jani Nikula
2015-01-12 23:48 ` Daniel Vetter
2015-01-09 12:21 ` [PATCH 4/7] drm/i915: Don't pretend SDVO hotplug works on 915 ville.syrjala
2015-01-09 15:04 ` Jani Nikula
2015-01-12 23:48 ` Daniel Vetter
2015-01-16 10:57 ` Ville Syrjälä
2015-01-09 12:21 ` [PATCH 5/7] drm/i915: Set intel_connector->polled to DRM_CONNECTOR_POLL_HPD when appropriate ville.syrjala
2015-01-09 12:21 ` [PATCH 6/7] drm/i915: Unify hpd setup between init and hpd storm handling ville.syrjala
2015-01-09 12:21 ` [PATCH 7/7] drm/i915: Disable HPD for disabled eDP ports ville.syrjala
2015-01-09 17:47 ` shuang.he
2015-01-13 0:46 ` [PATCH 0/7] drm/i915: Disable hpd " Sean V Kelley
2015-01-13 9:36 ` Ville Syrjälä
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