* [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier
@ 2015-01-13 22:15 Xander Huff
2015-01-13 22:15 ` [PATCH 2/2] net/macb: improved ethtool statistics support Xander Huff
` (3 more replies)
0 siblings, 4 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-13 22:15 UTC (permalink / raw)
To: nicolas.ferre
Cc: jaeden.amero, rich.tollerton, ben.shelton, brad.mouring, netdev,
linux-kernel, Xander Huff
This change is to help improve at-a-glace knowledge of the purpose of the
various Cadence MACB/GEM registers. Comments are more helpful for human
readability than short acronyms.
Describe various #define varibles Cadence MACB/GEM registers as documented
in Xilinix's "Zynq-7000 All Programmable SoC TechnicalReference Manual, v1.9.1
(UG-585)"
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
drivers/net/ethernet/cadence/macb.h | 269 ++++++++++++++++++++++--------------
1 file changed, 162 insertions(+), 107 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 084191b..8e8c3c9 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -15,20 +15,20 @@
#define MACB_MAX_QUEUES 8
/* MACB register offsets */
-#define MACB_NCR 0x0000
-#define MACB_NCFGR 0x0004
-#define MACB_NSR 0x0008
+#define MACB_NCR 0x0000 /* Network Control */
+#define MACB_NCFGR 0x0004 /* Network Config */
+#define MACB_NSR 0x0008 /* Network Status */
#define MACB_TAR 0x000c /* AT91RM9200 only */
#define MACB_TCR 0x0010 /* AT91RM9200 only */
-#define MACB_TSR 0x0014
-#define MACB_RBQP 0x0018
-#define MACB_TBQP 0x001c
-#define MACB_RSR 0x0020
-#define MACB_ISR 0x0024
-#define MACB_IER 0x0028
-#define MACB_IDR 0x002c
-#define MACB_IMR 0x0030
-#define MACB_MAN 0x0034
+#define MACB_TSR 0x0014 /* Transmit Status */
+#define MACB_RBQP 0x0018 /* RX Q Base Address */
+#define MACB_TBQP 0x001c /* TX Q Base Address */
+#define MACB_RSR 0x0020 /* Receive Status */
+#define MACB_ISR 0x0024 /* Interrupt Status */
+#define MACB_IER 0x0028 /* Interrupt Enable */
+#define MACB_IDR 0x002c /* Interrupt Disable */
+#define MACB_IMR 0x0030 /* Interrupt Mask */
+#define MACB_MAN 0x0034 /* PHY Maintenance */
#define MACB_PTR 0x0038
#define MACB_PFR 0x003c
#define MACB_FTO 0x0040
@@ -68,27 +68,27 @@
#define MACB_MID 0x00fc
/* GEM register offsets. */
-#define GEM_NCFGR 0x0004
-#define GEM_USRIO 0x000c
-#define GEM_DMACFG 0x0010
-#define GEM_HRB 0x0080
-#define GEM_HRT 0x0084
-#define GEM_SA1B 0x0088
-#define GEM_SA1T 0x008C
-#define GEM_SA2B 0x0090
-#define GEM_SA2T 0x0094
-#define GEM_SA3B 0x0098
-#define GEM_SA3T 0x009C
-#define GEM_SA4B 0x00A0
-#define GEM_SA4T 0x00A4
-#define GEM_OTX 0x0100
-#define GEM_DCFG1 0x0280
-#define GEM_DCFG2 0x0284
-#define GEM_DCFG3 0x0288
-#define GEM_DCFG4 0x028c
-#define GEM_DCFG5 0x0290
-#define GEM_DCFG6 0x0294
-#define GEM_DCFG7 0x0298
+#define GEM_NCFGR 0x0004 /* Network Config */
+#define GEM_USRIO 0x000c /* User IO */
+#define GEM_DMACFG 0x0010 /* DMA Configuration */
+#define GEM_HRB 0x0080 /* Hash Bottom */
+#define GEM_HRT 0x0084 /* Hash Top */
+#define GEM_SA1B 0x0088 /* Specific1 Bottom */
+#define GEM_SA1T 0x008C /* Specific1 Top */
+#define GEM_SA2B 0x0090 /* Specific2 Bottom */
+#define GEM_SA2T 0x0094 /* Specific2 Top */
+#define GEM_SA3B 0x0098 /* Specific3 Bottom */
+#define GEM_SA3T 0x009C /* Specific3 Top */
+#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
+#define GEM_SA4T 0x00A4 /* Specific4 Top */
+#define GEM_OTX 0x0100 /* Octets transmitted */
+#define GEM_DCFG1 0x0280 /* Design Config 1 */
+#define GEM_DCFG2 0x0284 /* Design Config 2 */
+#define GEM_DCFG3 0x0288 /* Design Config 3 */
+#define GEM_DCFG4 0x028c /* Design Config 4 */
+#define GEM_DCFG5 0x0290 /* Design Config 5 */
+#define GEM_DCFG6 0x0294 /* Design Config 6 */
+#define GEM_DCFG7 0x0298 /* Design Config 7 */
#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
@@ -98,67 +98,73 @@
#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
/* Bitfields in NCR */
-#define MACB_LB_OFFSET 0
+#define MACB_LB_OFFSET 0 /* reserved */
#define MACB_LB_SIZE 1
-#define MACB_LLB_OFFSET 1
+#define MACB_LLB_OFFSET 1 /* Loop back local */
#define MACB_LLB_SIZE 1
-#define MACB_RE_OFFSET 2
+#define MACB_RE_OFFSET 2 /* Receive enable */
#define MACB_RE_SIZE 1
-#define MACB_TE_OFFSET 3
+#define MACB_TE_OFFSET 3 /* Transmit enable */
#define MACB_TE_SIZE 1
-#define MACB_MPE_OFFSET 4
+#define MACB_MPE_OFFSET 4 /* Management port enable */
#define MACB_MPE_SIZE 1
-#define MACB_CLRSTAT_OFFSET 5
+#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
#define MACB_CLRSTAT_SIZE 1
-#define MACB_INCSTAT_OFFSET 6
+#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
#define MACB_INCSTAT_SIZE 1
-#define MACB_WESTAT_OFFSET 7
+#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
#define MACB_WESTAT_SIZE 1
-#define MACB_BP_OFFSET 8
+#define MACB_BP_OFFSET 8 /* Back pressure */
#define MACB_BP_SIZE 1
-#define MACB_TSTART_OFFSET 9
+#define MACB_TSTART_OFFSET 9 /* Start transmission */
#define MACB_TSTART_SIZE 1
-#define MACB_THALT_OFFSET 10
+#define MACB_THALT_OFFSET 10 /* Transmit halt */
#define MACB_THALT_SIZE 1
-#define MACB_NCR_TPF_OFFSET 11
+#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
#define MACB_NCR_TPF_SIZE 1
-#define MACB_TZQ_OFFSET 12
+#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum
+ * pause frame
+ */
#define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */
-#define MACB_SPD_OFFSET 0
+#define MACB_SPD_OFFSET 0 /* Speed */
#define MACB_SPD_SIZE 1
-#define MACB_FD_OFFSET 1
+#define MACB_FD_OFFSET 1 /* Full duplex */
#define MACB_FD_SIZE 1
-#define MACB_BIT_RATE_OFFSET 2
+#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
#define MACB_BIT_RATE_SIZE 1
-#define MACB_JFRAME_OFFSET 3
+#define MACB_JFRAME_OFFSET 3 /* reserved */
#define MACB_JFRAME_SIZE 1
-#define MACB_CAF_OFFSET 4
+#define MACB_CAF_OFFSET 4 /* Copy all frames */
#define MACB_CAF_SIZE 1
-#define MACB_NBC_OFFSET 5
+#define MACB_NBC_OFFSET 5 /* No broadcast */
#define MACB_NBC_SIZE 1
-#define MACB_NCFGR_MTI_OFFSET 6
+#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
#define MACB_NCFGR_MTI_SIZE 1
-#define MACB_UNI_OFFSET 7
+#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
#define MACB_UNI_SIZE 1
-#define MACB_BIG_OFFSET 8
+#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
#define MACB_BIG_SIZE 1
-#define MACB_EAE_OFFSET 9
+#define MACB_EAE_OFFSET 9 /* External address match
+ * enable
+ */
#define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2
-#define MACB_RTY_OFFSET 12
+#define MACB_RTY_OFFSET 12 /* Retry test */
#define MACB_RTY_SIZE 1
-#define MACB_PAE_OFFSET 13
+#define MACB_PAE_OFFSET 13 /* Pause enable */
#define MACB_PAE_SIZE 1
#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
-#define MACB_RBOF_OFFSET 14
+#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
#define MACB_RBOF_SIZE 2
-#define MACB_RLCE_OFFSET 16
+#define MACB_RLCE_OFFSET 16 /* Length field error frame
+ * discard
+ */
#define MACB_RLCE_SIZE 1
-#define MACB_DRFCS_OFFSET 17
+#define MACB_DRFCS_OFFSET 17 /* FCS remove */
#define MACB_DRFCS_SIZE 1
#define MACB_EFRHD_OFFSET 18
#define MACB_EFRHD_SIZE 1
@@ -166,111 +172,160 @@
#define MACB_IRXFCS_SIZE 1
/* GEM specific NCFGR bitfields. */
-#define GEM_GBE_OFFSET 10
+#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
#define GEM_GBE_SIZE 1
-#define GEM_CLK_OFFSET 18
+#define GEM_CLK_OFFSET 18 /* MDC clock division */
#define GEM_CLK_SIZE 3
-#define GEM_DBW_OFFSET 21
+#define GEM_DBW_OFFSET 21 /* Data bus width */
#define GEM_DBW_SIZE 2
#define GEM_RXCOEN_OFFSET 24
#define GEM_RXCOEN_SIZE 1
/* Constants for data bus width. */
-#define GEM_DBW32 0
-#define GEM_DBW64 1
-#define GEM_DBW128 2
+#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus
+ * width
+ */
+#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
+ * width
+ */
+#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
+ * width
+ */
/* Bitfields in DMACFG. */
-#define GEM_FBLDO_OFFSET 0
+#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for
+ * DMA data operations
+ */
#define GEM_FBLDO_SIZE 5
-#define GEM_ENDIA_OFFSET 7
+#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable
+ * for packet data accesses
+ */
#define GEM_ENDIA_SIZE 1
-#define GEM_RXBMS_OFFSET 8
+#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer
+ * memory size select
+ */
#define GEM_RXBMS_SIZE 2
-#define GEM_TXPBMS_OFFSET 10
+#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer
+ * memory size select
+ */
#define GEM_TXPBMS_SIZE 1
-#define GEM_TXCOEN_OFFSET 11
+#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and
+ * UDP checksum generation
+ * offload enable
+ */
#define GEM_TXCOEN_SIZE 1
-#define GEM_RXBS_OFFSET 16
+#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in
+ * AHB system memory
+ */
#define GEM_RXBS_SIZE 8
-#define GEM_DDRP_OFFSET 24
+#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
#define GEM_DDRP_SIZE 1
/* Bitfields in NSR */
-#define MACB_NSR_LINK_OFFSET 0
+#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
#define MACB_NSR_LINK_SIZE 1
-#define MACB_MDIO_OFFSET 1
+#define MACB_MDIO_OFFSET 1 /* status of the mdio_in
+ * pin
+ */
#define MACB_MDIO_SIZE 1
-#define MACB_IDLE_OFFSET 2
+#define MACB_IDLE_OFFSET 2 /* The PHY management logic is
+ * idle (i.e. has completed)
+ */
#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
-#define MACB_UBR_OFFSET 0
+#define MACB_UBR_OFFSET 0 /* Used bit read */
#define MACB_UBR_SIZE 1
-#define MACB_COL_OFFSET 1
+#define MACB_COL_OFFSET 1 /* Collision occurred */
#define MACB_COL_SIZE 1
-#define MACB_TSR_RLE_OFFSET 2
+#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
#define MACB_TSR_RLE_SIZE 1
-#define MACB_TGO_OFFSET 3
+#define MACB_TGO_OFFSET 3 /* Transmit go */
#define MACB_TGO_SIZE 1
-#define MACB_BEX_OFFSET 4
+#define MACB_BEX_OFFSET 4 /* Transmit frame corruption
+ * due to AHB error
+ */
#define MACB_BEX_SIZE 1
#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
-#define MACB_COMP_OFFSET 5
+#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
#define MACB_COMP_SIZE 1
-#define MACB_UND_OFFSET 6
+#define MACB_UND_OFFSET 6 /* Trnasmit under run */
#define MACB_UND_SIZE 1
/* Bitfields in RSR */
-#define MACB_BNA_OFFSET 0
+#define MACB_BNA_OFFSET 0 /* Buffer not available */
#define MACB_BNA_SIZE 1
-#define MACB_REC_OFFSET 1
+#define MACB_REC_OFFSET 1 /* Frame received */
#define MACB_REC_SIZE 1
-#define MACB_OVR_OFFSET 2
+#define MACB_OVR_OFFSET 2 /* Receive overrun */
#define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */
-#define MACB_MFD_OFFSET 0
+#define MACB_MFD_OFFSET 0 /* Management frame sent */
#define MACB_MFD_SIZE 1
-#define MACB_RCOMP_OFFSET 1
+#define MACB_RCOMP_OFFSET 1 /* Receive complete */
#define MACB_RCOMP_SIZE 1
-#define MACB_RXUBR_OFFSET 2
+#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
#define MACB_RXUBR_SIZE 1
-#define MACB_TXUBR_OFFSET 3
+#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
#define MACB_TXUBR_SIZE 1
-#define MACB_ISR_TUND_OFFSET 4
+#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer
+ * under run interrupt
+ */
#define MACB_ISR_TUND_SIZE 1
-#define MACB_ISR_RLE_OFFSET 5
+#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded
+ * or late collision interrupt
+ */
#define MACB_ISR_RLE_SIZE 1
-#define MACB_TXERR_OFFSET 6
+#define MACB_TXERR_OFFSET 6 /* Enable transmit frame
+ * corruption due to AHB error
+ * interrupt
+ */
#define MACB_TXERR_SIZE 1
-#define MACB_TCOMP_OFFSET 7
+#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete
+ * interrupt
+ */
#define MACB_TCOMP_SIZE 1
-#define MACB_ISR_LINK_OFFSET 9
+#define MACB_ISR_LINK_OFFSET 9 /* Enable link change
+ * interrupt
+ */
#define MACB_ISR_LINK_SIZE 1
-#define MACB_ISR_ROVR_OFFSET 10
+#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun
+ * interrupt
+ */
#define MACB_ISR_ROVR_SIZE 1
-#define MACB_HRESP_OFFSET 11
+#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK
+ * interrupt
+ */
#define MACB_HRESP_SIZE 1
-#define MACB_PFR_OFFSET 12
+#define MACB_PFR_OFFSET 12 /* Enable pause frame with
+ * non-zero pause quantum
+ * interrupt
+ */
#define MACB_PFR_SIZE 1
-#define MACB_PTZ_OFFSET 13
+#define MACB_PTZ_OFFSET 13 /* Enable pause time zero
+ * interrupt
+ */
#define MACB_PTZ_SIZE 1
/* Bitfields in MAN */
-#define MACB_DATA_OFFSET 0
+#define MACB_DATA_OFFSET 0 /* data */
#define MACB_DATA_SIZE 16
-#define MACB_CODE_OFFSET 16
+#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
#define MACB_CODE_SIZE 2
-#define MACB_REGA_OFFSET 18
+#define MACB_REGA_OFFSET 18 /* Register address */
#define MACB_REGA_SIZE 5
-#define MACB_PHYA_OFFSET 23
+#define MACB_PHYA_OFFSET 23 /* PHY address */
#define MACB_PHYA_SIZE 5
-#define MACB_RW_OFFSET 28
+#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01
+ * is write.
+ */
#define MACB_RW_SIZE 2
-#define MACB_SOF_OFFSET 30
+#define MACB_SOF_OFFSET 30 /* Must be written to 1 for
+ * Clause 22 operation
+ */
#define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */
@@ -286,7 +341,7 @@
/* Bitfields in USRIO (AT91) */
#define MACB_RMII_OFFSET 0
#define MACB_RMII_SIZE 1
-#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
+#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
#define GEM_RGMII_SIZE 1
#define MACB_CLKEN_OFFSET 1
#define MACB_CLKEN_SIZE 1
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 2/2] net/macb: improved ethtool statistics support
2015-01-13 22:15 [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier Xander Huff
@ 2015-01-13 22:15 ` Xander Huff
2015-01-14 5:26 ` David Miller
2015-01-14 15:53 ` Nicolas Ferre
2015-01-14 5:26 ` [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier David Miller
` (2 subsequent siblings)
3 siblings, 2 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-13 22:15 UTC (permalink / raw)
To: nicolas.ferre
Cc: jaeden.amero, rich.tollerton, ben.shelton, brad.mouring, netdev,
linux-kernel, Xander Huff
Currently `ethtool -S` simply returns "no stats available". It
would be more useful to see what the various ethtool statistics
registers' values are. This change implements get_ethtool_stats,
get_strings, and get_sset_count functions to accomplish this.
Read all GEM statistics registers and sum them into
macb.ethtool_stats. Add the necessary infrastructure to make this
accessible via `ethtool -S`.
Update gem_update_stats to utilize ethtool_stats.
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
drivers/net/ethernet/cadence/macb.c | 55 +++++++-
drivers/net/ethernet/cadence/macb.h | 256 ++++++++++++++++++++++++++++++++++++
2 files changed, 307 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 3767271..dd8c202 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1827,12 +1827,23 @@ static int macb_close(struct net_device *dev)
static void gem_update_stats(struct macb *bp)
{
- u32 __iomem *reg = bp->regs + GEM_OTX;
+ int i;
u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
- u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
- for (; p < end; p++, reg++)
- *p += __raw_readl(reg);
+ for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
+ u32 offset = gem_statistics[i].offset;
+ u64 val = __raw_readl(bp->regs+offset);
+
+ bp->ethtool_stats[i] += val;
+ *p += val;
+
+ if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
+ /* Add GEM_OCTTXH, GEM_OCTRXH */
+ val = __raw_readl(bp->regs+offset+4);
+ bp->ethtool_stats[i] += ((u64)val)<<32;
+ *(++p) += val;
+ }
+ }
}
static struct net_device_stats *gem_get_stats(struct macb *bp)
@@ -1873,6 +1884,39 @@ static struct net_device_stats *gem_get_stats(struct macb *bp)
return nstat;
}
+static void gem_get_ethtool_stats(struct net_device *dev,
+ struct ethtool_stats *stats, u64 *data)
+{
+ struct macb *bp;
+
+ bp = netdev_priv(dev);
+ gem_update_stats(bp);
+ memcpy(data, &bp->ethtool_stats, sizeof(u64)*GEM_STATS_LEN);
+}
+
+static int gem_get_sset_count(struct net_device *dev, int sset)
+{
+ switch (sset) {
+ case ETH_SS_STATS:
+ return GEM_STATS_LEN;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
+{
+ int i;
+
+ switch (sset) {
+ case ETH_SS_STATS:
+ for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
+ memcpy(p, gem_statistics[i].stat_string,
+ ETH_GSTRING_LEN);
+ break;
+ }
+}
+
struct net_device_stats *macb_get_stats(struct net_device *dev)
{
struct macb *bp = netdev_priv(dev);
@@ -1988,6 +2032,9 @@ const struct ethtool_ops macb_ethtool_ops = {
.get_regs = macb_get_regs,
.get_link = ethtool_op_get_link,
.get_ts_info = ethtool_op_get_ts_info,
+ .get_ethtool_stats = gem_get_ethtool_stats,
+ .get_strings = gem_get_ethtool_strings,
+ .get_sset_count = gem_get_sset_count,
};
EXPORT_SYMBOL_GPL(macb_ethtool_ops);
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 8e8c3c9..378b218 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -82,6 +82,159 @@
#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
#define GEM_SA4T 0x00A4 /* Specific4 Top */
#define GEM_OTX 0x0100 /* Octets transmitted */
+#define GEM_OCTTXL 0x0100 /* Octets transmitted
+ * [31:0]
+ */
+#define GEM_OCTTXH 0x0104 /* Octets transmitted
+ * [47:32]
+ */
+#define GEM_TXCNT 0x0108 /* Error-free Frames
+ * Transmitted counter
+ */
+#define GEM_TXBCCNT 0x010c /* Error-free Broadcast
+ * Frames counter
+ */
+#define GEM_TXMCCNT 0x0110 /* Error-free Multicast
+ * Frames counter
+ */
+#define GEM_TXPAUSECNT 0x0114 /* Pause Frames
+ * Transmitted Counter
+ */
+#define GEM_TX64CNT 0x0118 /* Error-free 64 byte
+ * Frames Transmitted
+ * counter
+ */
+#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte
+ * Frames Transmitted
+ * counter
+ */
+#define GEM_TX128CNT 0x0120 /* Error-free 128-255
+ * byte Frames
+ * Transmitted counter
+ */
+#define GEM_TX256CNT 0x0124 /* Error-free 256-511
+ * byte Frames
+ * transmitted counter
+ */
+#define GEM_TX512CNT 0x0128 /* Error-free 512-1023
+ * byte Frames
+ * transmitted counter
+ */
+#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518
+ * byte Frames
+ * transmitted counter
+ */
+#define GEM_TX1519CNT 0x0130 /* Error-free larger than
+ * 1519 byte Frames
+ * tranmitted counter
+ */
+#define GEM_TXURUNCNT 0x0134 /* TX under run error
+ * counter
+ */
+#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame
+ * Counter
+ */
+#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision
+ * Frame Counter
+ */
+#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision
+ * Frame Counter
+ */
+#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame
+ * Counter
+ */
+#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission
+ * Frame Counter
+ */
+#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error
+ * Counter
+ */
+#define GEM_ORX 0x0150 /* Octets received */
+#define GEM_OCTRXL 0x0150 /* Octets received
+ * [31:0]
+ */
+#define GEM_OCTRXH 0x0154 /* Octets received
+ * [47:32]
+ */
+#define GEM_RXCNT 0x0158 /* Error-free Frames
+ * Received Counter
+ */
+#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast
+ * Frames Received
+ * Counter
+ */
+#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast
+ * Frames Received
+ * Counter
+ */
+#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause
+ * Frames Received
+ * Counter
+ */
+#define GEM_RX64CNT 0x0168 /* Error-free 64 byte
+ * Frames Received
+ * Counter
+ */
+#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte
+ * Frames Received
+ * Counter
+ */
+#define GEM_RX128CNT 0x0170 /* Error-free 128-255
+ * byte Frames Received
+ * Counter
+ */
+#define GEM_RX256CNT 0x0174 /* Error-free 256-511
+ * byte Frames Received
+ * Counter
+ */
+#define GEM_RX512CNT 0x0178 /* Error-free 512-1023
+ * byte Frames Received
+ * Counter
+ */
+#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518
+ * byte Frames Received
+ * Counter
+ */
+#define GEM_RX1519CNT 0x0180 /* Error-free larger than
+ * 1519 Frames Received
+ * Counter
+ */
+#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames
+ * Received Counter
+ */
+#define GEM_RXOVRCNT 0x0188 /* Oversize Frames
+ * Received Counter
+ */
+#define GEM_RXJABCNT 0x018c /* Jabbers Received
+ * Counter
+ */
+#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence
+ * Error Counter
+ */
+#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error
+ * Counter
+ */
+#define GEM_RXSYMBCNT 0x0198 /* Symbol Error
+ * Counter
+ */
+#define GEM_RXALIGNCNT 0x019c /* Alignment Error
+ * Counter
+ */
+#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error
+ * Counter
+ */
+#define GEM_RXORCNT 0x01a4 /* Receive Overrun
+ * Counter
+ */
+#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum
+ * Error Counter
+ */
+#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error
+ * Counter
+ */
+#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error
+ * Counter
+ */
#define GEM_DCFG1 0x0280 /* Design Config 1 */
#define GEM_DCFG2 0x0284 /* Design Config 2 */
#define GEM_DCFG3 0x0288 /* Design Config 3 */
@@ -650,6 +803,107 @@ struct gem_stats {
u32 rx_udp_checksum_errors;
};
+/* Describes the name and offset of an individual statistic register, as
+ * returned by `ethtool -S`. Also describes which net_device_stats statistics
+ * this register should contribute to.
+ */
+struct gem_statistic {
+ char stat_string[ETH_GSTRING_LEN];
+ int offset;
+ u32 stat_bits;
+};
+
+/* Bitfield defs for net_device_stat statistics */
+#define GEM_NDS_RXERR_OFFSET 0
+#define GEM_NDS_RXLENERR_OFFSET 1
+#define GEM_NDS_RXOVERERR_OFFSET 2
+#define GEM_NDS_RXCRCERR_OFFSET 3
+#define GEM_NDS_RXFRAMEERR_OFFSET 4
+#define GEM_NDS_RXFIFOERR_OFFSET 5
+#define GEM_NDS_TXERR_OFFSET 6
+#define GEM_NDS_TXABORTEDERR_OFFSET 7
+#define GEM_NDS_TXCARRIERERR_OFFSET 8
+#define GEM_NDS_TXFIFOERR_OFFSET 9
+#define GEM_NDS_COLLISIONS_OFFSET 10
+
+#define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
+#define GEM_STAT_TITLE_BITS(name, title, bits) { \
+ .stat_string = title, \
+ .offset = GEM_##name, \
+ .stat_bits = bits \
+}
+
+/* list of gem statistic registers. The names MUST match the
+ * corresponding GEM_* definitions.
+ */
+static const struct gem_statistic gem_statistics[] = {
+ GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
+ GEM_STAT_TITLE(TXCNT, "tx_frames"),
+ GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
+ GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
+ GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
+ GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
+ GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
+ GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
+ GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
+ GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
+ GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
+ GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
+ GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
+ GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
+ GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
+ GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
+ GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
+ GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
+ GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
+ GEM_BIT(NDS_TXERR)|
+ GEM_BIT(NDS_TXABORTEDERR)|
+ GEM_BIT(NDS_COLLISIONS)),
+ GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
+ GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
+ GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
+ GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
+ GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
+ GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
+ GEM_STAT_TITLE(RXCNT, "rx_frames"),
+ GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
+ GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
+ GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
+ GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
+ GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
+ GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
+ GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
+ GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
+ GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
+ GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
+ GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
+ GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
+ GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
+ GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
+ GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
+ GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
+ GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
+ GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
+ GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
+ GEM_BIT(NDS_RXERR)),
+ GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
+ GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
+ GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
+ GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
+ GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
+ GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
+ GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
+ GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
+ GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
+ GEM_BIT(NDS_RXERR)),
+ GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
+ GEM_BIT(NDS_RXERR)),
+ GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
+ GEM_BIT(NDS_RXERR)),
+};
+
+#define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
+
struct macb;
struct macb_or_gem_ops {
@@ -728,6 +982,8 @@ struct macb {
dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
int skb_length; /* saved skb length for pci_unmap_single */
unsigned int max_tx_length;
+
+ u64 ethtool_stats[GEM_STATS_LEN];
};
extern const struct ethtool_ops macb_ethtool_ops;
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier
2015-01-13 22:15 [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier Xander Huff
2015-01-13 22:15 ` [PATCH 2/2] net/macb: improved ethtool statistics support Xander Huff
@ 2015-01-14 5:26 ` David Miller
2015-01-14 15:11 ` Brad Mouring
2015-01-14 15:10 ` Nicolas Ferre
[not found] ` <OFE030E01C.93929A2C-ON86257DCD.00524615-86257DCD.0052461A@ni.com>
3 siblings, 1 reply; 29+ messages in thread
From: David Miller @ 2015-01-14 5:26 UTC (permalink / raw)
To: xander.huff
Cc: nicolas.ferre, jaeden.amero, rich.tollerton, ben.shelton,
brad.mouring, netdev, linux-kernel
From: Xander Huff <xander.huff@ni.com>
Date: Tue, 13 Jan 2015 16:15:50 -0600
> This change is to help improve at-a-glace knowledge of the purpose of the
> various Cadence MACB/GEM registers. Comments are more helpful for human
> readability than short acronyms.
>
> Describe various #define varibles Cadence MACB/GEM registers as documented
> in Xilinix's "Zynq-7000 All Programmable SoC TechnicalReference Manual, v1.9.1
> (UG-585)"
>
> Signed-off-by: Xander Huff <xander.huff@ni.com>
Applied.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/2] net/macb: improved ethtool statistics support
2015-01-13 22:15 ` [PATCH 2/2] net/macb: improved ethtool statistics support Xander Huff
@ 2015-01-14 5:26 ` David Miller
2015-01-14 15:53 ` Nicolas Ferre
1 sibling, 0 replies; 29+ messages in thread
From: David Miller @ 2015-01-14 5:26 UTC (permalink / raw)
To: xander.huff
Cc: nicolas.ferre, jaeden.amero, rich.tollerton, ben.shelton,
brad.mouring, netdev, linux-kernel
From: Xander Huff <xander.huff@ni.com>
Date: Tue, 13 Jan 2015 16:15:51 -0600
> Currently `ethtool -S` simply returns "no stats available". It
> would be more useful to see what the various ethtool statistics
> registers' values are. This change implements get_ethtool_stats,
> get_strings, and get_sset_count functions to accomplish this.
>
> Read all GEM statistics registers and sum them into
> macb.ethtool_stats. Add the necessary infrastructure to make this
> accessible via `ethtool -S`.
>
> Update gem_update_stats to utilize ethtool_stats.
>
> Signed-off-by: Xander Huff <xander.huff@ni.com>
Applied.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier
2015-01-13 22:15 [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier Xander Huff
2015-01-13 22:15 ` [PATCH 2/2] net/macb: improved ethtool statistics support Xander Huff
2015-01-14 5:26 ` [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier David Miller
@ 2015-01-14 15:10 ` Nicolas Ferre
[not found] ` <OFE030E01C.93929A2C-ON86257DCD.00524615-86257DCD.0052461A@ni.com>
3 siblings, 0 replies; 29+ messages in thread
From: Nicolas Ferre @ 2015-01-14 15:10 UTC (permalink / raw)
To: Xander Huff
Cc: jaeden.amero, rich.tollerton, ben.shelton, brad.mouring, netdev,
linux-kernel
Le 13/01/2015 23:15, Xander Huff a écrit :
> This change is to help improve at-a-glace knowledge of the purpose of the
> various Cadence MACB/GEM registers. Comments are more helpful for human
> readability than short acronyms.
>
> Describe various #define varibles Cadence MACB/GEM registers as documented
> in Xilinix's "Zynq-7000 All Programmable SoC TechnicalReference Manual, v1.9.1
> (UG-585)"
>
> Signed-off-by: Xander Huff <xander.huff@ni.com>
For the record:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> drivers/net/ethernet/cadence/macb.h | 269 ++++++++++++++++++++++--------------
> 1 file changed, 162 insertions(+), 107 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 084191b..8e8c3c9 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -15,20 +15,20 @@
> #define MACB_MAX_QUEUES 8
>
> /* MACB register offsets */
> -#define MACB_NCR 0x0000
> -#define MACB_NCFGR 0x0004
> -#define MACB_NSR 0x0008
> +#define MACB_NCR 0x0000 /* Network Control */
> +#define MACB_NCFGR 0x0004 /* Network Config */
> +#define MACB_NSR 0x0008 /* Network Status */
> #define MACB_TAR 0x000c /* AT91RM9200 only */
> #define MACB_TCR 0x0010 /* AT91RM9200 only */
> -#define MACB_TSR 0x0014
> -#define MACB_RBQP 0x0018
> -#define MACB_TBQP 0x001c
> -#define MACB_RSR 0x0020
> -#define MACB_ISR 0x0024
> -#define MACB_IER 0x0028
> -#define MACB_IDR 0x002c
> -#define MACB_IMR 0x0030
> -#define MACB_MAN 0x0034
> +#define MACB_TSR 0x0014 /* Transmit Status */
> +#define MACB_RBQP 0x0018 /* RX Q Base Address */
> +#define MACB_TBQP 0x001c /* TX Q Base Address */
> +#define MACB_RSR 0x0020 /* Receive Status */
> +#define MACB_ISR 0x0024 /* Interrupt Status */
> +#define MACB_IER 0x0028 /* Interrupt Enable */
> +#define MACB_IDR 0x002c /* Interrupt Disable */
> +#define MACB_IMR 0x0030 /* Interrupt Mask */
> +#define MACB_MAN 0x0034 /* PHY Maintenance */
> #define MACB_PTR 0x0038
> #define MACB_PFR 0x003c
> #define MACB_FTO 0x0040
> @@ -68,27 +68,27 @@
> #define MACB_MID 0x00fc
>
> /* GEM register offsets. */
> -#define GEM_NCFGR 0x0004
> -#define GEM_USRIO 0x000c
> -#define GEM_DMACFG 0x0010
> -#define GEM_HRB 0x0080
> -#define GEM_HRT 0x0084
> -#define GEM_SA1B 0x0088
> -#define GEM_SA1T 0x008C
> -#define GEM_SA2B 0x0090
> -#define GEM_SA2T 0x0094
> -#define GEM_SA3B 0x0098
> -#define GEM_SA3T 0x009C
> -#define GEM_SA4B 0x00A0
> -#define GEM_SA4T 0x00A4
> -#define GEM_OTX 0x0100
> -#define GEM_DCFG1 0x0280
> -#define GEM_DCFG2 0x0284
> -#define GEM_DCFG3 0x0288
> -#define GEM_DCFG4 0x028c
> -#define GEM_DCFG5 0x0290
> -#define GEM_DCFG6 0x0294
> -#define GEM_DCFG7 0x0298
> +#define GEM_NCFGR 0x0004 /* Network Config */
> +#define GEM_USRIO 0x000c /* User IO */
> +#define GEM_DMACFG 0x0010 /* DMA Configuration */
> +#define GEM_HRB 0x0080 /* Hash Bottom */
> +#define GEM_HRT 0x0084 /* Hash Top */
> +#define GEM_SA1B 0x0088 /* Specific1 Bottom */
> +#define GEM_SA1T 0x008C /* Specific1 Top */
> +#define GEM_SA2B 0x0090 /* Specific2 Bottom */
> +#define GEM_SA2T 0x0094 /* Specific2 Top */
> +#define GEM_SA3B 0x0098 /* Specific3 Bottom */
> +#define GEM_SA3T 0x009C /* Specific3 Top */
> +#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
> +#define GEM_SA4T 0x00A4 /* Specific4 Top */
> +#define GEM_OTX 0x0100 /* Octets transmitted */
> +#define GEM_DCFG1 0x0280 /* Design Config 1 */
> +#define GEM_DCFG2 0x0284 /* Design Config 2 */
> +#define GEM_DCFG3 0x0288 /* Design Config 3 */
> +#define GEM_DCFG4 0x028c /* Design Config 4 */
> +#define GEM_DCFG5 0x0290 /* Design Config 5 */
> +#define GEM_DCFG6 0x0294 /* Design Config 6 */
> +#define GEM_DCFG7 0x0298 /* Design Config 7 */
>
> #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
> #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
> @@ -98,67 +98,73 @@
> #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
>
> /* Bitfields in NCR */
> -#define MACB_LB_OFFSET 0
> +#define MACB_LB_OFFSET 0 /* reserved */
> #define MACB_LB_SIZE 1
> -#define MACB_LLB_OFFSET 1
> +#define MACB_LLB_OFFSET 1 /* Loop back local */
> #define MACB_LLB_SIZE 1
> -#define MACB_RE_OFFSET 2
> +#define MACB_RE_OFFSET 2 /* Receive enable */
> #define MACB_RE_SIZE 1
> -#define MACB_TE_OFFSET 3
> +#define MACB_TE_OFFSET 3 /* Transmit enable */
> #define MACB_TE_SIZE 1
> -#define MACB_MPE_OFFSET 4
> +#define MACB_MPE_OFFSET 4 /* Management port enable */
> #define MACB_MPE_SIZE 1
> -#define MACB_CLRSTAT_OFFSET 5
> +#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
> #define MACB_CLRSTAT_SIZE 1
> -#define MACB_INCSTAT_OFFSET 6
> +#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
> #define MACB_INCSTAT_SIZE 1
> -#define MACB_WESTAT_OFFSET 7
> +#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
> #define MACB_WESTAT_SIZE 1
> -#define MACB_BP_OFFSET 8
> +#define MACB_BP_OFFSET 8 /* Back pressure */
> #define MACB_BP_SIZE 1
> -#define MACB_TSTART_OFFSET 9
> +#define MACB_TSTART_OFFSET 9 /* Start transmission */
> #define MACB_TSTART_SIZE 1
> -#define MACB_THALT_OFFSET 10
> +#define MACB_THALT_OFFSET 10 /* Transmit halt */
> #define MACB_THALT_SIZE 1
> -#define MACB_NCR_TPF_OFFSET 11
> +#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
> #define MACB_NCR_TPF_SIZE 1
> -#define MACB_TZQ_OFFSET 12
> +#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum
> + * pause frame
> + */
> #define MACB_TZQ_SIZE 1
>
> /* Bitfields in NCFGR */
> -#define MACB_SPD_OFFSET 0
> +#define MACB_SPD_OFFSET 0 /* Speed */
> #define MACB_SPD_SIZE 1
> -#define MACB_FD_OFFSET 1
> +#define MACB_FD_OFFSET 1 /* Full duplex */
> #define MACB_FD_SIZE 1
> -#define MACB_BIT_RATE_OFFSET 2
> +#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
> #define MACB_BIT_RATE_SIZE 1
> -#define MACB_JFRAME_OFFSET 3
> +#define MACB_JFRAME_OFFSET 3 /* reserved */
> #define MACB_JFRAME_SIZE 1
> -#define MACB_CAF_OFFSET 4
> +#define MACB_CAF_OFFSET 4 /* Copy all frames */
> #define MACB_CAF_SIZE 1
> -#define MACB_NBC_OFFSET 5
> +#define MACB_NBC_OFFSET 5 /* No broadcast */
> #define MACB_NBC_SIZE 1
> -#define MACB_NCFGR_MTI_OFFSET 6
> +#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
> #define MACB_NCFGR_MTI_SIZE 1
> -#define MACB_UNI_OFFSET 7
> +#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
> #define MACB_UNI_SIZE 1
> -#define MACB_BIG_OFFSET 8
> +#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
> #define MACB_BIG_SIZE 1
> -#define MACB_EAE_OFFSET 9
> +#define MACB_EAE_OFFSET 9 /* External address match
> + * enable
> + */
> #define MACB_EAE_SIZE 1
> #define MACB_CLK_OFFSET 10
> #define MACB_CLK_SIZE 2
> -#define MACB_RTY_OFFSET 12
> +#define MACB_RTY_OFFSET 12 /* Retry test */
> #define MACB_RTY_SIZE 1
> -#define MACB_PAE_OFFSET 13
> +#define MACB_PAE_OFFSET 13 /* Pause enable */
> #define MACB_PAE_SIZE 1
> #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
> #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
> -#define MACB_RBOF_OFFSET 14
> +#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
> #define MACB_RBOF_SIZE 2
> -#define MACB_RLCE_OFFSET 16
> +#define MACB_RLCE_OFFSET 16 /* Length field error frame
> + * discard
> + */
> #define MACB_RLCE_SIZE 1
> -#define MACB_DRFCS_OFFSET 17
> +#define MACB_DRFCS_OFFSET 17 /* FCS remove */
> #define MACB_DRFCS_SIZE 1
> #define MACB_EFRHD_OFFSET 18
> #define MACB_EFRHD_SIZE 1
> @@ -166,111 +172,160 @@
> #define MACB_IRXFCS_SIZE 1
>
> /* GEM specific NCFGR bitfields. */
> -#define GEM_GBE_OFFSET 10
> +#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
> #define GEM_GBE_SIZE 1
> -#define GEM_CLK_OFFSET 18
> +#define GEM_CLK_OFFSET 18 /* MDC clock division */
> #define GEM_CLK_SIZE 3
> -#define GEM_DBW_OFFSET 21
> +#define GEM_DBW_OFFSET 21 /* Data bus width */
> #define GEM_DBW_SIZE 2
> #define GEM_RXCOEN_OFFSET 24
> #define GEM_RXCOEN_SIZE 1
>
> /* Constants for data bus width. */
> -#define GEM_DBW32 0
> -#define GEM_DBW64 1
> -#define GEM_DBW128 2
> +#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus
> + * width
> + */
> +#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
> + * width
> + */
> +#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
> + * width
> + */
>
> /* Bitfields in DMACFG. */
> -#define GEM_FBLDO_OFFSET 0
> +#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for
> + * DMA data operations
> + */
> #define GEM_FBLDO_SIZE 5
> -#define GEM_ENDIA_OFFSET 7
> +#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable
> + * for packet data accesses
> + */
> #define GEM_ENDIA_SIZE 1
> -#define GEM_RXBMS_OFFSET 8
> +#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer
> + * memory size select
> + */
> #define GEM_RXBMS_SIZE 2
> -#define GEM_TXPBMS_OFFSET 10
> +#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer
> + * memory size select
> + */
> #define GEM_TXPBMS_SIZE 1
> -#define GEM_TXCOEN_OFFSET 11
> +#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and
> + * UDP checksum generation
> + * offload enable
> + */
> #define GEM_TXCOEN_SIZE 1
> -#define GEM_RXBS_OFFSET 16
> +#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in
> + * AHB system memory
> + */
> #define GEM_RXBS_SIZE 8
> -#define GEM_DDRP_OFFSET 24
> +#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
> #define GEM_DDRP_SIZE 1
>
>
> /* Bitfields in NSR */
> -#define MACB_NSR_LINK_OFFSET 0
> +#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
> #define MACB_NSR_LINK_SIZE 1
> -#define MACB_MDIO_OFFSET 1
> +#define MACB_MDIO_OFFSET 1 /* status of the mdio_in
> + * pin
> + */
> #define MACB_MDIO_SIZE 1
> -#define MACB_IDLE_OFFSET 2
> +#define MACB_IDLE_OFFSET 2 /* The PHY management logic is
> + * idle (i.e. has completed)
> + */
> #define MACB_IDLE_SIZE 1
>
> /* Bitfields in TSR */
> -#define MACB_UBR_OFFSET 0
> +#define MACB_UBR_OFFSET 0 /* Used bit read */
> #define MACB_UBR_SIZE 1
> -#define MACB_COL_OFFSET 1
> +#define MACB_COL_OFFSET 1 /* Collision occurred */
> #define MACB_COL_SIZE 1
> -#define MACB_TSR_RLE_OFFSET 2
> +#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
> #define MACB_TSR_RLE_SIZE 1
> -#define MACB_TGO_OFFSET 3
> +#define MACB_TGO_OFFSET 3 /* Transmit go */
> #define MACB_TGO_SIZE 1
> -#define MACB_BEX_OFFSET 4
> +#define MACB_BEX_OFFSET 4 /* Transmit frame corruption
> + * due to AHB error
> + */
> #define MACB_BEX_SIZE 1
> #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
> #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
> -#define MACB_COMP_OFFSET 5
> +#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
> #define MACB_COMP_SIZE 1
> -#define MACB_UND_OFFSET 6
> +#define MACB_UND_OFFSET 6 /* Trnasmit under run */
> #define MACB_UND_SIZE 1
>
> /* Bitfields in RSR */
> -#define MACB_BNA_OFFSET 0
> +#define MACB_BNA_OFFSET 0 /* Buffer not available */
> #define MACB_BNA_SIZE 1
> -#define MACB_REC_OFFSET 1
> +#define MACB_REC_OFFSET 1 /* Frame received */
> #define MACB_REC_SIZE 1
> -#define MACB_OVR_OFFSET 2
> +#define MACB_OVR_OFFSET 2 /* Receive overrun */
> #define MACB_OVR_SIZE 1
>
> /* Bitfields in ISR/IER/IDR/IMR */
> -#define MACB_MFD_OFFSET 0
> +#define MACB_MFD_OFFSET 0 /* Management frame sent */
> #define MACB_MFD_SIZE 1
> -#define MACB_RCOMP_OFFSET 1
> +#define MACB_RCOMP_OFFSET 1 /* Receive complete */
> #define MACB_RCOMP_SIZE 1
> -#define MACB_RXUBR_OFFSET 2
> +#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
> #define MACB_RXUBR_SIZE 1
> -#define MACB_TXUBR_OFFSET 3
> +#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
> #define MACB_TXUBR_SIZE 1
> -#define MACB_ISR_TUND_OFFSET 4
> +#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer
> + * under run interrupt
> + */
> #define MACB_ISR_TUND_SIZE 1
> -#define MACB_ISR_RLE_OFFSET 5
> +#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded
> + * or late collision interrupt
> + */
> #define MACB_ISR_RLE_SIZE 1
> -#define MACB_TXERR_OFFSET 6
> +#define MACB_TXERR_OFFSET 6 /* Enable transmit frame
> + * corruption due to AHB error
> + * interrupt
> + */
> #define MACB_TXERR_SIZE 1
> -#define MACB_TCOMP_OFFSET 7
> +#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete
> + * interrupt
> + */
> #define MACB_TCOMP_SIZE 1
> -#define MACB_ISR_LINK_OFFSET 9
> +#define MACB_ISR_LINK_OFFSET 9 /* Enable link change
> + * interrupt
> + */
> #define MACB_ISR_LINK_SIZE 1
> -#define MACB_ISR_ROVR_OFFSET 10
> +#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun
> + * interrupt
> + */
> #define MACB_ISR_ROVR_SIZE 1
> -#define MACB_HRESP_OFFSET 11
> +#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK
> + * interrupt
> + */
> #define MACB_HRESP_SIZE 1
> -#define MACB_PFR_OFFSET 12
> +#define MACB_PFR_OFFSET 12 /* Enable pause frame with
> + * non-zero pause quantum
> + * interrupt
> + */
> #define MACB_PFR_SIZE 1
> -#define MACB_PTZ_OFFSET 13
> +#define MACB_PTZ_OFFSET 13 /* Enable pause time zero
> + * interrupt
> + */
> #define MACB_PTZ_SIZE 1
>
> /* Bitfields in MAN */
> -#define MACB_DATA_OFFSET 0
> +#define MACB_DATA_OFFSET 0 /* data */
> #define MACB_DATA_SIZE 16
> -#define MACB_CODE_OFFSET 16
> +#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
> #define MACB_CODE_SIZE 2
> -#define MACB_REGA_OFFSET 18
> +#define MACB_REGA_OFFSET 18 /* Register address */
> #define MACB_REGA_SIZE 5
> -#define MACB_PHYA_OFFSET 23
> +#define MACB_PHYA_OFFSET 23 /* PHY address */
> #define MACB_PHYA_SIZE 5
> -#define MACB_RW_OFFSET 28
> +#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01
> + * is write.
> + */
> #define MACB_RW_SIZE 2
> -#define MACB_SOF_OFFSET 30
> +#define MACB_SOF_OFFSET 30 /* Must be written to 1 for
> + * Clause 22 operation
> + */
> #define MACB_SOF_SIZE 2
>
> /* Bitfields in USRIO (AVR32) */
> @@ -286,7 +341,7 @@
> /* Bitfields in USRIO (AT91) */
> #define MACB_RMII_OFFSET 0
> #define MACB_RMII_SIZE 1
> -#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
> +#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
> #define GEM_RGMII_SIZE 1
> #define MACB_CLKEN_OFFSET 1
> #define MACB_CLKEN_SIZE 1
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier
2015-01-14 5:26 ` [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier David Miller
@ 2015-01-14 15:11 ` Brad Mouring
0 siblings, 0 replies; 29+ messages in thread
From: Brad Mouring @ 2015-01-14 15:11 UTC (permalink / raw)
To: David Miller
Cc: xander.huff, nicolas.ferre, jaeden.amero, rich.tollerton,
ben.shelton, brad.mouring, netdev, linux-kernel
On Wed, Jan 14, 2015 at 12:26:09AM -0500, David Miller wrote:
> From: Xander Huff <xander.huff@ni.com>
> Date: Tue, 13 Jan 2015 16:15:50 -0600
>
> > This change is to help improve at-a-glace knowledge of the purpose of the
> > various Cadence MACB/GEM registers. Comments are more helpful for human
> > readability than short acronyms.
> >
> > Describe various #define varibles Cadence MACB/GEM registers as documented
> > in Xilinix's "Zynq-7000 All Programmable SoC TechnicalReference Manual, v1.9.1
s/Xilinix/Xilinx/. Sorry for the previous html-spam. Didn't follow the rule to always get coffee in the system prior to responding.
> > (UG-585)"
> >
> > Signed-off-by: Xander Huff <xander.huff@ni.com>
>
> Applied.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/2] net/macb: improved ethtool statistics support
2015-01-13 22:15 ` [PATCH 2/2] net/macb: improved ethtool statistics support Xander Huff
2015-01-14 5:26 ` David Miller
@ 2015-01-14 15:53 ` Nicolas Ferre
2015-01-14 20:21 ` [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier Xander Huff
2015-01-14 21:04 ` [PATCH 2/2] net/macb: improved ethtool statistics support David Miller
1 sibling, 2 replies; 29+ messages in thread
From: Nicolas Ferre @ 2015-01-14 15:53 UTC (permalink / raw)
To: Xander Huff, netdev, David Miller
Cc: jaeden.amero, rich.tollerton, ben.shelton, brad.mouring,
linux-kernel, Cyrille Pitchen
Le 13/01/2015 23:15, Xander Huff a écrit :
> Currently `ethtool -S` simply returns "no stats available". It
> would be more useful to see what the various ethtool statistics
> registers' values are. This change implements get_ethtool_stats,
> get_strings, and get_sset_count functions to accomplish this.
>
> Read all GEM statistics registers and sum them into
> macb.ethtool_stats. Add the necessary infrastructure to make this
> accessible via `ethtool -S`.
>
> Update gem_update_stats to utilize ethtool_stats.
>
> Signed-off-by: Xander Huff <xander.huff@ni.com>
David,
I see some issues with this patch: can you hold it a little bit please
(aka NAK)?
Remarks enclosed:
> ---
> drivers/net/ethernet/cadence/macb.c | 55 +++++++-
> drivers/net/ethernet/cadence/macb.h | 256 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 307 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index 3767271..dd8c202 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -1827,12 +1827,23 @@ static int macb_close(struct net_device *dev)
>
> static void gem_update_stats(struct macb *bp)
> {
> - u32 __iomem *reg = bp->regs + GEM_OTX;
> + int i;
> u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
> - u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
>
> - for (; p < end; p++, reg++)
> - *p += __raw_readl(reg);
> + for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
> + u32 offset = gem_statistics[i].offset;
> + u64 val = __raw_readl(bp->regs+offset);
> +
> + bp->ethtool_stats[i] += val;
> + *p += val;
> +
> + if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
> + /* Add GEM_OCTTXH, GEM_OCTRXH */
> + val = __raw_readl(bp->regs+offset+4);
style: whitespace around '+'
> + bp->ethtool_stats[i] += ((u64)val)<<32;
style: ditto
> + *(++p) += val;
> + }
> + }
> }
>
> static struct net_device_stats *gem_get_stats(struct macb *bp)
> @@ -1873,6 +1884,39 @@ static struct net_device_stats *gem_get_stats(struct macb *bp)
> return nstat;
> }
>
> +static void gem_get_ethtool_stats(struct net_device *dev,
> + struct ethtool_stats *stats, u64 *data)
> +{
> + struct macb *bp;
> +
> + bp = netdev_priv(dev);
> + gem_update_stats(bp);
> + memcpy(data, &bp->ethtool_stats, sizeof(u64)*GEM_STATS_LEN);
style: ditto
> +}
> +
> +static int gem_get_sset_count(struct net_device *dev, int sset)
> +{
> + switch (sset) {
> + case ETH_SS_STATS:
> + return GEM_STATS_LEN;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
> +{
> + int i;
> +
> + switch (sset) {
> + case ETH_SS_STATS:
> + for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
> + memcpy(p, gem_statistics[i].stat_string,
> + ETH_GSTRING_LEN);
> + break;
> + }
> +}
> +
> struct net_device_stats *macb_get_stats(struct net_device *dev)
> {
> struct macb *bp = netdev_priv(dev);
> @@ -1988,6 +2032,9 @@ const struct ethtool_ops macb_ethtool_ops = {
> .get_regs = macb_get_regs,
> .get_link = ethtool_op_get_link,
> .get_ts_info = ethtool_op_get_ts_info,
> + .get_ethtool_stats = gem_get_ethtool_stats,
> + .get_strings = gem_get_ethtool_strings,
> + .get_sset_count = gem_get_sset_count,
I think that the 10/100 macb version of this IP doesn't have the same
statistic possibilities: so you shouldn't register these functions for
all the variants of the IP.
Can you please verify this and only register these functions in the proper
if (macb_is_gem(bp)) alternative?
> };
> EXPORT_SYMBOL_GPL(macb_ethtool_ops);
>
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 8e8c3c9..378b218 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -82,6 +82,159 @@
> #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
> #define GEM_SA4T 0x00A4 /* Specific4 Top */
> #define GEM_OTX 0x0100 /* Octets transmitted */
> +#define GEM_OCTTXL 0x0100 /* Octets transmitted
> + * [31:0]
> + */
Well please place the comment on a single line. Even if it exceeds 80
characters, it can be an exception for this.
However, check with David but personally, I feel that this formatting is
not good...
> +#define GEM_OCTTXH 0x0104 /* Octets transmitted
> + * [47:32]
> + */
> +#define GEM_TXCNT 0x0108 /* Error-free Frames
> + * Transmitted counter
> + */
> +#define GEM_TXBCCNT 0x010c /* Error-free Broadcast
> + * Frames counter
> + */
> +#define GEM_TXMCCNT 0x0110 /* Error-free Multicast
> + * Frames counter
> + */
> +#define GEM_TXPAUSECNT 0x0114 /* Pause Frames
> + * Transmitted Counter
> + */
> +#define GEM_TX64CNT 0x0118 /* Error-free 64 byte
> + * Frames Transmitted
> + * counter
> + */
... particularly when it comes to reach 3 lines like above ^^^^^^
> +#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte
> + * Frames Transmitted
> + * counter
> + */
> +#define GEM_TX128CNT 0x0120 /* Error-free 128-255
> + * byte Frames
> + * Transmitted counter
> + */
> +#define GEM_TX256CNT 0x0124 /* Error-free 256-511
> + * byte Frames
> + * transmitted counter
> + */
> +#define GEM_TX512CNT 0x0128 /* Error-free 512-1023
> + * byte Frames
> + * transmitted counter
> + */
> +#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518
> + * byte Frames
> + * transmitted counter
> + */
> +#define GEM_TX1519CNT 0x0130 /* Error-free larger than
> + * 1519 byte Frames
> + * tranmitted counter
> + */
> +#define GEM_TXURUNCNT 0x0134 /* TX under run error
> + * counter
> + */
> +#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame
> + * Counter
> + */
> +#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision
> + * Frame Counter
> + */
> +#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision
> + * Frame Counter
> + */
> +#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame
> + * Counter
> + */
> +#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission
> + * Frame Counter
> + */
> +#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error
> + * Counter
> + */
> +#define GEM_ORX 0x0150 /* Octets received */
> +#define GEM_OCTRXL 0x0150 /* Octets received
> + * [31:0]
> + */
> +#define GEM_OCTRXH 0x0154 /* Octets received
> + * [47:32]
> + */
> +#define GEM_RXCNT 0x0158 /* Error-free Frames
> + * Received Counter
> + */
> +#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast
> + * Frames Received
> + * Counter
> + */
> +#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast
> + * Frames Received
> + * Counter
> + */
> +#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause
> + * Frames Received
> + * Counter
> + */
> +#define GEM_RX64CNT 0x0168 /* Error-free 64 byte
> + * Frames Received
> + * Counter
> + */
> +#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte
> + * Frames Received
> + * Counter
> + */
> +#define GEM_RX128CNT 0x0170 /* Error-free 128-255
> + * byte Frames Received
> + * Counter
> + */
> +#define GEM_RX256CNT 0x0174 /* Error-free 256-511
> + * byte Frames Received
> + * Counter
> + */
> +#define GEM_RX512CNT 0x0178 /* Error-free 512-1023
> + * byte Frames Received
> + * Counter
> + */
> +#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518
> + * byte Frames Received
> + * Counter
> + */
> +#define GEM_RX1519CNT 0x0180 /* Error-free larger than
> + * 1519 Frames Received
> + * Counter
> + */
> +#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames
> + * Received Counter
> + */
> +#define GEM_RXOVRCNT 0x0188 /* Oversize Frames
> + * Received Counter
> + */
> +#define GEM_RXJABCNT 0x018c /* Jabbers Received
> + * Counter
> + */
> +#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence
> + * Error Counter
> + */
> +#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error
> + * Counter
> + */
> +#define GEM_RXSYMBCNT 0x0198 /* Symbol Error
> + * Counter
> + */
> +#define GEM_RXALIGNCNT 0x019c /* Alignment Error
> + * Counter
> + */
> +#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error
> + * Counter
> + */
> +#define GEM_RXORCNT 0x01a4 /* Receive Overrun
> + * Counter
> + */
> +#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum
> + * Error Counter
> + */
> +#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error
> + * Counter
> + */
> +#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error
> + * Counter
> + */
> #define GEM_DCFG1 0x0280 /* Design Config 1 */
> #define GEM_DCFG2 0x0284 /* Design Config 2 */
> #define GEM_DCFG3 0x0288 /* Design Config 3 */
> @@ -650,6 +803,107 @@ struct gem_stats {
> u32 rx_udp_checksum_errors;
> };
>
> +/* Describes the name and offset of an individual statistic register, as
style: should be like this:
/*
* bla bla bla
*/
> + * returned by `ethtool -S`. Also describes which net_device_stats statistics
> + * this register should contribute to.
> + */
> +struct gem_statistic {
> + char stat_string[ETH_GSTRING_LEN];
> + int offset;
> + u32 stat_bits;
> +};
> +
> +/* Bitfield defs for net_device_stat statistics */
> +#define GEM_NDS_RXERR_OFFSET 0
> +#define GEM_NDS_RXLENERR_OFFSET 1
> +#define GEM_NDS_RXOVERERR_OFFSET 2
> +#define GEM_NDS_RXCRCERR_OFFSET 3
> +#define GEM_NDS_RXFRAMEERR_OFFSET 4
> +#define GEM_NDS_RXFIFOERR_OFFSET 5
> +#define GEM_NDS_TXERR_OFFSET 6
> +#define GEM_NDS_TXABORTEDERR_OFFSET 7
> +#define GEM_NDS_TXCARRIERERR_OFFSET 8
> +#define GEM_NDS_TXFIFOERR_OFFSET 9
> +#define GEM_NDS_COLLISIONS_OFFSET 10
> +
> +#define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
> +#define GEM_STAT_TITLE_BITS(name, title, bits) { \
> + .stat_string = title, \
> + .offset = GEM_##name, \
> + .stat_bits = bits \
> +}
> +
> +/* list of gem statistic registers. The names MUST match the
> + * corresponding GEM_* definitions.
> + */
> +static const struct gem_statistic gem_statistics[] = {
> + GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
> + GEM_STAT_TITLE(TXCNT, "tx_frames"),
> + GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
> + GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
> + GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
> + GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
> + GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
> + GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
> + GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
> + GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
> + GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
> + GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
> + GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
> + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
> + GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
> + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
> + GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
> + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
> + GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
> + GEM_BIT(NDS_TXERR)|
> + GEM_BIT(NDS_TXABORTEDERR)|
> + GEM_BIT(NDS_COLLISIONS)),
> + GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
> + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
> + GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
> + GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
> + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
> + GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
> + GEM_STAT_TITLE(RXCNT, "rx_frames"),
> + GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
> + GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
> + GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
> + GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
> + GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
> + GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
> + GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
> + GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
> + GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
> + GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
> + GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
> + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
> + GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
> + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
> + GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
> + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
> + GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
> + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
> + GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
> + GEM_BIT(NDS_RXERR)),
> + GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
> + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
> + GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
> + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
> + GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
> + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
> + GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
> + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
> + GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
> + GEM_BIT(NDS_RXERR)),
> + GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
> + GEM_BIT(NDS_RXERR)),
> + GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
> + GEM_BIT(NDS_RXERR)),
> +};
> +
> +#define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
> +
> struct macb;
>
> struct macb_or_gem_ops {
> @@ -728,6 +982,8 @@ struct macb {
> dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
> int skb_length; /* saved skb length for pci_unmap_single */
> unsigned int max_tx_length;
> +
> + u64 ethtool_stats[GEM_STATS_LEN];
> };
>
> extern const struct ethtool_ops macb_ethtool_ops;
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier
2015-01-14 15:53 ` Nicolas Ferre
@ 2015-01-14 20:21 ` Xander Huff
2015-01-14 20:21 ` [PATCH 2/2] fixup! net/macb: improved ethtool statistics support Xander Huff
2015-01-14 21:09 ` [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier David Miller
2015-01-14 21:04 ` [PATCH 2/2] net/macb: improved ethtool statistics support David Miller
1 sibling, 2 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-14 20:21 UTC (permalink / raw)
To: nicolas.ferre, netdev, davem
Cc: jaeden.amero, rich.tollerton, ben.shelton, brad.mouring,
linux-kernel, cyrille.pitchen, Xander Huff
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
drivers/net/ethernet/cadence/macb.h | 107 +++++++++---------------------------
1 file changed, 26 insertions(+), 81 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 378b218..d7b93d0 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -275,9 +275,7 @@
#define MACB_THALT_SIZE 1
#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
#define MACB_NCR_TPF_SIZE 1
-#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum
- * pause frame
- */
+#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
#define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */
@@ -299,9 +297,7 @@
#define MACB_UNI_SIZE 1
#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
#define MACB_BIG_SIZE 1
-#define MACB_EAE_OFFSET 9 /* External address match
- * enable
- */
+#define MACB_EAE_OFFSET 9 /* External address match enable */
#define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2
@@ -313,9 +309,7 @@
#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
#define MACB_RBOF_SIZE 2
-#define MACB_RLCE_OFFSET 16 /* Length field error frame
- * discard
- */
+#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
#define MACB_RLCE_SIZE 1
#define MACB_DRFCS_OFFSET 17 /* FCS remove */
#define MACB_DRFCS_SIZE 1
@@ -335,41 +329,22 @@
#define GEM_RXCOEN_SIZE 1
/* Constants for data bus width. */
-#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus
- * width
- */
-#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
- * width
- */
-#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
- * width
- */
+#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
+#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
+#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
/* Bitfields in DMACFG. */
-#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for
- * DMA data operations
- */
+#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for DMA data operations */
#define GEM_FBLDO_SIZE 5
-#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable
- * for packet data accesses
- */
+#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable for packet data accesses */
#define GEM_ENDIA_SIZE 1
-#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer
- * memory size select
- */
+#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer memory size select */
#define GEM_RXBMS_SIZE 2
-#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer
- * memory size select
- */
+#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer memory size select */
#define GEM_TXPBMS_SIZE 1
-#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and
- * UDP checksum generation
- * offload enable
- */
+#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and UDP checksum generation offload enable */
#define GEM_TXCOEN_SIZE 1
-#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in
- * AHB system memory
- */
+#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in AHB system memory */
#define GEM_RXBS_SIZE 8
#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
#define GEM_DDRP_SIZE 1
@@ -378,13 +353,9 @@
/* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
#define MACB_NSR_LINK_SIZE 1
-#define MACB_MDIO_OFFSET 1 /* status of the mdio_in
- * pin
- */
+#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
#define MACB_MDIO_SIZE 1
-#define MACB_IDLE_OFFSET 2 /* The PHY management logic is
- * idle (i.e. has completed)
- */
+#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle (i.e. has completed) */
#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
@@ -396,9 +367,7 @@
#define MACB_TSR_RLE_SIZE 1
#define MACB_TGO_OFFSET 3 /* Transmit go */
#define MACB_TGO_SIZE 1
-#define MACB_BEX_OFFSET 4 /* Transmit frame corruption
- * due to AHB error
- */
+#define MACB_BEX_OFFSET 4 /* Transmit frame corruption due to AHB error */
#define MACB_BEX_SIZE 1
#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
@@ -424,43 +393,23 @@
#define MACB_RXUBR_SIZE 1
#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
#define MACB_TXUBR_SIZE 1
-#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer
- * under run interrupt
- */
+#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer under run interrupt */
#define MACB_ISR_TUND_SIZE 1
-#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded
- * or late collision interrupt
- */
+#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded or late collision interrupt */
#define MACB_ISR_RLE_SIZE 1
-#define MACB_TXERR_OFFSET 6 /* Enable transmit frame
- * corruption due to AHB error
- * interrupt
- */
+#define MACB_TXERR_OFFSET 6 /* Enable transmit frame corruption due to AHB error interrupt */
#define MACB_TXERR_SIZE 1
-#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete
- * interrupt
- */
+#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
#define MACB_TCOMP_SIZE 1
-#define MACB_ISR_LINK_OFFSET 9 /* Enable link change
- * interrupt
- */
+#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
#define MACB_ISR_LINK_SIZE 1
-#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun
- * interrupt
- */
+#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
#define MACB_ISR_ROVR_SIZE 1
-#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK
- * interrupt
- */
+#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
#define MACB_HRESP_SIZE 1
-#define MACB_PFR_OFFSET 12 /* Enable pause frame with
- * non-zero pause quantum
- * interrupt
- */
+#define MACB_PFR_OFFSET 12 /* Enable pause frame with non-zero pause quantum interrupt */
#define MACB_PFR_SIZE 1
-#define MACB_PTZ_OFFSET 13 /* Enable pause time zero
- * interrupt
- */
+#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
#define MACB_PTZ_SIZE 1
/* Bitfields in MAN */
@@ -472,13 +421,9 @@
#define MACB_REGA_SIZE 5
#define MACB_PHYA_OFFSET 23 /* PHY address */
#define MACB_PHYA_SIZE 5
-#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01
- * is write.
- */
+#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
#define MACB_RW_SIZE 2
-#define MACB_SOF_OFFSET 30 /* Must be written to 1 for
- * Clause 22 operation
- */
+#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 operation */
#define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 2/2] fixup! net/macb: improved ethtool statistics support
2015-01-14 20:21 ` [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier Xander Huff
@ 2015-01-14 20:21 ` Xander Huff
2015-01-14 21:09 ` [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier David Miller
1 sibling, 0 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-14 20:21 UTC (permalink / raw)
To: nicolas.ferre, netdev, davem
Cc: jaeden.amero, rich.tollerton, ben.shelton, brad.mouring,
linux-kernel, cyrille.pitchen, Xander Huff
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
drivers/net/ethernet/cadence/macb.c | 25 +++--
drivers/net/ethernet/cadence/macb.h | 203 +++++++++---------------------------
2 files changed, 68 insertions(+), 160 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index dd8c202..f60f8f8 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1832,15 +1832,15 @@ static void gem_update_stats(struct macb *bp)
for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
u32 offset = gem_statistics[i].offset;
- u64 val = __raw_readl(bp->regs+offset);
+ u64 val = __raw_readl(bp->regs + offset);
bp->ethtool_stats[i] += val;
*p += val;
if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
/* Add GEM_OCTTXH, GEM_OCTRXH */
- val = __raw_readl(bp->regs+offset+4);
- bp->ethtool_stats[i] += ((u64)val)<<32;
+ val = __raw_readl(bp->regs+offset + 4);
+ bp->ethtool_stats[i] += ((u64)val) << 32;
*(++p) += val;
}
}
@@ -1891,7 +1891,7 @@ static void gem_get_ethtool_stats(struct net_device *dev,
bp = netdev_priv(dev);
gem_update_stats(bp);
- memcpy(data, &bp->ethtool_stats, sizeof(u64)*GEM_STATS_LEN);
+ memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
}
static int gem_get_sset_count(struct net_device *dev, int sset)
@@ -2032,11 +2032,21 @@ const struct ethtool_ops macb_ethtool_ops = {
.get_regs = macb_get_regs,
.get_link = ethtool_op_get_link,
.get_ts_info = ethtool_op_get_ts_info,
+};
+EXPORT_SYMBOL_GPL(macb_ethtool_ops);
+
+const struct ethtool_ops gem_ethtool_ops = {
+ .get_settings = macb_get_settings,
+ .set_settings = macb_set_settings,
+ .get_regs_len = macb_get_regs_len,
+ .get_regs = macb_get_regs,
+ .get_link = ethtool_op_get_link,
+ .get_ts_info = ethtool_op_get_ts_info,
.get_ethtool_stats = gem_get_ethtool_stats,
.get_strings = gem_get_ethtool_strings,
.get_sset_count = gem_get_sset_count,
};
-EXPORT_SYMBOL_GPL(macb_ethtool_ops);
+EXPORT_SYMBOL_GPL(gem_ethtool_ops);
int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
@@ -2325,7 +2335,10 @@ static int __init macb_probe(struct platform_device *pdev)
dev->netdev_ops = &macb_netdev_ops;
netif_napi_add(dev, &bp->napi, macb_poll, 64);
- dev->ethtool_ops = &macb_ethtool_ops;
+ if (macb_is_gem(bp))
+ dev->ethtool_ops = &gem_ethtool_ops;
+ else
+ dev->ethtool_ops = &macb_ethtool_ops;
dev->base_addr = regs->start;
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index d7b93d0..2ea5355 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -82,159 +82,52 @@
#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
#define GEM_SA4T 0x00A4 /* Specific4 Top */
#define GEM_OTX 0x0100 /* Octets transmitted */
-#define GEM_OCTTXL 0x0100 /* Octets transmitted
- * [31:0]
- */
-#define GEM_OCTTXH 0x0104 /* Octets transmitted
- * [47:32]
- */
-#define GEM_TXCNT 0x0108 /* Error-free Frames
- * Transmitted counter
- */
-#define GEM_TXBCCNT 0x010c /* Error-free Broadcast
- * Frames counter
- */
-#define GEM_TXMCCNT 0x0110 /* Error-free Multicast
- * Frames counter
- */
-#define GEM_TXPAUSECNT 0x0114 /* Pause Frames
- * Transmitted Counter
- */
-#define GEM_TX64CNT 0x0118 /* Error-free 64 byte
- * Frames Transmitted
- * counter
- */
-#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte
- * Frames Transmitted
- * counter
- */
-#define GEM_TX128CNT 0x0120 /* Error-free 128-255
- * byte Frames
- * Transmitted counter
- */
-#define GEM_TX256CNT 0x0124 /* Error-free 256-511
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX512CNT 0x0128 /* Error-free 512-1023
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX1519CNT 0x0130 /* Error-free larger than
- * 1519 byte Frames
- * tranmitted counter
- */
-#define GEM_TXURUNCNT 0x0134 /* TX under run error
- * counter
- */
-#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame
- * Counter
- */
-#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision
- * Frame Counter
- */
-#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision
- * Frame Counter
- */
-#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame
- * Counter
- */
-#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission
- * Frame Counter
- */
-#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error
- * Counter
- */
+#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
+#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
+#define GEM_TXCNT 0x0108 /* Error-free Frames Transmitted counter */
+#define GEM_TXBCCNT 0x010c /* Error-free Broadcast Frames counter */
+#define GEM_TXMCCNT 0x0110 /* Error-free Multicast Frames counter */
+#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
+#define GEM_TX64CNT 0x0118 /* Error-free 64 byte Frames Transmitted counter */
+#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte Frames Transmitted counter */
+#define GEM_TX128CNT 0x0120 /* Error-free 128-255 byte Frames Transmitted counter */
+#define GEM_TX256CNT 0x0124 /* Error-free 256-511 byte Frames transmitted counter */
+#define GEM_TX512CNT 0x0128 /* Error-free 512-1023 byte Frames transmitted counter */
+#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518 byte Frames transmitted counter */
+#define GEM_TX1519CNT 0x0130 /* Error-free larger than 1519 byte Frames tranmitted counter */
+#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
+#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
+#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
+#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
+#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
+#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
+#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
#define GEM_ORX 0x0150 /* Octets received */
-#define GEM_OCTRXL 0x0150 /* Octets received
- * [31:0]
- */
-#define GEM_OCTRXH 0x0154 /* Octets received
- * [47:32]
- */
-#define GEM_RXCNT 0x0158 /* Error-free Frames
- * Received Counter
- */
-#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast
- * Frames Received
- * Counter
- */
-#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast
- * Frames Received
- * Counter
- */
-#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause
- * Frames Received
- * Counter
- */
-#define GEM_RX64CNT 0x0168 /* Error-free 64 byte
- * Frames Received
- * Counter
- */
-#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte
- * Frames Received
- * Counter
- */
-#define GEM_RX128CNT 0x0170 /* Error-free 128-255
- * byte Frames Received
- * Counter
- */
-#define GEM_RX256CNT 0x0174 /* Error-free 256-511
- * byte Frames Received
- * Counter
- */
-#define GEM_RX512CNT 0x0178 /* Error-free 512-1023
- * byte Frames Received
- * Counter
- */
-#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518
- * byte Frames Received
- * Counter
- */
-#define GEM_RX1519CNT 0x0180 /* Error-free larger than
- * 1519 Frames Received
- * Counter
- */
-#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames
- * Received Counter
- */
-#define GEM_RXOVRCNT 0x0188 /* Oversize Frames
- * Received Counter
- */
-#define GEM_RXJABCNT 0x018c /* Jabbers Received
- * Counter
- */
-#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence
- * Error Counter
- */
-#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error
- * Counter
- */
-#define GEM_RXSYMBCNT 0x0198 /* Symbol Error
- * Counter
- */
-#define GEM_RXALIGNCNT 0x019c /* Alignment Error
- * Counter
- */
-#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error
- * Counter
- */
-#define GEM_RXORCNT 0x01a4 /* Receive Overrun
- * Counter
- */
-#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum
- * Error Counter
- */
-#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error
- * Counter
- */
-#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error
- * Counter
- */
+#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
+#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
+#define GEM_RXCNT 0x0158 /* Error-free Frames Received Counter */
+#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast Frames Received Counter */
+#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast Frames Received Counter */
+#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause Frames Received Counter */
+#define GEM_RX64CNT 0x0168 /* Error-free 64 byte Frames Received Counter */
+#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte Frames Received Counter */
+#define GEM_RX128CNT 0x0170 /* Error-free 128-255 byte Frames Received Counter */
+#define GEM_RX256CNT 0x0174 /* Error-free 256-511 byte Frames Received Counter */
+#define GEM_RX512CNT 0x0178 /* Error-free 512-1023 byte Frames Received Counter */
+#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518 byte Frames Received Counter */
+#define GEM_RX1519CNT 0x0180 /* Error-free larger than 1519 Frames Received Counter */
+#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
+#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
+#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
+#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
+#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
+#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
+#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
+#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
+#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
+#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
+#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
+#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
#define GEM_DCFG1 0x0280 /* Design Config 1 */
#define GEM_DCFG2 0x0284 /* Design Config 2 */
#define GEM_DCFG3 0x0288 /* Design Config 3 */
@@ -748,7 +641,8 @@ struct gem_stats {
u32 rx_udp_checksum_errors;
};
-/* Describes the name and offset of an individual statistic register, as
+/*
+ * Describes the name and offset of an individual statistic register, as
* returned by `ethtool -S`. Also describes which net_device_stats statistics
* this register should contribute to.
*/
@@ -778,7 +672,8 @@ struct gem_statistic {
.stat_bits = bits \
}
-/* list of gem statistic registers. The names MUST match the
+/*
+ * list of gem statistic registers. The names MUST match the
* corresponding GEM_* definitions.
*/
static const struct gem_statistic gem_statistics[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier
[not found] ` <OFE030E01C.93929A2C-ON86257DCD.00524615-86257DCD.0052461A@ni.com>
@ 2015-01-14 21:02 ` David Miller
0 siblings, 0 replies; 29+ messages in thread
From: David Miller @ 2015-01-14 21:02 UTC (permalink / raw)
To: brad.mouring
Cc: ben.shelton, jaeden.amero, linux-kernel, netdev, nicolas.ferre,
rich.tollerton, xander.huff
HTML encoded emails will be rejected by the list server, and also
completely not read by me.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/2] net/macb: improved ethtool statistics support
2015-01-14 15:53 ` Nicolas Ferre
2015-01-14 20:21 ` [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier Xander Huff
@ 2015-01-14 21:04 ` David Miller
1 sibling, 0 replies; 29+ messages in thread
From: David Miller @ 2015-01-14 21:04 UTC (permalink / raw)
To: nicolas.ferre
Cc: xander.huff, netdev, jaeden.amero, rich.tollerton, ben.shelton,
brad.mouring, linux-kernel, cyrille.pitchen
From: Nicolas Ferre <nicolas.ferre@atmel.com>
Date: Wed, 14 Jan 2015 16:53:25 +0100
> I see some issues with this patch: can you hold it a little bit please
> (aka NAK)?
I already applied these patches last night to my net-next tree, so
relative fixups against that will need to be submitted.
Submitting new versions of these patches therefore isn't going to
work.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier
2015-01-14 20:21 ` [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier Xander Huff
2015-01-14 20:21 ` [PATCH 2/2] fixup! net/macb: improved ethtool statistics support Xander Huff
@ 2015-01-14 21:09 ` David Miller
2015-01-14 21:18 ` Xander Huff
1 sibling, 1 reply; 29+ messages in thread
From: David Miller @ 2015-01-14 21:09 UTC (permalink / raw)
To: xander.huff
Cc: nicolas.ferre, netdev, jaeden.amero, rich.tollerton, ben.shelton,
brad.mouring, linux-kernel, cyrille.pitchen
As I mentioned, this won't do.
I've already applied your original patches to net-next, therefore you will
have to submit fixups relative to that.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier
2015-01-14 21:09 ` [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier David Miller
@ 2015-01-14 21:18 ` Xander Huff
2015-01-14 21:52 ` David Miller
0 siblings, 1 reply; 29+ messages in thread
From: Xander Huff @ 2015-01-14 21:18 UTC (permalink / raw)
To: David Miller
Cc: nicolas.ferre, netdev, jaeden.amero, rich.tollerton, ben.shelton,
brad.mouring, linux-kernel, cyrille.pitchen
On 1/14/2015 3:09 PM, David Miller wrote:
>
> As I mentioned, this won't do.
>
> I've already applied your original patches to net-next, therefore you will
> have to submit fixups relative to that.
>
These fixup commits are relative to an updated net-next, specifically "237de6e
Merge branch 'hip04'".
Do you need them relative to (what I'm seeing is the latest) "2733135 Merge
branch 'vxlan_rco'"?
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier
2015-01-14 21:18 ` Xander Huff
@ 2015-01-14 21:52 ` David Miller
2015-01-14 22:20 ` [PATCH v2 " Xander Huff
0 siblings, 1 reply; 29+ messages in thread
From: David Miller @ 2015-01-14 21:52 UTC (permalink / raw)
To: xander.huff
Cc: nicolas.ferre, netdev, jaeden.amero, rich.tollerton, ben.shelton,
brad.mouring, linux-kernel, cyrille.pitchen
From: Xander Huff <xander.huff@ni.com>
Date: Wed, 14 Jan 2015 15:18:34 -0600
> On 1/14/2015 3:09 PM, David Miller wrote:
>>
>> As I mentioned, this won't do.
>>
>> I've already applied your original patches to net-next, therefore you
>> will
>> have to submit fixups relative to that.
>>
> These fixup commits are relative to an updated net-next, specifically
> "237de6e Merge branch 'hip04'".
>
> Do you need them relative to (what I'm seeing is the latest) "2733135
> Merge branch 'vxlan_rco'"?
Why don't you make your subject lines and commit messages just say what
they are doing, rather than just saying "fix this other change"?
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier
2015-01-14 21:52 ` David Miller
@ 2015-01-14 22:20 ` Xander Huff
2015-01-14 22:20 ` [PATCH v2 2/2] fixup! net/macb: improved ethtool statistics support Xander Huff
` (2 more replies)
0 siblings, 3 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-14 22:20 UTC (permalink / raw)
To: davem, nicolas.ferre
Cc: netdev, jaeden.amero, rich.tollerton, ben.shelton, brad.mouring,
linux-kernel, cyrille.pitchen, Xander Huff
Put #define comments into a single line.
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
drivers/net/ethernet/cadence/macb.h | 107 +++++++++---------------------------
1 file changed, 26 insertions(+), 81 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 378b218..d7b93d0 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -275,9 +275,7 @@
#define MACB_THALT_SIZE 1
#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
#define MACB_NCR_TPF_SIZE 1
-#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum
- * pause frame
- */
+#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
#define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */
@@ -299,9 +297,7 @@
#define MACB_UNI_SIZE 1
#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
#define MACB_BIG_SIZE 1
-#define MACB_EAE_OFFSET 9 /* External address match
- * enable
- */
+#define MACB_EAE_OFFSET 9 /* External address match enable */
#define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2
@@ -313,9 +309,7 @@
#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
#define MACB_RBOF_SIZE 2
-#define MACB_RLCE_OFFSET 16 /* Length field error frame
- * discard
- */
+#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
#define MACB_RLCE_SIZE 1
#define MACB_DRFCS_OFFSET 17 /* FCS remove */
#define MACB_DRFCS_SIZE 1
@@ -335,41 +329,22 @@
#define GEM_RXCOEN_SIZE 1
/* Constants for data bus width. */
-#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus
- * width
- */
-#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
- * width
- */
-#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
- * width
- */
+#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
+#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
+#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
/* Bitfields in DMACFG. */
-#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for
- * DMA data operations
- */
+#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for DMA data operations */
#define GEM_FBLDO_SIZE 5
-#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable
- * for packet data accesses
- */
+#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable for packet data accesses */
#define GEM_ENDIA_SIZE 1
-#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer
- * memory size select
- */
+#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer memory size select */
#define GEM_RXBMS_SIZE 2
-#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer
- * memory size select
- */
+#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer memory size select */
#define GEM_TXPBMS_SIZE 1
-#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and
- * UDP checksum generation
- * offload enable
- */
+#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and UDP checksum generation offload enable */
#define GEM_TXCOEN_SIZE 1
-#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in
- * AHB system memory
- */
+#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in AHB system memory */
#define GEM_RXBS_SIZE 8
#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
#define GEM_DDRP_SIZE 1
@@ -378,13 +353,9 @@
/* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
#define MACB_NSR_LINK_SIZE 1
-#define MACB_MDIO_OFFSET 1 /* status of the mdio_in
- * pin
- */
+#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
#define MACB_MDIO_SIZE 1
-#define MACB_IDLE_OFFSET 2 /* The PHY management logic is
- * idle (i.e. has completed)
- */
+#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle (i.e. has completed) */
#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
@@ -396,9 +367,7 @@
#define MACB_TSR_RLE_SIZE 1
#define MACB_TGO_OFFSET 3 /* Transmit go */
#define MACB_TGO_SIZE 1
-#define MACB_BEX_OFFSET 4 /* Transmit frame corruption
- * due to AHB error
- */
+#define MACB_BEX_OFFSET 4 /* Transmit frame corruption due to AHB error */
#define MACB_BEX_SIZE 1
#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
@@ -424,43 +393,23 @@
#define MACB_RXUBR_SIZE 1
#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
#define MACB_TXUBR_SIZE 1
-#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer
- * under run interrupt
- */
+#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer under run interrupt */
#define MACB_ISR_TUND_SIZE 1
-#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded
- * or late collision interrupt
- */
+#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded or late collision interrupt */
#define MACB_ISR_RLE_SIZE 1
-#define MACB_TXERR_OFFSET 6 /* Enable transmit frame
- * corruption due to AHB error
- * interrupt
- */
+#define MACB_TXERR_OFFSET 6 /* Enable transmit frame corruption due to AHB error interrupt */
#define MACB_TXERR_SIZE 1
-#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete
- * interrupt
- */
+#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
#define MACB_TCOMP_SIZE 1
-#define MACB_ISR_LINK_OFFSET 9 /* Enable link change
- * interrupt
- */
+#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
#define MACB_ISR_LINK_SIZE 1
-#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun
- * interrupt
- */
+#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
#define MACB_ISR_ROVR_SIZE 1
-#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK
- * interrupt
- */
+#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
#define MACB_HRESP_SIZE 1
-#define MACB_PFR_OFFSET 12 /* Enable pause frame with
- * non-zero pause quantum
- * interrupt
- */
+#define MACB_PFR_OFFSET 12 /* Enable pause frame with non-zero pause quantum interrupt */
#define MACB_PFR_SIZE 1
-#define MACB_PTZ_OFFSET 13 /* Enable pause time zero
- * interrupt
- */
+#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
#define MACB_PTZ_SIZE 1
/* Bitfields in MAN */
@@ -472,13 +421,9 @@
#define MACB_REGA_SIZE 5
#define MACB_PHYA_OFFSET 23 /* PHY address */
#define MACB_PHYA_SIZE 5
-#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01
- * is write.
- */
+#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
#define MACB_RW_SIZE 2
-#define MACB_SOF_OFFSET 30 /* Must be written to 1 for
- * Clause 22 operation
- */
+#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 operation */
#define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 2/2] fixup! net/macb: improved ethtool statistics support
2015-01-14 22:20 ` [PATCH v2 " Xander Huff
@ 2015-01-14 22:20 ` Xander Huff
2015-01-15 10:35 ` Nicolas Ferre
2015-01-15 10:05 ` [PATCH v2 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier Nicolas Ferre
2015-01-15 11:46 ` David Laight
2 siblings, 1 reply; 29+ messages in thread
From: Xander Huff @ 2015-01-14 22:20 UTC (permalink / raw)
To: davem, nicolas.ferre
Cc: netdev, jaeden.amero, rich.tollerton, ben.shelton, brad.mouring,
linux-kernel, cyrille.pitchen, Xander Huff
Add spaces around arithmetic operators.
Make a separate gem_ethtool_ops for the new statistics functions.
Adjust new block comments to match the existing comments in macb.h.
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
drivers/net/ethernet/cadence/macb.c | 25 +++--
drivers/net/ethernet/cadence/macb.h | 203 +++++++++---------------------------
2 files changed, 68 insertions(+), 160 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index dd8c202..f60f8f8 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1832,15 +1832,15 @@ static void gem_update_stats(struct macb *bp)
for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
u32 offset = gem_statistics[i].offset;
- u64 val = __raw_readl(bp->regs+offset);
+ u64 val = __raw_readl(bp->regs + offset);
bp->ethtool_stats[i] += val;
*p += val;
if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
/* Add GEM_OCTTXH, GEM_OCTRXH */
- val = __raw_readl(bp->regs+offset+4);
- bp->ethtool_stats[i] += ((u64)val)<<32;
+ val = __raw_readl(bp->regs+offset + 4);
+ bp->ethtool_stats[i] += ((u64)val) << 32;
*(++p) += val;
}
}
@@ -1891,7 +1891,7 @@ static void gem_get_ethtool_stats(struct net_device *dev,
bp = netdev_priv(dev);
gem_update_stats(bp);
- memcpy(data, &bp->ethtool_stats, sizeof(u64)*GEM_STATS_LEN);
+ memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
}
static int gem_get_sset_count(struct net_device *dev, int sset)
@@ -2032,11 +2032,21 @@ const struct ethtool_ops macb_ethtool_ops = {
.get_regs = macb_get_regs,
.get_link = ethtool_op_get_link,
.get_ts_info = ethtool_op_get_ts_info,
+};
+EXPORT_SYMBOL_GPL(macb_ethtool_ops);
+
+const struct ethtool_ops gem_ethtool_ops = {
+ .get_settings = macb_get_settings,
+ .set_settings = macb_set_settings,
+ .get_regs_len = macb_get_regs_len,
+ .get_regs = macb_get_regs,
+ .get_link = ethtool_op_get_link,
+ .get_ts_info = ethtool_op_get_ts_info,
.get_ethtool_stats = gem_get_ethtool_stats,
.get_strings = gem_get_ethtool_strings,
.get_sset_count = gem_get_sset_count,
};
-EXPORT_SYMBOL_GPL(macb_ethtool_ops);
+EXPORT_SYMBOL_GPL(gem_ethtool_ops);
int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
@@ -2325,7 +2335,10 @@ static int __init macb_probe(struct platform_device *pdev)
dev->netdev_ops = &macb_netdev_ops;
netif_napi_add(dev, &bp->napi, macb_poll, 64);
- dev->ethtool_ops = &macb_ethtool_ops;
+ if (macb_is_gem(bp))
+ dev->ethtool_ops = &gem_ethtool_ops;
+ else
+ dev->ethtool_ops = &macb_ethtool_ops;
dev->base_addr = regs->start;
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index d7b93d0..2ea5355 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -82,159 +82,52 @@
#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
#define GEM_SA4T 0x00A4 /* Specific4 Top */
#define GEM_OTX 0x0100 /* Octets transmitted */
-#define GEM_OCTTXL 0x0100 /* Octets transmitted
- * [31:0]
- */
-#define GEM_OCTTXH 0x0104 /* Octets transmitted
- * [47:32]
- */
-#define GEM_TXCNT 0x0108 /* Error-free Frames
- * Transmitted counter
- */
-#define GEM_TXBCCNT 0x010c /* Error-free Broadcast
- * Frames counter
- */
-#define GEM_TXMCCNT 0x0110 /* Error-free Multicast
- * Frames counter
- */
-#define GEM_TXPAUSECNT 0x0114 /* Pause Frames
- * Transmitted Counter
- */
-#define GEM_TX64CNT 0x0118 /* Error-free 64 byte
- * Frames Transmitted
- * counter
- */
-#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte
- * Frames Transmitted
- * counter
- */
-#define GEM_TX128CNT 0x0120 /* Error-free 128-255
- * byte Frames
- * Transmitted counter
- */
-#define GEM_TX256CNT 0x0124 /* Error-free 256-511
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX512CNT 0x0128 /* Error-free 512-1023
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX1519CNT 0x0130 /* Error-free larger than
- * 1519 byte Frames
- * tranmitted counter
- */
-#define GEM_TXURUNCNT 0x0134 /* TX under run error
- * counter
- */
-#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame
- * Counter
- */
-#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision
- * Frame Counter
- */
-#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision
- * Frame Counter
- */
-#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame
- * Counter
- */
-#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission
- * Frame Counter
- */
-#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error
- * Counter
- */
+#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
+#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
+#define GEM_TXCNT 0x0108 /* Error-free Frames Transmitted counter */
+#define GEM_TXBCCNT 0x010c /* Error-free Broadcast Frames counter */
+#define GEM_TXMCCNT 0x0110 /* Error-free Multicast Frames counter */
+#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
+#define GEM_TX64CNT 0x0118 /* Error-free 64 byte Frames Transmitted counter */
+#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte Frames Transmitted counter */
+#define GEM_TX128CNT 0x0120 /* Error-free 128-255 byte Frames Transmitted counter */
+#define GEM_TX256CNT 0x0124 /* Error-free 256-511 byte Frames transmitted counter */
+#define GEM_TX512CNT 0x0128 /* Error-free 512-1023 byte Frames transmitted counter */
+#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518 byte Frames transmitted counter */
+#define GEM_TX1519CNT 0x0130 /* Error-free larger than 1519 byte Frames tranmitted counter */
+#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
+#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
+#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
+#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
+#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
+#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
+#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
#define GEM_ORX 0x0150 /* Octets received */
-#define GEM_OCTRXL 0x0150 /* Octets received
- * [31:0]
- */
-#define GEM_OCTRXH 0x0154 /* Octets received
- * [47:32]
- */
-#define GEM_RXCNT 0x0158 /* Error-free Frames
- * Received Counter
- */
-#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast
- * Frames Received
- * Counter
- */
-#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast
- * Frames Received
- * Counter
- */
-#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause
- * Frames Received
- * Counter
- */
-#define GEM_RX64CNT 0x0168 /* Error-free 64 byte
- * Frames Received
- * Counter
- */
-#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte
- * Frames Received
- * Counter
- */
-#define GEM_RX128CNT 0x0170 /* Error-free 128-255
- * byte Frames Received
- * Counter
- */
-#define GEM_RX256CNT 0x0174 /* Error-free 256-511
- * byte Frames Received
- * Counter
- */
-#define GEM_RX512CNT 0x0178 /* Error-free 512-1023
- * byte Frames Received
- * Counter
- */
-#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518
- * byte Frames Received
- * Counter
- */
-#define GEM_RX1519CNT 0x0180 /* Error-free larger than
- * 1519 Frames Received
- * Counter
- */
-#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames
- * Received Counter
- */
-#define GEM_RXOVRCNT 0x0188 /* Oversize Frames
- * Received Counter
- */
-#define GEM_RXJABCNT 0x018c /* Jabbers Received
- * Counter
- */
-#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence
- * Error Counter
- */
-#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error
- * Counter
- */
-#define GEM_RXSYMBCNT 0x0198 /* Symbol Error
- * Counter
- */
-#define GEM_RXALIGNCNT 0x019c /* Alignment Error
- * Counter
- */
-#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error
- * Counter
- */
-#define GEM_RXORCNT 0x01a4 /* Receive Overrun
- * Counter
- */
-#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum
- * Error Counter
- */
-#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error
- * Counter
- */
-#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error
- * Counter
- */
+#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
+#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
+#define GEM_RXCNT 0x0158 /* Error-free Frames Received Counter */
+#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast Frames Received Counter */
+#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast Frames Received Counter */
+#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause Frames Received Counter */
+#define GEM_RX64CNT 0x0168 /* Error-free 64 byte Frames Received Counter */
+#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte Frames Received Counter */
+#define GEM_RX128CNT 0x0170 /* Error-free 128-255 byte Frames Received Counter */
+#define GEM_RX256CNT 0x0174 /* Error-free 256-511 byte Frames Received Counter */
+#define GEM_RX512CNT 0x0178 /* Error-free 512-1023 byte Frames Received Counter */
+#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518 byte Frames Received Counter */
+#define GEM_RX1519CNT 0x0180 /* Error-free larger than 1519 Frames Received Counter */
+#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
+#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
+#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
+#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
+#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
+#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
+#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
+#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
+#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
+#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
+#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
+#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
#define GEM_DCFG1 0x0280 /* Design Config 1 */
#define GEM_DCFG2 0x0284 /* Design Config 2 */
#define GEM_DCFG3 0x0288 /* Design Config 3 */
@@ -748,7 +641,8 @@ struct gem_stats {
u32 rx_udp_checksum_errors;
};
-/* Describes the name and offset of an individual statistic register, as
+/*
+ * Describes the name and offset of an individual statistic register, as
* returned by `ethtool -S`. Also describes which net_device_stats statistics
* this register should contribute to.
*/
@@ -778,7 +672,8 @@ struct gem_statistic {
.stat_bits = bits \
}
-/* list of gem statistic registers. The names MUST match the
+/*
+ * list of gem statistic registers. The names MUST match the
* corresponding GEM_* definitions.
*/
static const struct gem_statistic gem_statistics[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH v2 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier
2015-01-14 22:20 ` [PATCH v2 " Xander Huff
2015-01-14 22:20 ` [PATCH v2 2/2] fixup! net/macb: improved ethtool statistics support Xander Huff
@ 2015-01-15 10:05 ` Nicolas Ferre
2015-01-15 11:46 ` David Laight
2 siblings, 0 replies; 29+ messages in thread
From: Nicolas Ferre @ 2015-01-15 10:05 UTC (permalink / raw)
To: Xander Huff, davem
Cc: netdev, jaeden.amero, rich.tollerton, ben.shelton, brad.mouring,
linux-kernel, cyrille.pitchen
Le 14/01/2015 23:20, Xander Huff a écrit :
> Put #define comments into a single line.
It seems that correction is not done for all the entries modified:
@ 0x0100 to 0x01b0
Can you please consider correcting this?
Thanks, bye.
> Signed-off-by: Xander Huff <xander.huff@ni.com>
> ---
> drivers/net/ethernet/cadence/macb.h | 107 +++++++++---------------------------
> 1 file changed, 26 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 378b218..d7b93d0 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -275,9 +275,7 @@
> #define MACB_THALT_SIZE 1
> #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
> #define MACB_NCR_TPF_SIZE 1
> -#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum
> - * pause frame
> - */
> +#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
> #define MACB_TZQ_SIZE 1
>
> /* Bitfields in NCFGR */
> @@ -299,9 +297,7 @@
> #define MACB_UNI_SIZE 1
> #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
> #define MACB_BIG_SIZE 1
> -#define MACB_EAE_OFFSET 9 /* External address match
> - * enable
> - */
> +#define MACB_EAE_OFFSET 9 /* External address match enable */
> #define MACB_EAE_SIZE 1
> #define MACB_CLK_OFFSET 10
> #define MACB_CLK_SIZE 2
> @@ -313,9 +309,7 @@
> #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
> #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
> #define MACB_RBOF_SIZE 2
> -#define MACB_RLCE_OFFSET 16 /* Length field error frame
> - * discard
> - */
> +#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
> #define MACB_RLCE_SIZE 1
> #define MACB_DRFCS_OFFSET 17 /* FCS remove */
> #define MACB_DRFCS_SIZE 1
> @@ -335,41 +329,22 @@
> #define GEM_RXCOEN_SIZE 1
>
> /* Constants for data bus width. */
> -#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus
> - * width
> - */
> -#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
> - * width
> - */
> -#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
> - * width
> - */
> +#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
> +#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
> +#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
>
> /* Bitfields in DMACFG. */
> -#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for
> - * DMA data operations
> - */
> +#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for DMA data operations */
> #define GEM_FBLDO_SIZE 5
> -#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable
> - * for packet data accesses
> - */
> +#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable for packet data accesses */
> #define GEM_ENDIA_SIZE 1
> -#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer
> - * memory size select
> - */
> +#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer memory size select */
> #define GEM_RXBMS_SIZE 2
> -#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer
> - * memory size select
> - */
> +#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer memory size select */
> #define GEM_TXPBMS_SIZE 1
> -#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and
> - * UDP checksum generation
> - * offload enable
> - */
> +#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and UDP checksum generation offload enable */
> #define GEM_TXCOEN_SIZE 1
> -#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in
> - * AHB system memory
> - */
> +#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in AHB system memory */
> #define GEM_RXBS_SIZE 8
> #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
> #define GEM_DDRP_SIZE 1
> @@ -378,13 +353,9 @@
> /* Bitfields in NSR */
> #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
> #define MACB_NSR_LINK_SIZE 1
> -#define MACB_MDIO_OFFSET 1 /* status of the mdio_in
> - * pin
> - */
> +#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
> #define MACB_MDIO_SIZE 1
> -#define MACB_IDLE_OFFSET 2 /* The PHY management logic is
> - * idle (i.e. has completed)
> - */
> +#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle (i.e. has completed) */
> #define MACB_IDLE_SIZE 1
>
> /* Bitfields in TSR */
> @@ -396,9 +367,7 @@
> #define MACB_TSR_RLE_SIZE 1
> #define MACB_TGO_OFFSET 3 /* Transmit go */
> #define MACB_TGO_SIZE 1
> -#define MACB_BEX_OFFSET 4 /* Transmit frame corruption
> - * due to AHB error
> - */
> +#define MACB_BEX_OFFSET 4 /* Transmit frame corruption due to AHB error */
> #define MACB_BEX_SIZE 1
> #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
> #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
> @@ -424,43 +393,23 @@
> #define MACB_RXUBR_SIZE 1
> #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
> #define MACB_TXUBR_SIZE 1
> -#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer
> - * under run interrupt
> - */
> +#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer under run interrupt */
> #define MACB_ISR_TUND_SIZE 1
> -#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded
> - * or late collision interrupt
> - */
> +#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded or late collision interrupt */
> #define MACB_ISR_RLE_SIZE 1
> -#define MACB_TXERR_OFFSET 6 /* Enable transmit frame
> - * corruption due to AHB error
> - * interrupt
> - */
> +#define MACB_TXERR_OFFSET 6 /* Enable transmit frame corruption due to AHB error interrupt */
> #define MACB_TXERR_SIZE 1
> -#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete
> - * interrupt
> - */
> +#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
> #define MACB_TCOMP_SIZE 1
> -#define MACB_ISR_LINK_OFFSET 9 /* Enable link change
> - * interrupt
> - */
> +#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
> #define MACB_ISR_LINK_SIZE 1
> -#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun
> - * interrupt
> - */
> +#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
> #define MACB_ISR_ROVR_SIZE 1
> -#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK
> - * interrupt
> - */
> +#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
> #define MACB_HRESP_SIZE 1
> -#define MACB_PFR_OFFSET 12 /* Enable pause frame with
> - * non-zero pause quantum
> - * interrupt
> - */
> +#define MACB_PFR_OFFSET 12 /* Enable pause frame with non-zero pause quantum interrupt */
> #define MACB_PFR_SIZE 1
> -#define MACB_PTZ_OFFSET 13 /* Enable pause time zero
> - * interrupt
> - */
> +#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
> #define MACB_PTZ_SIZE 1
>
> /* Bitfields in MAN */
> @@ -472,13 +421,9 @@
> #define MACB_REGA_SIZE 5
> #define MACB_PHYA_OFFSET 23 /* PHY address */
> #define MACB_PHYA_SIZE 5
> -#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01
> - * is write.
> - */
> +#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
> #define MACB_RW_SIZE 2
> -#define MACB_SOF_OFFSET 30 /* Must be written to 1 for
> - * Clause 22 operation
> - */
> +#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 operation */
> #define MACB_SOF_SIZE 2
>
> /* Bitfields in USRIO (AVR32) */
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 2/2] fixup! net/macb: improved ethtool statistics support
2015-01-14 22:20 ` [PATCH v2 2/2] fixup! net/macb: improved ethtool statistics support Xander Huff
@ 2015-01-15 10:35 ` Nicolas Ferre
2015-01-15 15:32 ` Xander Huff
0 siblings, 1 reply; 29+ messages in thread
From: Nicolas Ferre @ 2015-01-15 10:35 UTC (permalink / raw)
To: Xander Huff, davem
Cc: netdev, jaeden.amero, rich.tollerton, ben.shelton, brad.mouring,
linux-kernel, cyrille.pitchen
Le 14/01/2015 23:20, Xander Huff a écrit :
> Add spaces around arithmetic operators.
> Make a separate gem_ethtool_ops for the new statistics functions.
> Adjust new block comments to match the existing comments in macb.h.
I wouldn't have mixed the 3 modification in one patch.
More comments below...
> Signed-off-by: Xander Huff <xander.huff@ni.com>
> ---
> drivers/net/ethernet/cadence/macb.c | 25 +++--
> drivers/net/ethernet/cadence/macb.h | 203 +++++++++---------------------------
> 2 files changed, 68 insertions(+), 160 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index dd8c202..f60f8f8 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -1832,15 +1832,15 @@ static void gem_update_stats(struct macb *bp)
>
> for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
> u32 offset = gem_statistics[i].offset;
> - u64 val = __raw_readl(bp->regs+offset);
> + u64 val = __raw_readl(bp->regs + offset);
>
> bp->ethtool_stats[i] += val;
> *p += val;
>
> if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
> /* Add GEM_OCTTXH, GEM_OCTRXH */
> - val = __raw_readl(bp->regs+offset+4);
> - bp->ethtool_stats[i] += ((u64)val)<<32;
> + val = __raw_readl(bp->regs+offset + 4);
> + bp->ethtool_stats[i] += ((u64)val) << 32;
> *(++p) += val;
> }
> }
> @@ -1891,7 +1891,7 @@ static void gem_get_ethtool_stats(struct net_device *dev,
>
> bp = netdev_priv(dev);
> gem_update_stats(bp);
> - memcpy(data, &bp->ethtool_stats, sizeof(u64)*GEM_STATS_LEN);
> + memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
> }
>
> static int gem_get_sset_count(struct net_device *dev, int sset)
> @@ -2032,11 +2032,21 @@ const struct ethtool_ops macb_ethtool_ops = {
> .get_regs = macb_get_regs,
> .get_link = ethtool_op_get_link,
> .get_ts_info = ethtool_op_get_ts_info,
> +};
> +EXPORT_SYMBOL_GPL(macb_ethtool_ops);
> +
> +const struct ethtool_ops gem_ethtool_ops = {
> + .get_settings = macb_get_settings,
> + .set_settings = macb_set_settings,
> + .get_regs_len = macb_get_regs_len,
> + .get_regs = macb_get_regs,
> + .get_link = ethtool_op_get_link,
> + .get_ts_info = ethtool_op_get_ts_info,
> .get_ethtool_stats = gem_get_ethtool_stats,
> .get_strings = gem_get_ethtool_strings,
> .get_sset_count = gem_get_sset_count,
> };
> -EXPORT_SYMBOL_GPL(macb_ethtool_ops);
> +EXPORT_SYMBOL_GPL(gem_ethtool_ops);
>
> int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
> {
> @@ -2325,7 +2335,10 @@ static int __init macb_probe(struct platform_device *pdev)
>
> dev->netdev_ops = &macb_netdev_ops;
> netif_napi_add(dev, &bp->napi, macb_poll, 64);
> - dev->ethtool_ops = &macb_ethtool_ops;
> + if (macb_is_gem(bp))
There is such a test 3 lines after: why not insert these setup there? It
seems to me that ethtool_ops is not used in the gap.
> + dev->ethtool_ops = &gem_ethtool_ops;
> + else
> + dev->ethtool_ops = &macb_ethtool_ops;
>
> dev->base_addr = regs->start;
>
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index d7b93d0..2ea5355 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -82,159 +82,52 @@
> #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
> #define GEM_SA4T 0x00A4 /* Specific4 Top */
> #define GEM_OTX 0x0100 /* Octets transmitted */
I see, it's modified hereafter! Why not integrate this part in previous
patch?
> -#define GEM_OCTTXL 0x0100 /* Octets transmitted
> - * [31:0]
> - */
> -#define GEM_OCTTXH 0x0104 /* Octets transmitted
> - * [47:32]
> - */
> -#define GEM_TXCNT 0x0108 /* Error-free Frames
> - * Transmitted counter
> - */
> -#define GEM_TXBCCNT 0x010c /* Error-free Broadcast
> - * Frames counter
> - */
> -#define GEM_TXMCCNT 0x0110 /* Error-free Multicast
> - * Frames counter
> - */
> -#define GEM_TXPAUSECNT 0x0114 /* Pause Frames
> - * Transmitted Counter
> - */
> -#define GEM_TX64CNT 0x0118 /* Error-free 64 byte
> - * Frames Transmitted
> - * counter
> - */
> -#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte
> - * Frames Transmitted
> - * counter
> - */
> -#define GEM_TX128CNT 0x0120 /* Error-free 128-255
> - * byte Frames
> - * Transmitted counter
> - */
> -#define GEM_TX256CNT 0x0124 /* Error-free 256-511
> - * byte Frames
> - * transmitted counter
> - */
> -#define GEM_TX512CNT 0x0128 /* Error-free 512-1023
> - * byte Frames
> - * transmitted counter
> - */
> -#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518
> - * byte Frames
> - * transmitted counter
> - */
> -#define GEM_TX1519CNT 0x0130 /* Error-free larger than
> - * 1519 byte Frames
> - * tranmitted counter
> - */
> -#define GEM_TXURUNCNT 0x0134 /* TX under run error
> - * counter
> - */
> -#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame
> - * Counter
> - */
> -#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision
> - * Frame Counter
> - */
> -#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision
> - * Frame Counter
> - */
> -#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame
> - * Counter
> - */
> -#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission
> - * Frame Counter
> - */
> -#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error
> - * Counter
> - */
> +#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
> +#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
> +#define GEM_TXCNT 0x0108 /* Error-free Frames Transmitted counter */
> +#define GEM_TXBCCNT 0x010c /* Error-free Broadcast Frames counter */
> +#define GEM_TXMCCNT 0x0110 /* Error-free Multicast Frames counter */
> +#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
> +#define GEM_TX64CNT 0x0118 /* Error-free 64 byte Frames Transmitted counter */
> +#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte Frames Transmitted counter */
> +#define GEM_TX128CNT 0x0120 /* Error-free 128-255 byte Frames Transmitted counter */
> +#define GEM_TX256CNT 0x0124 /* Error-free 256-511 byte Frames transmitted counter */
> +#define GEM_TX512CNT 0x0128 /* Error-free 512-1023 byte Frames transmitted counter */
> +#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518 byte Frames transmitted counter */
> +#define GEM_TX1519CNT 0x0130 /* Error-free larger than 1519 byte Frames tranmitted counter */
> +#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
> +#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
> +#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
> +#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
> +#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
> +#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
> +#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
> #define GEM_ORX 0x0150 /* Octets received */
> -#define GEM_OCTRXL 0x0150 /* Octets received
> - * [31:0]
> - */
> -#define GEM_OCTRXH 0x0154 /* Octets received
> - * [47:32]
> - */
> -#define GEM_RXCNT 0x0158 /* Error-free Frames
> - * Received Counter
> - */
> -#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast
> - * Frames Received
> - * Counter
> - */
> -#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast
> - * Frames Received
> - * Counter
> - */
> -#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause
> - * Frames Received
> - * Counter
> - */
> -#define GEM_RX64CNT 0x0168 /* Error-free 64 byte
> - * Frames Received
> - * Counter
> - */
> -#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte
> - * Frames Received
> - * Counter
> - */
> -#define GEM_RX128CNT 0x0170 /* Error-free 128-255
> - * byte Frames Received
> - * Counter
> - */
> -#define GEM_RX256CNT 0x0174 /* Error-free 256-511
> - * byte Frames Received
> - * Counter
> - */
> -#define GEM_RX512CNT 0x0178 /* Error-free 512-1023
> - * byte Frames Received
> - * Counter
> - */
> -#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518
> - * byte Frames Received
> - * Counter
> - */
> -#define GEM_RX1519CNT 0x0180 /* Error-free larger than
> - * 1519 Frames Received
> - * Counter
> - */
> -#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames
> - * Received Counter
> - */
> -#define GEM_RXOVRCNT 0x0188 /* Oversize Frames
> - * Received Counter
> - */
> -#define GEM_RXJABCNT 0x018c /* Jabbers Received
> - * Counter
> - */
> -#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence
> - * Error Counter
> - */
> -#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error
> - * Counter
> - */
> -#define GEM_RXSYMBCNT 0x0198 /* Symbol Error
> - * Counter
> - */
> -#define GEM_RXALIGNCNT 0x019c /* Alignment Error
> - * Counter
> - */
> -#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error
> - * Counter
> - */
> -#define GEM_RXORCNT 0x01a4 /* Receive Overrun
> - * Counter
> - */
> -#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum
> - * Error Counter
> - */
> -#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error
> - * Counter
> - */
> -#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error
> - * Counter
> - */
> +#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
> +#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
> +#define GEM_RXCNT 0x0158 /* Error-free Frames Received Counter */
> +#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast Frames Received Counter */
> +#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast Frames Received Counter */
> +#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause Frames Received Counter */
> +#define GEM_RX64CNT 0x0168 /* Error-free 64 byte Frames Received Counter */
> +#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte Frames Received Counter */
> +#define GEM_RX128CNT 0x0170 /* Error-free 128-255 byte Frames Received Counter */
> +#define GEM_RX256CNT 0x0174 /* Error-free 256-511 byte Frames Received Counter */
> +#define GEM_RX512CNT 0x0178 /* Error-free 512-1023 byte Frames Received Counter */
> +#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518 byte Frames Received Counter */
> +#define GEM_RX1519CNT 0x0180 /* Error-free larger than 1519 Frames Received Counter */
> +#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
> +#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
> +#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
> +#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
> +#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
> +#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
> +#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
> +#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
> +#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
> +#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
> +#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
> +#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
> #define GEM_DCFG1 0x0280 /* Design Config 1 */
> #define GEM_DCFG2 0x0284 /* Design Config 2 */
> #define GEM_DCFG3 0x0288 /* Design Config 3 */
> @@ -748,7 +641,8 @@ struct gem_stats {
> u32 rx_udp_checksum_errors;
> };
>
> -/* Describes the name and offset of an individual statistic register, as
> +/*
> + * Describes the name and offset of an individual statistic register, as
> * returned by `ethtool -S`. Also describes which net_device_stats statistics
> * this register should contribute to.
> */
> @@ -778,7 +672,8 @@ struct gem_statistic {
> .stat_bits = bits \
> }
>
> -/* list of gem statistic registers. The names MUST match the
> +/*
> + * list of gem statistic registers. The names MUST match the
> * corresponding GEM_* definitions.
> */
> static const struct gem_statistic gem_statistics[] = {
Anyway, thanks for having posted a new revision. Can you prepare another
series?
Bye,
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: [PATCH v2 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier
2015-01-14 22:20 ` [PATCH v2 " Xander Huff
2015-01-14 22:20 ` [PATCH v2 2/2] fixup! net/macb: improved ethtool statistics support Xander Huff
2015-01-15 10:05 ` [PATCH v2 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier Nicolas Ferre
@ 2015-01-15 11:46 ` David Laight
2015-01-15 21:45 ` [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines Xander Huff
2015-01-15 21:55 ` Xander Huff
2 siblings, 2 replies; 29+ messages in thread
From: David Laight @ 2015-01-15 11:46 UTC (permalink / raw)
To: 'Xander Huff', davem, nicolas.ferre
Cc: netdev, jaeden.amero, rich.tollerton, ben.shelton, brad.mouring,
linux-kernel, cyrille.pitchen
From: Xander Huff
> Put #define comments into a single line.
Breaks the 80 char limit.
I suspect the definitions could be made to fit by judicial editing.
But that probably requires knowing exactly what the comments mean.
David
> Signed-off-by: Xander Huff <xander.huff@ni.com>
> ---
> drivers/net/ethernet/cadence/macb.h | 107 +++++++++---------------------------
> 1 file changed, 26 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 378b218..d7b93d0 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -275,9 +275,7 @@
> #define MACB_THALT_SIZE 1
> #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
> #define MACB_NCR_TPF_SIZE 1
> -#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum
> - * pause frame
> - */
> +#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
> #define MACB_TZQ_SIZE 1
>
> /* Bitfields in NCFGR */
> @@ -299,9 +297,7 @@
> #define MACB_UNI_SIZE 1
> #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
> #define MACB_BIG_SIZE 1
> -#define MACB_EAE_OFFSET 9 /* External address match
> - * enable
> - */
> +#define MACB_EAE_OFFSET 9 /* External address match enable */
> #define MACB_EAE_SIZE 1
> #define MACB_CLK_OFFSET 10
> #define MACB_CLK_SIZE 2
> @@ -313,9 +309,7 @@
> #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
> #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
> #define MACB_RBOF_SIZE 2
> -#define MACB_RLCE_OFFSET 16 /* Length field error frame
> - * discard
> - */
> +#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
> #define MACB_RLCE_SIZE 1
> #define MACB_DRFCS_OFFSET 17 /* FCS remove */
> #define MACB_DRFCS_SIZE 1
> @@ -335,41 +329,22 @@
> #define GEM_RXCOEN_SIZE 1
>
> /* Constants for data bus width. */
> -#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus
> - * width
> - */
> -#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
> - * width
> - */
> -#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
> - * width
> - */
> +#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
> +#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
> +#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
>
> /* Bitfields in DMACFG. */
> -#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for
> - * DMA data operations
> - */
> +#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for DMA data operations */
> #define GEM_FBLDO_SIZE 5
> -#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable
> - * for packet data accesses
> - */
> +#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable for packet data accesses */
> #define GEM_ENDIA_SIZE 1
> -#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer
> - * memory size select
> - */
> +#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer memory size select */
> #define GEM_RXBMS_SIZE 2
> -#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer
> - * memory size select
> - */
> +#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer memory size select */
> #define GEM_TXPBMS_SIZE 1
> -#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and
> - * UDP checksum generation
> - * offload enable
> - */
> +#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and UDP checksum generation
> offload enable */
> #define GEM_TXCOEN_SIZE 1
> -#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in
> - * AHB system memory
> - */
> +#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in AHB system memory */
> #define GEM_RXBS_SIZE 8
> #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
> #define GEM_DDRP_SIZE 1
> @@ -378,13 +353,9 @@
> /* Bitfields in NSR */
> #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
> #define MACB_NSR_LINK_SIZE 1
> -#define MACB_MDIO_OFFSET 1 /* status of the mdio_in
> - * pin
> - */
> +#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
> #define MACB_MDIO_SIZE 1
> -#define MACB_IDLE_OFFSET 2 /* The PHY management logic is
> - * idle (i.e. has completed)
> - */
> +#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle (i.e. has completed)
> */
> #define MACB_IDLE_SIZE 1
>
> /* Bitfields in TSR */
> @@ -396,9 +367,7 @@
> #define MACB_TSR_RLE_SIZE 1
> #define MACB_TGO_OFFSET 3 /* Transmit go */
> #define MACB_TGO_SIZE 1
> -#define MACB_BEX_OFFSET 4 /* Transmit frame corruption
> - * due to AHB error
> - */
> +#define MACB_BEX_OFFSET 4 /* Transmit frame corruption due to AHB error */
> #define MACB_BEX_SIZE 1
> #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
> #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
> @@ -424,43 +393,23 @@
> #define MACB_RXUBR_SIZE 1
> #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
> #define MACB_TXUBR_SIZE 1
> -#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer
> - * under run interrupt
> - */
> +#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer under run interrupt */
> #define MACB_ISR_TUND_SIZE 1
> -#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded
> - * or late collision interrupt
> - */
> +#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded or late collision interrupt
> */
> #define MACB_ISR_RLE_SIZE 1
> -#define MACB_TXERR_OFFSET 6 /* Enable transmit frame
> - * corruption due to AHB error
> - * interrupt
> - */
> +#define MACB_TXERR_OFFSET 6 /* Enable transmit frame corruption due to AHB error
> interrupt */
> #define MACB_TXERR_SIZE 1
> -#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete
> - * interrupt
> - */
> +#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
> #define MACB_TCOMP_SIZE 1
> -#define MACB_ISR_LINK_OFFSET 9 /* Enable link change
> - * interrupt
> - */
> +#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
> #define MACB_ISR_LINK_SIZE 1
> -#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun
> - * interrupt
> - */
> +#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
> #define MACB_ISR_ROVR_SIZE 1
> -#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK
> - * interrupt
> - */
> +#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
> #define MACB_HRESP_SIZE 1
> -#define MACB_PFR_OFFSET 12 /* Enable pause frame with
> - * non-zero pause quantum
> - * interrupt
> - */
> +#define MACB_PFR_OFFSET 12 /* Enable pause frame with non-zero pause quantum
> interrupt */
> #define MACB_PFR_SIZE 1
> -#define MACB_PTZ_OFFSET 13 /* Enable pause time zero
> - * interrupt
> - */
> +#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
> #define MACB_PTZ_SIZE 1
>
> /* Bitfields in MAN */
> @@ -472,13 +421,9 @@
> #define MACB_REGA_SIZE 5
> #define MACB_PHYA_OFFSET 23 /* PHY address */
> #define MACB_PHYA_SIZE 5
> -#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01
> - * is write.
> - */
> +#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
> #define MACB_RW_SIZE 2
> -#define MACB_SOF_OFFSET 30 /* Must be written to 1 for
> - * Clause 22 operation
> - */
> +#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 operation */
> #define MACB_SOF_SIZE 2
>
> /* Bitfields in USRIO (AVR32) */
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 2/2] fixup! net/macb: improved ethtool statistics support
2015-01-15 10:35 ` Nicolas Ferre
@ 2015-01-15 15:32 ` Xander Huff
0 siblings, 0 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-15 15:32 UTC (permalink / raw)
To: Nicolas Ferre, davem
Cc: netdev, jaeden.amero, rich.tollerton, ben.shelton, brad.mouring,
linux-kernel, cyrille.pitchen
On 1/15/2015 4:35 AM, Nicolas Ferre wrote:
>> #define GEM_OTX 0x0100 /* Octets transmitted */
> I see, it's modified hereafter! Why not integrate this part in previous
> patch?
>
>
I split these up the way I did by using the --fixup argument to allow the rebase
--autosquash to work. I could instead have a series of fixup commits to fix each
type of style issue and then also the functional issue if you'd prefer, but
--autosquash will no longer work.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines
2015-01-15 11:46 ` David Laight
@ 2015-01-15 21:45 ` Xander Huff
2015-01-15 21:45 ` [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators Xander Huff
` (2 more replies)
2015-01-15 21:55 ` Xander Huff
1 sibling, 3 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-15 21:45 UTC (permalink / raw)
To: davem, nicolas.ferre, david.light
Cc: netdev, jaeden.amero, rich.tollerton, brad.mouring, linux-kernel,
cyrille.pitchen, Xander Huff
Change comments to not exceed 80 characters per line.
Update block comments in macb.h to start on the line after /*.
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
drivers/net/ethernet/cadence/macb.h | 734 ++++++++++++++----------------------
1 file changed, 284 insertions(+), 450 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 378b218..31dc080 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -15,471 +15,309 @@
#define MACB_MAX_QUEUES 8
/* MACB register offsets */
-#define MACB_NCR 0x0000 /* Network Control */
-#define MACB_NCFGR 0x0004 /* Network Config */
-#define MACB_NSR 0x0008 /* Network Status */
-#define MACB_TAR 0x000c /* AT91RM9200 only */
-#define MACB_TCR 0x0010 /* AT91RM9200 only */
-#define MACB_TSR 0x0014 /* Transmit Status */
-#define MACB_RBQP 0x0018 /* RX Q Base Address */
-#define MACB_TBQP 0x001c /* TX Q Base Address */
-#define MACB_RSR 0x0020 /* Receive Status */
-#define MACB_ISR 0x0024 /* Interrupt Status */
-#define MACB_IER 0x0028 /* Interrupt Enable */
-#define MACB_IDR 0x002c /* Interrupt Disable */
-#define MACB_IMR 0x0030 /* Interrupt Mask */
-#define MACB_MAN 0x0034 /* PHY Maintenance */
-#define MACB_PTR 0x0038
-#define MACB_PFR 0x003c
-#define MACB_FTO 0x0040
-#define MACB_SCF 0x0044
-#define MACB_MCF 0x0048
-#define MACB_FRO 0x004c
-#define MACB_FCSE 0x0050
-#define MACB_ALE 0x0054
-#define MACB_DTF 0x0058
-#define MACB_LCOL 0x005c
-#define MACB_EXCOL 0x0060
-#define MACB_TUND 0x0064
-#define MACB_CSE 0x0068
-#define MACB_RRE 0x006c
-#define MACB_ROVR 0x0070
-#define MACB_RSE 0x0074
-#define MACB_ELE 0x0078
-#define MACB_RJA 0x007c
-#define MACB_USF 0x0080
-#define MACB_STE 0x0084
-#define MACB_RLE 0x0088
-#define MACB_TPF 0x008c
-#define MACB_HRB 0x0090
-#define MACB_HRT 0x0094
-#define MACB_SA1B 0x0098
-#define MACB_SA1T 0x009c
-#define MACB_SA2B 0x00a0
-#define MACB_SA2T 0x00a4
-#define MACB_SA3B 0x00a8
-#define MACB_SA3T 0x00ac
-#define MACB_SA4B 0x00b0
-#define MACB_SA4T 0x00b4
-#define MACB_TID 0x00b8
-#define MACB_TPQ 0x00bc
-#define MACB_USRIO 0x00c0
-#define MACB_WOL 0x00c4
-#define MACB_MID 0x00fc
+#define MACB_NCR 0x0000 /* Network Control */
+#define MACB_NCFGR 0x0004 /* Network Config */
+#define MACB_NSR 0x0008 /* Network Status */
+#define MACB_TAR 0x000c /* AT91RM9200 only */
+#define MACB_TCR 0x0010 /* AT91RM9200 only */
+#define MACB_TSR 0x0014 /* Transmit Status */
+#define MACB_RBQP 0x0018 /* RX Q Base Address */
+#define MACB_TBQP 0x001c /* TX Q Base Address */
+#define MACB_RSR 0x0020 /* Receive Status */
+#define MACB_ISR 0x0024 /* Interrupt Status */
+#define MACB_IER 0x0028 /* Interrupt Enable */
+#define MACB_IDR 0x002c /* Interrupt Disable */
+#define MACB_IMR 0x0030 /* Interrupt Mask */
+#define MACB_MAN 0x0034 /* PHY Maintenance */
+#define MACB_PTR 0x0038
+#define MACB_PFR 0x003c
+#define MACB_FTO 0x0040
+#define MACB_SCF 0x0044
+#define MACB_MCF 0x0048
+#define MACB_FRO 0x004c
+#define MACB_FCSE 0x0050
+#define MACB_ALE 0x0054
+#define MACB_DTF 0x0058
+#define MACB_LCOL 0x005c
+#define MACB_EXCOL 0x0060
+#define MACB_TUND 0x0064
+#define MACB_CSE 0x0068
+#define MACB_RRE 0x006c
+#define MACB_ROVR 0x0070
+#define MACB_RSE 0x0074
+#define MACB_ELE 0x0078
+#define MACB_RJA 0x007c
+#define MACB_USF 0x0080
+#define MACB_STE 0x0084
+#define MACB_RLE 0x0088
+#define MACB_TPF 0x008c
+#define MACB_HRB 0x0090
+#define MACB_HRT 0x0094
+#define MACB_SA1B 0x0098
+#define MACB_SA1T 0x009c
+#define MACB_SA2B 0x00a0
+#define MACB_SA2T 0x00a4
+#define MACB_SA3B 0x00a8
+#define MACB_SA3T 0x00ac
+#define MACB_SA4B 0x00b0
+#define MACB_SA4T 0x00b4
+#define MACB_TID 0x00b8
+#define MACB_TPQ 0x00bc
+#define MACB_USRIO 0x00c0
+#define MACB_WOL 0x00c4
+#define MACB_MID 0x00fc
/* GEM register offsets. */
-#define GEM_NCFGR 0x0004 /* Network Config */
-#define GEM_USRIO 0x000c /* User IO */
-#define GEM_DMACFG 0x0010 /* DMA Configuration */
-#define GEM_HRB 0x0080 /* Hash Bottom */
-#define GEM_HRT 0x0084 /* Hash Top */
-#define GEM_SA1B 0x0088 /* Specific1 Bottom */
-#define GEM_SA1T 0x008C /* Specific1 Top */
-#define GEM_SA2B 0x0090 /* Specific2 Bottom */
-#define GEM_SA2T 0x0094 /* Specific2 Top */
-#define GEM_SA3B 0x0098 /* Specific3 Bottom */
-#define GEM_SA3T 0x009C /* Specific3 Top */
-#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
-#define GEM_SA4T 0x00A4 /* Specific4 Top */
-#define GEM_OTX 0x0100 /* Octets transmitted */
-#define GEM_OCTTXL 0x0100 /* Octets transmitted
- * [31:0]
- */
-#define GEM_OCTTXH 0x0104 /* Octets transmitted
- * [47:32]
- */
-#define GEM_TXCNT 0x0108 /* Error-free Frames
- * Transmitted counter
- */
-#define GEM_TXBCCNT 0x010c /* Error-free Broadcast
- * Frames counter
- */
-#define GEM_TXMCCNT 0x0110 /* Error-free Multicast
- * Frames counter
- */
-#define GEM_TXPAUSECNT 0x0114 /* Pause Frames
- * Transmitted Counter
- */
-#define GEM_TX64CNT 0x0118 /* Error-free 64 byte
- * Frames Transmitted
- * counter
- */
-#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte
- * Frames Transmitted
- * counter
- */
-#define GEM_TX128CNT 0x0120 /* Error-free 128-255
- * byte Frames
- * Transmitted counter
- */
-#define GEM_TX256CNT 0x0124 /* Error-free 256-511
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX512CNT 0x0128 /* Error-free 512-1023
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX1519CNT 0x0130 /* Error-free larger than
- * 1519 byte Frames
- * tranmitted counter
- */
-#define GEM_TXURUNCNT 0x0134 /* TX under run error
- * counter
- */
-#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame
- * Counter
- */
-#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision
- * Frame Counter
- */
-#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision
- * Frame Counter
- */
-#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame
- * Counter
- */
-#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission
- * Frame Counter
- */
-#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error
- * Counter
- */
-#define GEM_ORX 0x0150 /* Octets received */
-#define GEM_OCTRXL 0x0150 /* Octets received
- * [31:0]
- */
-#define GEM_OCTRXH 0x0154 /* Octets received
- * [47:32]
- */
-#define GEM_RXCNT 0x0158 /* Error-free Frames
- * Received Counter
- */
-#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast
- * Frames Received
- * Counter
- */
-#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast
- * Frames Received
- * Counter
- */
-#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause
- * Frames Received
- * Counter
- */
-#define GEM_RX64CNT 0x0168 /* Error-free 64 byte
- * Frames Received
- * Counter
- */
-#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte
- * Frames Received
- * Counter
- */
-#define GEM_RX128CNT 0x0170 /* Error-free 128-255
- * byte Frames Received
- * Counter
- */
-#define GEM_RX256CNT 0x0174 /* Error-free 256-511
- * byte Frames Received
- * Counter
- */
-#define GEM_RX512CNT 0x0178 /* Error-free 512-1023
- * byte Frames Received
- * Counter
- */
-#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518
- * byte Frames Received
- * Counter
- */
-#define GEM_RX1519CNT 0x0180 /* Error-free larger than
- * 1519 Frames Received
- * Counter
- */
-#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames
- * Received Counter
- */
-#define GEM_RXOVRCNT 0x0188 /* Oversize Frames
- * Received Counter
- */
-#define GEM_RXJABCNT 0x018c /* Jabbers Received
- * Counter
- */
-#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence
- * Error Counter
- */
-#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error
- * Counter
- */
-#define GEM_RXSYMBCNT 0x0198 /* Symbol Error
- * Counter
- */
-#define GEM_RXALIGNCNT 0x019c /* Alignment Error
- * Counter
- */
-#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error
- * Counter
- */
-#define GEM_RXORCNT 0x01a4 /* Receive Overrun
- * Counter
- */
-#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum
- * Error Counter
- */
-#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error
- * Counter
- */
-#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error
- * Counter
- */
-#define GEM_DCFG1 0x0280 /* Design Config 1 */
-#define GEM_DCFG2 0x0284 /* Design Config 2 */
-#define GEM_DCFG3 0x0288 /* Design Config 3 */
-#define GEM_DCFG4 0x028c /* Design Config 4 */
-#define GEM_DCFG5 0x0290 /* Design Config 5 */
-#define GEM_DCFG6 0x0294 /* Design Config 6 */
-#define GEM_DCFG7 0x0298 /* Design Config 7 */
-
-#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
-#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
-#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
-#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
-#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
-#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
+#define GEM_NCFGR 0x0004 /* Network Config */
+#define GEM_USRIO 0x000c /* User IO */
+#define GEM_DMACFG 0x0010 /* DMA Configuration */
+#define GEM_HRB 0x0080 /* Hash Bottom */
+#define GEM_HRT 0x0084 /* Hash Top */
+#define GEM_SA1B 0x0088 /* Specific1 Bottom */
+#define GEM_SA1T 0x008C /* Specific1 Top */
+#define GEM_SA2B 0x0090 /* Specific2 Bottom */
+#define GEM_SA2T 0x0094 /* Specific2 Top */
+#define GEM_SA3B 0x0098 /* Specific3 Bottom */
+#define GEM_SA3T 0x009C /* Specific3 Top */
+#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
+#define GEM_SA4T 0x00A4 /* Specific4 Top */
+#define GEM_OTX 0x0100 /* Octets transmitted */
+#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
+#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
+#define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
+#define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
+#define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
+#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
+#define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
+#define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
+#define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
+#define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
+#define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
+#define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
+#define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
+#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
+#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
+#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
+#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
+#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
+#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
+#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
+#define GEM_ORX 0x0150 /* Octets received */
+#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
+#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
+#define GEM_RXCNT 0x0158 /* Frames Received Counter */
+#define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
+#define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
+#define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
+#define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
+#define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
+#define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
+#define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
+#define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
+#define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
+#define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
+#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
+#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
+#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
+#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
+#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
+#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
+#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
+#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
+#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
+#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
+#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
+#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
+#define GEM_DCFG1 0x0280 /* Design Config 1 */
+#define GEM_DCFG2 0x0284 /* Design Config 2 */
+#define GEM_DCFG3 0x0288 /* Design Config 3 */
+#define GEM_DCFG4 0x028c /* Design Config 4 */
+#define GEM_DCFG5 0x0290 /* Design Config 5 */
+#define GEM_DCFG6 0x0294 /* Design Config 6 */
+#define GEM_DCFG7 0x0298 /* Design Config 7 */
+
+#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
+#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
+#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
+#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
+#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
+#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
/* Bitfields in NCR */
-#define MACB_LB_OFFSET 0 /* reserved */
-#define MACB_LB_SIZE 1
-#define MACB_LLB_OFFSET 1 /* Loop back local */
-#define MACB_LLB_SIZE 1
-#define MACB_RE_OFFSET 2 /* Receive enable */
-#define MACB_RE_SIZE 1
-#define MACB_TE_OFFSET 3 /* Transmit enable */
-#define MACB_TE_SIZE 1
-#define MACB_MPE_OFFSET 4 /* Management port enable */
-#define MACB_MPE_SIZE 1
-#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
-#define MACB_CLRSTAT_SIZE 1
-#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
-#define MACB_INCSTAT_SIZE 1
-#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
-#define MACB_WESTAT_SIZE 1
-#define MACB_BP_OFFSET 8 /* Back pressure */
-#define MACB_BP_SIZE 1
-#define MACB_TSTART_OFFSET 9 /* Start transmission */
-#define MACB_TSTART_SIZE 1
-#define MACB_THALT_OFFSET 10 /* Transmit halt */
-#define MACB_THALT_SIZE 1
-#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
-#define MACB_NCR_TPF_SIZE 1
-#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum
- * pause frame
- */
-#define MACB_TZQ_SIZE 1
+#define MACB_LB_OFFSET 0 /* reserved */
+#define MACB_LB_SIZE 1
+#define MACB_LLB_OFFSET 1 /* Loop back local */
+#define MACB_LLB_SIZE 1
+#define MACB_RE_OFFSET 2 /* Receive enable */
+#define MACB_RE_SIZE 1
+#define MACB_TE_OFFSET 3 /* Transmit enable */
+#define MACB_TE_SIZE 1
+#define MACB_MPE_OFFSET 4 /* Management port enable */
+#define MACB_MPE_SIZE 1
+#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
+#define MACB_CLRSTAT_SIZE 1
+#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
+#define MACB_INCSTAT_SIZE 1
+#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
+#define MACB_WESTAT_SIZE 1
+#define MACB_BP_OFFSET 8 /* Back pressure */
+#define MACB_BP_SIZE 1
+#define MACB_TSTART_OFFSET 9 /* Start transmission */
+#define MACB_TSTART_SIZE 1
+#define MACB_THALT_OFFSET 10 /* Transmit halt */
+#define MACB_THALT_SIZE 1
+#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
+#define MACB_NCR_TPF_SIZE 1
+#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
+#define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */
-#define MACB_SPD_OFFSET 0 /* Speed */
-#define MACB_SPD_SIZE 1
-#define MACB_FD_OFFSET 1 /* Full duplex */
-#define MACB_FD_SIZE 1
-#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
-#define MACB_BIT_RATE_SIZE 1
-#define MACB_JFRAME_OFFSET 3 /* reserved */
-#define MACB_JFRAME_SIZE 1
-#define MACB_CAF_OFFSET 4 /* Copy all frames */
-#define MACB_CAF_SIZE 1
-#define MACB_NBC_OFFSET 5 /* No broadcast */
-#define MACB_NBC_SIZE 1
-#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
-#define MACB_NCFGR_MTI_SIZE 1
-#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
-#define MACB_UNI_SIZE 1
-#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
-#define MACB_BIG_SIZE 1
-#define MACB_EAE_OFFSET 9 /* External address match
- * enable
- */
-#define MACB_EAE_SIZE 1
-#define MACB_CLK_OFFSET 10
-#define MACB_CLK_SIZE 2
-#define MACB_RTY_OFFSET 12 /* Retry test */
-#define MACB_RTY_SIZE 1
-#define MACB_PAE_OFFSET 13 /* Pause enable */
-#define MACB_PAE_SIZE 1
-#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
-#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
-#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
-#define MACB_RBOF_SIZE 2
-#define MACB_RLCE_OFFSET 16 /* Length field error frame
- * discard
- */
-#define MACB_RLCE_SIZE 1
-#define MACB_DRFCS_OFFSET 17 /* FCS remove */
-#define MACB_DRFCS_SIZE 1
-#define MACB_EFRHD_OFFSET 18
-#define MACB_EFRHD_SIZE 1
-#define MACB_IRXFCS_OFFSET 19
-#define MACB_IRXFCS_SIZE 1
+#define MACB_SPD_OFFSET 0 /* Speed */
+#define MACB_SPD_SIZE 1
+#define MACB_FD_OFFSET 1 /* Full duplex */
+#define MACB_FD_SIZE 1
+#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
+#define MACB_BIT_RATE_SIZE 1
+#define MACB_JFRAME_OFFSET 3 /* reserved */
+#define MACB_JFRAME_SIZE 1
+#define MACB_CAF_OFFSET 4 /* Copy all frames */
+#define MACB_CAF_SIZE 1
+#define MACB_NBC_OFFSET 5 /* No broadcast */
+#define MACB_NBC_SIZE 1
+#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
+#define MACB_NCFGR_MTI_SIZE 1
+#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
+#define MACB_UNI_SIZE 1
+#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
+#define MACB_BIG_SIZE 1
+#define MACB_EAE_OFFSET 9 /* External address match enable */
+#define MACB_EAE_SIZE 1
+#define MACB_CLK_OFFSET 10
+#define MACB_CLK_SIZE 2
+#define MACB_RTY_OFFSET 12 /* Retry test */
+#define MACB_RTY_SIZE 1
+#define MACB_PAE_OFFSET 13 /* Pause enable */
+#define MACB_PAE_SIZE 1
+#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
+#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
+#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
+#define MACB_RBOF_SIZE 2
+#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
+#define MACB_RLCE_SIZE 1
+#define MACB_DRFCS_OFFSET 17 /* FCS remove */
+#define MACB_DRFCS_SIZE 1
+#define MACB_EFRHD_OFFSET 18
+#define MACB_EFRHD_SIZE 1
+#define MACB_IRXFCS_OFFSET 19
+#define MACB_IRXFCS_SIZE 1
/* GEM specific NCFGR bitfields. */
-#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
-#define GEM_GBE_SIZE 1
-#define GEM_CLK_OFFSET 18 /* MDC clock division */
-#define GEM_CLK_SIZE 3
-#define GEM_DBW_OFFSET 21 /* Data bus width */
-#define GEM_DBW_SIZE 2
-#define GEM_RXCOEN_OFFSET 24
-#define GEM_RXCOEN_SIZE 1
+#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
+#define GEM_GBE_SIZE 1
+#define GEM_CLK_OFFSET 18 /* MDC clock division */
+#define GEM_CLK_SIZE 3
+#define GEM_DBW_OFFSET 21 /* Data bus width */
+#define GEM_DBW_SIZE 2
+#define GEM_RXCOEN_OFFSET 24
+#define GEM_RXCOEN_SIZE 1
/* Constants for data bus width. */
-#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus
- * width
- */
-#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
- * width
- */
-#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
- * width
- */
+#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
+#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
+#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
/* Bitfields in DMACFG. */
-#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for
- * DMA data operations
- */
-#define GEM_FBLDO_SIZE 5
-#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable
- * for packet data accesses
- */
-#define GEM_ENDIA_SIZE 1
-#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer
- * memory size select
- */
-#define GEM_RXBMS_SIZE 2
-#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer
- * memory size select
- */
-#define GEM_TXPBMS_SIZE 1
-#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and
- * UDP checksum generation
- * offload enable
- */
-#define GEM_TXCOEN_SIZE 1
-#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in
- * AHB system memory
- */
-#define GEM_RXBS_SIZE 8
-#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
-#define GEM_DDRP_SIZE 1
+#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
+#define GEM_FBLDO_SIZE 5
+#define GEM_ENDIA_OFFSET 7 /* endian swap mode for packet data access */
+#define GEM_ENDIA_SIZE 1
+#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
+#define GEM_RXBMS_SIZE 2
+#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
+#define GEM_TXPBMS_SIZE 1
+#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
+#define GEM_TXCOEN_SIZE 1
+#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
+#define GEM_RXBS_SIZE 8
+#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
+#define GEM_DDRP_SIZE 1
/* Bitfields in NSR */
-#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
-#define MACB_NSR_LINK_SIZE 1
-#define MACB_MDIO_OFFSET 1 /* status of the mdio_in
- * pin
- */
-#define MACB_MDIO_SIZE 1
-#define MACB_IDLE_OFFSET 2 /* The PHY management logic is
- * idle (i.e. has completed)
- */
-#define MACB_IDLE_SIZE 1
+#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
+#define MACB_NSR_LINK_SIZE 1
+#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
+#define MACB_MDIO_SIZE 1
+#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
+#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
-#define MACB_UBR_OFFSET 0 /* Used bit read */
-#define MACB_UBR_SIZE 1
-#define MACB_COL_OFFSET 1 /* Collision occurred */
-#define MACB_COL_SIZE 1
-#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
-#define MACB_TSR_RLE_SIZE 1
-#define MACB_TGO_OFFSET 3 /* Transmit go */
-#define MACB_TGO_SIZE 1
-#define MACB_BEX_OFFSET 4 /* Transmit frame corruption
- * due to AHB error
- */
-#define MACB_BEX_SIZE 1
-#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
-#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
-#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
-#define MACB_COMP_SIZE 1
-#define MACB_UND_OFFSET 6 /* Trnasmit under run */
-#define MACB_UND_SIZE 1
+#define MACB_UBR_OFFSET 0 /* Used bit read */
+#define MACB_UBR_SIZE 1
+#define MACB_COL_OFFSET 1 /* Collision occurred */
+#define MACB_COL_SIZE 1
+#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
+#define MACB_TSR_RLE_SIZE 1
+#define MACB_TGO_OFFSET 3 /* Transmit go */
+#define MACB_TGO_SIZE 1
+#define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
+#define MACB_BEX_SIZE 1
+#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
+#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
+#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
+#define MACB_COMP_SIZE 1
+#define MACB_UND_OFFSET 6 /* Trnasmit under run */
+#define MACB_UND_SIZE 1
/* Bitfields in RSR */
-#define MACB_BNA_OFFSET 0 /* Buffer not available */
-#define MACB_BNA_SIZE 1
-#define MACB_REC_OFFSET 1 /* Frame received */
-#define MACB_REC_SIZE 1
-#define MACB_OVR_OFFSET 2 /* Receive overrun */
-#define MACB_OVR_SIZE 1
+#define MACB_BNA_OFFSET 0 /* Buffer not available */
+#define MACB_BNA_SIZE 1
+#define MACB_REC_OFFSET 1 /* Frame received */
+#define MACB_REC_SIZE 1
+#define MACB_OVR_OFFSET 2 /* Receive overrun */
+#define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */
-#define MACB_MFD_OFFSET 0 /* Management frame sent */
-#define MACB_MFD_SIZE 1
-#define MACB_RCOMP_OFFSET 1 /* Receive complete */
-#define MACB_RCOMP_SIZE 1
-#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
-#define MACB_RXUBR_SIZE 1
-#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
-#define MACB_TXUBR_SIZE 1
-#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer
- * under run interrupt
- */
-#define MACB_ISR_TUND_SIZE 1
-#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded
- * or late collision interrupt
- */
-#define MACB_ISR_RLE_SIZE 1
-#define MACB_TXERR_OFFSET 6 /* Enable transmit frame
- * corruption due to AHB error
- * interrupt
- */
-#define MACB_TXERR_SIZE 1
-#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete
- * interrupt
- */
-#define MACB_TCOMP_SIZE 1
-#define MACB_ISR_LINK_OFFSET 9 /* Enable link change
- * interrupt
- */
-#define MACB_ISR_LINK_SIZE 1
-#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun
- * interrupt
- */
-#define MACB_ISR_ROVR_SIZE 1
-#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK
- * interrupt
- */
-#define MACB_HRESP_SIZE 1
-#define MACB_PFR_OFFSET 12 /* Enable pause frame with
- * non-zero pause quantum
- * interrupt
- */
-#define MACB_PFR_SIZE 1
-#define MACB_PTZ_OFFSET 13 /* Enable pause time zero
- * interrupt
- */
-#define MACB_PTZ_SIZE 1
+#define MACB_MFD_OFFSET 0 /* Management frame sent */
+#define MACB_MFD_SIZE 1
+#define MACB_RCOMP_OFFSET 1 /* Receive complete */
+#define MACB_RCOMP_SIZE 1
+#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
+#define MACB_RXUBR_SIZE 1
+#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
+#define MACB_TXUBR_SIZE 1
+#define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
+#define MACB_ISR_TUND_SIZE 1
+#define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
+#define MACB_ISR_RLE_SIZE 1
+#define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
+#define MACB_TXERR_SIZE 1
+#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
+#define MACB_TCOMP_SIZE 1
+#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
+#define MACB_ISR_LINK_SIZE 1
+#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
+#define MACB_ISR_ROVR_SIZE 1
+#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
+#define MACB_HRESP_SIZE 1
+#define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
+#define MACB_PFR_SIZE 1
+#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
+#define MACB_PTZ_SIZE 1
/* Bitfields in MAN */
-#define MACB_DATA_OFFSET 0 /* data */
-#define MACB_DATA_SIZE 16
-#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
-#define MACB_CODE_SIZE 2
-#define MACB_REGA_OFFSET 18 /* Register address */
-#define MACB_REGA_SIZE 5
-#define MACB_PHYA_OFFSET 23 /* PHY address */
-#define MACB_PHYA_SIZE 5
-#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01
- * is write.
- */
-#define MACB_RW_SIZE 2
-#define MACB_SOF_OFFSET 30 /* Must be written to 1 for
- * Clause 22 operation
- */
-#define MACB_SOF_SIZE 2
+#define MACB_DATA_OFFSET 0 /* data */
+#define MACB_DATA_SIZE 16
+#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
+#define MACB_CODE_SIZE 2
+#define MACB_REGA_OFFSET 18 /* Register address */
+#define MACB_REGA_SIZE 5
+#define MACB_PHYA_OFFSET 23 /* PHY address */
+#define MACB_PHYA_SIZE 5
+#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
+#define MACB_RW_SIZE 2
+#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
+#define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */
#define MACB_MII_OFFSET 0
@@ -597,8 +435,7 @@
#define queue_writel(queue, reg, value) \
__raw_writel((value), (queue)->bp->regs + (queue)->reg)
-/*
- * Conditional GEM/MACB macros. These perform the operation to the correct
+/* Conditional GEM/MACB macros. These perform the operation to the correct
* register dependent on whether the device is a GEM or a MACB. For registers
* and bitfields that are common across both devices, use macb_{read,write}l
* to avoid the cost of the conditional.
@@ -621,8 +458,7 @@
__v; \
})
-/**
- * struct macb_dma_desc - Hardware DMA descriptor
+/* struct macb_dma_desc - Hardware DMA descriptor
* @addr: DMA address of data buffer
* @ctrl: Control and status bits
*/
@@ -711,8 +547,7 @@ struct macb_dma_desc {
/* limit RX checksum offload to TCP and UDP packets */
#define GEM_RX_CSUM_CHECKED_MASK 2
-/**
- * struct macb_tx_skb - data about an skb which is being transmitted
+/* struct macb_tx_skb - data about an skb which is being transmitted
* @skb: skb currently being transmitted, only set for the last buffer
* of the frame
* @mapping: DMA address of the skb's fragment buffer
@@ -727,8 +562,7 @@ struct macb_tx_skb {
bool mapped_as_page;
};
-/*
- * Hardware-collected statistics. Used when updating the network
+/* Hardware-collected statistics. Used when updating the network
* device stats by a periodic timer.
*/
struct macb_stats {
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators
2015-01-15 21:45 ` [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines Xander Huff
@ 2015-01-15 21:45 ` Xander Huff
2015-01-16 5:32 ` David Miller
2015-01-15 21:45 ` [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions Xander Huff
2015-01-16 5:31 ` [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines David Miller
2 siblings, 1 reply; 29+ messages in thread
From: Xander Huff @ 2015-01-15 21:45 UTC (permalink / raw)
To: davem, nicolas.ferre, david.light
Cc: netdev, jaeden.amero, rich.tollerton, brad.mouring, linux-kernel,
cyrille.pitchen, Xander Huff
Spaces should surround add, multiply, and bitshift operators.
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
drivers/net/ethernet/cadence/macb.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index dd8c202..9edd787 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1691,7 +1691,7 @@ static int hash_get_index(__u8 *addr)
for (j = 0; j < 6; j++) {
for (i = 0, bitval = 0; i < 8; i++)
- bitval ^= hash_bit_value(i*6 + j, addr);
+ bitval ^= hash_bit_value(i * 6 + j, addr);
hash_index |= (bitval << j);
}
@@ -1832,15 +1832,15 @@ static void gem_update_stats(struct macb *bp)
for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
u32 offset = gem_statistics[i].offset;
- u64 val = __raw_readl(bp->regs+offset);
+ u64 val = __raw_readl(bp->regs + offset);
bp->ethtool_stats[i] += val;
*p += val;
if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
/* Add GEM_OCTTXH, GEM_OCTRXH */
- val = __raw_readl(bp->regs+offset+4);
- bp->ethtool_stats[i] += ((u64)val)<<32;
+ val = __raw_readl(bp->regs + offset + 4);
+ bp->ethtool_stats[i] += ((u64)val) << 32;
*(++p) += val;
}
}
@@ -1891,7 +1891,7 @@ static void gem_get_ethtool_stats(struct net_device *dev,
bp = netdev_priv(dev);
gem_update_stats(bp);
- memcpy(data, &bp->ethtool_stats, sizeof(u64)*GEM_STATS_LEN);
+ memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
}
static int gem_get_sset_count(struct net_device *dev, int sset)
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions
2015-01-15 21:45 ` [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines Xander Huff
2015-01-15 21:45 ` [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators Xander Huff
@ 2015-01-15 21:45 ` Xander Huff
2015-01-16 5:32 ` David Miller
2015-01-16 5:31 ` [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines David Miller
2 siblings, 1 reply; 29+ messages in thread
From: Xander Huff @ 2015-01-15 21:45 UTC (permalink / raw)
To: davem, nicolas.ferre, david.light
Cc: netdev, jaeden.amero, rich.tollerton, brad.mouring, linux-kernel,
cyrille.pitchen, Xander Huff
10/100 MACB does not have the same statistics possibilities as GEM. Separate
macb_ethtool_ops to make a new GEM-specific struct with the new statistics
functions included.
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
drivers/net/ethernet/cadence/macb.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 9edd787..f2f9ca0 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2032,11 +2032,21 @@ const struct ethtool_ops macb_ethtool_ops = {
.get_regs = macb_get_regs,
.get_link = ethtool_op_get_link,
.get_ts_info = ethtool_op_get_ts_info,
+};
+EXPORT_SYMBOL_GPL(macb_ethtool_ops);
+
+const struct ethtool_ops gem_ethtool_ops = {
+ .get_settings = macb_get_settings,
+ .set_settings = macb_set_settings,
+ .get_regs_len = macb_get_regs_len,
+ .get_regs = macb_get_regs,
+ .get_link = ethtool_op_get_link,
+ .get_ts_info = ethtool_op_get_ts_info,
.get_ethtool_stats = gem_get_ethtool_stats,
.get_strings = gem_get_ethtool_strings,
.get_sset_count = gem_get_sset_count,
};
-EXPORT_SYMBOL_GPL(macb_ethtool_ops);
+EXPORT_SYMBOL_GPL(gem_ethtool_ops);
int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
@@ -2325,7 +2335,6 @@ static int __init macb_probe(struct platform_device *pdev)
dev->netdev_ops = &macb_netdev_ops;
netif_napi_add(dev, &bp->napi, macb_poll, 64);
- dev->ethtool_ops = &macb_ethtool_ops;
dev->base_addr = regs->start;
@@ -2339,12 +2348,14 @@ static int __init macb_probe(struct platform_device *pdev)
bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
bp->macbgem_ops.mog_init_rings = gem_init_rings;
bp->macbgem_ops.mog_rx = gem_rx;
+ dev->ethtool_ops = &gem_ethtool_ops;
} else {
bp->max_tx_length = MACB_MAX_TX_LEN;
bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
bp->macbgem_ops.mog_init_rings = macb_init_rings;
bp->macbgem_ops.mog_rx = macb_rx;
+ dev->ethtool_ops = &macb_ethtool_ops;
}
/* Set features */
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines
2015-01-15 11:46 ` David Laight
2015-01-15 21:45 ` [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines Xander Huff
@ 2015-01-15 21:55 ` Xander Huff
2015-01-15 21:55 ` [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators Xander Huff
2015-01-15 21:55 ` [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions Xander Huff
1 sibling, 2 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-15 21:55 UTC (permalink / raw)
To: davem, nicolas.ferre, david.laight
Cc: netdev, jaeden.amero, rich.tollerton, brad.mouring, linux-kernel,
cyrille.pitchen, Xander Huff
Change comments to not exceed 80 characters per line.
Update block comments in macb.h to start on the line after /*.
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
Re-sending to properly include David Laight
drivers/net/ethernet/cadence/macb.h | 734 ++++++++++++++----------------------
1 file changed, 284 insertions(+), 450 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 378b218..31dc080 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -15,471 +15,309 @@
#define MACB_MAX_QUEUES 8
/* MACB register offsets */
-#define MACB_NCR 0x0000 /* Network Control */
-#define MACB_NCFGR 0x0004 /* Network Config */
-#define MACB_NSR 0x0008 /* Network Status */
-#define MACB_TAR 0x000c /* AT91RM9200 only */
-#define MACB_TCR 0x0010 /* AT91RM9200 only */
-#define MACB_TSR 0x0014 /* Transmit Status */
-#define MACB_RBQP 0x0018 /* RX Q Base Address */
-#define MACB_TBQP 0x001c /* TX Q Base Address */
-#define MACB_RSR 0x0020 /* Receive Status */
-#define MACB_ISR 0x0024 /* Interrupt Status */
-#define MACB_IER 0x0028 /* Interrupt Enable */
-#define MACB_IDR 0x002c /* Interrupt Disable */
-#define MACB_IMR 0x0030 /* Interrupt Mask */
-#define MACB_MAN 0x0034 /* PHY Maintenance */
-#define MACB_PTR 0x0038
-#define MACB_PFR 0x003c
-#define MACB_FTO 0x0040
-#define MACB_SCF 0x0044
-#define MACB_MCF 0x0048
-#define MACB_FRO 0x004c
-#define MACB_FCSE 0x0050
-#define MACB_ALE 0x0054
-#define MACB_DTF 0x0058
-#define MACB_LCOL 0x005c
-#define MACB_EXCOL 0x0060
-#define MACB_TUND 0x0064
-#define MACB_CSE 0x0068
-#define MACB_RRE 0x006c
-#define MACB_ROVR 0x0070
-#define MACB_RSE 0x0074
-#define MACB_ELE 0x0078
-#define MACB_RJA 0x007c
-#define MACB_USF 0x0080
-#define MACB_STE 0x0084
-#define MACB_RLE 0x0088
-#define MACB_TPF 0x008c
-#define MACB_HRB 0x0090
-#define MACB_HRT 0x0094
-#define MACB_SA1B 0x0098
-#define MACB_SA1T 0x009c
-#define MACB_SA2B 0x00a0
-#define MACB_SA2T 0x00a4
-#define MACB_SA3B 0x00a8
-#define MACB_SA3T 0x00ac
-#define MACB_SA4B 0x00b0
-#define MACB_SA4T 0x00b4
-#define MACB_TID 0x00b8
-#define MACB_TPQ 0x00bc
-#define MACB_USRIO 0x00c0
-#define MACB_WOL 0x00c4
-#define MACB_MID 0x00fc
+#define MACB_NCR 0x0000 /* Network Control */
+#define MACB_NCFGR 0x0004 /* Network Config */
+#define MACB_NSR 0x0008 /* Network Status */
+#define MACB_TAR 0x000c /* AT91RM9200 only */
+#define MACB_TCR 0x0010 /* AT91RM9200 only */
+#define MACB_TSR 0x0014 /* Transmit Status */
+#define MACB_RBQP 0x0018 /* RX Q Base Address */
+#define MACB_TBQP 0x001c /* TX Q Base Address */
+#define MACB_RSR 0x0020 /* Receive Status */
+#define MACB_ISR 0x0024 /* Interrupt Status */
+#define MACB_IER 0x0028 /* Interrupt Enable */
+#define MACB_IDR 0x002c /* Interrupt Disable */
+#define MACB_IMR 0x0030 /* Interrupt Mask */
+#define MACB_MAN 0x0034 /* PHY Maintenance */
+#define MACB_PTR 0x0038
+#define MACB_PFR 0x003c
+#define MACB_FTO 0x0040
+#define MACB_SCF 0x0044
+#define MACB_MCF 0x0048
+#define MACB_FRO 0x004c
+#define MACB_FCSE 0x0050
+#define MACB_ALE 0x0054
+#define MACB_DTF 0x0058
+#define MACB_LCOL 0x005c
+#define MACB_EXCOL 0x0060
+#define MACB_TUND 0x0064
+#define MACB_CSE 0x0068
+#define MACB_RRE 0x006c
+#define MACB_ROVR 0x0070
+#define MACB_RSE 0x0074
+#define MACB_ELE 0x0078
+#define MACB_RJA 0x007c
+#define MACB_USF 0x0080
+#define MACB_STE 0x0084
+#define MACB_RLE 0x0088
+#define MACB_TPF 0x008c
+#define MACB_HRB 0x0090
+#define MACB_HRT 0x0094
+#define MACB_SA1B 0x0098
+#define MACB_SA1T 0x009c
+#define MACB_SA2B 0x00a0
+#define MACB_SA2T 0x00a4
+#define MACB_SA3B 0x00a8
+#define MACB_SA3T 0x00ac
+#define MACB_SA4B 0x00b0
+#define MACB_SA4T 0x00b4
+#define MACB_TID 0x00b8
+#define MACB_TPQ 0x00bc
+#define MACB_USRIO 0x00c0
+#define MACB_WOL 0x00c4
+#define MACB_MID 0x00fc
/* GEM register offsets. */
-#define GEM_NCFGR 0x0004 /* Network Config */
-#define GEM_USRIO 0x000c /* User IO */
-#define GEM_DMACFG 0x0010 /* DMA Configuration */
-#define GEM_HRB 0x0080 /* Hash Bottom */
-#define GEM_HRT 0x0084 /* Hash Top */
-#define GEM_SA1B 0x0088 /* Specific1 Bottom */
-#define GEM_SA1T 0x008C /* Specific1 Top */
-#define GEM_SA2B 0x0090 /* Specific2 Bottom */
-#define GEM_SA2T 0x0094 /* Specific2 Top */
-#define GEM_SA3B 0x0098 /* Specific3 Bottom */
-#define GEM_SA3T 0x009C /* Specific3 Top */
-#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
-#define GEM_SA4T 0x00A4 /* Specific4 Top */
-#define GEM_OTX 0x0100 /* Octets transmitted */
-#define GEM_OCTTXL 0x0100 /* Octets transmitted
- * [31:0]
- */
-#define GEM_OCTTXH 0x0104 /* Octets transmitted
- * [47:32]
- */
-#define GEM_TXCNT 0x0108 /* Error-free Frames
- * Transmitted counter
- */
-#define GEM_TXBCCNT 0x010c /* Error-free Broadcast
- * Frames counter
- */
-#define GEM_TXMCCNT 0x0110 /* Error-free Multicast
- * Frames counter
- */
-#define GEM_TXPAUSECNT 0x0114 /* Pause Frames
- * Transmitted Counter
- */
-#define GEM_TX64CNT 0x0118 /* Error-free 64 byte
- * Frames Transmitted
- * counter
- */
-#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte
- * Frames Transmitted
- * counter
- */
-#define GEM_TX128CNT 0x0120 /* Error-free 128-255
- * byte Frames
- * Transmitted counter
- */
-#define GEM_TX256CNT 0x0124 /* Error-free 256-511
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX512CNT 0x0128 /* Error-free 512-1023
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518
- * byte Frames
- * transmitted counter
- */
-#define GEM_TX1519CNT 0x0130 /* Error-free larger than
- * 1519 byte Frames
- * tranmitted counter
- */
-#define GEM_TXURUNCNT 0x0134 /* TX under run error
- * counter
- */
-#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame
- * Counter
- */
-#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision
- * Frame Counter
- */
-#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision
- * Frame Counter
- */
-#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame
- * Counter
- */
-#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission
- * Frame Counter
- */
-#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error
- * Counter
- */
-#define GEM_ORX 0x0150 /* Octets received */
-#define GEM_OCTRXL 0x0150 /* Octets received
- * [31:0]
- */
-#define GEM_OCTRXH 0x0154 /* Octets received
- * [47:32]
- */
-#define GEM_RXCNT 0x0158 /* Error-free Frames
- * Received Counter
- */
-#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast
- * Frames Received
- * Counter
- */
-#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast
- * Frames Received
- * Counter
- */
-#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause
- * Frames Received
- * Counter
- */
-#define GEM_RX64CNT 0x0168 /* Error-free 64 byte
- * Frames Received
- * Counter
- */
-#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte
- * Frames Received
- * Counter
- */
-#define GEM_RX128CNT 0x0170 /* Error-free 128-255
- * byte Frames Received
- * Counter
- */
-#define GEM_RX256CNT 0x0174 /* Error-free 256-511
- * byte Frames Received
- * Counter
- */
-#define GEM_RX512CNT 0x0178 /* Error-free 512-1023
- * byte Frames Received
- * Counter
- */
-#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518
- * byte Frames Received
- * Counter
- */
-#define GEM_RX1519CNT 0x0180 /* Error-free larger than
- * 1519 Frames Received
- * Counter
- */
-#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames
- * Received Counter
- */
-#define GEM_RXOVRCNT 0x0188 /* Oversize Frames
- * Received Counter
- */
-#define GEM_RXJABCNT 0x018c /* Jabbers Received
- * Counter
- */
-#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence
- * Error Counter
- */
-#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error
- * Counter
- */
-#define GEM_RXSYMBCNT 0x0198 /* Symbol Error
- * Counter
- */
-#define GEM_RXALIGNCNT 0x019c /* Alignment Error
- * Counter
- */
-#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error
- * Counter
- */
-#define GEM_RXORCNT 0x01a4 /* Receive Overrun
- * Counter
- */
-#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum
- * Error Counter
- */
-#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error
- * Counter
- */
-#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error
- * Counter
- */
-#define GEM_DCFG1 0x0280 /* Design Config 1 */
-#define GEM_DCFG2 0x0284 /* Design Config 2 */
-#define GEM_DCFG3 0x0288 /* Design Config 3 */
-#define GEM_DCFG4 0x028c /* Design Config 4 */
-#define GEM_DCFG5 0x0290 /* Design Config 5 */
-#define GEM_DCFG6 0x0294 /* Design Config 6 */
-#define GEM_DCFG7 0x0298 /* Design Config 7 */
-
-#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
-#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
-#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
-#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
-#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
-#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
+#define GEM_NCFGR 0x0004 /* Network Config */
+#define GEM_USRIO 0x000c /* User IO */
+#define GEM_DMACFG 0x0010 /* DMA Configuration */
+#define GEM_HRB 0x0080 /* Hash Bottom */
+#define GEM_HRT 0x0084 /* Hash Top */
+#define GEM_SA1B 0x0088 /* Specific1 Bottom */
+#define GEM_SA1T 0x008C /* Specific1 Top */
+#define GEM_SA2B 0x0090 /* Specific2 Bottom */
+#define GEM_SA2T 0x0094 /* Specific2 Top */
+#define GEM_SA3B 0x0098 /* Specific3 Bottom */
+#define GEM_SA3T 0x009C /* Specific3 Top */
+#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
+#define GEM_SA4T 0x00A4 /* Specific4 Top */
+#define GEM_OTX 0x0100 /* Octets transmitted */
+#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
+#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
+#define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
+#define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
+#define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
+#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
+#define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
+#define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
+#define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
+#define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
+#define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
+#define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
+#define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
+#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
+#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
+#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
+#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
+#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
+#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
+#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
+#define GEM_ORX 0x0150 /* Octets received */
+#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
+#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
+#define GEM_RXCNT 0x0158 /* Frames Received Counter */
+#define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
+#define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
+#define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
+#define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
+#define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
+#define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
+#define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
+#define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
+#define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
+#define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
+#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
+#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
+#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
+#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
+#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
+#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
+#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
+#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
+#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
+#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
+#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
+#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
+#define GEM_DCFG1 0x0280 /* Design Config 1 */
+#define GEM_DCFG2 0x0284 /* Design Config 2 */
+#define GEM_DCFG3 0x0288 /* Design Config 3 */
+#define GEM_DCFG4 0x028c /* Design Config 4 */
+#define GEM_DCFG5 0x0290 /* Design Config 5 */
+#define GEM_DCFG6 0x0294 /* Design Config 6 */
+#define GEM_DCFG7 0x0298 /* Design Config 7 */
+
+#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
+#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
+#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
+#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
+#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
+#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
/* Bitfields in NCR */
-#define MACB_LB_OFFSET 0 /* reserved */
-#define MACB_LB_SIZE 1
-#define MACB_LLB_OFFSET 1 /* Loop back local */
-#define MACB_LLB_SIZE 1
-#define MACB_RE_OFFSET 2 /* Receive enable */
-#define MACB_RE_SIZE 1
-#define MACB_TE_OFFSET 3 /* Transmit enable */
-#define MACB_TE_SIZE 1
-#define MACB_MPE_OFFSET 4 /* Management port enable */
-#define MACB_MPE_SIZE 1
-#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
-#define MACB_CLRSTAT_SIZE 1
-#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
-#define MACB_INCSTAT_SIZE 1
-#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
-#define MACB_WESTAT_SIZE 1
-#define MACB_BP_OFFSET 8 /* Back pressure */
-#define MACB_BP_SIZE 1
-#define MACB_TSTART_OFFSET 9 /* Start transmission */
-#define MACB_TSTART_SIZE 1
-#define MACB_THALT_OFFSET 10 /* Transmit halt */
-#define MACB_THALT_SIZE 1
-#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
-#define MACB_NCR_TPF_SIZE 1
-#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum
- * pause frame
- */
-#define MACB_TZQ_SIZE 1
+#define MACB_LB_OFFSET 0 /* reserved */
+#define MACB_LB_SIZE 1
+#define MACB_LLB_OFFSET 1 /* Loop back local */
+#define MACB_LLB_SIZE 1
+#define MACB_RE_OFFSET 2 /* Receive enable */
+#define MACB_RE_SIZE 1
+#define MACB_TE_OFFSET 3 /* Transmit enable */
+#define MACB_TE_SIZE 1
+#define MACB_MPE_OFFSET 4 /* Management port enable */
+#define MACB_MPE_SIZE 1
+#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
+#define MACB_CLRSTAT_SIZE 1
+#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
+#define MACB_INCSTAT_SIZE 1
+#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
+#define MACB_WESTAT_SIZE 1
+#define MACB_BP_OFFSET 8 /* Back pressure */
+#define MACB_BP_SIZE 1
+#define MACB_TSTART_OFFSET 9 /* Start transmission */
+#define MACB_TSTART_SIZE 1
+#define MACB_THALT_OFFSET 10 /* Transmit halt */
+#define MACB_THALT_SIZE 1
+#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
+#define MACB_NCR_TPF_SIZE 1
+#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
+#define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */
-#define MACB_SPD_OFFSET 0 /* Speed */
-#define MACB_SPD_SIZE 1
-#define MACB_FD_OFFSET 1 /* Full duplex */
-#define MACB_FD_SIZE 1
-#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
-#define MACB_BIT_RATE_SIZE 1
-#define MACB_JFRAME_OFFSET 3 /* reserved */
-#define MACB_JFRAME_SIZE 1
-#define MACB_CAF_OFFSET 4 /* Copy all frames */
-#define MACB_CAF_SIZE 1
-#define MACB_NBC_OFFSET 5 /* No broadcast */
-#define MACB_NBC_SIZE 1
-#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
-#define MACB_NCFGR_MTI_SIZE 1
-#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
-#define MACB_UNI_SIZE 1
-#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
-#define MACB_BIG_SIZE 1
-#define MACB_EAE_OFFSET 9 /* External address match
- * enable
- */
-#define MACB_EAE_SIZE 1
-#define MACB_CLK_OFFSET 10
-#define MACB_CLK_SIZE 2
-#define MACB_RTY_OFFSET 12 /* Retry test */
-#define MACB_RTY_SIZE 1
-#define MACB_PAE_OFFSET 13 /* Pause enable */
-#define MACB_PAE_SIZE 1
-#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
-#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
-#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
-#define MACB_RBOF_SIZE 2
-#define MACB_RLCE_OFFSET 16 /* Length field error frame
- * discard
- */
-#define MACB_RLCE_SIZE 1
-#define MACB_DRFCS_OFFSET 17 /* FCS remove */
-#define MACB_DRFCS_SIZE 1
-#define MACB_EFRHD_OFFSET 18
-#define MACB_EFRHD_SIZE 1
-#define MACB_IRXFCS_OFFSET 19
-#define MACB_IRXFCS_SIZE 1
+#define MACB_SPD_OFFSET 0 /* Speed */
+#define MACB_SPD_SIZE 1
+#define MACB_FD_OFFSET 1 /* Full duplex */
+#define MACB_FD_SIZE 1
+#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
+#define MACB_BIT_RATE_SIZE 1
+#define MACB_JFRAME_OFFSET 3 /* reserved */
+#define MACB_JFRAME_SIZE 1
+#define MACB_CAF_OFFSET 4 /* Copy all frames */
+#define MACB_CAF_SIZE 1
+#define MACB_NBC_OFFSET 5 /* No broadcast */
+#define MACB_NBC_SIZE 1
+#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
+#define MACB_NCFGR_MTI_SIZE 1
+#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
+#define MACB_UNI_SIZE 1
+#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
+#define MACB_BIG_SIZE 1
+#define MACB_EAE_OFFSET 9 /* External address match enable */
+#define MACB_EAE_SIZE 1
+#define MACB_CLK_OFFSET 10
+#define MACB_CLK_SIZE 2
+#define MACB_RTY_OFFSET 12 /* Retry test */
+#define MACB_RTY_SIZE 1
+#define MACB_PAE_OFFSET 13 /* Pause enable */
+#define MACB_PAE_SIZE 1
+#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
+#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
+#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
+#define MACB_RBOF_SIZE 2
+#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
+#define MACB_RLCE_SIZE 1
+#define MACB_DRFCS_OFFSET 17 /* FCS remove */
+#define MACB_DRFCS_SIZE 1
+#define MACB_EFRHD_OFFSET 18
+#define MACB_EFRHD_SIZE 1
+#define MACB_IRXFCS_OFFSET 19
+#define MACB_IRXFCS_SIZE 1
/* GEM specific NCFGR bitfields. */
-#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
-#define GEM_GBE_SIZE 1
-#define GEM_CLK_OFFSET 18 /* MDC clock division */
-#define GEM_CLK_SIZE 3
-#define GEM_DBW_OFFSET 21 /* Data bus width */
-#define GEM_DBW_SIZE 2
-#define GEM_RXCOEN_OFFSET 24
-#define GEM_RXCOEN_SIZE 1
+#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
+#define GEM_GBE_SIZE 1
+#define GEM_CLK_OFFSET 18 /* MDC clock division */
+#define GEM_CLK_SIZE 3
+#define GEM_DBW_OFFSET 21 /* Data bus width */
+#define GEM_DBW_SIZE 2
+#define GEM_RXCOEN_OFFSET 24
+#define GEM_RXCOEN_SIZE 1
/* Constants for data bus width. */
-#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus
- * width
- */
-#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
- * width
- */
-#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
- * width
- */
+#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
+#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
+#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
/* Bitfields in DMACFG. */
-#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for
- * DMA data operations
- */
-#define GEM_FBLDO_SIZE 5
-#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable
- * for packet data accesses
- */
-#define GEM_ENDIA_SIZE 1
-#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer
- * memory size select
- */
-#define GEM_RXBMS_SIZE 2
-#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer
- * memory size select
- */
-#define GEM_TXPBMS_SIZE 1
-#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and
- * UDP checksum generation
- * offload enable
- */
-#define GEM_TXCOEN_SIZE 1
-#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in
- * AHB system memory
- */
-#define GEM_RXBS_SIZE 8
-#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
-#define GEM_DDRP_SIZE 1
+#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
+#define GEM_FBLDO_SIZE 5
+#define GEM_ENDIA_OFFSET 7 /* endian swap mode for packet data access */
+#define GEM_ENDIA_SIZE 1
+#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
+#define GEM_RXBMS_SIZE 2
+#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
+#define GEM_TXPBMS_SIZE 1
+#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
+#define GEM_TXCOEN_SIZE 1
+#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
+#define GEM_RXBS_SIZE 8
+#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
+#define GEM_DDRP_SIZE 1
/* Bitfields in NSR */
-#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
-#define MACB_NSR_LINK_SIZE 1
-#define MACB_MDIO_OFFSET 1 /* status of the mdio_in
- * pin
- */
-#define MACB_MDIO_SIZE 1
-#define MACB_IDLE_OFFSET 2 /* The PHY management logic is
- * idle (i.e. has completed)
- */
-#define MACB_IDLE_SIZE 1
+#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
+#define MACB_NSR_LINK_SIZE 1
+#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
+#define MACB_MDIO_SIZE 1
+#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
+#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
-#define MACB_UBR_OFFSET 0 /* Used bit read */
-#define MACB_UBR_SIZE 1
-#define MACB_COL_OFFSET 1 /* Collision occurred */
-#define MACB_COL_SIZE 1
-#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
-#define MACB_TSR_RLE_SIZE 1
-#define MACB_TGO_OFFSET 3 /* Transmit go */
-#define MACB_TGO_SIZE 1
-#define MACB_BEX_OFFSET 4 /* Transmit frame corruption
- * due to AHB error
- */
-#define MACB_BEX_SIZE 1
-#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
-#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
-#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
-#define MACB_COMP_SIZE 1
-#define MACB_UND_OFFSET 6 /* Trnasmit under run */
-#define MACB_UND_SIZE 1
+#define MACB_UBR_OFFSET 0 /* Used bit read */
+#define MACB_UBR_SIZE 1
+#define MACB_COL_OFFSET 1 /* Collision occurred */
+#define MACB_COL_SIZE 1
+#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
+#define MACB_TSR_RLE_SIZE 1
+#define MACB_TGO_OFFSET 3 /* Transmit go */
+#define MACB_TGO_SIZE 1
+#define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
+#define MACB_BEX_SIZE 1
+#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
+#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
+#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
+#define MACB_COMP_SIZE 1
+#define MACB_UND_OFFSET 6 /* Trnasmit under run */
+#define MACB_UND_SIZE 1
/* Bitfields in RSR */
-#define MACB_BNA_OFFSET 0 /* Buffer not available */
-#define MACB_BNA_SIZE 1
-#define MACB_REC_OFFSET 1 /* Frame received */
-#define MACB_REC_SIZE 1
-#define MACB_OVR_OFFSET 2 /* Receive overrun */
-#define MACB_OVR_SIZE 1
+#define MACB_BNA_OFFSET 0 /* Buffer not available */
+#define MACB_BNA_SIZE 1
+#define MACB_REC_OFFSET 1 /* Frame received */
+#define MACB_REC_SIZE 1
+#define MACB_OVR_OFFSET 2 /* Receive overrun */
+#define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */
-#define MACB_MFD_OFFSET 0 /* Management frame sent */
-#define MACB_MFD_SIZE 1
-#define MACB_RCOMP_OFFSET 1 /* Receive complete */
-#define MACB_RCOMP_SIZE 1
-#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
-#define MACB_RXUBR_SIZE 1
-#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
-#define MACB_TXUBR_SIZE 1
-#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer
- * under run interrupt
- */
-#define MACB_ISR_TUND_SIZE 1
-#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded
- * or late collision interrupt
- */
-#define MACB_ISR_RLE_SIZE 1
-#define MACB_TXERR_OFFSET 6 /* Enable transmit frame
- * corruption due to AHB error
- * interrupt
- */
-#define MACB_TXERR_SIZE 1
-#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete
- * interrupt
- */
-#define MACB_TCOMP_SIZE 1
-#define MACB_ISR_LINK_OFFSET 9 /* Enable link change
- * interrupt
- */
-#define MACB_ISR_LINK_SIZE 1
-#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun
- * interrupt
- */
-#define MACB_ISR_ROVR_SIZE 1
-#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK
- * interrupt
- */
-#define MACB_HRESP_SIZE 1
-#define MACB_PFR_OFFSET 12 /* Enable pause frame with
- * non-zero pause quantum
- * interrupt
- */
-#define MACB_PFR_SIZE 1
-#define MACB_PTZ_OFFSET 13 /* Enable pause time zero
- * interrupt
- */
-#define MACB_PTZ_SIZE 1
+#define MACB_MFD_OFFSET 0 /* Management frame sent */
+#define MACB_MFD_SIZE 1
+#define MACB_RCOMP_OFFSET 1 /* Receive complete */
+#define MACB_RCOMP_SIZE 1
+#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
+#define MACB_RXUBR_SIZE 1
+#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
+#define MACB_TXUBR_SIZE 1
+#define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
+#define MACB_ISR_TUND_SIZE 1
+#define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
+#define MACB_ISR_RLE_SIZE 1
+#define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
+#define MACB_TXERR_SIZE 1
+#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
+#define MACB_TCOMP_SIZE 1
+#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
+#define MACB_ISR_LINK_SIZE 1
+#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
+#define MACB_ISR_ROVR_SIZE 1
+#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
+#define MACB_HRESP_SIZE 1
+#define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
+#define MACB_PFR_SIZE 1
+#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
+#define MACB_PTZ_SIZE 1
/* Bitfields in MAN */
-#define MACB_DATA_OFFSET 0 /* data */
-#define MACB_DATA_SIZE 16
-#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
-#define MACB_CODE_SIZE 2
-#define MACB_REGA_OFFSET 18 /* Register address */
-#define MACB_REGA_SIZE 5
-#define MACB_PHYA_OFFSET 23 /* PHY address */
-#define MACB_PHYA_SIZE 5
-#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01
- * is write.
- */
-#define MACB_RW_SIZE 2
-#define MACB_SOF_OFFSET 30 /* Must be written to 1 for
- * Clause 22 operation
- */
-#define MACB_SOF_SIZE 2
+#define MACB_DATA_OFFSET 0 /* data */
+#define MACB_DATA_SIZE 16
+#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
+#define MACB_CODE_SIZE 2
+#define MACB_REGA_OFFSET 18 /* Register address */
+#define MACB_REGA_SIZE 5
+#define MACB_PHYA_OFFSET 23 /* PHY address */
+#define MACB_PHYA_SIZE 5
+#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
+#define MACB_RW_SIZE 2
+#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
+#define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */
#define MACB_MII_OFFSET 0
@@ -597,8 +435,7 @@
#define queue_writel(queue, reg, value) \
__raw_writel((value), (queue)->bp->regs + (queue)->reg)
-/*
- * Conditional GEM/MACB macros. These perform the operation to the correct
+/* Conditional GEM/MACB macros. These perform the operation to the correct
* register dependent on whether the device is a GEM or a MACB. For registers
* and bitfields that are common across both devices, use macb_{read,write}l
* to avoid the cost of the conditional.
@@ -621,8 +458,7 @@
__v; \
})
-/**
- * struct macb_dma_desc - Hardware DMA descriptor
+/* struct macb_dma_desc - Hardware DMA descriptor
* @addr: DMA address of data buffer
* @ctrl: Control and status bits
*/
@@ -711,8 +547,7 @@ struct macb_dma_desc {
/* limit RX checksum offload to TCP and UDP packets */
#define GEM_RX_CSUM_CHECKED_MASK 2
-/**
- * struct macb_tx_skb - data about an skb which is being transmitted
+/* struct macb_tx_skb - data about an skb which is being transmitted
* @skb: skb currently being transmitted, only set for the last buffer
* of the frame
* @mapping: DMA address of the skb's fragment buffer
@@ -727,8 +562,7 @@ struct macb_tx_skb {
bool mapped_as_page;
};
-/*
- * Hardware-collected statistics. Used when updating the network
+/* Hardware-collected statistics. Used when updating the network
* device stats by a periodic timer.
*/
struct macb_stats {
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators
2015-01-15 21:55 ` Xander Huff
@ 2015-01-15 21:55 ` Xander Huff
2015-01-15 21:55 ` [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions Xander Huff
1 sibling, 0 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-15 21:55 UTC (permalink / raw)
To: davem, nicolas.ferre, david.laight
Cc: netdev, jaeden.amero, rich.tollerton, brad.mouring, linux-kernel,
cyrille.pitchen, Xander Huff
Spaces should surround add, multiply, and bitshift operators.
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
Re-sending to properly include David Laight
drivers/net/ethernet/cadence/macb.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index dd8c202..9edd787 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1691,7 +1691,7 @@ static int hash_get_index(__u8 *addr)
for (j = 0; j < 6; j++) {
for (i = 0, bitval = 0; i < 8; i++)
- bitval ^= hash_bit_value(i*6 + j, addr);
+ bitval ^= hash_bit_value(i * 6 + j, addr);
hash_index |= (bitval << j);
}
@@ -1832,15 +1832,15 @@ static void gem_update_stats(struct macb *bp)
for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
u32 offset = gem_statistics[i].offset;
- u64 val = __raw_readl(bp->regs+offset);
+ u64 val = __raw_readl(bp->regs + offset);
bp->ethtool_stats[i] += val;
*p += val;
if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
/* Add GEM_OCTTXH, GEM_OCTRXH */
- val = __raw_readl(bp->regs+offset+4);
- bp->ethtool_stats[i] += ((u64)val)<<32;
+ val = __raw_readl(bp->regs + offset + 4);
+ bp->ethtool_stats[i] += ((u64)val) << 32;
*(++p) += val;
}
}
@@ -1891,7 +1891,7 @@ static void gem_get_ethtool_stats(struct net_device *dev,
bp = netdev_priv(dev);
gem_update_stats(bp);
- memcpy(data, &bp->ethtool_stats, sizeof(u64)*GEM_STATS_LEN);
+ memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
}
static int gem_get_sset_count(struct net_device *dev, int sset)
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions
2015-01-15 21:55 ` Xander Huff
2015-01-15 21:55 ` [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators Xander Huff
@ 2015-01-15 21:55 ` Xander Huff
1 sibling, 0 replies; 29+ messages in thread
From: Xander Huff @ 2015-01-15 21:55 UTC (permalink / raw)
To: davem, nicolas.ferre, david.laight
Cc: netdev, jaeden.amero, rich.tollerton, brad.mouring, linux-kernel,
cyrille.pitchen, Xander Huff
10/100 MACB does not have the same statistics possibilities as GEM. Separate
macb_ethtool_ops to make a new GEM-specific struct with the new statistics
functions included.
Signed-off-by: Xander Huff <xander.huff@ni.com>
---
Re-sending to properly include David Laight
drivers/net/ethernet/cadence/macb.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 9edd787..f2f9ca0 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2032,11 +2032,21 @@ const struct ethtool_ops macb_ethtool_ops = {
.get_regs = macb_get_regs,
.get_link = ethtool_op_get_link,
.get_ts_info = ethtool_op_get_ts_info,
+};
+EXPORT_SYMBOL_GPL(macb_ethtool_ops);
+
+const struct ethtool_ops gem_ethtool_ops = {
+ .get_settings = macb_get_settings,
+ .set_settings = macb_set_settings,
+ .get_regs_len = macb_get_regs_len,
+ .get_regs = macb_get_regs,
+ .get_link = ethtool_op_get_link,
+ .get_ts_info = ethtool_op_get_ts_info,
.get_ethtool_stats = gem_get_ethtool_stats,
.get_strings = gem_get_ethtool_strings,
.get_sset_count = gem_get_sset_count,
};
-EXPORT_SYMBOL_GPL(macb_ethtool_ops);
+EXPORT_SYMBOL_GPL(gem_ethtool_ops);
int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
@@ -2325,7 +2335,6 @@ static int __init macb_probe(struct platform_device *pdev)
dev->netdev_ops = &macb_netdev_ops;
netif_napi_add(dev, &bp->napi, macb_poll, 64);
- dev->ethtool_ops = &macb_ethtool_ops;
dev->base_addr = regs->start;
@@ -2339,12 +2348,14 @@ static int __init macb_probe(struct platform_device *pdev)
bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
bp->macbgem_ops.mog_init_rings = gem_init_rings;
bp->macbgem_ops.mog_rx = gem_rx;
+ dev->ethtool_ops = &gem_ethtool_ops;
} else {
bp->max_tx_length = MACB_MAX_TX_LEN;
bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
bp->macbgem_ops.mog_init_rings = macb_init_rings;
bp->macbgem_ops.mog_rx = macb_rx;
+ dev->ethtool_ops = &macb_ethtool_ops;
}
/* Set features */
--
1.9.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines
2015-01-15 21:45 ` [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines Xander Huff
2015-01-15 21:45 ` [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators Xander Huff
2015-01-15 21:45 ` [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions Xander Huff
@ 2015-01-16 5:31 ` David Miller
2 siblings, 0 replies; 29+ messages in thread
From: David Miller @ 2015-01-16 5:31 UTC (permalink / raw)
To: xander.huff
Cc: nicolas.ferre, david.light, netdev, jaeden.amero, rich.tollerton,
brad.mouring, linux-kernel, cyrille.pitchen
From: Xander Huff <xander.huff@ni.com>
Date: Thu, 15 Jan 2015 15:45:14 -0600
> Change comments to not exceed 80 characters per line.
> Update block comments in macb.h to start on the line after /*.
>
> Signed-off-by: Xander Huff <xander.huff@ni.com>
Applied.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators
2015-01-15 21:45 ` [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators Xander Huff
@ 2015-01-16 5:32 ` David Miller
0 siblings, 0 replies; 29+ messages in thread
From: David Miller @ 2015-01-16 5:32 UTC (permalink / raw)
To: xander.huff
Cc: nicolas.ferre, david.light, netdev, jaeden.amero, rich.tollerton,
brad.mouring, linux-kernel, cyrille.pitchen
From: Xander Huff <xander.huff@ni.com>
Date: Thu, 15 Jan 2015 15:45:15 -0600
> Spaces should surround add, multiply, and bitshift operators.
>
> Signed-off-by: Xander Huff <xander.huff@ni.com>
Applied.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions
2015-01-15 21:45 ` [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions Xander Huff
@ 2015-01-16 5:32 ` David Miller
0 siblings, 0 replies; 29+ messages in thread
From: David Miller @ 2015-01-16 5:32 UTC (permalink / raw)
To: xander.huff
Cc: nicolas.ferre, david.light, netdev, jaeden.amero, rich.tollerton,
brad.mouring, linux-kernel, cyrille.pitchen
From: Xander Huff <xander.huff@ni.com>
Date: Thu, 15 Jan 2015 15:45:16 -0600
> 10/100 MACB does not have the same statistics possibilities as GEM. Separate
> macb_ethtool_ops to make a new GEM-specific struct with the new statistics
> functions included.
>
> Signed-off-by: Xander Huff <xander.huff@ni.com>
Applied.
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2015-01-16 5:32 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-13 22:15 [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier Xander Huff
2015-01-13 22:15 ` [PATCH 2/2] net/macb: improved ethtool statistics support Xander Huff
2015-01-14 5:26 ` David Miller
2015-01-14 15:53 ` Nicolas Ferre
2015-01-14 20:21 ` [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier Xander Huff
2015-01-14 20:21 ` [PATCH 2/2] fixup! net/macb: improved ethtool statistics support Xander Huff
2015-01-14 21:09 ` [PATCH 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier David Miller
2015-01-14 21:18 ` Xander Huff
2015-01-14 21:52 ` David Miller
2015-01-14 22:20 ` [PATCH v2 " Xander Huff
2015-01-14 22:20 ` [PATCH v2 2/2] fixup! net/macb: improved ethtool statistics support Xander Huff
2015-01-15 10:35 ` Nicolas Ferre
2015-01-15 15:32 ` Xander Huff
2015-01-15 10:05 ` [PATCH v2 1/2] fixup! net/macb: Adding comments to various #defs to make interpretation easier Nicolas Ferre
2015-01-15 11:46 ` David Laight
2015-01-15 21:45 ` [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines Xander Huff
2015-01-15 21:45 ` [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators Xander Huff
2015-01-16 5:32 ` David Miller
2015-01-15 21:45 ` [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions Xander Huff
2015-01-16 5:32 ` David Miller
2015-01-16 5:31 ` [PATCH v3 1/3] net/macb: Fix comments to meet style guidelines David Miller
2015-01-15 21:55 ` Xander Huff
2015-01-15 21:55 ` [PATCH v3 2/3] net/macb: Add whitespace around arithmetic operators Xander Huff
2015-01-15 21:55 ` [PATCH v3 3/3] net/macb: Create gem_ethtool_ops for new statistics functions Xander Huff
2015-01-14 21:04 ` [PATCH 2/2] net/macb: improved ethtool statistics support David Miller
2015-01-14 5:26 ` [PATCH 1/2] net/macb: Adding comments to various #defs to make interpretation easier David Miller
2015-01-14 15:11 ` Brad Mouring
2015-01-14 15:10 ` Nicolas Ferre
[not found] ` <OFE030E01C.93929A2C-ON86257DCD.00524615-86257DCD.0052461A@ni.com>
2015-01-14 21:02 ` David Miller
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