* [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well
@ 2015-01-29 12:42 Damien Lespiau
2015-01-30 16:23 ` Daniel Vetter
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Damien Lespiau @ 2015-01-29 12:42 UTC (permalink / raw)
To: intel-gfx
Suggested-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0e9bf82..0a1089b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -329,7 +329,8 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
if (HAS_FPGA_DBG_UNCLAIMED(dev))
__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
- if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
+ if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
+ INTEL_INFO(dev)->gen >= 9) &&
(__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
/* The docs do not explain exactly how the calculation can be
* made. It is somewhat guessable, but for now, it's always
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well
2015-01-29 12:42 [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well Damien Lespiau
@ 2015-01-30 16:23 ` Daniel Vetter
2015-02-02 15:08 ` Damien Lespiau
2015-01-30 17:10 ` Ville Syrjälä
2015-01-31 17:30 ` shuang.he
2 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2015-01-30 16:23 UTC (permalink / raw)
To: Damien Lespiau; +Cc: intel-gfx
On Thu, Jan 29, 2015 at 12:42:35PM +0000, Damien Lespiau wrote:
> Suggested-by: Daniel Vetter <daniel@ffwll.ch>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Hm, I've thought the magic bit moved ... or have you found it in configdb
again?
-Daniel
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 0e9bf82..0a1089b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -329,7 +329,8 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
> if (HAS_FPGA_DBG_UNCLAIMED(dev))
> __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
>
> - if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
> + if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
> + INTEL_INFO(dev)->gen >= 9) &&
> (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
> /* The docs do not explain exactly how the calculation can be
> * made. It is somewhat guessable, but for now, it's always
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well
2015-01-30 16:23 ` Daniel Vetter
@ 2015-02-02 15:08 ` Damien Lespiau
0 siblings, 0 replies; 5+ messages in thread
From: Damien Lespiau @ 2015-02-02 15:08 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Fri, Jan 30, 2015 at 05:23:06PM +0100, Daniel Vetter wrote:
> On Thu, Jan 29, 2015 at 12:42:35PM +0000, Damien Lespiau wrote:
> > Suggested-by: Daniel Vetter <daniel@ffwll.ch>
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>
> Hm, I've thought the magic bit moved ... or have you found it in configdb
> again?
The eDRAM present bit is still bit 0. However the code has changed and
the patch needs rebasing already. Also I realized we don't actually
select bit 0 and compare with the full register value. Patches to
follow...
--
Damien
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well
2015-01-29 12:42 [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well Damien Lespiau
2015-01-30 16:23 ` Daniel Vetter
@ 2015-01-30 17:10 ` Ville Syrjälä
2015-01-31 17:30 ` shuang.he
2 siblings, 0 replies; 5+ messages in thread
From: Ville Syrjälä @ 2015-01-30 17:10 UTC (permalink / raw)
To: Damien Lespiau; +Cc: intel-gfx
On Thu, Jan 29, 2015 at 12:42:35PM +0000, Damien Lespiau wrote:
> Suggested-by: Daniel Vetter <daniel@ffwll.ch>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 0e9bf82..0a1089b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -329,7 +329,8 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
> if (HAS_FPGA_DBG_UNCLAIMED(dev))
> __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
>
> - if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
> + if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
> + INTEL_INFO(dev)->gen >= 9) &&
Should this perhaps be IS_SKYLAKE()?
> (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
> /* The docs do not explain exactly how the calculation can be
> * made. It is somewhat guessable, but for now, it's always
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well
2015-01-29 12:42 [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well Damien Lespiau
2015-01-30 16:23 ` Daniel Vetter
2015-01-30 17:10 ` Ville Syrjälä
@ 2015-01-31 17:30 ` shuang.he
2 siblings, 0 replies; 5+ messages in thread
From: shuang.he @ 2015-01-31 17:30 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, damien.lespiau
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5681
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 353/353 353/353
ILK 200/200 200/200
SNB 400/422 400/422
IVB +2 485/487 487/487
BYT 296/296 296/296
HSW +1-1 507/508 507/508
BDW 401/402 401/402
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
IVB igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(6, M34M21)PASS(8, M4M34) PASS(1, M4)
IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(5, M34M4)PASS(15, M34M4M21) PASS(1, M4)
HSW igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1, M40)PASS(18, M40M20) PASS(1, M40)
*HSW igt_gem_pwrite_pread_uncached-copy-performance PASS(2, M40) DMESG_WARN(1, M40)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-02-02 15:08 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2015-01-29 12:42 [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well Damien Lespiau
2015-01-30 16:23 ` Daniel Vetter
2015-02-02 15:08 ` Damien Lespiau
2015-01-30 17:10 ` Ville Syrjälä
2015-01-31 17:30 ` shuang.he
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