* Octeon breakage from 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed
@ 2015-02-23 18:48 Paul Martin
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From: Paul Martin @ 2015-02-23 18:48 UTC (permalink / raw)
To: linux-mips
Commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed
MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction
causes problems on Octeon when trying to run a 4.0-rc1 kernel:
Kernel panic - not syncing: No TLB refill handler yet (CPU type: 79)
as arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
contains
#define cpu_has_mips64r2 1
#define cpu_has_mips_r2_exec_hazard 0
Reverting the patch allows the kernel to boot normally.
I'm not sure which is wrong: the use of cpu_has_mips_r2_exec_hazard to
detect the EHB instruction, or the Cavium headers. I suspect the
override in the latter may be wrong.
I'll just note that 3.19 does not make any use of this value.
--
Paul Martin http://www.codethink.co.uk/
Senior Software Developer, Codethink Ltd.
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2015-02-23 18:48 Octeon breakage from 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed Paul Martin
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