* [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry
@ 2015-03-04 22:22 Marek Vasut
2015-03-04 22:22 ` [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI " Marek Vasut
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Marek Vasut @ 2015-03-04 22:22 UTC (permalink / raw)
To: u-boot
Add DWC SPI controller Kconfig entry.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
---
drivers/spi/Kconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7ae2727..c0b2570 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -10,3 +10,9 @@ config DM_SPI
as 'parent data' to every slave on each bus. Slaves
typically use driver-private data instead of extending the
spi_slave structure.
+
+config DESIGNWARE_SPI
+ bool "Designware SPI driver"
+ depends on DM_SPI
+ help
+ Enable the Designware SPI driver.
--
2.1.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
2015-03-04 22:22 [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry Marek Vasut
@ 2015-03-04 22:22 ` Marek Vasut
2015-03-05 9:47 ` Stefan Roese
2015-03-05 15:58 ` Simon Glass
2015-03-05 9:47 ` [U-Boot] [PATCH 1/2] spi: Add Designware SPI " Stefan Roese
` (2 subsequent siblings)
3 siblings, 2 replies; 12+ messages in thread
From: Marek Vasut @ 2015-03-04 22:22 UTC (permalink / raw)
To: u-boot
Add Cadence QSPI controller Kconfig entry.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
---
drivers/spi/Kconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c0b2570..eaf31ed 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -16,3 +16,9 @@ config DESIGNWARE_SPI
depends on DM_SPI
help
Enable the Designware SPI driver.
+
+config CADENCE_QSPI
+ bool "Cadence QSPI driver"
+ depends on DM_SPI
+ help
+ Enable the Cadence QSPI driver.
--
2.1.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry
2015-03-04 22:22 [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry Marek Vasut
2015-03-04 22:22 ` [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI " Marek Vasut
@ 2015-03-05 9:47 ` Stefan Roese
2015-03-05 10:57 ` Pavel Machek
2015-03-05 19:48 ` Simon Glass
3 siblings, 0 replies; 12+ messages in thread
From: Stefan Roese @ 2015-03-05 9:47 UTC (permalink / raw)
To: u-boot
On 04.03.2015 23:22, Marek Vasut wrote:
> Add DWC SPI controller Kconfig entry.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Vince Bridgers <vbridger@opensource.altera.com>
Acked-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
2015-03-04 22:22 ` [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI " Marek Vasut
@ 2015-03-05 9:47 ` Stefan Roese
2015-03-05 15:58 ` Simon Glass
1 sibling, 0 replies; 12+ messages in thread
From: Stefan Roese @ 2015-03-05 9:47 UTC (permalink / raw)
To: u-boot
On 04.03.2015 23:22, Marek Vasut wrote:
> Add Cadence QSPI controller Kconfig entry.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Vince Bridgers <vbridger@opensource.altera.com>
Acked-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry
2015-03-04 22:22 [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry Marek Vasut
2015-03-04 22:22 ` [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI " Marek Vasut
2015-03-05 9:47 ` [U-Boot] [PATCH 1/2] spi: Add Designware SPI " Stefan Roese
@ 2015-03-05 10:57 ` Pavel Machek
2015-03-05 19:48 ` Simon Glass
3 siblings, 0 replies; 12+ messages in thread
From: Pavel Machek @ 2015-03-05 10:57 UTC (permalink / raw)
To: u-boot
On Wed 2015-03-04 23:22:50, Marek Vasut wrote:
> Add DWC SPI controller Kconfig entry.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
(For both patches in the series).
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
2015-03-04 22:22 ` [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI " Marek Vasut
2015-03-05 9:47 ` Stefan Roese
@ 2015-03-05 15:58 ` Simon Glass
2015-03-05 16:14 ` Marek Vasut
1 sibling, 1 reply; 12+ messages in thread
From: Simon Glass @ 2015-03-05 15:58 UTC (permalink / raw)
To: u-boot
Hi Marek,
On 4 March 2015 at 15:22, Marek Vasut <marex@denx.de> wrote:
> Add Cadence QSPI controller Kconfig entry.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Vince Bridgers <vbridger@opensource.altera.com>
> ---
> drivers/spi/Kconfig | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index c0b2570..eaf31ed 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
> depends on DM_SPI
> help
> Enable the Designware SPI driver.
> +
> +config CADENCE_QSPI
> + bool "Cadence QSPI driver"
> + depends on DM_SPI
> + help
> + Enable the Cadence QSPI driver.
Can we get a bit more detail here? What does QSPI mean? What features
does it support?
Regards,
Simon
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
2015-03-05 15:58 ` Simon Glass
@ 2015-03-05 16:14 ` Marek Vasut
2015-03-05 16:30 ` Stefan Roese
0 siblings, 1 reply; 12+ messages in thread
From: Marek Vasut @ 2015-03-05 16:14 UTC (permalink / raw)
To: u-boot
On Thursday, March 05, 2015 at 04:58:19 PM, Simon Glass wrote:
> Hi Marek,
>
> On 4 March 2015 at 15:22, Marek Vasut <marex@denx.de> wrote:
> > Add Cadence QSPI controller Kconfig entry.
> >
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Chin Liang See <clsee@opensource.altera.com>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> > Cc: Pavel Machek <pavel@denx.de>
> > Cc: Simon Glass <sjg@chromium.org>
> > Cc: Stefan Roese <sr@denx.de>
> > Cc: Tom Rini <trini@konsulko.com>
> > Cc: Vince Bridgers <vbridger@opensource.altera.com>
> > ---
> >
> > drivers/spi/Kconfig | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index c0b2570..eaf31ed 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
> >
> > depends on DM_SPI
> > help
> >
> > Enable the Designware SPI driver.
> >
> > +
> > +config CADENCE_QSPI
> > + bool "Cadence QSPI driver"
> > + depends on DM_SPI
> > + help
> > + Enable the Cadence QSPI driver.
>
> Can we get a bit more detail here? What does QSPI mean? What features
> does it support?
Stefan ? ;-)
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
2015-03-05 16:14 ` Marek Vasut
@ 2015-03-05 16:30 ` Stefan Roese
2015-03-05 16:39 ` Tom Rini
0 siblings, 1 reply; 12+ messages in thread
From: Stefan Roese @ 2015-03-05 16:30 UTC (permalink / raw)
To: u-boot
On 05.03.2015 17:14, Marek Vasut wrote:
>>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>>> index c0b2570..eaf31ed 100644
>>> --- a/drivers/spi/Kconfig
>>> +++ b/drivers/spi/Kconfig
>>> @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
>>>
>>> depends on DM_SPI
>>> help
>>>
>>> Enable the Designware SPI driver.
>>>
>>> +
>>> +config CADENCE_QSPI
>>> + bool "Cadence QSPI driver"
>>> + depends on DM_SPI
>>> + help
>>> + Enable the Cadence QSPI driver.
>>
>> Can we get a bit more detail here? What does QSPI mean? What features
>> does it support?
>
> Stefan ? ;-)
Its the IP core from Cadence supporting SPI NOR flash and is present on
the Altera SoCFPGA. Enabling access to such SPI NOR flash devices. QSPI
stands for Quad-SPI and refers to the optional use of up to 4 data lines
for flash access.
So perhaps something like this:
+
+config CADENCE_QSPI
+ bool "Cadence QSPI driver"
+ depends on DM_SPI
+ help
+ Enable the Cadence QSPI driver. This driver can be used to +
access the SPI NOR flash on platforms embedding this
+ Cadence IP core (like the Altera SoCFPGA). QSPI stands for
+ Quad-SPI and refers to the optional use of up to 4 data lines
+ for flash access.
HTP.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
2015-03-05 16:30 ` Stefan Roese
@ 2015-03-05 16:39 ` Tom Rini
2015-03-05 16:47 ` Stefan Roese
0 siblings, 1 reply; 12+ messages in thread
From: Tom Rini @ 2015-03-05 16:39 UTC (permalink / raw)
To: u-boot
On Thu, Mar 05, 2015 at 05:30:26PM +0100, Stefan Roese wrote:
> On 05.03.2015 17:14, Marek Vasut wrote:
> >>>diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> >>>index c0b2570..eaf31ed 100644
> >>>--- a/drivers/spi/Kconfig
> >>>+++ b/drivers/spi/Kconfig
> >>>@@ -16,3 +16,9 @@ config DESIGNWARE_SPI
> >>>
> >>> depends on DM_SPI
> >>> help
> >>>
> >>> Enable the Designware SPI driver.
> >>>
> >>>+
> >>>+config CADENCE_QSPI
> >>>+ bool "Cadence QSPI driver"
> >>>+ depends on DM_SPI
> >>>+ help
> >>>+ Enable the Cadence QSPI driver.
> >>
> >>Can we get a bit more detail here? What does QSPI mean? What features
> >>does it support?
> >
> >Stefan ? ;-)
>
> Its the IP core from Cadence supporting SPI NOR flash and is present
> on the Altera SoCFPGA. Enabling access to such SPI NOR flash
> devices. QSPI stands for Quad-SPI and refers to the optional use of
> up to 4 data lines for flash access.
>
> So perhaps something like this:
>
> +
> +config CADENCE_QSPI
> + bool "Cadence QSPI driver"
> + depends on DM_SPI
> + help
> + Enable the Cadence QSPI driver. This driver can be used to +
> access the SPI NOR flash on platforms embedding this
> + Cadence IP core (like the Altera SoCFPGA). QSPI stands for
> + Quad-SPI and refers to the optional use of up to 4 data lines
> + for flash access.
Please don't mention platforms in the help for what I think of as
IP-block-vendor drivers. The Cadence QSPI block will be reused by
others and I can see someone "needing" to patch the help text. How
about:
Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to
access the SPI NOR flash on platforms embedding this
Cadence IP core.
--
Tom
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
2015-03-05 16:39 ` Tom Rini
@ 2015-03-05 16:47 ` Stefan Roese
2015-03-05 20:48 ` Marek Vasut
0 siblings, 1 reply; 12+ messages in thread
From: Stefan Roese @ 2015-03-05 16:47 UTC (permalink / raw)
To: u-boot
On 05.03.2015 17:39, Tom Rini wrote:
> On Thu, Mar 05, 2015 at 05:30:26PM +0100, Stefan Roese wrote:
>> On 05.03.2015 17:14, Marek Vasut wrote:
>>>>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>>>>> index c0b2570..eaf31ed 100644
>>>>> --- a/drivers/spi/Kconfig
>>>>> +++ b/drivers/spi/Kconfig
>>>>> @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
>>>>>
>>>>> depends on DM_SPI
>>>>> help
>>>>>
>>>>> Enable the Designware SPI driver.
>>>>>
>>>>> +
>>>>> +config CADENCE_QSPI
>>>>> + bool "Cadence QSPI driver"
>>>>> + depends on DM_SPI
>>>>> + help
>>>>> + Enable the Cadence QSPI driver.
>>>>
>>>> Can we get a bit more detail here? What does QSPI mean? What features
>>>> does it support?
>>>
>>> Stefan ? ;-)
>>
>> Its the IP core from Cadence supporting SPI NOR flash and is present
>> on the Altera SoCFPGA. Enabling access to such SPI NOR flash
>> devices. QSPI stands for Quad-SPI and refers to the optional use of
>> up to 4 data lines for flash access.
>>
>> So perhaps something like this:
>>
>> +
>> +config CADENCE_QSPI
>> + bool "Cadence QSPI driver"
>> + depends on DM_SPI
>> + help
>> + Enable the Cadence QSPI driver. This driver can be used to +
>> access the SPI NOR flash on platforms embedding this
>> + Cadence IP core (like the Altera SoCFPGA). QSPI stands for
>> + Quad-SPI and refers to the optional use of up to 4 data lines
>> + for flash access.
>
> Please don't mention platforms in the help for what I think of as
> IP-block-vendor drivers. The Cadence QSPI block will be reused by
> others and I can see someone "needing" to patch the help text. How
> about:
> Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to
> access the SPI NOR flash on platforms embedding this
> Cadence IP core.
Even better.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry
2015-03-04 22:22 [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry Marek Vasut
` (2 preceding siblings ...)
2015-03-05 10:57 ` Pavel Machek
@ 2015-03-05 19:48 ` Simon Glass
3 siblings, 0 replies; 12+ messages in thread
From: Simon Glass @ 2015-03-05 19:48 UTC (permalink / raw)
To: u-boot
Hi,
On 4 March 2015 at 15:22, Marek Vasut <marex@denx.de> wrote:
> Add DWC SPI controller Kconfig entry.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@opensource.altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Vince Bridgers <vbridger@opensource.altera.com>
> ---
> drivers/spi/Kconfig | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 7ae2727..c0b2570 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -10,3 +10,9 @@ config DM_SPI
> as 'parent data' to every slave on each bus. Slaves
> typically use driver-private data instead of extending the
> spi_slave structure.
> +
> +config DESIGNWARE_SPI
> + bool "Designware SPI driver"
> + depends on DM_SPI
> + help
> + Enable the Designware SPI driver.
At least for driver model I'd like to have a nice long help message.
Regards,
Simon
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
2015-03-05 16:47 ` Stefan Roese
@ 2015-03-05 20:48 ` Marek Vasut
0 siblings, 0 replies; 12+ messages in thread
From: Marek Vasut @ 2015-03-05 20:48 UTC (permalink / raw)
To: u-boot
On Thursday, March 05, 2015 at 05:47:01 PM, Stefan Roese wrote:
[...]
> > Please don't mention platforms in the help for what I think of as
> > IP-block-vendor drivers. The Cadence QSPI block will be reused by
> > others and I can see someone "needing" to patch the help text. How
> >
> > about:
> > Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to
> > access the SPI NOR flash on platforms embedding this
> > Cadence IP core.
>
> Even better.
Thanks
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2015-03-05 20:48 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-04 22:22 [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry Marek Vasut
2015-03-04 22:22 ` [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI " Marek Vasut
2015-03-05 9:47 ` Stefan Roese
2015-03-05 15:58 ` Simon Glass
2015-03-05 16:14 ` Marek Vasut
2015-03-05 16:30 ` Stefan Roese
2015-03-05 16:39 ` Tom Rini
2015-03-05 16:47 ` Stefan Roese
2015-03-05 20:48 ` Marek Vasut
2015-03-05 9:47 ` [U-Boot] [PATCH 1/2] spi: Add Designware SPI " Stefan Roese
2015-03-05 10:57 ` Pavel Machek
2015-03-05 19:48 ` Simon Glass
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