[PATCH v2 0/5] GICv3: add 32bit compatibility

[PATCH v2 0/5] GICv3: add 32bit compatibility

[Jean-Philippe Brucker]

This series adds 32bit compatibility to Marc's GICv3 driver. Only SGIs,
PPIs and SPIs support is present, no ITS.

It is now based on Linux 4.0-rc1, which contains Andre's GICv3 emulation
series for KVM [1]. With this support along with the kvmtool patches
mentioned in [1], it is possible to run ARM guests that use GICv3.

Changes since v1 [2]:
* rebased on 4.0-rc1
* fix the mistakes pointed out by Russell and Vladimir
* add a patch to select ARM_GIC_V3 under ARCH_VIRT, as suggested by Marc

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/316230.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/310124.htm

Cheers,
Jean


Jean-Philippe Brucker (5):
  arm64: GICv3: refactor the AArch64 specific parts
  arm64: GICv3: change unsigned types for AArch32 compatibility
  arm64: GICv3: Specialize readq and writeq accesses
  ARM: add 32bit support to GICv3
  ARM: virt: select ARM_GIC_V3

 arch/arm/Kconfig                    |   1 +
 arch/arm/include/asm/arch_gicv3.h   | 182 ++++++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/arch_gicv3.h | 141 ++++++++++++++++++++++++++++
 drivers/irqchip/irq-gic-v3.c        |  69 ++++----------
 include/linux/irqchip/arm-gic-v3.h  | 115 ++++++-----------------
 5 files changed, 369 insertions(+), 139 deletions(-)
 create mode 100644 arch/arm/include/asm/arch_gicv3.h
 create mode 100644 arch/arm64/include/asm/arch_gicv3.h

-- 
2.2.0.rc1

[PATCH v2 1/5] arm64: GICv3: refactor the AArch64 specific parts

[Jean-Philippe Brucker]

This patch moves the GICv3 system register access helpers to
arch/arm64/. Their 32bit counterparts will need to use mrc/mcr accesses
instead of mrs_s/msr_s.

Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
---
 arch/arm64/include/asm/arch_gicv3.h | 133 ++++++++++++++++++++++++++++++++++++
 drivers/irqchip/irq-gic-v3.c        |  38 +----------
 include/linux/irqchip/arm-gic-v3.h  |  97 +++++---------------------
 3 files changed, 154 insertions(+), 114 deletions(-)
 create mode 100644 arch/arm64/include/asm/arch_gicv3.h

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
new file mode 100644
index 0000000..5409dff
--- /dev/null
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -0,0 +1,133 @@
+/*
+ * arch/arm64/include/asm/arch_gicv3.h
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_ARCH_GICV3_H
+#define __ASM_ARCH_GICV3_H
+
+#include <asm/sysreg.h>
+
+#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)
+#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)
+#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)
+#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
+#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)
+#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
+#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)
+
+#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
+
+/*
+ * System register definitions
+ */
+#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)
+#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
+#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
+#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)
+#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)
+#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)
+#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)
+
+#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)
+#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)
+
+#define ICH_LR0_EL2			__LR0_EL2(0)
+#define ICH_LR1_EL2			__LR0_EL2(1)
+#define ICH_LR2_EL2			__LR0_EL2(2)
+#define ICH_LR3_EL2			__LR0_EL2(3)
+#define ICH_LR4_EL2			__LR0_EL2(4)
+#define ICH_LR5_EL2			__LR0_EL2(5)
+#define ICH_LR6_EL2			__LR0_EL2(6)
+#define ICH_LR7_EL2			__LR0_EL2(7)
+#define ICH_LR8_EL2			__LR8_EL2(0)
+#define ICH_LR9_EL2			__LR8_EL2(1)
+#define ICH_LR10_EL2			__LR8_EL2(2)
+#define ICH_LR11_EL2			__LR8_EL2(3)
+#define ICH_LR12_EL2			__LR8_EL2(4)
+#define ICH_LR13_EL2			__LR8_EL2(5)
+#define ICH_LR14_EL2			__LR8_EL2(6)
+#define ICH_LR15_EL2			__LR8_EL2(7)
+
+#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)
+#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)
+#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)
+#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)
+#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)
+
+#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)
+#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)
+#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)
+#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)
+#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)
+
+#ifndef __ASSEMBLY__
+
+#include <linux/stringify.h>
+
+/* Low level accessors */
+
+static inline void gic_write_eoir(u64 irq)
+{
+	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
+	isb();
+}
+
+static inline u64 gic_read_iar(void)
+{
+	u64 irqstat;
+
+	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
+	return irqstat;
+}
+
+static inline void gic_write_pmr(u64 val)
+{
+	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
+}
+
+static inline void gic_write_ctlr(u64 val)
+{
+	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
+	isb();
+}
+
+static inline void gic_write_grpen1(u64 val)
+{
+	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
+	isb();
+}
+
+static inline void gic_write_sgi1r(u64 val)
+{
+	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
+}
+
+static inline u64 gic_read_sre(void)
+{
+	u64 val;
+
+	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
+	return val;
+}
+
+static inline void gic_write_sre(u64 val)
+{
+	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
+	isb();
+}
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_GICV3_H */
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 1c6dea2..63fb8f6 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -106,45 +106,13 @@ static void gic_redist_wait_for_rwp(void)
 	gic_do_wait_for_rwp(gic_data_rdist_rd_base());
 }
 
-/* Low level accessors */
-static u64 __maybe_unused gic_read_iar(void)
-{
-	u64 irqstat;
-
-	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
-	return irqstat;
-}
-
-static void __maybe_unused gic_write_pmr(u64 val)
-{
-	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
-}
-
-static void __maybe_unused gic_write_ctlr(u64 val)
-{
-	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
-	isb();
-}
-
-static void __maybe_unused gic_write_grpen1(u64 val)
-{
-	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
-	isb();
-}
-
-static void __maybe_unused gic_write_sgi1r(u64 val)
-{
-	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
-}
-
 static void gic_enable_sre(void)
 {
 	u64 val;
 
-	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
+	val = gic_read_sre();
 	val |= ICC_SRE_EL1_SRE;
-	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
-	isb();
+	gic_write_sre(val);
 
 	/*
 	 * Need to check that the SRE bit has actually been set. If
@@ -153,7 +121,7 @@ static void gic_enable_sre(void)
 	 *
 	 * Kindly inform the luser.
 	 */
-	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
+	val = gic_read_sre();
 	if (!(val & ICC_SRE_EL1_SRE))
 		pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
 }
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 800544b..bbe9c34 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -18,8 +18,6 @@
 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
 #define __LINUX_IRQCHIP_ARM_GIC_V3_H
 
-#include <asm/sysreg.h>
-
 /*
  * Distributor registers. We assume we're running non-secure, with ARE
  * being set. Secure-only and non-ARE registers are not described.
@@ -239,6 +237,23 @@
 #define ICC_CTLR_EL1_EOImode_drop	(1U << 1)
 #define ICC_SRE_EL1_SRE			(1U << 0)
 
+#define ICC_SRE_EL2_SRE			(1 << 0)
+#define ICC_SRE_EL2_ENABLE		(1 << 3)
+
+#define ICC_IAR1_EL1_SPURIOUS		0x3ff
+
+#define ICC_SGI1R_TARGET_LIST_SHIFT	0
+#define ICC_SGI1R_TARGET_LIST_MASK	(0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
+#define ICC_SGI1R_AFFINITY_1_SHIFT	16
+#define ICC_SGI1R_AFFINITY_1_MASK	(0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
+#define ICC_SGI1R_SGI_ID_SHIFT		24
+#define ICC_SGI1R_SGI_ID_MASK		(0xff << ICC_SGI1R_SGI_ID_SHIFT)
+#define ICC_SGI1R_AFFINITY_2_SHIFT	32
+#define ICC_SGI1R_AFFINITY_2_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
+#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT	40
+#define ICC_SGI1R_AFFINITY_3_SHIFT	48
+#define ICC_SGI1R_AFFINITY_3_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
+
 /*
  * Hypervisor interface registers (SRE only)
  */
@@ -265,80 +280,10 @@
 #define ICH_VMCR_PMR_SHIFT		24
 #define ICH_VMCR_PMR_MASK		(0xffUL << ICH_VMCR_PMR_SHIFT)
 
-#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)
-#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)
-#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)
-#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
-#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)
-#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
-#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)
-
-#define ICC_IAR1_EL1_SPURIOUS		0x3ff
-
-#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
-
-#define ICC_SRE_EL2_SRE			(1 << 0)
-#define ICC_SRE_EL2_ENABLE		(1 << 3)
-
-#define ICC_SGI1R_TARGET_LIST_SHIFT	0
-#define ICC_SGI1R_TARGET_LIST_MASK	(0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
-#define ICC_SGI1R_AFFINITY_1_SHIFT	16
-#define ICC_SGI1R_AFFINITY_1_MASK	(0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
-#define ICC_SGI1R_SGI_ID_SHIFT		24
-#define ICC_SGI1R_SGI_ID_MASK		(0xff << ICC_SGI1R_SGI_ID_SHIFT)
-#define ICC_SGI1R_AFFINITY_2_SHIFT	32
-#define ICC_SGI1R_AFFINITY_2_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
-#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT	40
-#define ICC_SGI1R_AFFINITY_3_SHIFT	48
-#define ICC_SGI1R_AFFINITY_3_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
-
-/*
- * System register definitions
- */
-#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)
-#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
-#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
-#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)
-#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)
-#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)
-#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)
-
-#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)
-#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)
-
-#define ICH_LR0_EL2			__LR0_EL2(0)
-#define ICH_LR1_EL2			__LR0_EL2(1)
-#define ICH_LR2_EL2			__LR0_EL2(2)
-#define ICH_LR3_EL2			__LR0_EL2(3)
-#define ICH_LR4_EL2			__LR0_EL2(4)
-#define ICH_LR5_EL2			__LR0_EL2(5)
-#define ICH_LR6_EL2			__LR0_EL2(6)
-#define ICH_LR7_EL2			__LR0_EL2(7)
-#define ICH_LR8_EL2			__LR8_EL2(0)
-#define ICH_LR9_EL2			__LR8_EL2(1)
-#define ICH_LR10_EL2			__LR8_EL2(2)
-#define ICH_LR11_EL2			__LR8_EL2(3)
-#define ICH_LR12_EL2			__LR8_EL2(4)
-#define ICH_LR13_EL2			__LR8_EL2(5)
-#define ICH_LR14_EL2			__LR8_EL2(6)
-#define ICH_LR15_EL2			__LR8_EL2(7)
-
-#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)
-#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)
-#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)
-#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)
-#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)
-
-#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)
-#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)
-#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)
-#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)
-#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)
+#include <asm/arch_gicv3.h>
 
 #ifndef __ASSEMBLY__
 
-#include <linux/stringify.h>
-
 /*
  * We need a value to serve as a irq-type for LPIs. Choose one that will
  * hopefully pique the interest of the reviewer.
@@ -356,12 +301,6 @@ struct rdists {
 	u64			flags;
 };
 
-static inline void gic_write_eoir(u64 irq)
-{
-	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
-	isb();
-}
-
 struct irq_domain;
 int its_cpu_init(void);
 int its_init(struct device_node *node, struct rdists *rdists,
-- 
2.2.0.rc1

[PATCH v2 2/5] arm64: GICv3: change unsigned types for AArch32 compatibility

[Jean-Philippe Brucker]

This patch does a few simple compatibility-related changes:
- change the system register access prototypes to their actual size,
- homogenise mpidr accesses with unsigned long,
- force the 64bit register values to unsigned long long.

Note: the list registers are 64bit on GICv3, but the AArch32 vGIC driver
will need to split their values into two 32bit registers: LRn and LRCn.

Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
---
 arch/arm64/include/asm/arch_gicv3.h | 31 ++++++++++++++++++-------------
 drivers/irqchip/irq-gic-v3.c        | 25 ++++++++++++-------------
 include/linux/irqchip/arm-gic-v3.h  | 18 +++++++++---------
 3 files changed, 39 insertions(+), 35 deletions(-)

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 5409dff..50d0045 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -77,15 +77,20 @@
 
 #include <linux/stringify.h>
 
-/* Low level accessors */
+/*
+ * Low-level accessors
+ *
+ * These system registers are 32 bits, but we make sure that the compiler
+ * sets the GP register's most significant bits to 0 with an explicit cast.
+ */
 
-static inline void gic_write_eoir(u64 irq)
+static inline void gic_write_eoir(u32 irq)
 {
-	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
+	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));
 	isb();
 }
 
-static inline u64 gic_read_iar(void)
+static inline u32 gic_read_iar(void)
 {
 	u64 irqstat;
 
@@ -93,20 +98,20 @@ static inline u64 gic_read_iar(void)
 	return irqstat;
 }
 
-static inline void gic_write_pmr(u64 val)
+static inline void gic_write_pmr(u32 val)
 {
-	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
+	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));
 }
 
-static inline void gic_write_ctlr(u64 val)
+static inline void gic_write_ctlr(u32 val)
 {
-	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
+	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val));
 	isb();
 }
 
-static inline void gic_write_grpen1(u64 val)
+static inline void gic_write_grpen1(u32 val)
 {
-	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
+	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));
 	isb();
 }
 
@@ -115,7 +120,7 @@ static inline void gic_write_sgi1r(u64 val)
 	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
 }
 
-static inline u64 gic_read_sre(void)
+static inline u32 gic_read_sre(void)
 {
 	u64 val;
 
@@ -123,9 +128,9 @@ static inline u64 gic_read_sre(void)
 	return val;
 }
 
-static inline void gic_write_sre(u64 val)
+static inline void gic_write_sre(u32 val)
 {
-	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
+	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val));
 	isb();
 }
 
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 63fb8f6..a907235 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -222,11 +222,11 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
 	return gic_configure_irq(irq, type, base, rwp_wait);
 }
 
-static u64 gic_mpidr_to_affinity(u64 mpidr)
+static u64 gic_mpidr_to_affinity(unsigned long mpidr)
 {
 	u64 aff;
 
-	aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
+	aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
 	       MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 	       MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8  |
 	       MPIDR_AFFINITY_LEVEL(mpidr, 0));
@@ -236,7 +236,7 @@ static u64 gic_mpidr_to_affinity(u64 mpidr)
 
 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 {
-	u64 irqnr;
+	u32 irqnr;
 
 	do {
 		irqnr = gic_read_iar();
@@ -289,7 +289,7 @@ static void __init gic_dist_init(void)
 
 static int gic_populate_rdist(void)
 {
-	u64 mpidr = cpu_logical_map(smp_processor_id());
+	unsigned long mpidr = cpu_logical_map(smp_processor_id());
 	u64 typer;
 	u32 aff;
 	int i;
@@ -320,10 +320,9 @@ static int gic_populate_rdist(void)
 				u64 offset = ptr - gic_data.redist_regions[i].redist_base;
 				gic_data_rdist_rd_base() = ptr;
 				gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset;
-				pr_info("CPU%d: found redistributor %llx region %d:%pa\n",
-					smp_processor_id(),
-					(unsigned long long)mpidr,
-					i, &gic_data_rdist()->phys_base);
+				pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
+					smp_processor_id(), mpidr, i,
+					&gic_data_rdist()->phys_base);
 				return 0;
 			}
 
@@ -338,8 +337,8 @@ static int gic_populate_rdist(void)
 	}
 
 	/* We couldn't even deal with ourselves... */
-	WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
-	     smp_processor_id(), (unsigned long long)mpidr);
+	WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
+	     smp_processor_id(), mpidr);
 	return -ENODEV;
 }
 
@@ -417,10 +416,10 @@ static struct notifier_block gic_cpu_notifier = {
 };
 
 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
-				   u64 cluster_id)
+				   unsigned long cluster_id)
 {
 	int cpu = *base_cpu;
-	u64 mpidr = cpu_logical_map(cpu);
+	unsigned long mpidr = cpu_logical_map(cpu);
 	u16 tlist = 0;
 
 	while (cpu < nr_cpu_ids) {
@@ -481,7 +480,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 	smp_wmb();
 
 	for_each_cpu_mask(cpu, *mask) {
-		u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
+		unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL;
 		u16 tlist;
 
 		tlist = gic_compute_target_list(&cpu, mask, cluster_id);
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index bbe9c34..0ee95c4 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -42,7 +42,7 @@
 #define GICD_ICFGR			0x0C00
 #define GICD_IGRPMODR			0x0D00
 #define GICD_NSACR			0x0E00
-#define GICD_IROUTER			0x6000
+#define GICD_IROUTER			0x6000		/* 64bit */
 #define GICD_IDREGS			0xFFD0
 #define GICD_PIDR2			0xFFE8
 
@@ -91,7 +91,7 @@
 #define GICR_IIDR			0x0004
 #define GICR_TYPER			0x0008
 #define GICR_STATUSR			GICD_STATUSR
-#define GICR_WAKER			0x0014
+#define GICR_WAKER			0x0014		/* 32bit */
 #define GICR_SETLPIR			0x0040
 #define GICR_CLRLPIR			0x0048
 #define GICR_SEIR			GICD_SEIR
@@ -99,7 +99,7 @@
 #define GICR_PENDBASER			0x0078
 #define GICR_INVLPIR			0x00A0
 #define GICR_INVALLR			0x00B0
-#define GICR_SYNCR			0x00C0
+#define GICR_SYNCR			0x00C0		/* 32bit */
 #define GICR_MOVLPIR			0x0100
 #define GICR_MOVALLR			0x0110
 #define GICR_IDREGS			GICD_IDREGS
@@ -257,13 +257,13 @@
 /*
  * Hypervisor interface registers (SRE only)
  */
-#define ICH_LR_VIRTUAL_ID_MASK		((1UL << 32) - 1)
+#define ICH_LR_VIRTUAL_ID_MASK		((1ULL << 32) - 1)
 
-#define ICH_LR_EOI			(1UL << 41)
-#define ICH_LR_GROUP			(1UL << 60)
-#define ICH_LR_STATE			(3UL << 62)
-#define ICH_LR_PENDING_BIT		(1UL << 62)
-#define ICH_LR_ACTIVE_BIT		(1UL << 63)
+#define ICH_LR_EOI			(1ULL << 41)
+#define ICH_LR_GROUP			(1ULL << 60)
+#define ICH_LR_STATE			(3ULL << 62)
+#define ICH_LR_PENDING_BIT		(1ULL << 62)
+#define ICH_LR_ACTIVE_BIT		(1ULL << 63)
 
 #define ICH_MISR_EOI			(1 << 0)
 #define ICH_MISR_U			(1 << 1)
-- 
2.2.0.rc1

[PATCH v2 3/5] arm64: GICv3: Specialize readq and writeq accesses

[Jean-Philippe Brucker]

On 32bit platforms, we cannot assure that an I/O ldrd or strd will be
done atomically. Besides, an hypervisor would be unable to emulate such
accesses.
In order to allow the AArch32 version of the driver to split them into
two 32bit accesses while keeping the requirement for atomic writes, this
patch specializes the IROUTER and TYPER accesses.
Since the latter is an ID register, it won't need to be read atomically,
but we still avoid future confusion by using gic_read_typer instead of a
generic gic_readq.

Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
---
 arch/arm64/include/asm/arch_gicv3.h | 3 +++
 drivers/irqchip/irq-gic-v3.c        | 6 +++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 50d0045..1787580 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -134,5 +134,8 @@ static inline void gic_write_sre(u32 val)
 	isb();
 }
 
+#define gic_read_typer(c)		readq_relaxed(c)
+#define gic_write_irouter(v, c)		writeq_relaxed(v, c)
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_GICV3_H */
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index a907235..c52cd23 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -284,7 +284,7 @@ static void __init gic_dist_init(void)
 	 */
 	affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
 	for (i = 32; i < gic_data.irq_nr; i++)
-		writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
+		gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
 }
 
 static int gic_populate_rdist(void)
@@ -315,7 +315,7 @@ static int gic_populate_rdist(void)
 		}
 
 		do {
-			typer = readq_relaxed(ptr + GICR_TYPER);
+			typer = gic_read_typer(ptr + GICR_TYPER);
 			if ((typer >> 32) == aff) {
 				u64 offset = ptr - gic_data.redist_regions[i].redist_base;
 				gic_data_rdist_rd_base() = ptr;
@@ -516,7 +516,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 	reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
 	val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
 
-	writeq_relaxed(val, reg);
+	gic_write_irouter(val, reg);
 
 	/*
 	 * If the interrupt was enabled, enabled it again. Otherwise,
-- 
2.2.0.rc1

[PATCH v2 4/5] ARM: add 32bit support to GICv3

[Jean-Philippe Brucker]

Implement the system and memory-mapped register accesses in
asm/arch_gicv3.h for 32bit architectures.

This patch is a straightforward translation of the arm64 header. 64bit
accesses are done in two times and don't need atomicity: TYPER is
read-only, and the upper-word of IROUTER is always zero on 32bit
architectures.

Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
---
 arch/arm/include/asm/arch_gicv3.h | 182 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 182 insertions(+)
 create mode 100644 arch/arm/include/asm/arch_gicv3.h

diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
new file mode 100644
index 0000000..c2c3603
--- /dev/null
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -0,0 +1,182 @@
+/*
+ * arch/arm/include/asm/arch_gicv3.h
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_ARCH_GICV3_H
+#define __ASM_ARCH_GICV3_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/io.h>
+
+#define __ACCESS_CP15(CRn, Op1, CRm, Op2)	p15, Op1, %0, CRn, CRm, Op2
+#define __ACCESS_CP15_64(Op1, CRm)		p15, Op1, %Q0, %R0, CRm
+
+#define ICC_EOIR1			__ACCESS_CP15(c12, 0, c12, 1)
+#define ICC_IAR1			__ACCESS_CP15(c12, 0, c12, 0)
+#define ICC_SGI1R			__ACCESS_CP15_64(0, c12)
+#define ICC_PMR				__ACCESS_CP15(c4, 0, c6, 0)
+#define ICC_CTLR			__ACCESS_CP15(c12, 0, c12, 4)
+#define ICC_SRE				__ACCESS_CP15(c12, 0, c12, 5)
+#define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)
+
+#define ICC_HSRE			__ACCESS_CP15(c12, 4, c9, 5)
+
+#define ICH_VSEIR			__ACCESS_CP15(c12, 4, c9, 4)
+#define ICH_HCR				__ACCESS_CP15(c12, 4, c11, 0)
+#define ICH_VTR				__ACCESS_CP15(c12, 4, c11, 1)
+#define ICH_MISR			__ACCESS_CP15(c12, 4, c11, 2)
+#define ICH_EISR			__ACCESS_CP15(c12, 4, c11, 3)
+#define ICH_ELSR			__ACCESS_CP15(c12, 4, c11, 5)
+#define ICH_VMCR			__ACCESS_CP15(c12, 4, c11, 7)
+
+#define __LR0(x)			__ACCESS_CP15(c12, 4, c12, x)
+#define __LR8(x)			__ACCESS_CP15(c12, 4, c13, x)
+
+#define ICH_LR0				__LR0(0)
+#define ICH_LR1				__LR0(1)
+#define ICH_LR2				__LR0(2)
+#define ICH_LR3				__LR0(3)
+#define ICH_LR4				__LR0(4)
+#define ICH_LR5				__LR0(5)
+#define ICH_LR6				__LR0(6)
+#define ICH_LR7				__LR0(7)
+#define ICH_LR8				__LR8(0)
+#define ICH_LR9				__LR8(1)
+#define ICH_LR10			__LR8(2)
+#define ICH_LR11			__LR8(3)
+#define ICH_LR12			__LR8(4)
+#define ICH_LR13			__LR8(5)
+#define ICH_LR14			__LR8(6)
+#define ICH_LR15			__LR8(7)
+
+/* LR top half */
+#define __LRC0(x)			__ACCESS_CP15(c12, 4, c14, x)
+#define __LRC8(x)			__ACCESS_CP15(c12, 4, c15, x)
+
+#define ICH_LRC0			__LRC0(0)
+#define ICH_LRC1			__LRC0(1)
+#define ICH_LRC2			__LRC0(2)
+#define ICH_LRC3			__LRC0(3)
+#define ICH_LRC4			__LRC0(4)
+#define ICH_LRC5			__LRC0(5)
+#define ICH_LRC6			__LRC0(6)
+#define ICH_LRC7			__LRC0(7)
+#define ICH_LRC8			__LRC8(0)
+#define ICH_LRC9			__LRC8(1)
+#define ICH_LRC10			__LRC8(2)
+#define ICH_LRC11			__LRC8(3)
+#define ICH_LRC12			__LRC8(4)
+#define ICH_LRC13			__LRC8(5)
+#define ICH_LRC14			__LRC8(6)
+#define ICH_LRC15			__LRC8(7)
+
+#define __AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)
+#define ICH_AP0R0			__AP0Rx(0)
+#define ICH_AP0R1			__AP0Rx(1)
+#define ICH_AP0R2			__AP0Rx(2)
+#define ICH_AP0R3			__AP0Rx(3)
+
+#define __AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)
+#define ICH_AP1R0			__AP1Rx(0)
+#define ICH_AP1R1			__AP1Rx(1)
+#define ICH_AP1R2			__AP1Rx(2)
+#define ICH_AP1R3			__AP1Rx(3)
+
+/* Low-level accessors */
+
+static inline void gic_write_eoir(u32 irq)
+{
+	asm volatile("mcr " __stringify(ICC_EOIR1) : : "r" (irq));
+	isb();
+}
+
+static inline u32 gic_read_iar(void)
+{
+	u32 irqstat;
+
+	asm volatile("mrc " __stringify(ICC_IAR1) : "=r" (irqstat));
+	return irqstat;
+}
+
+static inline void gic_write_pmr(u32 val)
+{
+	asm volatile("mcr " __stringify(ICC_PMR) : : "r" (val));
+	isb();
+}
+
+static inline void gic_write_ctlr(u32 val)
+{
+	asm volatile("mcr " __stringify(ICC_CTLR) : : "r" (val));
+	isb();
+}
+
+static inline void gic_write_grpen1(u32 val)
+{
+	asm volatile("mcr " __stringify(ICC_IGRPEN1) : : "r" (val));
+	isb();
+}
+
+static inline void gic_write_sgi1r(u64 val)
+{
+	asm volatile("mcrr " __stringify(ICC_SGI1R) : : "r" (val));
+}
+
+static inline u32 gic_read_sre(void)
+{
+	u32 val;
+
+	asm volatile("mrc " __stringify(ICC_SRE) : "=r" (val));
+	return val;
+}
+
+static inline void gic_write_sre(u32 val)
+{
+	asm volatile("mcr " __stringify(ICC_SRE) : : "r" (val));
+	isb();
+}
+
+/*
+ * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
+ * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
+ * make much sense.
+ * Moreover, 64bit I/O emulation is extremely difficult to implement on
+ * AArch32, since the syndrome register doesn't provide any information for
+ * them.
+ * Consequently, the following IO helpers use 32bit accesses.
+ *
+ * There are only two registers that need 64bit accesses in this driver:
+ * - GICD_IROUTERn, contain the affinity values associated to each interrupt.
+ *   The upper-word (aff3) will always be 0, so there is no need for a lock.
+ * - GICR_TYPER is an ID register and doesn't need atomicity.
+ */
+static void gic_write_irouter(u64 val, volatile void __iomem *addr)
+{
+	writel_relaxed((u32)val, addr);
+	writel_relaxed((u32)(val >> 32), addr + 4);
+}
+
+static inline u64 gic_read_typer(const volatile void __iomem *addr)
+{
+	u64 val;
+
+	val = readl_relaxed(addr);
+	val |= (u64)readl_relaxed(addr + 4) << 32;
+	return val;
+}
+
+#endif /* !__ASSEMBLY__ */
+#endif /* !__ASM_ARCH_GICV3_H */
-- 
2.2.0.rc1

[PATCH v2 5/5] ARM: virt: select ARM_GIC_V3

[Jean-Philippe Brucker]

This patch allows ARM guests to use GICv3 on an arm64 host

Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9f1f09a..76246cc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -834,6 +834,7 @@ config ARCH_VIRT
 	bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 	select ARM_AMBA
 	select ARM_GIC
+	select ARM_GIC_V3
 	select ARM_PSCI
 	select HAVE_ARM_ARCH_TIMER
 
-- 
2.2.0.rc1

[PATCH v2 0/5] GICv3: add 32bit compatibility

[Vladimir Murzin]

On 02/03/15 18:20, Jean-Philippe Brucker wrote:
> This series adds 32bit compatibility to Marc's GICv3 driver. Only SGIs,
> PPIs and SPIs support is present, no ITS.
> 
> It is now based on Linux 4.0-rc1, which contains Andre's GICv3 emulation
> series for KVM [1]. With this support along with the kvmtool patches
> mentioned in [1], it is possible to run ARM guests that use GICv3.
> 
> Changes since v1 [2]:
> * rebased on 4.0-rc1
> * fix the mistakes pointed out by Russell and Vladimir
> * add a patch to select ARM_GIC_V3 under ARCH_VIRT, as suggested by Marc
> 
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/316230.html
> [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/310124.htm
> 

Hi Jean,

In case CONFIG_KVM_ARM_VGIC=y there is build error:

  CC      arch/arm/kvm/../../../virt/kvm/arm/vgic.o
 arch/arm/kvm/../../../virt/kvm/arm/vgic.c: In function 'kvm_vgic_addr':
 arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1703:7: error:
'KVM_VGIC_V3_ADDR_TYPE_DIST' undeclared (first use in this function)
   case KVM_VGIC_V3_ADDR_TYPE_DIST:
        ^
 arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1703:7: note: each undeclared
identifier is reported only once for each function it appears in
 arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1706:16: error:
'KVM_VGIC_V3_DIST_SIZE' undeclared (first use in this function)
    block_size = KVM_VGIC_V3_DIST_SIZE;
                 ^
 arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1709:7: error:
'KVM_VGIC_V3_ADDR_TYPE_REDIST' undeclared (first use in this function)
   case KVM_VGIC_V3_ADDR_TYPE_REDIST:
        ^
 arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1712:16: error:
'KVM_VGIC_V3_REDIST_SIZE' undeclared (first use in this function)
    block_size = KVM_VGIC_V3_REDIST_SIZE;
                 ^
 make[1]: *** [arch/arm/kvm/../../../virt/kvm/arm/vgic.o] Error 1
 make: *** [arch/arm/kvm] Error 2

Thanks
Vladimir

> Cheers,
> Jean
> 
> 
> Jean-Philippe Brucker (5):
>   arm64: GICv3: refactor the AArch64 specific parts
>   arm64: GICv3: change unsigned types for AArch32 compatibility
>   arm64: GICv3: Specialize readq and writeq accesses
>   ARM: add 32bit support to GICv3
>   ARM: virt: select ARM_GIC_V3
> 
>  arch/arm/Kconfig                    |   1 +
>  arch/arm/include/asm/arch_gicv3.h   | 182 ++++++++++++++++++++++++++++++++++++
>  arch/arm64/include/asm/arch_gicv3.h | 141 ++++++++++++++++++++++++++++
>  drivers/irqchip/irq-gic-v3.c        |  69 ++++----------
>  include/linux/irqchip/arm-gic-v3.h  | 115 ++++++-----------------
>  5 files changed, 369 insertions(+), 139 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch_gicv3.h
>  create mode 100644 arch/arm64/include/asm/arch_gicv3.h
> 

[PATCH v2 0/5] GICv3: add 32bit compatibility

[Jason Cooper]

Jean-Philippe,

On Mon, Mar 02, 2015 at 06:20:27PM +0000, Jean-Philippe Brucker wrote:
> This series adds 32bit compatibility to Marc's GICv3 driver. Only SGIs,
> PPIs and SPIs support is present, no ITS.
> 
> It is now based on Linux 4.0-rc1, which contains Andre's GICv3 emulation
> series for KVM [1]. With this support along with the kvmtool patches
> mentioned in [1], it is possible to run ARM guests that use GICv3.
> 
> Changes since v1 [2]:
> * rebased on 4.0-rc1
> * fix the mistakes pointed out by Russell and Vladimir
> * add a patch to select ARM_GIC_V3 under ARCH_VIRT, as suggested by Marc
> 
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/316230.html
> [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/310124.htm
> 
> Cheers,
> Jean
> 
> 
> Jean-Philippe Brucker (5):
>   arm64: GICv3: refactor the AArch64 specific parts
>   arm64: GICv3: change unsigned types for AArch32 compatibility
>   arm64: GICv3: Specialize readq and writeq accesses
>   ARM: add 32bit support to GICv3
>   ARM: virt: select ARM_GIC_V3
> 
>  arch/arm/Kconfig                    |   1 +
>  arch/arm/include/asm/arch_gicv3.h   | 182 ++++++++++++++++++++++++++++++++++++
>  arch/arm64/include/asm/arch_gicv3.h | 141 ++++++++++++++++++++++++++++
>  drivers/irqchip/irq-gic-v3.c        |  69 ++++----------
>  include/linux/irqchip/arm-gic-v3.h  | 115 ++++++-----------------

Please include the irqchip maintainers (myself and Thomas) on future revisions
of this series.

thx,

Jason.

[PATCH v2 0/5] GICv3: add 32bit compatibility

[Jean-Philippe Brucker]

Hi Vladimir,

On Wed, Mar 11, 2015 at 11:19:08AM +0000, Vladimir Murzin wrote:
> On 02/03/15 18:20, Jean-Philippe Brucker wrote:
> > This series adds 32bit compatibility to Marc's GICv3 driver. Only SGIs,
> > PPIs and SPIs support is present, no ITS.
> > 
> > It is now based on Linux 4.0-rc1, which contains Andre's GICv3 emulation
> > series for KVM [1]. With this support along with the kvmtool patches
> > mentioned in [1], it is possible to run ARM guests that use GICv3.
> > 
> > Changes since v1 [2]:
> > * rebased on 4.0-rc1
> > * fix the mistakes pointed out by Russell and Vladimir
> > * add a patch to select ARM_GIC_V3 under ARCH_VIRT, as suggested by Marc
> > 
> > [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/316230.html
> > [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/310124.htm
> > 
> 
> Hi Jean,
> 
> In case CONFIG_KVM_ARM_VGIC=y there is build error:
> 
>   CC      arch/arm/kvm/../../../virt/kvm/arm/vgic.o
>  arch/arm/kvm/../../../virt/kvm/arm/vgic.c: In function 'kvm_vgic_addr':
>  arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1703:7: error:
> 'KVM_VGIC_V3_ADDR_TYPE_DIST' undeclared (first use in this function)
>    case KVM_VGIC_V3_ADDR_TYPE_DIST:
>         ^
>  arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1703:7: note: each undeclared
> identifier is reported only once for each function it appears in
>  arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1706:16: error:
> 'KVM_VGIC_V3_DIST_SIZE' undeclared (first use in this function)
>     block_size = KVM_VGIC_V3_DIST_SIZE;
>                  ^
>  arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1709:7: error:
> 'KVM_VGIC_V3_ADDR_TYPE_REDIST' undeclared (first use in this function)
>    case KVM_VGIC_V3_ADDR_TYPE_REDIST:
>         ^
>  arch/arm/kvm/../../../virt/kvm/arm/vgic.c:1712:16: error:
> 'KVM_VGIC_V3_REDIST_SIZE' undeclared (first use in this function)
>     block_size = KVM_VGIC_V3_REDIST_SIZE;
>                  ^
>  make[1]: *** [arch/arm/kvm/../../../virt/kvm/arm/vgic.o] Error 1
>  make: *** [arch/arm/kvm] Error 2
> 

Indeed. I will add a 6th patch in the next series to use *VGIC_V3 (along
with vgic_v3_probe) only when CONFIG_ARM64 is set.

Thanks,
Jean

[PATCH v2 4/5] ARM: add 32bit support to GICv3

[Vladimir Murzin]

Hi Jean,

On 02/03/15 18:20, Jean-Philippe Brucker wrote:
> Implement the system and memory-mapped register accesses in
> asm/arch_gicv3.h for 32bit architectures.
> 
> This patch is a straightforward translation of the arm64 header. 64bit
> accesses are done in two times and don't need atomicity: TYPER is
> read-only, and the upper-word of IROUTER is always zero on 32bit
> architectures.
> 
> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
> ---
>  arch/arm/include/asm/arch_gicv3.h | 182 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 182 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch_gicv3.h
> 
> diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
> new file mode 100644
> index 0000000..c2c3603
> --- /dev/null
> +++ b/arch/arm/include/asm/arch_gicv3.h
> @@ -0,0 +1,182 @@
> +/*
> + * arch/arm/include/asm/arch_gicv3.h
> + *
> + * Copyright (C) 2014 ARM Ltd.
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_ARCH_GICV3_H
> +#define __ASM_ARCH_GICV3_H
> +
> +#ifndef __ASSEMBLY__
> +
> +#include <linux/io.h>
> +
> +#define __ACCESS_CP15(CRn, Op1, CRm, Op2)	p15, Op1, %0, CRn, CRm, Op2
> +#define __ACCESS_CP15_64(Op1, CRm)		p15, Op1, %Q0, %R0, CRm
> +
> +#define ICC_EOIR1			__ACCESS_CP15(c12, 0, c12, 1)
> +#define ICC_IAR1			__ACCESS_CP15(c12, 0, c12, 0)
> +#define ICC_SGI1R			__ACCESS_CP15_64(0, c12)
> +#define ICC_PMR				__ACCESS_CP15(c4, 0, c6, 0)
> +#define ICC_CTLR			__ACCESS_CP15(c12, 0, c12, 4)
> +#define ICC_SRE				__ACCESS_CP15(c12, 0, c12, 5)
> +#define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)
> +
> +#define ICC_HSRE			__ACCESS_CP15(c12, 4, c9, 5)
> +
> +#define ICH_VSEIR			__ACCESS_CP15(c12, 4, c9, 4)
> +#define ICH_HCR				__ACCESS_CP15(c12, 4, c11, 0)
> +#define ICH_VTR				__ACCESS_CP15(c12, 4, c11, 1)
> +#define ICH_MISR			__ACCESS_CP15(c12, 4, c11, 2)
> +#define ICH_EISR			__ACCESS_CP15(c12, 4, c11, 3)
> +#define ICH_ELSR			__ACCESS_CP15(c12, 4, c11, 5)
> +#define ICH_VMCR			__ACCESS_CP15(c12, 4, c11, 7)
> +
> +#define __LR0(x)			__ACCESS_CP15(c12, 4, c12, x)
> +#define __LR8(x)			__ACCESS_CP15(c12, 4, c13, x)
> +
> +#define ICH_LR0				__LR0(0)
> +#define ICH_LR1				__LR0(1)
> +#define ICH_LR2				__LR0(2)
> +#define ICH_LR3				__LR0(3)
> +#define ICH_LR4				__LR0(4)
> +#define ICH_LR5				__LR0(5)
> +#define ICH_LR6				__LR0(6)
> +#define ICH_LR7				__LR0(7)
> +#define ICH_LR8				__LR8(0)
> +#define ICH_LR9				__LR8(1)
> +#define ICH_LR10			__LR8(2)
> +#define ICH_LR11			__LR8(3)
> +#define ICH_LR12			__LR8(4)
> +#define ICH_LR13			__LR8(5)
> +#define ICH_LR14			__LR8(6)
> +#define ICH_LR15			__LR8(7)
> +
> +/* LR top half */
> +#define __LRC0(x)			__ACCESS_CP15(c12, 4, c14, x)
> +#define __LRC8(x)			__ACCESS_CP15(c12, 4, c15, x)
> +
> +#define ICH_LRC0			__LRC0(0)
> +#define ICH_LRC1			__LRC0(1)
> +#define ICH_LRC2			__LRC0(2)
> +#define ICH_LRC3			__LRC0(3)
> +#define ICH_LRC4			__LRC0(4)
> +#define ICH_LRC5			__LRC0(5)
> +#define ICH_LRC6			__LRC0(6)
> +#define ICH_LRC7			__LRC0(7)
> +#define ICH_LRC8			__LRC8(0)
> +#define ICH_LRC9			__LRC8(1)
> +#define ICH_LRC10			__LRC8(2)
> +#define ICH_LRC11			__LRC8(3)
> +#define ICH_LRC12			__LRC8(4)
> +#define ICH_LRC13			__LRC8(5)
> +#define ICH_LRC14			__LRC8(6)
> +#define ICH_LRC15			__LRC8(7)
> +
> +#define __AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)
> +#define ICH_AP0R0			__AP0Rx(0)
> +#define ICH_AP0R1			__AP0Rx(1)
> +#define ICH_AP0R2			__AP0Rx(2)
> +#define ICH_AP0R3			__AP0Rx(3)
> +
> +#define __AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)
> +#define ICH_AP1R0			__AP1Rx(0)
> +#define ICH_AP1R1			__AP1Rx(1)
> +#define ICH_AP1R2			__AP1Rx(2)
> +#define ICH_AP1R3			__AP1Rx(3)
> +
> +/* Low-level accessors */
> +
> +static inline void gic_write_eoir(u32 irq)
> +{
> +	asm volatile("mcr " __stringify(ICC_EOIR1) : : "r" (irq));
> +	isb();
> +}
> +
> +static inline u32 gic_read_iar(void)
> +{
> +	u32 irqstat;
> +
> +	asm volatile("mrc " __stringify(ICC_IAR1) : "=r" (irqstat));
> +	return irqstat;
> +}
> +
> +static inline void gic_write_pmr(u32 val)
> +{
> +	asm volatile("mcr " __stringify(ICC_PMR) : : "r" (val));
> +	isb();
> +}
> +
> +static inline void gic_write_ctlr(u32 val)
> +{
> +	asm volatile("mcr " __stringify(ICC_CTLR) : : "r" (val));
> +	isb();
> +}
> +
> +static inline void gic_write_grpen1(u32 val)
> +{
> +	asm volatile("mcr " __stringify(ICC_IGRPEN1) : : "r" (val));
> +	isb();
> +}
> +
> +static inline void gic_write_sgi1r(u64 val)
> +{
> +	asm volatile("mcrr " __stringify(ICC_SGI1R) : : "r" (val));
> +}
> +
> +static inline u32 gic_read_sre(void)
> +{
> +	u32 val;
> +
> +	asm volatile("mrc " __stringify(ICC_SRE) : "=r" (val));
> +	return val;
> +}
> +
> +static inline void gic_write_sre(u32 val)
> +{
> +	asm volatile("mcr " __stringify(ICC_SRE) : : "r" (val));
> +	isb();
> +}
> +
> +/*
> + * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
> + * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
> + * make much sense.
> + * Moreover, 64bit I/O emulation is extremely difficult to implement on
> + * AArch32, since the syndrome register doesn't provide any information for
> + * them.
> + * Consequently, the following IO helpers use 32bit accesses.
> + *
> + * There are only two registers that need 64bit accesses in this driver:
> + * - GICD_IROUTERn, contain the affinity values associated to each interrupt.
> + *   The upper-word (aff3) will always be 0, so there is no need for a lock.
> + * - GICR_TYPER is an ID register and doesn't need atomicity.
> + */
> +static void gic_write_irouter(u64 val, volatile void __iomem *addr)

Any reason not to be inlined like other functions do?

Cheers
Vladimir

> +{
> +	writel_relaxed((u32)val, addr);
> +	writel_relaxed((u32)(val >> 32), addr + 4);
> +}
> +
> +static inline u64 gic_read_typer(const volatile void __iomem *addr)
> +{
> +	u64 val;
> +
> +	val = readl_relaxed(addr);
> +	val |= (u64)readl_relaxed(addr + 4) << 32;
> +	return val;
> +}
> +
> +#endif /* !__ASSEMBLY__ */
> +#endif /* !__ASM_ARCH_GICV3_H */
> 

[PATCH v2 4/5] ARM: add 32bit support to GICv3

[Jean-Philippe Brucker]

On Wed, Mar 11, 2015 at 02:52:34PM +0000, Vladimir Murzin wrote:
> Hi Jean,
> 
> On 02/03/15 18:20, Jean-Philippe Brucker wrote:
> > Implement the system and memory-mapped register accesses in
> > asm/arch_gicv3.h for 32bit architectures.
> > 
> > This patch is a straightforward translation of the arm64 header. 64bit
> > accesses are done in two times and don't need atomicity: TYPER is
> > read-only, and the upper-word of IROUTER is always zero on 32bit
> > architectures.
> > 
> > Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
> > ---
> >  arch/arm/include/asm/arch_gicv3.h | 182 ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 182 insertions(+)
> >  create mode 100644 arch/arm/include/asm/arch_gicv3.h
> > 
> > diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
> > new file mode 100644
> > index 0000000..c2c3603
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch_gicv3.h
> > @@ -0,0 +1,182 @@

[...]

> > +static inline void gic_write_sre(u32 val)
> > +{
> > +	asm volatile("mcr " __stringify(ICC_SRE) : : "r" (val));
> > +	isb();
> > +}
> > +
> > +/*
> > + * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
> > + * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
> > + * make much sense.
> > + * Moreover, 64bit I/O emulation is extremely difficult to implement on
> > + * AArch32, since the syndrome register doesn't provide any information for
> > + * them.
> > + * Consequently, the following IO helpers use 32bit accesses.
> > + *
> > + * There are only two registers that need 64bit accesses in this driver:
> > + * - GICD_IROUTERn, contain the affinity values associated to each interrupt.
> > + *   The upper-word (aff3) will always be 0, so there is no need for a lock.
> > + * - GICR_TYPER is an ID register and doesn't need atomicity.
> > + */
> > +static void gic_write_irouter(u64 val, volatile void __iomem *addr)
> 
> Any reason not to be inlined like other functions do?
> 
No, it should be inlined. Good catch!

Thanks,
Jean