[PATCH 00/18] A few more workarounds

[PATCH 00/18] A few more workarounds

[Damien Lespiau]

Following Nick's work, I found a few more.

-- 
Damien

Damien Lespiau (18):
  drm/i915: Support not having an init clock gating function defined
  drm/i915/skl: Implement WaDisableHBR2
  drm/i915/skl: Document the WM read latency W/A with its name
  drm/i915/skl: Provide a gen9 specific init_render_ring()
  drm/i915/skl: Make the init clock gating function skylake specific
  drm/i915/skl: Implement WaSetGAPSunitClckGateDisable
  drm/i915/skl: Implement
    WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
  drm/i915/skl: Document that we implement WaRsClearFWBitsAtReset
  drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrement
  drm/i915/skl: Implement WaDisableVFUnitClockGating
  drm/i915/skl: Introduce a SKL specific init_workarounds()
  drm/i915/skl: Implement WaDisablePowerCompilerClockGating
  drm/i915/skl: Implement WaDisablePartialResolveInVc
  drm/i915/skl: Implement WaDisableLSQCROPERFforOCL
  drm/i915/skl: Implement WaDisableHDCInvalidation
  drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS
  drm/i915/skl: Implement WaCcsTlbPrefetchDisable:skl
  drm/i915/skl: Implement WaBarrierPerformanceFixDisable

 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/i915_reg.h         | 24 +++++++++++++++++--
 drivers/gpu/drm/i915/intel_dp.c         |  5 +++-
 drivers/gpu/drm/i915/intel_lrc.c        | 16 ++++++++++++-
 drivers/gpu/drm/i915/intel_pm.c         | 41 ++++++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 41 ++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_uncore.c     |  1 +
 7 files changed, 121 insertions(+), 8 deletions(-)

-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 01/18] drm/i915: Support not having an init clock gating function defined

[Damien Lespiau]

When enabling new platforms, we may not have any W/A to apply,
especially that, now, a bunch of them have to be done from the ring.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3c64810..a3b979d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6386,7 +6386,8 @@ void intel_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	dev_priv->display.init_clock_gating(dev);
+	if (dev_priv->display.init_clock_gating)
+		dev_priv->display.init_clock_gating(dev);
 }
 
 void intel_suspend_hw(struct drm_device *dev)
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 02/18] drm/i915/skl: Implement WaDisableHBR2

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d4c82d7..4a60c6a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -129,7 +129,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
 	case DP_LINK_BW_2_7:
 		break;
 	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
+		if (IS_SKYLAKE(dev) && dev->pdev->revision <= 0x1)
+			/* WaDisableHBR2:skl */
+			max_link_bw = DP_LINK_BW_2_7;
+		else if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 		     INTEL_INFO(dev)->gen >= 8) &&
 		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 			max_link_bw = DP_LINK_BW_5_4;
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 03/18] drm/i915/skl: Document the WM read latency W/A with its name

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a3b979d..6fd6f26 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1701,6 +1701,8 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
 				GEN9_MEM_LATENCY_LEVEL_MASK;
 
 		/*
+		 * WaWmMemoryReadLatency:skl
+		 *
 		 * punit doesn't take into account the read latency so we need
 		 * to add 2us to the various latency levels we retrieve from
 		 * the punit.
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 04/18] drm/i915/skl: Provide a gen9 specific init_render_ring()

[Damien Lespiau]

WaDisableAsyncFlipPerfMode isn't listed for SKL and
INSTPM_FORCE_ORDERING is MBZ so let's make a gen9 specific render init
function.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d05f3bc..fe25ced 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1149,6 +1149,17 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring)
 	return init_workarounds_ring(ring);
 }
 
+static int gen9_init_render_ring(struct intel_engine_cs *ring)
+{
+	int ret;
+
+	ret = gen8_init_common_ring(ring);
+	if (ret)
+		return ret;
+
+	return init_workarounds_ring(ring);
+}
+
 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
 			      struct intel_context *ctx,
 			      u64 offset, unsigned flags)
@@ -1408,7 +1419,10 @@ static int logical_render_ring_init(struct drm_device *dev)
 	if (HAS_L3_DPF(dev))
 		ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
-	ring->init_hw = gen8_init_render_ring;
+	if (INTEL_INFO(dev)->gen >= 9)
+		ring->init_hw = gen9_init_render_ring;
+	else
+		ring->init_hw = gen8_init_render_ring;
 	ring->init_context = gen8_init_rcs_context;
 	ring->cleanup = intel_fini_pipe_control;
 	ring->get_seqno = gen8_get_seqno;
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 05/18] drm/i915/skl: Make the init clock gating function skylake specific

[Damien Lespiau]

We'll gather cross-gen9 W/A in a separate function later.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6fd6f26..03e27c2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -52,7 +52,7 @@
 #define INTEL_RC6p_ENABLE			(1<<1)
 #define INTEL_RC6pp_ENABLE			(1<<2)
 
-static void gen9_init_clock_gating(struct drm_device *dev)
+static void skl_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
@@ -6415,7 +6415,7 @@ void intel_init_pm(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen >= 9) {
 		skl_setup_wm_latency(dev);
 
-		dev_priv->display.init_clock_gating = gen9_init_clock_gating;
+		dev_priv->display.init_clock_gating = skl_init_clock_gating;
 		dev_priv->display.update_wm = skl_update_wm;
 		dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
 	} else if (HAS_PCH_SPLIT(dev)) {
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 06/18] drm/i915/skl: Implement WaSetGAPSunitClckGateDisable

[Damien Lespiau]

Let's also take the opportunity the remove the comment telling it's a
pre-prod W/A, it should be obvious from the stepping test.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4ee1964..578fd90 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6016,6 +6016,7 @@ enum skl_disp_power_wells {
 #define GEN6_RSTCTL				0x9420
 
 #define GEN8_UCGCTL6				0x9430
+#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
 
 #define GEN6_GFXPAUSE				0xA000
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03e27c2..2c66423 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -59,9 +59,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
 	if (INTEL_REVID(dev) == SKL_REVID_A0) {
 		/*
 		 * WaDisableSDEUnitClockGating:skl
-		 * This seems to be a pre-production w/a.
+		 * WaSetGAPSunitClckGateDisable:skl
 		 */
 		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
 			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 	}
 }
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 07/18] drm/i915/skl: Implement WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 578fd90..cb66c8f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5237,12 +5237,16 @@ enum skl_disp_power_wells {
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
+# define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
 #define COMMON_SLICE_CHICKEN2			0x7014
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
 
 #define HIZ_CHICKEN				0x7018
 # define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
 
+#define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
+#define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
+
 #define GEN7_L3SQCREG1				0xB010
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 293d1b6..b15d596 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -897,6 +897,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 			~GEN9_DG_MIRROR_FIX_ENABLE);
 	}
 
+	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
+		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
+		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
+				  GEN9_RHWO_OPTIMIZATION_DISABLE);
+		WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
+				  DISABLE_PIXEL_MASK_CAMMING);
+	}
+
 	if (INTEL_REVID(dev) >= SKL_REVID_C0) {
 		/* WaEnableYV12BugFixInHalfSliceChicken7:skl */
 		WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 08/18] drm/i915/skl: Document that we implement WaRsClearFWBitsAtReset

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c47a3ba..ad71575 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -972,6 +972,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
 		d->val_set = FORCEWAKE_KERNEL;
 		d->val_clear = 0;
 	} else {
+		/* WaRsClearFWBitsAtReset:bdw,skl */
 		d->val_reset = _MASKED_BIT_DISABLE(0xffff);
 		d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
 		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 09/18] drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrement

[Damien Lespiau]

This W/A is put in a gen9 specific function because it may well be
needed on other gen9 platforms.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cb66c8f..2043e82 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5275,6 +5275,9 @@ enum skl_disp_power_wells {
 #define HSW_SCRATCH1				0xb038
 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)
 
+#define BDW_SCRATCH1					0xb11c
+#define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1<<2)
+
 /* PCH */
 
 /* south display engine interrupt: IBX */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2c66423..ed029e7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -52,10 +52,21 @@
 #define INTEL_RC6p_ENABLE			(1<<1)
 #define INTEL_RC6pp_ENABLE			(1<<2)
 
+static void gen9_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* WaEnableLbsSlaRetryTimerDecrement:skl */
+	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
+		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+}
+
 static void skl_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	gen9_init_clock_gating(dev);
+
 	if (INTEL_REVID(dev) == SKL_REVID_A0) {
 		/*
 		 * WaDisableSDEUnitClockGating:skl
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 10/18] drm/i915/skl: Implement WaDisableVFUnitClockGating

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2043e82..a457c28 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6007,6 +6007,7 @@ enum skl_disp_power_wells {
 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
 
 #define GEN6_UCGCTL2				0x9404
+# define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed029e7..ff4e289 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -75,6 +75,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
 		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
 			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+		/* WaDisableVFUnitClockGating:skl */
+		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
+			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
 	}
 }
 
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 11/18] drm/i915/skl: Introduce a SKL specific init_workarounds()

[Damien Lespiau]

This function will host SKL-only W/As.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b15d596..27d101c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -928,6 +928,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	return 0;
 }
 
+static int skl_init_workarounds(struct intel_engine_cs *ring)
+{
+	gen9_init_workarounds(ring);
+
+	return 0;
+}
+
 int init_workarounds_ring(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
@@ -943,7 +950,9 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
 	if (IS_CHERRYVIEW(dev))
 		return chv_init_workarounds(ring);
 
-	if (IS_GEN9(dev))
+	if (IS_SKYLAKE(dev))
+		return skl_init_workarounds(ring);
+	else if (IS_GEN9(dev))
 		return gen9_init_workarounds(ring);
 
 	return 0;
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 12/18] drm/i915/skl: Implement WaDisablePowerCompilerClockGating

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 5 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a457c28..fdfbdb3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5241,8 +5241,9 @@ enum skl_disp_power_wells {
 #define COMMON_SLICE_CHICKEN2			0x7014
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
 
-#define HIZ_CHICKEN				0x7018
-# define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
+#define HIZ_CHICKEN					0x7018
+# define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
+# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1<<3)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
 #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 27d101c..3135192 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -930,8 +930,16 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 
 static int skl_init_workarounds(struct intel_engine_cs *ring)
 {
+	struct drm_device *dev = ring->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
 	gen9_init_workarounds(ring);
 
+	/* WaDisablePowerCompilerClockGating:skl */
+	if (INTEL_REVID(dev) == SKL_REVID_B0)
+		WA_SET_BIT_MASKED(HIZ_CHICKEN,
+				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
+
 	return 0;
 }
 
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 13/18] drm/i915/skl: Implement WaDisablePartialResolveInVc

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fdfbdb3..d519ed9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1483,6 +1483,7 @@ enum skl_disp_power_wells {
 #define CACHE_MODE_1		0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1<<6)
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
 
 #define GEN6_BLITTER_ECOSKPD	0x221d0
 #define   GEN6_BLITTER_LOCK_SHIFT			16
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3135192..db83baf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -925,6 +925,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	/* Wa4x4STCOptimizationDisable:skl */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
+	/* WaDisablePartialResolveInVc:skl */
+	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
+
 	return 0;
 }
 
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 14/18] drm/i915/skl: Implement WaDisableLSQCROPERFforOCL

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 5 +++++
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0b8644..0765bd1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2391,6 +2391,7 @@ struct drm_i915_cmd_table {
 #define SKL_REVID_B0		(0x1)
 #define SKL_REVID_C0		(0x2)
 #define SKL_REVID_D0		(0x3)
+#define SKL_REVID_E0		(0x4)
 
 /*
  * The genX designation typically refers to the render engine, so render
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d519ed9..3ae7a09 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5264,6 +5264,9 @@ enum skl_disp_power_wells {
 #define GEN7_L3SQCREG4				0xb034
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
 
+#define GEN8_L3SQCREG4				0xb118
+#define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
+
 /* GEN8 chicken */
 #define HDC_CHICKEN0				0x7300
 #define  HDC_FORCE_NON_COHERENT			(1<<4)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ff4e289..f53ef11 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -80,6 +80,11 @@ static void skl_init_clock_gating(struct drm_device *dev)
 		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
 			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
 	}
+
+	if (INTEL_REVID(dev) <= SKL_REVID_E0)
+		/* WaDisableLSQCROPERFforOCL:skl */
+		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+			   GEN8_LQSC_RO_PERF_DIS);
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 15/18] drm/i915/skl: Implement WaDisableHDCInvalidation

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ae7a09..b363c5e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -140,6 +140,7 @@
 #define GEN8_RING_PDP_LDW(ring, n)	((ring)->mmio_base+0x270 + (n) * 8)
 
 #define GAM_ECOCHK			0x4090
+#define   BDW_DISABLE_HDC_INVALIDATION	(1<<25)
 #define   ECOCHK_SNB_BIT		(1<<10)
 #define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
 #define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f53ef11..8f9149b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -81,6 +81,12 @@ static void skl_init_clock_gating(struct drm_device *dev)
 			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
 	}
 
+	if (INTEL_REVID(dev) <= SKL_REVID_D0)
+		/* WaDisableHDCInvalidation:skl */
+		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+			   BDW_DISABLE_HDC_INVALIDATION);
+
+
 	if (INTEL_REVID(dev) <= SKL_REVID_E0)
 		/* WaDisableLSQCROPERFforOCL:skl */
 		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 16/18] drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b363c5e..610fcd4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5236,6 +5236,9 @@ enum skl_disp_power_wells {
 #define HSW_NDE_RSTWRN_OPT	0x46408
 #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
 
+#define FF_SLICE_CS_CHICKEN2			0x02e4
+#define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
+
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8f9149b..6254102 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -81,11 +81,16 @@ static void skl_init_clock_gating(struct drm_device *dev)
 			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
 	}
 
-	if (INTEL_REVID(dev) <= SKL_REVID_D0)
+	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
 		/* WaDisableHDCInvalidation:skl */
 		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 			   BDW_DISABLE_HDC_INVALIDATION);
 
+		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
+		I915_WRITE(FF_SLICE_CS_CHICKEN2,
+			   I915_READ(FF_SLICE_CS_CHICKEN2) |
+			   GEN9_TSG_BARRIER_ACK_DISABLE);
+	}
 
 	if (INTEL_REVID(dev) <= SKL_REVID_E0)
 		/* WaDisableLSQCROPERFforOCL:skl */
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 17/18] drm/i915/skl: Implement WaCcsTlbPrefetchDisable:skl

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 610fcd4..090ddd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6216,6 +6216,7 @@ enum skl_disp_power_wells {
 
 #define GEN9_HALF_SLICE_CHICKEN5	0xe188
 #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
+#define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1<<3)
 
 #define GEN8_ROW_CHICKEN		0xe4f0
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index db83baf..57432ca 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -928,6 +928,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	/* WaDisablePartialResolveInVc:skl */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 
+	/* WaCcsTlbPrefetchDisable:skl */
+	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
+			  GEN9_CCS_TLB_PREFETCH_ENABLE);
+
 	return 0;
 }
 
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 18/18] drm/i915/skl: Implement WaBarrierPerformanceFixDisable

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 090ddd7..b4abd50 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5276,6 +5276,7 @@ enum skl_disp_power_wells {
 #define  HDC_FORCE_NON_COHERENT			(1<<4)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
+#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
 
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 57432ca..93365fe 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -947,6 +947,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(HIZ_CHICKEN,
 				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
 
+	if (INTEL_REVID(dev) == SKL_REVID_C0 ||
+	    INTEL_REVID(dev) == SKL_REVID_D0)
+		/* WaBarrierPerformanceFixDisable:skl */
+		WA_SET_BIT_MASKED(HDC_CHICKEN0,
+				  HDC_FENCE_DEST_SLM_DISABLE |
+				  HDC_BARRIER_PERFORMANCE_DISABLE);
+
 	return 0;
 }
 
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 01/18] drm/i915: Support not having an init clock gating function defined

[Daniel Vetter]

On Mon, Feb 09, 2015 at 07:33:05PM +0000, Damien Lespiau wrote:
> When enabling new platforms, we may not have any W/A to apply,
> especially that, now, a bunch of them have to be done from the ring.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Queued for -next, thanks for the patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3c64810..a3b979d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6386,7 +6386,8 @@ void intel_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	dev_priv->display.init_clock_gating(dev);
> +	if (dev_priv->display.init_clock_gating)
> +		dev_priv->display.init_clock_gating(dev);
>  }
>  
>  void intel_suspend_hw(struct drm_device *dev)
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 18/18] drm/i915/skl: Implement WaBarrierPerformanceFixDisable

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5737
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  282/283              282/283
ILK                                  308/315              308/315
SNB              +1-22              340/346              319/346
IVB              +1-2              378/384              377/384
BYT                                  296/296              296/296
HSW              +2                 421/428              423/428
BDW                                  318/333              318/333
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*SNB  igt_kms_flip_dpms-vs-vblank-race      PASS(4, M22)      DMESG_WARN(1, M22)
 SNB  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(3, M22)PASS(2, M22)      DMESG_WARN(1, M22)
 SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_kms_pipe_crc_basic_read-crc-pipe-A      DMESG_WARN(1, M22)PASS(6, M22)      PASS(1, M22)
 SNB  igt_kms_rotation_crc_primary-rotation      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_cursor      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_cursor-dpms      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_drm-resources-equal      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_fences      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_fences-dpms      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-execbuf      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-pread      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_i2c      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_pci-d3-state      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_rte      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 IVB  igt_gem_pwrite_pread_snooped-copy-performance      DMESG_WARN(1, M34)PASS(5, M34)      DMESG_WARN(1, M34)
 IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(2, M34)PASS(2, M34)      PASS(1, M34)
 IVB  igt_gem_storedw_batches_loop_secure-dispatch      DMESG_WARN(1, M34)PASS(3, M34)      DMESG_WARN(1, M34)
 HSW  igt_gem_storedw_loop_blt      DMESG_WARN(3, M20)PASS(3, M20)      PASS(1, M20)
 HSW  igt_gem_storedw_loop_vebox      DMESG_WARN(3, M20)PASS(2, M20)      PASS(1, M20)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 01/18] drm/i915: Support not having an init clock gating function defined

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> When enabling new platforms, we may not have any W/A to apply,
> especially that, now, a bunch of them have to be done from the ring.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3c64810..a3b979d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6386,7 +6386,8 @@ void intel_init_clock_gating(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>
> -	dev_priv->display.init_clock_gating(dev);
> +	if (dev_priv->display.init_clock_gating)
> +		dev_priv->display.init_clock_gating(dev);
>   }
>
>   void intel_suspend_hw(struct drm_device *dev)
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 02/18] drm/i915/skl: Implement WaDisableHBR2

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d4c82d7..4a60c6a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -129,7 +129,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
>   	case DP_LINK_BW_2_7:
>   		break;
>   	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
> -		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> +		if (IS_SKYLAKE(dev) && dev->pdev->revision <= 0x1)

Should be: if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ?

> +			/* WaDisableHBR2:skl */
> +			max_link_bw = DP_LINK_BW_2_7;
> +		else if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>   		     INTEL_INFO(dev)->gen >= 8) &&
>   		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
>   			max_link_bw = DP_LINK_BW_5_4;
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 03/18] drm/i915/skl: Document the WM read latency W/A with its name

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_pm.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a3b979d..6fd6f26 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1701,6 +1701,8 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
>   				GEN9_MEM_LATENCY_LEVEL_MASK;
>
>   		/*
> +		 * WaWmMemoryReadLatency:skl
> +		 *
>   		 * punit doesn't take into account the read latency so we need
>   		 * to add 2us to the various latency levels we retrieve from
>   		 * the punit.
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 04/18] drm/i915/skl: Provide a gen9 specific init_render_ring()

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> WaDisableAsyncFlipPerfMode isn't listed for SKL and
> INSTPM_FORCE_ORDERING is MBZ so let's make a gen9 specific render init
> function.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 16 +++++++++++++++-
>   1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d05f3bc..fe25ced 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1149,6 +1149,17 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring)
>   	return init_workarounds_ring(ring);
>   }
>
> +static int gen9_init_render_ring(struct intel_engine_cs *ring)
> +{
> +	int ret;
> +
> +	ret = gen8_init_common_ring(ring);
> +	if (ret)
> +		return ret;
> +
> +	return init_workarounds_ring(ring);
> +}
> +
>   static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
>   			      struct intel_context *ctx,
>   			      u64 offset, unsigned flags)
> @@ -1408,7 +1419,10 @@ static int logical_render_ring_init(struct drm_device *dev)
>   	if (HAS_L3_DPF(dev))
>   		ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
>
> -	ring->init_hw = gen8_init_render_ring;
> +	if (INTEL_INFO(dev)->gen >= 9)
> +		ring->init_hw = gen9_init_render_ring;
> +	else
> +		ring->init_hw = gen8_init_render_ring;
>   	ring->init_context = gen8_init_rcs_context;
>   	ring->cleanup = intel_fini_pipe_control;
>   	ring->get_seqno = gen8_get_seqno;
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 05/18] drm/i915/skl: Make the init clock gating function skylake specific

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> We'll gather cross-gen9 W/A in a separate function later.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_pm.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6fd6f26..03e27c2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -52,7 +52,7 @@
>   #define INTEL_RC6p_ENABLE			(1<<1)
>   #define INTEL_RC6pp_ENABLE			(1<<2)
>
> -static void gen9_init_clock_gating(struct drm_device *dev)
> +static void skl_init_clock_gating(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>
> @@ -6415,7 +6415,7 @@ void intel_init_pm(struct drm_device *dev)
>   	if (INTEL_INFO(dev)->gen >= 9) {
>   		skl_setup_wm_latency(dev);
>
> -		dev_priv->display.init_clock_gating = gen9_init_clock_gating;
> +		dev_priv->display.init_clock_gating = skl_init_clock_gating;
>   		dev_priv->display.update_wm = skl_update_wm;
>   		dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
>   	} else if (HAS_PCH_SPLIT(dev)) {
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 06/18] drm/i915/skl: Implement WaSetGAPSunitClckGateDisable

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Let's also take the opportunity the remove the comment telling it's a
> pre-prod W/A, it should be obvious from the stepping test.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>   2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4ee1964..578fd90 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6016,6 +6016,7 @@ enum skl_disp_power_wells {
>   #define GEN6_RSTCTL				0x9420
>
>   #define GEN8_UCGCTL6				0x9430
> +#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
>   #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
>
>   #define GEN6_GFXPAUSE				0xA000
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 03e27c2..2c66423 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -59,9 +59,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
>   	if (INTEL_REVID(dev) == SKL_REVID_A0) {
>   		/*
>   		 * WaDisableSDEUnitClockGating:skl
> -		 * This seems to be a pre-production w/a.
> +		 * WaSetGAPSunitClckGateDisable:skl
>   		 */
>   		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> +			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
>   			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>   	}
>   }
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 08/18] drm/i915/skl: Document that we implement WaRsClearFWBitsAtReset

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_uncore.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index c47a3ba..ad71575 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -972,6 +972,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
>   		d->val_set = FORCEWAKE_KERNEL;
>   		d->val_clear = 0;
>   	} else {
> +		/* WaRsClearFWBitsAtReset:bdw,skl */
>   		d->val_reset = _MASKED_BIT_DISABLE(0xffff);
>   		d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
>   		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 10/18] drm/i915/skl: Implement WaDisableVFUnitClockGating

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>   2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2043e82..a457c28 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6007,6 +6007,7 @@ enum skl_disp_power_wells {
>   # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
>
>   #define GEN6_UCGCTL2				0x9404
> +# define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
>   # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
>   # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
>   # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ed029e7..ff4e289 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -75,6 +75,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
>   		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>   			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
>   			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
> +		/* WaDisableVFUnitClockGating:skl */
> +		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
> +			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);

bspec says this should be until B0

>   	}
>   }
>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 11/18] drm/i915/skl: Introduce a SKL specific init_workarounds()

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> This function will host SKL-only W/As.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index b15d596..27d101c 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -928,6 +928,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>   	return 0;
>   }
>
> +static int skl_init_workarounds(struct intel_engine_cs *ring)
> +{
> +	gen9_init_workarounds(ring);
> +
> +	return 0;
> +}
> +
>   int init_workarounds_ring(struct intel_engine_cs *ring)
>   {
>   	struct drm_device *dev = ring->dev;
> @@ -943,7 +950,9 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
>   	if (IS_CHERRYVIEW(dev))
>   		return chv_init_workarounds(ring);
>
> -	if (IS_GEN9(dev))
> +	if (IS_SKYLAKE(dev))
> +		return skl_init_workarounds(ring);
> +	else if (IS_GEN9(dev))
>   		return gen9_init_workarounds(ring);
>
>   	return 0;
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 12/18] drm/i915/skl: Implement WaDisablePowerCompilerClockGating

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 5 +++--
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
>   2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a457c28..fdfbdb3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5241,8 +5241,9 @@ enum skl_disp_power_wells {
>   #define COMMON_SLICE_CHICKEN2			0x7014
>   # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
>
> -#define HIZ_CHICKEN				0x7018
> -# define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
> +#define HIZ_CHICKEN					0x7018
> +# define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
> +# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1<<3)
>
>   #define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
>   #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 27d101c..3135192 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -930,8 +930,16 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>
>   static int skl_init_workarounds(struct intel_engine_cs *ring)
>   {
> +	struct drm_device *dev = ring->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
>   	gen9_init_workarounds(ring);
>
> +	/* WaDisablePowerCompilerClockGating:skl */
> +	if (INTEL_REVID(dev) == SKL_REVID_B0)

Should this be <= ?

> +		WA_SET_BIT_MASKED(HIZ_CHICKEN,
> +				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
> +
>   	return 0;
>   }
>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 13/18] drm/i915/skl: Implement WaDisablePartialResolveInVc

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 1 +
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>   2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fdfbdb3..d519ed9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1483,6 +1483,7 @@ enum skl_disp_power_wells {
>   #define CACHE_MODE_1		0x7004 /* IVB+ */
>   #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1<<6)
>   #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
> +#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
>
>   #define GEN6_BLITTER_ECOSKPD	0x221d0
>   #define   GEN6_BLITTER_LOCK_SHIFT			16
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 3135192..db83baf 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -925,6 +925,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>   	/* Wa4x4STCOptimizationDisable:skl */
>   	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
>
> +	/* WaDisablePartialResolveInVc:skl */
> +	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
> +
>   	return 0;
>   }
>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 14/18] drm/i915/skl: Implement WaDisableLSQCROPERFforOCL

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_drv.h | 1 +
>   drivers/gpu/drm/i915/i915_reg.h | 3 +++
>   drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>   3 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c0b8644..0765bd1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2391,6 +2391,7 @@ struct drm_i915_cmd_table {
>   #define SKL_REVID_B0		(0x1)
>   #define SKL_REVID_C0		(0x2)
>   #define SKL_REVID_D0		(0x3)
> +#define SKL_REVID_E0		(0x4)
>
>   /*
>    * The genX designation typically refers to the render engine, so render
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d519ed9..3ae7a09 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5264,6 +5264,9 @@ enum skl_disp_power_wells {
>   #define GEN7_L3SQCREG4				0xb034
>   #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
>
> +#define GEN8_L3SQCREG4				0xb118
> +#define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
> +
>   /* GEN8 chicken */
>   #define HDC_CHICKEN0				0x7300
>   #define  HDC_FORCE_NON_COHERENT			(1<<4)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ff4e289..f53ef11 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -80,6 +80,11 @@ static void skl_init_clock_gating(struct drm_device *dev)
>   		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
>   			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
>   	}
> +
> +	if (INTEL_REVID(dev) <= SKL_REVID_E0)
> +		/* WaDisableLSQCROPERFforOCL:skl */
> +		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
> +			   GEN8_LQSC_RO_PERF_DIS);
>   }
>
>   static void i915_pineview_get_mem_freq(struct drm_device *dev)
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 15/18] drm/i915/skl: Implement WaDisableHDCInvalidation

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>   2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3ae7a09..b363c5e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -140,6 +140,7 @@
>   #define GEN8_RING_PDP_LDW(ring, n)	((ring)->mmio_base+0x270 + (n) * 8)
>
>   #define GAM_ECOCHK			0x4090
> +#define   BDW_DISABLE_HDC_INVALIDATION	(1<<25)
>   #define   ECOCHK_SNB_BIT		(1<<10)
>   #define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
>   #define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f53ef11..8f9149b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -81,6 +81,12 @@ static void skl_init_clock_gating(struct drm_device *dev)
>   			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
>   	}
>
> +	if (INTEL_REVID(dev) <= SKL_REVID_D0)
> +		/* WaDisableHDCInvalidation:skl */
> +		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> +			   BDW_DISABLE_HDC_INVALIDATION);
> +
> +
>   	if (INTEL_REVID(dev) <= SKL_REVID_E0)
>   		/* WaDisableLSQCROPERFforOCL:skl */
>   		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 16/18] drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h | 3 +++
>   drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
>   2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b363c5e..610fcd4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5236,6 +5236,9 @@ enum skl_disp_power_wells {
>   #define HSW_NDE_RSTWRN_OPT	0x46408
>   #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
>
> +#define FF_SLICE_CS_CHICKEN2			0x02e4
> +#define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
> +
>   /* GEN7 chicken */
>   #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
>   # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8f9149b..6254102 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -81,11 +81,16 @@ static void skl_init_clock_gating(struct drm_device *dev)
>   			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
>   	}
>
> -	if (INTEL_REVID(dev) <= SKL_REVID_D0)
> +	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
>   		/* WaDisableHDCInvalidation:skl */
>   		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>   			   BDW_DISABLE_HDC_INVALIDATION);
>
> +		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
> +		I915_WRITE(FF_SLICE_CS_CHICKEN2,
> +			   I915_READ(FF_SLICE_CS_CHICKEN2) |
> +			   GEN9_TSG_BARRIER_ACK_DISABLE);
> +	}
>
>   	if (INTEL_REVID(dev) <= SKL_REVID_E0)
>   		/* WaDisableLSQCROPERFforOCL:skl */
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 17/18] drm/i915/skl: Implement WaCcsTlbPrefetchDisable:skl

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 1 +
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
>   2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 610fcd4..090ddd7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6216,6 +6216,7 @@ enum skl_disp_power_wells {
>
>   #define GEN9_HALF_SLICE_CHICKEN5	0xe188
>   #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
> +#define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1<<3)
>
>   #define GEN8_ROW_CHICKEN		0xe4f0
>   #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index db83baf..57432ca 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -928,6 +928,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>   	/* WaDisablePartialResolveInVc:skl */
>   	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
>
> +	/* WaCcsTlbPrefetchDisable:skl */
> +	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> +			  GEN9_CCS_TLB_PREFETCH_ENABLE);
> +
>   	return 0;
>   }
>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 18/18] drm/i915/skl: Implement WaBarrierPerformanceFixDisable

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 1 +
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 090ddd7..b4abd50 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5276,6 +5276,7 @@ enum skl_disp_power_wells {
>   #define  HDC_FORCE_NON_COHERENT			(1<<4)
>   #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
> +#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
>
>   /* WaCatErrorRejectionIssue */
>   #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 57432ca..93365fe 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -947,6 +947,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>   		WA_SET_BIT_MASKED(HIZ_CHICKEN,
>   				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
>
> +	if (INTEL_REVID(dev) == SKL_REVID_C0 ||
> +	    INTEL_REVID(dev) == SKL_REVID_D0)
> +		/* WaBarrierPerformanceFixDisable:skl */
> +		WA_SET_BIT_MASKED(HDC_CHICKEN0,
> +				  HDC_FENCE_DEST_SLM_DISABLE |
> +				  HDC_BARRIER_PERFORMANCE_DISABLE);
> +
>   	return 0;
>   }
>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 16/18] drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS

[Daniel Vetter]

On Wed, Feb 11, 2015 at 03:42:16PM +0000, Nick Hoath wrote:
> On 09/02/2015 19:33, Damien Lespiau wrote:
> >Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> 
> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

Merged all the ones Nick has reviewd already.

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2] drm/i915/skl: Implement WaDisableHBR2

[Damien Lespiau]

v2: Use the recently introduced INTEL_REVID() and SKL_REVID defines
    (Nick Hoath)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d4c82d7..a7bc3e8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -129,7 +129,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
 	case DP_LINK_BW_2_7:
 		break;
 	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
+		if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
+			/* WaDisableHBR2:skl */
+			max_link_bw = DP_LINK_BW_2_7;
+		else if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 		     INTEL_INFO(dev)->gen >= 8) &&
 		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 			max_link_bw = DP_LINK_BW_5_4;
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 12/18] drm/i915/skl: Implement WaDisablePowerCompilerClockGating

[Damien Lespiau]

On Wed, Feb 11, 2015 at 03:29:51PM +0000, Nick Hoath wrote:
> On 09/02/2015 19:33, Damien Lespiau wrote:
> >Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> >---
> >  drivers/gpu/drm/i915/i915_reg.h         | 5 +++--
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
> >  2 files changed, 11 insertions(+), 2 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >index a457c28..fdfbdb3 100644
> >--- a/drivers/gpu/drm/i915/i915_reg.h
> >+++ b/drivers/gpu/drm/i915/i915_reg.h
> >@@ -5241,8 +5241,9 @@ enum skl_disp_power_wells {
> >  #define COMMON_SLICE_CHICKEN2			0x7014
> >  # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
> >
> >-#define HIZ_CHICKEN				0x7018
> >-# define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
> >+#define HIZ_CHICKEN					0x7018
> >+# define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
> >+# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1<<3)
> >
> >  #define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
> >  #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
> >diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >index 27d101c..3135192 100644
> >--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >@@ -930,8 +930,16 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >
> >  static int skl_init_workarounds(struct intel_engine_cs *ring)
> >  {
> >+	struct drm_device *dev = ring->dev;
> >+	struct drm_i915_private *dev_priv = dev->dev_private;
> >+
> >  	gen9_init_workarounds(ring);
> >
> >+	/* WaDisablePowerCompilerClockGating:skl */
> >+	if (INTEL_REVID(dev) == SKL_REVID_B0)
> 
> Should this be <= ?

Nop, both specs (SKL:GT2:B) and the wa db (SIWA_ONLY_SKL_B0) state
firmly B0 only.

-- 
Damien
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 07/18] drm/i915/skl: Implement WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
>   2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 578fd90..cb66c8f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5237,12 +5237,16 @@ enum skl_disp_power_wells {
>   /* GEN7 chicken */
>   #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
>   # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
> +# define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
>   #define COMMON_SLICE_CHICKEN2			0x7014
>   # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
>
>   #define HIZ_CHICKEN				0x7018
>   # define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
>
> +#define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
> +#define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
> +
>   #define GEN7_L3SQCREG1				0xB010
>   #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 293d1b6..b15d596 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -897,6 +897,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>   			~GEN9_DG_MIRROR_FIX_ENABLE);
>   	}
>
> +	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
> +		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
> +		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> +				  GEN9_RHWO_OPTIMIZATION_DISABLE);
> +		WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
> +				  DISABLE_PIXEL_MASK_CAMMING);
> +	}
> +
>   	if (INTEL_REVID(dev) >= SKL_REVID_C0) {
>   		/* WaEnableYV12BugFixInHalfSliceChicken7:skl */
>   		WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 09/18] drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrement

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> This W/A is put in a gen9 specific function because it may well be
> needed on other gen9 platforms.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h |  3 +++
>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>   2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cb66c8f..2043e82 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5275,6 +5275,9 @@ enum skl_disp_power_wells {
>   #define HSW_SCRATCH1				0xb038
>   #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)
>
> +#define BDW_SCRATCH1					0xb11c
> +#define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1<<2)
> +
>   /* PCH */
>
>   /* south display engine interrupt: IBX */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2c66423..ed029e7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -52,10 +52,21 @@
>   #define INTEL_RC6p_ENABLE			(1<<1)
>   #define INTEL_RC6pp_ENABLE			(1<<2)
>
> +static void gen9_init_clock_gating(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* WaEnableLbsSlaRetryTimerDecrement:skl */
> +	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
> +		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
> +}
> +
>   static void skl_init_clock_gating(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>
> +	gen9_init_clock_gating(dev);
> +
>   	if (INTEL_REVID(dev) == SKL_REVID_A0) {
>   		/*
>   		 * WaDisableSDEUnitClockGating:skl
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2] drm/i915/skl: Implement WaDisableHBR2

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5762
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              282/282              281/282
ILK                                  313/313              313/313
SNB                                  309/323              309/323
IVB                                  380/380              380/380
BYT                                  296/296              296/296
HSW                 -1              425/425              424/425
BDW                 -1              318/318              317/318
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gen3_render_linear_blits      PASS(5)      CRASH(1)PASS(1)
*HSW  igt_gem_storedw_loop_blt      PASS(3)      DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(8)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 12/18] drm/i915/skl: Implement WaDisablePowerCompilerClockGating

[Nick Hoath]

On 11/02/2015 17:48, Lespiau, Damien wrote:
> On Wed, Feb 11, 2015 at 03:29:51PM +0000, Nick Hoath wrote:
>> On 09/02/2015 19:33, Damien Lespiau wrote:
>>> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_reg.h         | 5 +++--
>>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
>>>   2 files changed, 11 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index a457c28..fdfbdb3 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -5241,8 +5241,9 @@ enum skl_disp_power_wells {
>>>   #define COMMON_SLICE_CHICKEN2			0x7014
>>>   # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
>>>
>>> -#define HIZ_CHICKEN				0x7018
>>> -# define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
>>> +#define HIZ_CHICKEN					0x7018
>>> +# define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
>>> +# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1<<3)
>>>
>>>   #define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
>>>   #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
>>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> index 27d101c..3135192 100644
>>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> @@ -930,8 +930,16 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>>>
>>>   static int skl_init_workarounds(struct intel_engine_cs *ring)
>>>   {
>>> +	struct drm_device *dev = ring->dev;
>>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>> +
>>>   	gen9_init_workarounds(ring);
>>>
>>> +	/* WaDisablePowerCompilerClockGating:skl */
>>> +	if (INTEL_REVID(dev) == SKL_REVID_B0)
>>
>> Should this be <= ?
>
> Nop, both specs (SKL:GT2:B) and the wa db (SIWA_ONLY_SKL_B0) state
> firmly B0 only.
>

In that case:
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 12/18] drm/i915/skl: Implement WaDisablePowerCompilerClockGating

[Daniel Vetter]

On Wed, Feb 18, 2015 at 09:57:52AM +0000, Nick Hoath wrote:
> On 11/02/2015 17:48, Lespiau, Damien wrote:
> >On Wed, Feb 11, 2015 at 03:29:51PM +0000, Nick Hoath wrote:
> >>On 09/02/2015 19:33, Damien Lespiau wrote:
> >>>Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> >>>---
> >>>  drivers/gpu/drm/i915/i915_reg.h         | 5 +++--
> >>>  drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
> >>>  2 files changed, 11 insertions(+), 2 deletions(-)
> >>>
> >>>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>>index a457c28..fdfbdb3 100644
> >>>--- a/drivers/gpu/drm/i915/i915_reg.h
> >>>+++ b/drivers/gpu/drm/i915/i915_reg.h
> >>>@@ -5241,8 +5241,9 @@ enum skl_disp_power_wells {
> >>>  #define COMMON_SLICE_CHICKEN2			0x7014
> >>>  # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
> >>>
> >>>-#define HIZ_CHICKEN				0x7018
> >>>-# define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
> >>>+#define HIZ_CHICKEN					0x7018
> >>>+# define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
> >>>+# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1<<3)
> >>>
> >>>  #define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
> >>>  #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
> >>>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>>index 27d101c..3135192 100644
> >>>--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>>@@ -930,8 +930,16 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >>>
> >>>  static int skl_init_workarounds(struct intel_engine_cs *ring)
> >>>  {
> >>>+	struct drm_device *dev = ring->dev;
> >>>+	struct drm_i915_private *dev_priv = dev->dev_private;
> >>>+
> >>>  	gen9_init_workarounds(ring);
> >>>
> >>>+	/* WaDisablePowerCompilerClockGating:skl */
> >>>+	if (INTEL_REVID(dev) == SKL_REVID_B0)
> >>
> >>Should this be <= ?
> >
> >Nop, both specs (SKL:GT2:B) and the wa db (SIWA_ONLY_SKL_B0) state
> >firmly B0 only.
> >
> 
> In that case:
> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2] drm/i915/skl: Implement WaDisableHBR2

[Jesse Barnes]

On 02/11/2015 09:43 AM, Damien Lespiau wrote:
> v2: Use the recently introduced INTEL_REVID() and SKL_REVID defines
>     (Nick Hoath)
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d4c82d7..a7bc3e8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -129,7 +129,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
>  	case DP_LINK_BW_2_7:
>  		break;
>  	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
> -		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> +		if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> +			/* WaDisableHBR2:skl */
> +			max_link_bw = DP_LINK_BW_2_7;
> +		else if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>  		     INTEL_INFO(dev)->gen >= 8) &&
>  		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
>  			max_link_bw = DP_LINK_BW_5_4;
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2] drm/i915/skl: Implement WaDisableHBR2

[Jani Nikula]

On Thu, 12 Mar 2015, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> On 02/11/2015 09:43 AM, Damien Lespiau wrote:
>> v2: Use the recently introduced INTEL_REVID() and SKL_REVID defines
>>     (Nick Hoath)
>> 
>> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index d4c82d7..a7bc3e8 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -129,7 +129,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
>>  	case DP_LINK_BW_2_7:
>>  		break;
>>  	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
>> -		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>> +		if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
>> +			/* WaDisableHBR2:skl */
>> +			max_link_bw = DP_LINK_BW_2_7;
>> +		else if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>>  		     INTEL_INFO(dev)->gen >= 8) &&
>>  		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
>>  			max_link_bw = DP_LINK_BW_5_4;
>> 
>
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Potentially

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89554


> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2] drm/i915/skl: Implement WaDisableHBR2

[Jesse Barnes]

On 03/12/2015 11:36 AM, Jani Nikula wrote:
> On Thu, 12 Mar 2015, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>> On 02/11/2015 09:43 AM, Damien Lespiau wrote:
>>> v2: Use the recently introduced INTEL_REVID() and SKL_REVID defines
>>>     (Nick Hoath)
>>>
>>> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
>>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>> index d4c82d7..a7bc3e8 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -129,7 +129,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
>>>  	case DP_LINK_BW_2_7:
>>>  		break;
>>>  	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
>>> -		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>>> +		if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
>>> +			/* WaDisableHBR2:skl */
>>> +			max_link_bw = DP_LINK_BW_2_7;
>>> +		else if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>>>  		     INTEL_INFO(dev)->gen >= 8) &&
>>>  		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
>>>  			max_link_bw = DP_LINK_BW_5_4;
>>>
>>
>> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>> Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Potentially
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89554

Yeah hopefully.  I definitely need it here for eDP to come up reliably.

Jesse
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2] drm/i915/skl: Implement WaDisableHBR2

[Daniel Vetter]

On Thu, Mar 12, 2015 at 12:03:51PM -0700, Jesse Barnes wrote:
> On 03/12/2015 11:36 AM, Jani Nikula wrote:
> > On Thu, 12 Mar 2015, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> >> On 02/11/2015 09:43 AM, Damien Lespiau wrote:
> >>> v2: Use the recently introduced INTEL_REVID() and SKL_REVID defines
> >>>     (Nick Hoath)
> >>>
> >>> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> >>> ---
> >>>  drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
> >>>  1 file changed, 4 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >>> index d4c82d7..a7bc3e8 100644
> >>> --- a/drivers/gpu/drm/i915/intel_dp.c
> >>> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >>> @@ -129,7 +129,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
> >>>  	case DP_LINK_BW_2_7:
> >>>  		break;
> >>>  	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
> >>> -		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> >>> +		if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> >>> +			/* WaDisableHBR2:skl */
> >>> +			max_link_bw = DP_LINK_BW_2_7;
> >>> +		else if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> >>>  		     INTEL_INFO(dev)->gen >= 8) &&
> >>>  		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
> >>>  			max_link_bw = DP_LINK_BW_5_4;
> >>>
> >>
> >> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> >> Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > 
> > Potentially
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89554
> 
> Yeah hopefully.  I definitely need it here for eDP to come up reliably.

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx