From: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
To: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: "linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org"
<arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org"
<heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Subject: Re: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Date: Fri, 13 Mar 2015 10:34:54 +0000 [thread overview]
Message-ID: <20150313103453.GA3592@leverpostej> (raw)
In-Reply-To: <F0B0524B-AC0E-4E60-9A21-1208C4A978F5-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> > Which of spin-table/psci are you planning on using for SMP support, and
> > when would that be likely to appear?
>
> We have a qcom specific SMP enablement method for this device. This
> was one of our first devices so it utilized as much from arm 32-bit as
> possible.
Implementation specific enable methods are something we really don't
want to see for arm64. If PSCI is out of the question then a spin-table
shim in your bootloader shouldn't be too hard to implement.
> > Which exception level do CPUs enter the kernel? Even without a
> > virt-capable GIC booting at EL2 is less work for the FW and gives the
> > kernel a better chance of fixing things up (e.g. CNTVOFF).
>
> I think the enter in EL1.
That's unfortunate, but so long as they are consistent, it's not the end
of the world.
Mark.
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WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com>
To: Kumar Gala <galak@codeaurora.org>
Cc: "linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"arm@kernel.org" <arm@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"heiko@sntech.de" <heiko@sntech.de>
Subject: Re: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Date: Fri, 13 Mar 2015 10:34:54 +0000 [thread overview]
Message-ID: <20150313103453.GA3592@leverpostej> (raw)
In-Reply-To: <F0B0524B-AC0E-4E60-9A21-1208C4A978F5@codeaurora.org>
> > Which of spin-table/psci are you planning on using for SMP support, and
> > when would that be likely to appear?
>
> We have a qcom specific SMP enablement method for this device. This
> was one of our first devices so it utilized as much from arm 32-bit as
> possible.
Implementation specific enable methods are something we really don't
want to see for arm64. If PSCI is out of the question then a spin-table
shim in your bootloader shouldn't be too hard to implement.
> > Which exception level do CPUs enter the kernel? Even without a
> > virt-capable GIC booting at EL2 is less work for the FW and gives the
> > kernel a better chance of fixing things up (e.g. CNTVOFF).
>
> I think the enter in EL1.
That's unfortunate, but so long as they are consistent, it's not the end
of the world.
Mark.
WARNING: multiple messages have this Message-ID (diff)
From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts
Date: Fri, 13 Mar 2015 10:34:54 +0000 [thread overview]
Message-ID: <20150313103453.GA3592@leverpostej> (raw)
In-Reply-To: <F0B0524B-AC0E-4E60-9A21-1208C4A978F5@codeaurora.org>
> > Which of spin-table/psci are you planning on using for SMP support, and
> > when would that be likely to appear?
>
> We have a qcom specific SMP enablement method for this device. This
> was one of our first devices so it utilized as much from arm 32-bit as
> possible.
Implementation specific enable methods are something we really don't
want to see for arm64. If PSCI is out of the question then a spin-table
shim in your bootloader shouldn't be too hard to implement.
> > Which exception level do CPUs enter the kernel? Even without a
> > virt-capable GIC booting at EL2 is less work for the FW and gives the
> > kernel a better chance of fixing things up (e.g. CNTVOFF).
>
> I think the enter in EL1.
That's unfortunate, but so long as they are consistent, it's not the end
of the world.
Mark.
next prev parent reply other threads:[~2015-03-13 10:34 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-11 20:51 [PATCH v3 1/4] arm64: qcom: Add support for Qualcomm MSM8916 SoC Kumar Gala
2015-03-11 20:51 ` Kumar Gala
2015-03-11 20:51 ` [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts Kumar Gala
2015-03-11 20:51 ` Kumar Gala
2015-03-12 17:05 ` Mark Rutland
2015-03-12 17:05 ` Mark Rutland
2015-03-12 17:05 ` Mark Rutland
2015-03-12 17:33 ` Kumar Gala
2015-03-12 17:33 ` Kumar Gala
2015-03-12 17:33 ` Kumar Gala
2015-03-12 18:25 ` Mark Rutland
2015-03-12 18:25 ` Mark Rutland
2015-03-12 18:25 ` Mark Rutland
2015-03-12 19:54 ` Kumar Gala
2015-03-12 19:54 ` Kumar Gala
2015-03-12 19:54 ` Kumar Gala
[not found] ` <F0B0524B-AC0E-4E60-9A21-1208C4A978F5-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-03-13 10:34 ` Mark Rutland [this message]
2015-03-13 10:34 ` Mark Rutland
2015-03-13 10:34 ` Mark Rutland
2015-03-13 12:07 ` Catalin Marinas
2015-03-13 12:07 ` Catalin Marinas
2015-03-13 12:07 ` Catalin Marinas
2015-03-11 20:51 ` [PATCH v3 3/4] devicetree: bindings: Document qcom,msm-id and qcom,board-id Kumar Gala
2015-03-11 20:51 ` [PATCH v3 3/4] devicetree: bindings: Document qcom, msm-id and qcom, board-id Kumar Gala
2015-03-11 20:51 ` [PATCH v3 4/4] arm64: dts: Add Qualcomm MSM8916 & MTP8916 ids Kumar Gala
2015-03-11 20:51 ` Kumar Gala
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