[PATCH 00/13] drm/i915: Clean up the DP link rate code

[PATCH 00/13] drm/i915: Clean up the DP link rate code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have a bit of a mess with the source vs. sink link rate handling, so I
went ahead and tried to clean it up. So now we keep the source and sink
rates neatly in their own corners and compute the intersection when needed.

I considered storing the intersection itself under intel_dp, but for
eDP 1.4 we need to convert the chose rate back to the index from which
we got, which means keeping the original sink rates around as well. So
in the end I figured it's not a huge deal if we keep computing the
intersection on demand.

I also ended up adding eDP 1.4 intermediate frequency support for CHV, but
as I don't have an eDP 1.4 panel in my BSW I couldn't actually test it.

Ville Syrjälä (13):
  drm/i915: Make the DP rates int instead of uint32_t
  drm/i915: Store the converted link rates in
    intel_dp->supported_rates[]
  drm/i915: Don't copy the DP source rates arrays
  drm/i915: Don't copy sink rates either
  drm/i915: Remove special case from intel_supported_rates()
  drm/i915: Fully separate source vs. sink rates
  drm/i915: Hide the source vs. sink rate handling from
    intel_dp_compute_config()
  drm/i915: Fix max link rate in intel_dp_mode_valid()
  drm/i915: Use DP_LINK_RATE_SET whenever possible
  drm/i915: Fix MST link rate handling
  drm/i915: Avoid overflowing the DP link rate arrays
  drm/i915: Add eDP intermediate frequencies for CHV
  drm/i915: Include the sink/source/supported rates in debug output

 drivers/gpu/drm/i915/intel_dp.c     | 221 +++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_dp_mst.c |  16 ++-
 drivers/gpu/drm/i915/intel_drv.h    |   6 +-
 3 files changed, 157 insertions(+), 86 deletions(-)

-- 
2.0.5

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[PATCH 01/13] drm/i915: Make the DP rates int instead of uint32_t

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No point in using uint32_t here, just plain old int will do.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 33d5877..1fa8cc1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -85,10 +85,9 @@ static const struct dp_link_dpll chv_dpll[] = {
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 /* Skylake supports following rates */
-static const uint32_t gen9_rates[] = { 162000, 216000, 270000, 324000,
-					432000, 540000 };
-
-static const uint32_t default_rates[] = { 162000, 270000, 540000 };
+static const int gen9_rates[] = { 162000, 216000, 270000,
+				  324000, 432000, 540000 };
+static const int default_rates[] = { 162000, 270000, 540000 };
 
 /**
  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
@@ -1139,7 +1138,7 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
 }
 
 static int
-intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
+intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	int i = 0;
@@ -1166,7 +1165,7 @@ intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
 }
 
 static int
-intel_read_source_rates(struct intel_dp *intel_dp, uint32_t *source_rates)
+intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	int i;
@@ -1217,8 +1216,9 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 	}
 }
 
-static int intel_supported_rates(const uint32_t *source_rates, int source_len,
-const uint32_t *sink_rates, int sink_len, uint32_t *supported_rates)
+static int intel_supported_rates(const int *source_rates, int source_len,
+				 const int *sink_rates, int sink_len,
+				 int *supported_rates)
 {
 	int i = 0, j = 0, k = 0;
 
@@ -1245,7 +1245,7 @@ const uint32_t *sink_rates, int sink_len, uint32_t *supported_rates)
 	return k;
 }
 
-static int rate_to_index(uint32_t find, const uint32_t *rates)
+static int rate_to_index(int find, const int *rates)
 {
 	int i = 0;
 
@@ -1275,9 +1275,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int max_clock;
 	int bpp, mode_rate;
 	int link_avail, link_clock;
-	uint32_t sink_rates[8];
-	uint32_t supported_rates[8] = {0};
-	uint32_t source_rates[8];
+	int sink_rates[8];
+	int supported_rates[8] = {0};
+	int source_rates[8];
 	int source_len, sink_len, supported_len;
 
 	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
-- 
2.0.5

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[PATCH 02/13] drm/i915: Store the converted link rates in intel_dp->supported_rates[]

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No point in converting from hardware format every single time, just
store the rates in the final format under intel_dp.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 33 +++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_drv.h |  3 ++-
 2 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1fa8cc1..d638f5e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1141,8 +1141,6 @@ static int
 intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	int i = 0;
-	uint16_t val;
 
 	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
 		/*
@@ -1150,18 +1148,12 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
 		 * link rate table method, so read link rates from
 		 * supported_link_rates
 		 */
-		for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {
-			val = le16_to_cpu(intel_dp->supported_rates[i]);
-			if (val == 0)
-				break;
-
-			sink_rates[i] = val * 200;
-		}
+		memcpy(sink_rates, intel_dp->supported_rates,
+		       sizeof(intel_dp->supported_rates));
 
-		if (i <= 0)
-			DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
+		return intel_dp->num_supported_rates;
 	}
-	return i;
+	return 0;
 }
 
 static int
@@ -3751,10 +3743,23 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
 	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
 	    (rev >= 0x03)) { /* eDp v1.4 or higher */
+		__le16 supported_rates[DP_MAX_SUPPORTED_RATES];
+		int i;
+
 		intel_dp_dpcd_read_wake(&intel_dp->aux,
 				DP_SUPPORTED_LINK_RATES,
-				intel_dp->supported_rates,
-				sizeof(intel_dp->supported_rates));
+				supported_rates,
+				sizeof(supported_rates));
+
+		for (i = 0; i < ARRAY_SIZE(supported_rates); i++) {
+			int val = le16_to_cpu(supported_rates[i]);
+
+			if (val == 0)
+				break;
+
+			intel_dp->supported_rates[i] = val * 200;
+		}
+		intel_dp->num_supported_rates = i;
 	}
 	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 	      DP_DWN_STRM_PORT_PRESENT))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c77128c..69c8437 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -627,7 +627,8 @@ struct intel_dp {
 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
-	__le16 supported_rates[DP_MAX_SUPPORTED_RATES];
+	uint8_t num_supported_rates;
+	int supported_rates[DP_MAX_SUPPORTED_RATES];
 	struct drm_dp_aux aux;
 	uint8_t train_set[4];
 	int panel_power_up_delay;
-- 
2.0.5

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[PATCH 03/13] drm/i915: Don't copy the DP source rates arrays

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The source rates don't change, so we can just point the caller at the
const arrays.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d638f5e..537f1d0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1157,22 +1157,18 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
 }
 
 static int
-intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
+intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	int i;
-	int max_default_rate;
 
-	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
-		for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
-			source_rates[i] = gen9_rates[i];
-	} else {
-		/* Index of the max_link_bw supported + 1 */
-		max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
-		for (i = 0; i < max_default_rate; ++i)
-			source_rates[i] = default_rates[i];
+	if (INTEL_INFO(dev)->gen >= 9) {
+		*source_rates = gen9_rates;
+		return ARRAY_SIZE(gen9_rates);
 	}
-	return i;
+
+	*source_rates = default_rates;
+
+	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
 }
 
 static void
@@ -1269,12 +1265,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int link_avail, link_clock;
 	int sink_rates[8];
 	int supported_rates[8] = {0};
-	int source_rates[8];
+	const int *source_rates;
 	int source_len, sink_len, supported_len;
 
 	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
 
-	source_len = intel_read_source_rates(intel_dp, source_rates);
+	source_len = intel_dp_source_rates(intel_dp, &source_rates);
 
 	supported_len = intel_supported_rates(source_rates, source_len,
 				sink_rates, sink_len, supported_rates);
-- 
2.0.5

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[PATCH 04/13] drm/i915: Don't copy sink rates either

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Once we've read the rates from the sink we don't have to mess with them,
so the caller can just look at the stored rates without doing extra
copies. If the sink doesn't support the new link rate stuff, we just
point the caller at the default_rates[] array.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 24 +++++++++---------------
 1 file changed, 9 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 537f1d0..d6098a0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1138,22 +1138,16 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
 }
 
 static int
-intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
+intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 {
-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-
-	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
-		/*
-		 * Receiver supports only main-link rate selection by
-		 * link rate table method, so read link rates from
-		 * supported_link_rates
-		 */
-		memcpy(sink_rates, intel_dp->supported_rates,
-		       sizeof(intel_dp->supported_rates));
-
+	if (intel_dp->num_supported_rates) {
+		*sink_rates = intel_dp->supported_rates;
 		return intel_dp->num_supported_rates;
 	}
-	return 0;
+
+	*sink_rates = default_rates;
+
+	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
 }
 
 static int
@@ -1263,12 +1257,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int max_clock;
 	int bpp, mode_rate;
 	int link_avail, link_clock;
-	int sink_rates[8];
+	const int *sink_rates;
 	int supported_rates[8] = {0};
 	const int *source_rates;
 	int source_len, sink_len, supported_len;
 
-	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
+	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
 
 	source_len = intel_dp_source_rates(intel_dp, &source_rates);
 
-- 
2.0.5

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[PATCH 05/13] drm/i915: Remove special case from intel_supported_rates()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that both source and sink rates are always filled in there's no need
for any special cases in intel_supported_rates().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d6098a0..aa373a2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1204,14 +1204,6 @@ static int intel_supported_rates(const int *source_rates, int source_len,
 {
 	int i = 0, j = 0, k = 0;
 
-	/* For panels with edp version less than 1.4 */
-	if (sink_len == 0) {
-		for (i = 0; i < source_len; ++i)
-			supported_rates[i] = source_rates[i];
-		return source_len;
-	}
-
-	/* For edp1.4 panels, find the common rates between source and sink */
 	while (i < source_len && j < sink_len) {
 		if (source_rates[i] == sink_rates[j]) {
 			supported_rates[k] = source_rates[i];
-- 
2.0.5

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[PATCH 06/13] drm/i915: Fully separate source vs. sink rates

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Remove the sink vs. source limit mess from intel_dp_max_link_bw() and
just move the source restriction checks to intel_dp_source_rates().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aa373a2..61538f4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -126,19 +126,11 @@ int
 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 {
 	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
-	struct drm_device *dev = intel_dp->attached_connector->base.dev;
 
 	switch (max_link_bw) {
 	case DP_LINK_BW_1_62:
 	case DP_LINK_BW_2_7:
-		break;
-	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
-		     INTEL_INFO(dev)->gen >= 8) &&
-		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
-			max_link_bw = DP_LINK_BW_5_4;
-		else
-			max_link_bw = DP_LINK_BW_2_7;
+	case DP_LINK_BW_5_4:
 		break;
 	default:
 		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
@@ -1151,10 +1143,8 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 }
 
 static int
-intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
+intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-
 	if (INTEL_INFO(dev)->gen >= 9) {
 		*source_rates = gen9_rates;
 		return ARRAY_SIZE(gen9_rates);
@@ -1162,7 +1152,11 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
 
 	*source_rates = default_rates;
 
-	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
+	if (INTEL_INFO(dev)->gen >= 8 ||
+	    (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
+		return (DP_LINK_BW_5_4 >> 3) + 1;
+	else
+		return (DP_LINK_BW_2_7 >> 3) + 1;
 }
 
 static void
@@ -1256,7 +1250,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
 
-	source_len = intel_dp_source_rates(intel_dp, &source_rates);
+	source_len = intel_dp_source_rates(dev, &source_rates);
 
 	supported_len = intel_supported_rates(source_rates, source_len,
 				sink_rates, sink_len, supported_rates);
-- 
2.0.5

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[PATCH 07/13] drm/i915: Hide the source vs. sink rate handling from intel_dp_compute_config()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_dp_compute_config() only really needs to know the rates supported
by both source and sink, so hide the raw source and sink arrays from it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++--------------
 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 61538f4..a88f932 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1192,9 +1192,9 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 	}
 }
 
-static int intel_supported_rates(const int *source_rates, int source_len,
-				 const int *sink_rates, int sink_len,
-				 int *supported_rates)
+static int intersect_rates(const int *source_rates, int source_len,
+			   const int *sink_rates, int sink_len,
+			   int *supported_rates)
 {
 	int i = 0, j = 0, k = 0;
 
@@ -1213,6 +1213,21 @@ static int intel_supported_rates(const int *source_rates, int source_len,
 	return k;
 }
 
+static int intel_supported_rates(struct intel_dp *intel_dp,
+				 int *supported_rates)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	const int *source_rates, *sink_rates;
+	int source_len, sink_len;
+
+	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
+	source_len = intel_dp_source_rates(dev, &source_rates);
+
+	return intersect_rates(source_rates, source_len,
+			       sink_rates, sink_len,
+			       supported_rates);
+}
+
 static int rate_to_index(int find, const int *rates)
 {
 	int i = 0;
@@ -1243,17 +1258,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int max_clock;
 	int bpp, mode_rate;
 	int link_avail, link_clock;
-	const int *sink_rates;
-	int supported_rates[8] = {0};
-	const int *source_rates;
-	int source_len, sink_len, supported_len;
-
-	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
-
-	source_len = intel_dp_source_rates(dev, &source_rates);
+	int supported_rates[DP_MAX_SUPPORTED_RATES] = {};
+	int supported_len;
 
-	supported_len = intel_supported_rates(source_rates, source_len,
-				sink_rates, sink_len, supported_rates);
+	supported_len = intel_supported_rates(intel_dp, supported_rates);
 
 	/* No common link rates between source and sink */
 	WARN_ON(supported_len <= 0);
@@ -1352,7 +1360,8 @@ found:
 
 	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
 		intel_dp->rate_select =
-			rate_to_index(supported_rates[clock], sink_rates);
+			rate_to_index(supported_rates[clock],
+				      intel_dp->supported_rates);
 		intel_dp->link_bw = 0;
 	}
 
-- 
2.0.5

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[PATCH 08/13] drm/i915: Fix max link rate in intel_dp_mode_valid()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Consider the link rates reported by the sink via
DP_SUPPORTED_LINK_RATES when checking modes against the max link
rate.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 15 ++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a88f932..63c3ef4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -206,7 +206,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 		target_clock = fixed_mode->clock;
 	}
 
-	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
+	max_link_clock = intel_dp_max_link_rate(intel_dp);
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
@@ -1239,6 +1239,19 @@ static int rate_to_index(int find, const int *rates)
 	return i;
 }
 
+int
+intel_dp_max_link_rate(struct intel_dp *intel_dp)
+{
+	int rates[DP_MAX_SUPPORTED_RATES] = {};
+	int len;
+
+	len = intel_supported_rates(intel_dp, rates);
+	if (WARN_ON(len <= 0))
+		return 162000;
+
+	return rates[rate_to_index(0, rates) - 1];
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 69c8437..d5a1f1f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1062,6 +1062,7 @@ void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *co
 void intel_dp_mst_suspend(struct drm_device *dev);
 void intel_dp_mst_resume(struct drm_device *dev);
 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
+int intel_dp_max_link_rate(struct intel_dp *intel_dp);
 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
-- 
2.0.5

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[PATCH 09/13] drm/i915: Use DP_LINK_RATE_SET whenever possible

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Drop the gen9 checks from the code and issue DP_LINK_RATE_SET whenever
the sink reports to support it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 63c3ef4..28d9249 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1368,14 +1368,15 @@ found:
 
 	intel_dp->lane_count = lane_count;
 
-	intel_dp->link_bw =
-		drm_dp_link_rate_to_bw_code(supported_rates[clock]);
-
-	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
+	if (intel_dp->num_supported_rates) {
+		intel_dp->link_bw = 0;
 		intel_dp->rate_select =
 			rate_to_index(supported_rates[clock],
 				      intel_dp->supported_rates);
-		intel_dp->link_bw = 0;
+	} else {
+		intel_dp->link_bw =
+			drm_dp_link_rate_to_bw_code(supported_rates[clock]);
+		intel_dp->rate_select = 0;
 	}
 
 	pipe_config->pipe_bpp = bpp;
@@ -3489,7 +3490,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
-	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0])
+	if (intel_dp->num_supported_rates)
 		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 				&intel_dp->rate_select, 1);
 
-- 
2.0.5

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[PATCH 10/13] drm/i915: Fix MST link rate handling

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that intel_dp_max_link_bw() no longer considers the source
restrictions we may try to enable MST with 5.4GHz even when the source
doesn't support it. To fix that switch the code over to handle the link
rate in the same way as the SST code handles it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c     | 12 ++++++++----
 drivers/gpu/drm/i915/intel_dp_mst.c | 16 +++++++++++++---
 drivers/gpu/drm/i915/intel_drv.h    |  2 +-
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 28d9249..52376fd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -122,8 +122,8 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 static void vlv_steal_power_sequencer(struct drm_device *dev,
 				      enum pipe pipe);
 
-int
-intel_dp_max_link_bw(struct intel_dp *intel_dp)
+static int
+intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 {
 	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 
@@ -1252,6 +1252,11 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
 	return rates[rate_to_index(0, rates) - 1];
 }
 
+int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
+{
+	return rate_to_index(rate, intel_dp->supported_rates);
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config)
@@ -1371,8 +1376,7 @@ found:
 	if (intel_dp->num_supported_rates) {
 		intel_dp->link_bw = 0;
 		intel_dp->rate_select =
-			rate_to_index(supported_rates[clock],
-				      intel_dp->supported_rates);
+			intel_dp_rate_select(intel_dp, supported_rates[clock]);
 	} else {
 		intel_dp->link_bw =
 			drm_dp_link_rate_to_bw_code(supported_rates[clock]);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index be12492..7e6f1259 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -38,7 +38,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = &intel_dig_port->dp;
 	struct drm_device *dev = encoder->base.dev;
 	int bpp;
-	int lane_count, slots;
+	int lane_count, slots, rate;
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	struct intel_connector *found = NULL, *intel_connector;
 	int mst_pbn;
@@ -52,11 +52,21 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	 * seem to suggest we should do otherwise.
 	 */
 	lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
-	intel_dp->link_bw = intel_dp_max_link_bw(intel_dp);
+
+	rate = intel_dp_max_link_rate(intel_dp);
+
+	if (intel_dp->num_supported_rates) {
+		intel_dp->link_bw = 0;
+		intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
+	} else {
+		intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate);
+		intel_dp->rate_select = 0;
+	}
+
 	intel_dp->lane_count = lane_count;
 
 	pipe_config->pipe_bpp = 24;
-	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
+	pipe_config->port_clock = rate;
 
 	for_each_intel_connector(dev, intel_connector) {
 		if (intel_connector->new_encoder == encoder) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d5a1f1f..4174198 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1061,8 +1061,8 @@ void intel_edp_panel_off(struct intel_dp *intel_dp);
 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
 void intel_dp_mst_suspend(struct drm_device *dev);
 void intel_dp_mst_resume(struct drm_device *dev);
-int intel_dp_max_link_bw(struct intel_dp *intel_dp);
 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
+int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
-- 
2.0.5

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[PATCH 11/13] drm/i915: Avoid overflowing the DP link rate arrays

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Complain loudly if we ever attempt to overflow the the supported_rates[]
array. This should never happen since the sink_rates[] array will always
be smaller or of equal size. But should someone change that we want to
catch it without scribblign over the stack.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 52376fd..a088186 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1200,6 +1200,8 @@ static int intersect_rates(const int *source_rates, int source_len,
 
 	while (i < source_len && j < sink_len) {
 		if (source_rates[i] == sink_rates[j]) {
+			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
+				return k;
 			supported_rates[k] = source_rates[i];
 			++k;
 			++i;
-- 
2.0.5

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[PATCH 12/13] drm/i915: Add eDP intermediate frequencies for CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

"P1273_DPLL_Programming Spreadsheet.xlsm" lists a boatload of
frequencies for eDP. Try to use them all.

For now I've decided not to add hardcoded DPLL dividers for these cases
since chv_find_best_dpll() works just fine.

I've not actually tested any of these since I don't have an eDP 1.4 panel.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a088186..8392bd3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -87,6 +87,9 @@ static const struct dp_link_dpll chv_dpll[] = {
 /* Skylake supports following rates */
 static const int gen9_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
+static const int chv_rates[] = { 162000, 202500, 210000, 216000,
+				 243000, 270000, 324000, 405000,
+				 420000, 432000, 540000 };
 static const int default_rates[] = { 162000, 270000, 540000 };
 
 /**
@@ -1148,6 +1151,9 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 	if (INTEL_INFO(dev)->gen >= 9) {
 		*source_rates = gen9_rates;
 		return ARRAY_SIZE(gen9_rates);
+	} else if (IS_CHERRYVIEW(dev)) {
+		*source_rates = chv_rates;
+		return ARRAY_SIZE(chv_rates);
 	}
 
 	*source_rates = default_rates;
-- 
2.0.5

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[PATCH 13/13] drm/i915: Include the sink/source/supported rates in debug output

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

TODO: Is there an actually nice way to print an array of ints?

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 43 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8392bd3..715694a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1236,6 +1236,46 @@ static int intel_supported_rates(struct intel_dp *intel_dp,
 			       supported_rates);
 }
 
+static void snprintf_int_array(char *str, size_t len,
+			       const int *array, int nelem)
+{
+	int i;
+
+	str[0] = '\0';
+
+	for (i = 0; i < nelem; i++) {
+		int r = snprintf(str, len, "%d,", array[i]);
+		if (r >= len)
+			return;
+		str += r;
+		len -= r;
+	}
+}
+
+static void intel_dp_print_rates(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	const int *source_rates, *sink_rates;
+	int source_len, sink_len, supported_len;
+	int supported_rates[DP_MAX_SUPPORTED_RATES];
+	char str[128]; /* FIXME: too big for stack? */
+
+	if ((drm_debug & DRM_UT_KMS) == 0)
+		return;
+
+	source_len = intel_dp_source_rates(dev, &source_rates);
+	snprintf_int_array(str, sizeof(str), source_rates, source_len);
+	DRM_DEBUG_KMS("source rates: %s\n", str);
+
+	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
+	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
+	DRM_DEBUG_KMS("sink rates: %s\n", str);
+
+	supported_len = intel_supported_rates(intel_dp, supported_rates);
+	snprintf_int_array(str, sizeof(str), supported_rates, supported_len);
+	DRM_DEBUG_KMS("supported rates: %s\n", str);
+}
+
 static int rate_to_index(int find, const int *rates)
 {
 	int i = 0;
@@ -3772,6 +3812,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 		}
 		intel_dp->num_supported_rates = i;
 	}
+
+	intel_dp_print_rates(intel_dp);
+
 	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 	      DP_DWN_STRM_PORT_PRESENT))
 		return true; /* native DP sink */
-- 
2.0.5

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Re: [PATCH 13/13] drm/i915: Include the sink/source/supported rates in debug output

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5942
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -2              275/275              273/275
ILK                                  302/302              302/302
SNB                                  281/281              281/281
IVB                                  341/341              341/341
BYT                                  287/287              287/287
HSW                 -1              361/361              360/361
BDW                                  308/308              308/308
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gem_userptr_blits_minor-normal-sync      PASS(2)      DMESG_WARN(2)
*PNV  igt_gem_userptr_blits_minor-unsync-normal      PASS(4)      DMESG_WARN(2)
*HSW  igt_gem_storedw_loop_blt      PASS(2)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 07/13] drm/i915: Hide the source vs. sink rate handling from intel_dp_compute_config()

[sonika]

On Thursday 12 March 2015 08:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_dp_compute_config() only really needs to know the rates supported
> by both source and sink, so hide the raw source and sink arrays from it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++--------------
>   1 file changed, 23 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 61538f4..a88f932 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1192,9 +1192,9 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>   	}
>   }
>   
> -static int intel_supported_rates(const int *source_rates, int source_len,
> -				 const int *sink_rates, int sink_len,
> -				 int *supported_rates)
> +static int intersect_rates(const int *source_rates, int source_len,
> +			   const int *sink_rates, int sink_len,
> +			   int *supported_rates)
>   {
>   	int i = 0, j = 0, k = 0;
>   
> @@ -1213,6 +1213,21 @@ static int intel_supported_rates(const int *source_rates, int source_len,
>   	return k;
>   }
>   
> +static int intel_supported_rates(struct intel_dp *intel_dp,
> +				 int *supported_rates)
> +{
> +	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> +	const int *source_rates, *sink_rates;
> +	int source_len, sink_len;
> +
> +	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> +	source_len = intel_dp_source_rates(dev, &source_rates);
> +
> +	return intersect_rates(source_rates, source_len,
> +			       sink_rates, sink_len,
> +			       supported_rates);
> +}
> +
Now when I am looking at it, the name "supported_rates", sounds 
confusing. Because first we are using it for sink_rates in 
intel_dp->supported_rates
and then we use it to store the intersect_rates. Since sink_rates are 
termed supported_rates in the spec, can we remove the sink_rates altogether
and have source_rates, sink_supported_rates and common_rates (or 
something else ?)

-Sonika
>   static int rate_to_index(int find, const int *rates)
>   {
>   	int i = 0;
> @@ -1243,17 +1258,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   	int max_clock;
>   	int bpp, mode_rate;
>   	int link_avail, link_clock;
> -	const int *sink_rates;
> -	int supported_rates[8] = {0};
> -	const int *source_rates;
> -	int source_len, sink_len, supported_len;
> -
> -	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> -
> -	source_len = intel_dp_source_rates(dev, &source_rates);
> +	int supported_rates[DP_MAX_SUPPORTED_RATES] = {};
> +	int supported_len;
>   
> -	supported_len = intel_supported_rates(source_rates, source_len,
> -				sink_rates, sink_len, supported_rates);
> +	supported_len = intel_supported_rates(intel_dp, supported_rates);
>   
>   	/* No common link rates between source and sink */
>   	WARN_ON(supported_len <= 0);
> @@ -1352,7 +1360,8 @@ found:
>   
>   	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
>   		intel_dp->rate_select =
> -			rate_to_index(supported_rates[clock], sink_rates);
> +			rate_to_index(supported_rates[clock],
> +				      intel_dp->supported_rates);
>   		intel_dp->link_bw = 0;
>   	}
>   

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Re: [PATCH 07/13] drm/i915: Hide the source vs. sink rate handling from intel_dp_compute_config()

[sonika]

On Friday 13 March 2015 05:32 PM, Ville Syrjälä wrote:
> On Fri, Mar 13, 2015 at 05:14:59PM +0530, sonika wrote:
>> On Thursday 12 March 2015 08:40 PM, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> intel_dp_compute_config() only really needs to know the rates supported
>>> by both source and sink, so hide the raw source and sink arrays from it.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++--------------
>>>    1 file changed, 23 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>> index 61538f4..a88f932 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -1192,9 +1192,9 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>>>    	}
>>>    }
>>>    
>>> -static int intel_supported_rates(const int *source_rates, int source_len,
>>> -				 const int *sink_rates, int sink_len,
>>> -				 int *supported_rates)
>>> +static int intersect_rates(const int *source_rates, int source_len,
>>> +			   const int *sink_rates, int sink_len,
>>> +			   int *supported_rates)
>>>    {
>>>    	int i = 0, j = 0, k = 0;
>>>    
>>> @@ -1213,6 +1213,21 @@ static int intel_supported_rates(const int *source_rates, int source_len,
>>>    	return k;
>>>    }
>>>    
>>> +static int intel_supported_rates(struct intel_dp *intel_dp,
>>> +				 int *supported_rates)
>>> +{
>>> +	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>>> +	const int *source_rates, *sink_rates;
>>> +	int source_len, sink_len;
>>> +
>>> +	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
>>> +	source_len = intel_dp_source_rates(dev, &source_rates);
>>> +
>>> +	return intersect_rates(source_rates, source_len,
>>> +			       sink_rates, sink_len,
>>> +			       supported_rates);
>>> +}
>>> +
>> Now when I am looking at it, the name "supported_rates", sounds
>> confusing. Because first we are using it for sink_rates in
>> intel_dp->supported_rates
>> and then we use it to store the intersect_rates. Since sink_rates are
>> termed supported_rates in the spec, can we remove the sink_rates altogether
>> and have source_rates, sink_supported_rates and common_rates (or
>> something else ?)
> Hmm. Yeah. Maybe just rename to intel_dp->sink_rates? And common_rates
> would seem like a decent name for the intersection.
Sounds good.
>> -Sonika
>>>    static int rate_to_index(int find, const int *rates)
>>>    {
>>>    	int i = 0;
>>> @@ -1243,17 +1258,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>>    	int max_clock;
>>>    	int bpp, mode_rate;
>>>    	int link_avail, link_clock;
>>> -	const int *sink_rates;
>>> -	int supported_rates[8] = {0};
>>> -	const int *source_rates;
>>> -	int source_len, sink_len, supported_len;
>>> -
>>> -	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
>>> -
>>> -	source_len = intel_dp_source_rates(dev, &source_rates);
>>> +	int supported_rates[DP_MAX_SUPPORTED_RATES] = {};
>>> +	int supported_len;
>>>    
>>> -	supported_len = intel_supported_rates(source_rates, source_len,
>>> -				sink_rates, sink_len, supported_rates);
>>> +	supported_len = intel_supported_rates(intel_dp, supported_rates);
>>>    
>>>    	/* No common link rates between source and sink */
>>>    	WARN_ON(supported_len <= 0);
>>> @@ -1352,7 +1360,8 @@ found:
>>>    
>>>    	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
>>>    		intel_dp->rate_select =
>>> -			rate_to_index(supported_rates[clock], sink_rates);
>>> +			rate_to_index(supported_rates[clock],
>>> +				      intel_dp->supported_rates);
>>>    		intel_dp->link_bw = 0;
>>>    	}
>>>    

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Re: [PATCH 07/13] drm/i915: Hide the source vs. sink rate handling from intel_dp_compute_config()

[Ville Syrjälä]

On Fri, Mar 13, 2015 at 05:14:59PM +0530, sonika wrote:
> 
> On Thursday 12 March 2015 08:40 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > intel_dp_compute_config() only really needs to know the rates supported
> > by both source and sink, so hide the raw source and sink arrays from it.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++--------------
> >   1 file changed, 23 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 61538f4..a88f932 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1192,9 +1192,9 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> >   	}
> >   }
> >   
> > -static int intel_supported_rates(const int *source_rates, int source_len,
> > -				 const int *sink_rates, int sink_len,
> > -				 int *supported_rates)
> > +static int intersect_rates(const int *source_rates, int source_len,
> > +			   const int *sink_rates, int sink_len,
> > +			   int *supported_rates)
> >   {
> >   	int i = 0, j = 0, k = 0;
> >   
> > @@ -1213,6 +1213,21 @@ static int intel_supported_rates(const int *source_rates, int source_len,
> >   	return k;
> >   }
> >   
> > +static int intel_supported_rates(struct intel_dp *intel_dp,
> > +				 int *supported_rates)
> > +{
> > +	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > +	const int *source_rates, *sink_rates;
> > +	int source_len, sink_len;
> > +
> > +	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> > +	source_len = intel_dp_source_rates(dev, &source_rates);
> > +
> > +	return intersect_rates(source_rates, source_len,
> > +			       sink_rates, sink_len,
> > +			       supported_rates);
> > +}
> > +
> Now when I am looking at it, the name "supported_rates", sounds 
> confusing. Because first we are using it for sink_rates in 
> intel_dp->supported_rates
> and then we use it to store the intersect_rates. Since sink_rates are 
> termed supported_rates in the spec, can we remove the sink_rates altogether
> and have source_rates, sink_supported_rates and common_rates (or 
> something else ?)

Hmm. Yeah. Maybe just rename to intel_dp->sink_rates? And common_rates
would seem like a decent name for the intersection.

> 
> -Sonika
> >   static int rate_to_index(int find, const int *rates)
> >   {
> >   	int i = 0;
> > @@ -1243,17 +1258,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >   	int max_clock;
> >   	int bpp, mode_rate;
> >   	int link_avail, link_clock;
> > -	const int *sink_rates;
> > -	int supported_rates[8] = {0};
> > -	const int *source_rates;
> > -	int source_len, sink_len, supported_len;
> > -
> > -	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> > -
> > -	source_len = intel_dp_source_rates(dev, &source_rates);
> > +	int supported_rates[DP_MAX_SUPPORTED_RATES] = {};
> > +	int supported_len;
> >   
> > -	supported_len = intel_supported_rates(source_rates, source_len,
> > -				sink_rates, sink_len, supported_rates);
> > +	supported_len = intel_supported_rates(intel_dp, supported_rates);
> >   
> >   	/* No common link rates between source and sink */
> >   	WARN_ON(supported_len <= 0);
> > @@ -1352,7 +1360,8 @@ found:
> >   
> >   	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> >   		intel_dp->rate_select =
> > -			rate_to_index(supported_rates[clock], sink_rates);
> > +			rate_to_index(supported_rates[clock],
> > +				      intel_dp->supported_rates);
> >   		intel_dp->link_bw = 0;
> >   	}
> >   

-- 
Ville Syrjälä
Intel OTC
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[PATCH 14/13] drm/i915: Unconfuse DP link rate array names

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To keep things clear rename the intel_dp->supported_rates[] to
intel_dp->sink_rates[], and rename the supported_rates[] name we used
elsewhere for the intersection of source and sink rates to
common_rates[].

Cc: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c     | 70 ++++++++++++++++++-------------------
 drivers/gpu/drm/i915/intel_dp_mst.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h    |  5 +--
 3 files changed, 39 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 715694a..393feed 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1135,9 +1135,9 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
 static int
 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 {
-	if (intel_dp->num_supported_rates) {
-		*sink_rates = intel_dp->supported_rates;
-		return intel_dp->num_supported_rates;
+	if (intel_dp->num_sink_rates) {
+		*sink_rates = intel_dp->sink_rates;
+		return intel_dp->num_sink_rates;
 	}
 
 	*sink_rates = default_rates;
@@ -1200,7 +1200,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 
 static int intersect_rates(const int *source_rates, int source_len,
 			   const int *sink_rates, int sink_len,
-			   int *supported_rates)
+			   int *common_rates)
 {
 	int i = 0, j = 0, k = 0;
 
@@ -1208,7 +1208,7 @@ static int intersect_rates(const int *source_rates, int source_len,
 		if (source_rates[i] == sink_rates[j]) {
 			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 				return k;
-			supported_rates[k] = source_rates[i];
+			common_rates[k] = source_rates[i];
 			++k;
 			++i;
 			++j;
@@ -1221,8 +1221,8 @@ static int intersect_rates(const int *source_rates, int source_len,
 	return k;
 }
 
-static int intel_supported_rates(struct intel_dp *intel_dp,
-				 int *supported_rates)
+static int intel_dp_common_rates(struct intel_dp *intel_dp,
+				 int *common_rates)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	const int *source_rates, *sink_rates;
@@ -1233,7 +1233,7 @@ static int intel_supported_rates(struct intel_dp *intel_dp,
 
 	return intersect_rates(source_rates, source_len,
 			       sink_rates, sink_len,
-			       supported_rates);
+			       common_rates);
 }
 
 static void snprintf_int_array(char *str, size_t len,
@@ -1256,8 +1256,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	const int *source_rates, *sink_rates;
-	int source_len, sink_len, supported_len;
-	int supported_rates[DP_MAX_SUPPORTED_RATES];
+	int source_len, sink_len, common_len;
+	int common_rates[DP_MAX_SUPPORTED_RATES];
 	char str[128]; /* FIXME: too big for stack? */
 
 	if ((drm_debug & DRM_UT_KMS) == 0)
@@ -1271,9 +1271,9 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
 	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
 	DRM_DEBUG_KMS("sink rates: %s\n", str);
 
-	supported_len = intel_supported_rates(intel_dp, supported_rates);
-	snprintf_int_array(str, sizeof(str), supported_rates, supported_len);
-	DRM_DEBUG_KMS("supported rates: %s\n", str);
+	common_len = intel_dp_common_rates(intel_dp, common_rates);
+	snprintf_int_array(str, sizeof(str), common_rates, common_len);
+	DRM_DEBUG_KMS("common rates: %s\n", str);
 }
 
 static int rate_to_index(int find, const int *rates)
@@ -1293,7 +1293,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
 	int rates[DP_MAX_SUPPORTED_RATES] = {};
 	int len;
 
-	len = intel_supported_rates(intel_dp, rates);
+	len = intel_dp_common_rates(intel_dp, rates);
 	if (WARN_ON(len <= 0))
 		return 162000;
 
@@ -1302,7 +1302,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
 
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 {
-	return rate_to_index(rate, intel_dp->supported_rates);
+	return rate_to_index(rate, intel_dp->sink_rates);
 }
 
 bool
@@ -1324,15 +1324,15 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int max_clock;
 	int bpp, mode_rate;
 	int link_avail, link_clock;
-	int supported_rates[DP_MAX_SUPPORTED_RATES] = {};
-	int supported_len;
+	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
+	int common_len;
 
-	supported_len = intel_supported_rates(intel_dp, supported_rates);
+	common_len = intel_dp_common_rates(intel_dp, common_rates);
 
 	/* No common link rates between source and sink */
-	WARN_ON(supported_len <= 0);
+	WARN_ON(common_len <= 0);
 
-	max_clock = supported_len - 1;
+	max_clock = common_len - 1;
 
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 		pipe_config->has_pch_encoder = true;
@@ -1357,7 +1357,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	DRM_DEBUG_KMS("DP link computation with max lane count %i "
 		      "max bw %d pixel clock %iKHz\n",
-		      max_lane_count, supported_rates[max_clock],
+		      max_lane_count, common_rates[max_clock],
 		      adjusted_mode->crtc_clock);
 
 	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
@@ -1390,7 +1390,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 				lane_count <= max_lane_count;
 				lane_count <<= 1) {
 
-				link_clock = supported_rates[clock];
+				link_clock = common_rates[clock];
 				link_avail = intel_dp_max_data_rate(link_clock,
 								    lane_count);
 
@@ -1421,18 +1421,18 @@ found:
 
 	intel_dp->lane_count = lane_count;
 
-	if (intel_dp->num_supported_rates) {
+	if (intel_dp->num_sink_rates) {
 		intel_dp->link_bw = 0;
 		intel_dp->rate_select =
-			intel_dp_rate_select(intel_dp, supported_rates[clock]);
+			intel_dp_rate_select(intel_dp, common_rates[clock]);
 	} else {
 		intel_dp->link_bw =
-			drm_dp_link_rate_to_bw_code(supported_rates[clock]);
+			drm_dp_link_rate_to_bw_code(common_rates[clock]);
 		intel_dp->rate_select = 0;
 	}
 
 	pipe_config->pipe_bpp = bpp;
-	pipe_config->port_clock = supported_rates[clock];
+	pipe_config->port_clock = common_rates[clock];
 
 	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 		      intel_dp->link_bw, intel_dp->lane_count,
@@ -1455,7 +1455,7 @@ found:
 	}
 
 	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
-		skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
+		skl_edp_set_pll_config(pipe_config, common_rates[clock]);
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
 	else
@@ -3542,7 +3542,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
-	if (intel_dp->num_supported_rates)
+	if (intel_dp->num_sink_rates)
 		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 				&intel_dp->rate_select, 1);
 
@@ -3794,23 +3794,23 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
 	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
 	    (rev >= 0x03)) { /* eDp v1.4 or higher */
-		__le16 supported_rates[DP_MAX_SUPPORTED_RATES];
+		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 		int i;
 
 		intel_dp_dpcd_read_wake(&intel_dp->aux,
 				DP_SUPPORTED_LINK_RATES,
-				supported_rates,
-				sizeof(supported_rates));
+				sink_rates,
+				sizeof(sink_rates));
 
-		for (i = 0; i < ARRAY_SIZE(supported_rates); i++) {
-			int val = le16_to_cpu(supported_rates[i]);
+		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
+			int val = le16_to_cpu(sink_rates[i]);
 
 			if (val == 0)
 				break;
 
-			intel_dp->supported_rates[i] = val * 200;
+			intel_dp->sink_rates[i] = val * 200;
 		}
-		intel_dp->num_supported_rates = i;
+		intel_dp->num_sink_rates = i;
 	}
 
 	intel_dp_print_rates(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 7e6f1259..971163e 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -55,7 +55,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 
 	rate = intel_dp_max_link_rate(intel_dp);
 
-	if (intel_dp->num_supported_rates) {
+	if (intel_dp->num_sink_rates) {
 		intel_dp->link_bw = 0;
 		intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4174198..a1baaa1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -627,8 +627,9 @@ struct intel_dp {
 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
-	uint8_t num_supported_rates;
-	int supported_rates[DP_MAX_SUPPORTED_RATES];
+	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
+	uint8_t num_sink_rates;
+	int sink_rates[DP_MAX_SUPPORTED_RATES];
 	struct drm_dp_aux aux;
 	uint8_t train_set[4];
 	int panel_power_up_delay;
-- 
2.0.5

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Re: [PATCH 01/13] drm/i915: Make the DP rates int instead of uint32_t

[Todd Previte]

On 3/12/2015 8:10 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No point in using uint32_t here, just plain old int will do.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++------------
>   1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 33d5877..1fa8cc1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -85,10 +85,9 @@ static const struct dp_link_dpll chv_dpll[] = {
>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>   };
>   /* Skylake supports following rates */
> -static const uint32_t gen9_rates[] = { 162000, 216000, 270000, 324000,
> -					432000, 540000 };
> -
> -static const uint32_t default_rates[] = { 162000, 270000, 540000 };
> +static const int gen9_rates[] = { 162000, 216000, 270000,
> +				  324000, 432000, 540000 };
> +static const int default_rates[] = { 162000, 270000, 540000 };
>   
>   /**
>    * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
> @@ -1139,7 +1138,7 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
>   }
>   
>   static int
> -intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
> +intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
>   {
>   	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>   	int i = 0;
> @@ -1166,7 +1165,7 @@ intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
>   }
>   
>   static int
> -intel_read_source_rates(struct intel_dp *intel_dp, uint32_t *source_rates)
> +intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
>   {
>   	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>   	int i;
> @@ -1217,8 +1216,9 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>   	}
>   }
>   
> -static int intel_supported_rates(const uint32_t *source_rates, int source_len,
> -const uint32_t *sink_rates, int sink_len, uint32_t *supported_rates)
> +static int intel_supported_rates(const int *source_rates, int source_len,
> +				 const int *sink_rates, int sink_len,
> +				 int *supported_rates)
>   {
>   	int i = 0, j = 0, k = 0;
>   
> @@ -1245,7 +1245,7 @@ const uint32_t *sink_rates, int sink_len, uint32_t *supported_rates)
>   	return k;
>   }
>   
> -static int rate_to_index(uint32_t find, const uint32_t *rates)
> +static int rate_to_index(int find, const int *rates)
>   {
>   	int i = 0;
>   
> @@ -1275,9 +1275,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   	int max_clock;
>   	int bpp, mode_rate;
>   	int link_avail, link_clock;
> -	uint32_t sink_rates[8];
> -	uint32_t supported_rates[8] = {0};
> -	uint32_t source_rates[8];
> +	int sink_rates[8];
> +	int supported_rates[8] = {0};
> +	int source_rates[8];
>   	int source_len, sink_len, supported_len;
>   
>   	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
Since you're going through the work to redo all the link rates, does it 
make more sense to have the numerical rates defined in an enum then 
referenced by enumerated type in the arrays? Functionally it really 
won't make any difference but it might make it easier to understand 
which platforms support which rates at a glance. Certainly not a 
blocking request, just a thought.

Otherwise this looks fine.

Reviewed-by: Todd Previte <tprevite@gmail.com>
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Re: [PATCH 02/13] drm/i915: Store the converted link rates in intel_dp->supported_rates[]

[Todd Previte]

On 3/12/2015 8:10 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No point in converting from hardware format every single time, just
> store the rates in the final format under intel_dp.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c  | 33 +++++++++++++++++++--------------
>   drivers/gpu/drm/i915/intel_drv.h |  3 ++-
>   2 files changed, 21 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1fa8cc1..d638f5e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1141,8 +1141,6 @@ static int
>   intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
>   {
>   	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> -	int i = 0;
> -	uint16_t val;
>   
>   	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
>   		/*
> @@ -1150,18 +1148,12 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
>   		 * link rate table method, so read link rates from
>   		 * supported_link_rates
>   		 */
> -		for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {
> -			val = le16_to_cpu(intel_dp->supported_rates[i]);
> -			if (val == 0)
> -				break;
> -
> -			sink_rates[i] = val * 200;
> -		}
> +		memcpy(sink_rates, intel_dp->supported_rates,
> +		       sizeof(intel_dp->supported_rates));
>   
> -		if (i <= 0)
> -			DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
> +		return intel_dp->num_supported_rates;
>   	}
> -	return i;
> +	return 0;
>   }
>   
>   static int
> @@ -3751,10 +3743,23 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>   	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
>   	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
>   	    (rev >= 0x03)) { /* eDp v1.4 or higher */
> +		__le16 supported_rates[DP_MAX_SUPPORTED_RATES];
> +		int i;
> +
>   		intel_dp_dpcd_read_wake(&intel_dp->aux,
>   				DP_SUPPORTED_LINK_RATES,
> -				intel_dp->supported_rates,
> -				sizeof(intel_dp->supported_rates));
> +				supported_rates,
> +				sizeof(supported_rates));
> +
> +		for (i = 0; i < ARRAY_SIZE(supported_rates); i++) {
> +			int val = le16_to_cpu(supported_rates[i]);
> +
> +			if (val == 0)
> +				break;
> +
> +			intel_dp->supported_rates[i] = val * 200;
> +		}
> +		intel_dp->num_supported_rates = i;
>   	}
>   	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
>   	      DP_DWN_STRM_PORT_PRESENT))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c77128c..69c8437 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -627,7 +627,8 @@ struct intel_dp {
>   	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
>   	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>   	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> -	__le16 supported_rates[DP_MAX_SUPPORTED_RATES];
> +	uint8_t num_supported_rates;
> +	int supported_rates[DP_MAX_SUPPORTED_RATES];
>   	struct drm_dp_aux aux;
>   	uint8_t train_set[4];
>   	int panel_power_up_delay;
The code looks good from here. Only thing to double check is where 
intel_read_sink_rates() is called and make sure it's now expecting 0 as 
a success case.

Reviewed-by: Todd Previte <tprevite@gmail.com>

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Re: [PATCH 03/13] drm/i915: Don't copy the DP source rates arrays

[Todd Previte]

On 3/12/2015 8:10 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The source rates don't change, so we can just point the caller at the
> const arrays.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++--------------
>   1 file changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d638f5e..537f1d0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1157,22 +1157,18 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
>   }
>   
>   static int
> -intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
> +intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
>   {
>   	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> -	int i;
> -	int max_default_rate;
>   
> -	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> -		for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
> -			source_rates[i] = gen9_rates[i];
> -	} else {
> -		/* Index of the max_link_bw supported + 1 */
> -		max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> -		for (i = 0; i < max_default_rate; ++i)
> -			source_rates[i] = default_rates[i];
> +	if (INTEL_INFO(dev)->gen >= 9) {
> +		*source_rates = gen9_rates;
> +		return ARRAY_SIZE(gen9_rates);
>   	}
> -	return i;
> +
> +	*source_rates = default_rates;
> +
> +	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
>   }
>   
>   static void
> @@ -1269,12 +1265,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   	int link_avail, link_clock;
>   	int sink_rates[8];
>   	int supported_rates[8] = {0};
> -	int source_rates[8];
> +	const int *source_rates;
>   	int source_len, sink_len, supported_len;
>   
>   	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
>   
> -	source_len = intel_read_source_rates(intel_dp, source_rates);
> +	source_len = intel_dp_source_rates(intel_dp, &source_rates);
>   
>   	supported_len = intel_supported_rates(source_rates, source_len,
>   				sink_rates, sink_len, supported_rates);
Looks like it's good to go.

Reviewed-by: Todd Previte <tprevite@gmail.com>

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Re: [PATCH 03/13] drm/i915: Don't copy the DP source rates arrays

[Jindal, Sonika]

On 3/12/2015 8:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The source rates don't change, so we can just point the caller at the
> const arrays.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++--------------
>   1 file changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d638f5e..537f1d0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1157,22 +1157,18 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
>   }
>
>   static int
> -intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
> +intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
>   {
>   	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> -	int i;
> -	int max_default_rate;
>
> -	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> -		for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
> -			source_rates[i] = gen9_rates[i];
> -	} else {
> -		/* Index of the max_link_bw supported + 1 */
> -		max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> -		for (i = 0; i < max_default_rate; ++i)
> -			source_rates[i] = default_rates[i];
> +	if (INTEL_INFO(dev)->gen >= 9) {
> +		*source_rates = gen9_rates;
> +		return ARRAY_SIZE(gen9_rates);
>   	}
> -	return i;
> +
> +	*source_rates = default_rates;
> +
> +	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
Now when intel_dp_max_link_bw doesn't do much, can this be simply 
ARRAY_SIZE(default_rates)? and we can get away with this function.
>   }
>
>   static void
> @@ -1269,12 +1265,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   	int link_avail, link_clock;
>   	int sink_rates[8];
>   	int supported_rates[8] = {0};
> -	int source_rates[8];
> +	const int *source_rates;
>   	int source_len, sink_len, supported_len;
>
>   	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
>
> -	source_len = intel_read_source_rates(intel_dp, source_rates);
> +	source_len = intel_dp_source_rates(intel_dp, &source_rates);
>
>   	supported_len = intel_supported_rates(source_rates, source_len,
>   				sink_rates, sink_len, supported_rates);
>
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Re: [PATCH 03/13] drm/i915: Don't copy the DP source rates arrays

[Ville Syrjälä]

On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika wrote:
> 
> 
> On 3/12/2015 8:40 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The source rates don't change, so we can just point the caller at the
> > const arrays.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++--------------
> >   1 file changed, 10 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index d638f5e..537f1d0 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1157,22 +1157,18 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
> >   }
> >
> >   static int
> > -intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
> > +intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
> >   {
> >   	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > -	int i;
> > -	int max_default_rate;
> >
> > -	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> > -		for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
> > -			source_rates[i] = gen9_rates[i];
> > -	} else {
> > -		/* Index of the max_link_bw supported + 1 */
> > -		max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> > -		for (i = 0; i < max_default_rate; ++i)
> > -			source_rates[i] = default_rates[i];
> > +	if (INTEL_INFO(dev)->gen >= 9) {
> > +		*source_rates = gen9_rates;
> > +		return ARRAY_SIZE(gen9_rates);
> >   	}
> > -	return i;
> > +
> > +	*source_rates = default_rates;
> > +
> > +	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> Now when intel_dp_max_link_bw doesn't do much, can this be simply 
> ARRAY_SIZE(default_rates)? and we can get away with this function.

If you'll look at patch 6 you'll see me moving the source limitations 
from intel_dp_max_link_bw() to intel_dp_source_rates().

> >   }
> >
> >   static void
> > @@ -1269,12 +1265,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >   	int link_avail, link_clock;
> >   	int sink_rates[8];
> >   	int supported_rates[8] = {0};
> > -	int source_rates[8];
> > +	const int *source_rates;
> >   	int source_len, sink_len, supported_len;
> >
> >   	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
> >
> > -	source_len = intel_read_source_rates(intel_dp, source_rates);
> > +	source_len = intel_dp_source_rates(intel_dp, &source_rates);
> >
> >   	supported_len = intel_supported_rates(source_rates, source_len,
> >   				sink_rates, sink_len, supported_rates);
> >

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 03/13] drm/i915: Don't copy the DP source rates arrays

[Jindal, Sonika]

On 3/16/2015 3:04 PM, Ville Syrjälä wrote:
> On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika wrote:
>>
>>
>> On 3/12/2015 8:40 PM, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> The source rates don't change, so we can just point the caller at the
>>> const arrays.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++--------------
>>>    1 file changed, 10 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>> index d638f5e..537f1d0 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -1157,22 +1157,18 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
>>>    }
>>>
>>>    static int
>>> -intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
>>> +intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
>>>    {
>>>    	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>>> -	int i;
>>> -	int max_default_rate;
>>>
>>> -	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
>>> -		for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
>>> -			source_rates[i] = gen9_rates[i];
>>> -	} else {
>>> -		/* Index of the max_link_bw supported + 1 */
>>> -		max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
>>> -		for (i = 0; i < max_default_rate; ++i)
>>> -			source_rates[i] = default_rates[i];
>>> +	if (INTEL_INFO(dev)->gen >= 9) {
>>> +		*source_rates = gen9_rates;
>>> +		return ARRAY_SIZE(gen9_rates);
>>>    	}
>>> -	return i;
>>> +
>>> +	*source_rates = default_rates;
>>> +
>>> +	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
>> Now when intel_dp_max_link_bw doesn't do much, can this be simply
>> ARRAY_SIZE(default_rates)? and we can get away with this function.
>
> If you'll look at patch 6 you'll see me moving the source limitations
> from intel_dp_max_link_bw() to intel_dp_source_rates().
>
Yes, thats why I think we can remove the intel_dp_max_link_bw function 
altogether.
>>>    }
>>>
>>>    static void
>>> @@ -1269,12 +1265,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>>    	int link_avail, link_clock;
>>>    	int sink_rates[8];
>>>    	int supported_rates[8] = {0};
>>> -	int source_rates[8];
>>> +	const int *source_rates;
>>>    	int source_len, sink_len, supported_len;
>>>
>>>    	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
>>>
>>> -	source_len = intel_read_source_rates(intel_dp, source_rates);
>>> +	source_len = intel_dp_source_rates(intel_dp, &source_rates);
>>>
>>>    	supported_len = intel_supported_rates(source_rates, source_len,
>>>    				sink_rates, sink_len, supported_rates);
>>>
>
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Re: [PATCH 03/13] drm/i915: Don't copy the DP source rates arrays

[Ville Syrjälä]

On Mon, Mar 16, 2015 at 03:07:05PM +0530, Jindal, Sonika wrote:
> 
> 
> On 3/16/2015 3:04 PM, Ville Syrjälä wrote:
> > On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika wrote:
> >>
> >>
> >> On 3/12/2015 8:40 PM, ville.syrjala@linux.intel.com wrote:
> >>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>
> >>> The source rates don't change, so we can just point the caller at the
> >>> const arrays.
> >>>
> >>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++--------------
> >>>    1 file changed, 10 insertions(+), 14 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >>> index d638f5e..537f1d0 100644
> >>> --- a/drivers/gpu/drm/i915/intel_dp.c
> >>> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >>> @@ -1157,22 +1157,18 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
> >>>    }
> >>>
> >>>    static int
> >>> -intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
> >>> +intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
> >>>    {
> >>>    	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> >>> -	int i;
> >>> -	int max_default_rate;
> >>>
> >>> -	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> >>> -		for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
> >>> -			source_rates[i] = gen9_rates[i];
> >>> -	} else {
> >>> -		/* Index of the max_link_bw supported + 1 */
> >>> -		max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> >>> -		for (i = 0; i < max_default_rate; ++i)
> >>> -			source_rates[i] = default_rates[i];
> >>> +	if (INTEL_INFO(dev)->gen >= 9) {
> >>> +		*source_rates = gen9_rates;
> >>> +		return ARRAY_SIZE(gen9_rates);
> >>>    	}
> >>> -	return i;
> >>> +
> >>> +	*source_rates = default_rates;
> >>> +
> >>> +	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> >> Now when intel_dp_max_link_bw doesn't do much, can this be simply
> >> ARRAY_SIZE(default_rates)? and we can get away with this function.
> >
> > If you'll look at patch 6 you'll see me moving the source limitations
> > from intel_dp_max_link_bw() to intel_dp_source_rates().
> >
> Yes, thats why I think we can remove the intel_dp_max_link_bw function 
> altogether.

We still need it to limit the sink rates appropriately when
SUPPORTED_LINK_RATES is not present.

> >>>    }
> >>>
> >>>    static void
> >>> @@ -1269,12 +1265,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >>>    	int link_avail, link_clock;
> >>>    	int sink_rates[8];
> >>>    	int supported_rates[8] = {0};
> >>> -	int source_rates[8];
> >>> +	const int *source_rates;
> >>>    	int source_len, sink_len, supported_len;
> >>>
> >>>    	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
> >>>
> >>> -	source_len = intel_read_source_rates(intel_dp, source_rates);
> >>> +	source_len = intel_dp_source_rates(intel_dp, &source_rates);
> >>>
> >>>    	supported_len = intel_supported_rates(source_rates, source_len,
> >>>    				sink_rates, sink_len, supported_rates);
> >>>
> >

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 03/13] drm/i915: Don't copy the DP source rates arrays

[sonika]

On Monday 16 March 2015 04:25 PM, Ville Syrjälä wrote:
> On Mon, Mar 16, 2015 at 03:07:05PM +0530, Jindal, Sonika wrote:
>>
>> On 3/16/2015 3:04 PM, Ville Syrjälä wrote:
>>> On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika wrote:
>>>>
>>>> On 3/12/2015 8:40 PM, ville.syrjala@linux.intel.com wrote:
>>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>>
>>>>> The source rates don't change, so we can just point the caller at the
>>>>> const arrays.
>>>>>
>>>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>> ---
>>>>>     drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++--------------
>>>>>     1 file changed, 10 insertions(+), 14 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>>>> index d638f5e..537f1d0 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>>>> @@ -1157,22 +1157,18 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
>>>>>     }
>>>>>
>>>>>     static int
>>>>> -intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
>>>>> +intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
>>>>>     {
>>>>>     	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>>>>> -	int i;
>>>>> -	int max_default_rate;
>>>>>
>>>>> -	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
>>>>> -		for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
>>>>> -			source_rates[i] = gen9_rates[i];
>>>>> -	} else {
>>>>> -		/* Index of the max_link_bw supported + 1 */
>>>>> -		max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
>>>>> -		for (i = 0; i < max_default_rate; ++i)
>>>>> -			source_rates[i] = default_rates[i];
>>>>> +	if (INTEL_INFO(dev)->gen >= 9) {
>>>>> +		*source_rates = gen9_rates;
>>>>> +		return ARRAY_SIZE(gen9_rates);
>>>>>     	}
>>>>> -	return i;
>>>>> +
>>>>> +	*source_rates = default_rates;
>>>>> +
>>>>> +	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
>>>> Now when intel_dp_max_link_bw doesn't do much, can this be simply
>>>> ARRAY_SIZE(default_rates)? and we can get away with this function.
>>> If you'll look at patch 6 you'll see me moving the source limitations
>>> from intel_dp_max_link_bw() to intel_dp_source_rates().
>>>
>> Yes, thats why I think we can remove the intel_dp_max_link_bw function
>> altogether.
> We still need it to limit the sink rates appropriately when
> SUPPORTED_LINK_RATES is not present.
But with this series, haven't we already removed that? We are not using 
it anymore.
>>>>>     }
>>>>>
>>>>>     static void
>>>>> @@ -1269,12 +1265,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>>>>     	int link_avail, link_clock;
>>>>>     	int sink_rates[8];
>>>>>     	int supported_rates[8] = {0};
>>>>> -	int source_rates[8];
>>>>> +	const int *source_rates;
>>>>>     	int source_len, sink_len, supported_len;
>>>>>
>>>>>     	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
>>>>>
>>>>> -	source_len = intel_read_source_rates(intel_dp, source_rates);
>>>>> +	source_len = intel_dp_source_rates(intel_dp, &source_rates);
>>>>>
>>>>>     	supported_len = intel_supported_rates(source_rates, source_len,
>>>>>     				sink_rates, sink_len, supported_rates);
>>>>>

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Re: [PATCH 03/13] drm/i915: Don't copy the DP source rates arrays

[Ville Syrjälä]

On Mon, Mar 16, 2015 at 05:03:28PM +0530, sonika wrote:
> 
> On Monday 16 March 2015 04:25 PM, Ville Syrjälä wrote:
> > On Mon, Mar 16, 2015 at 03:07:05PM +0530, Jindal, Sonika wrote:
> >>
> >> On 3/16/2015 3:04 PM, Ville Syrjälä wrote:
> >>> On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika wrote:
> >>>>
> >>>> On 3/12/2015 8:40 PM, ville.syrjala@linux.intel.com wrote:
> >>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>>>
> >>>>> The source rates don't change, so we can just point the caller at the
> >>>>> const arrays.
> >>>>>
> >>>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>>> ---
> >>>>>     drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++--------------
> >>>>>     1 file changed, 10 insertions(+), 14 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >>>>> index d638f5e..537f1d0 100644
> >>>>> --- a/drivers/gpu/drm/i915/intel_dp.c
> >>>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >>>>> @@ -1157,22 +1157,18 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
> >>>>>     }
> >>>>>
> >>>>>     static int
> >>>>> -intel_read_source_rates(struct intel_dp *intel_dp, int *source_rates)
> >>>>> +intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
> >>>>>     {
> >>>>>     	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> >>>>> -	int i;
> >>>>> -	int max_default_rate;
> >>>>>
> >>>>> -	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> >>>>> -		for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
> >>>>> -			source_rates[i] = gen9_rates[i];
> >>>>> -	} else {
> >>>>> -		/* Index of the max_link_bw supported + 1 */
> >>>>> -		max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> >>>>> -		for (i = 0; i < max_default_rate; ++i)
> >>>>> -			source_rates[i] = default_rates[i];
> >>>>> +	if (INTEL_INFO(dev)->gen >= 9) {
> >>>>> +		*source_rates = gen9_rates;
> >>>>> +		return ARRAY_SIZE(gen9_rates);
> >>>>>     	}
> >>>>> -	return i;
> >>>>> +
> >>>>> +	*source_rates = default_rates;
> >>>>> +
> >>>>> +	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> >>>> Now when intel_dp_max_link_bw doesn't do much, can this be simply
> >>>> ARRAY_SIZE(default_rates)? and we can get away with this function.
> >>> If you'll look at patch 6 you'll see me moving the source limitations
> >>> from intel_dp_max_link_bw() to intel_dp_source_rates().
> >>>
> >> Yes, thats why I think we can remove the intel_dp_max_link_bw function
> >> altogether.
> > We still need it to limit the sink rates appropriately when
> > SUPPORTED_LINK_RATES is not present.
> But with this series, haven't we already removed that? We are not using 
> it anymore.

SUPPORTED_LINK_RATES may not be there. We obviously still need to
find out what's the maximum link rate supported by the sink when it's
not available. Hence we still need intel_dp_max_link_bw() to decode
the MAX_LINK_RATE (actually the only thing it does after my
patches is filter out invalid values of MAX_LINK_RATE and issue a
warning).

> >>>>>     }
> >>>>>
> >>>>>     static void
> >>>>> @@ -1269,12 +1265,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >>>>>     	int link_avail, link_clock;
> >>>>>     	int sink_rates[8];
> >>>>>     	int supported_rates[8] = {0};
> >>>>> -	int source_rates[8];
> >>>>> +	const int *source_rates;
> >>>>>     	int source_len, sink_len, supported_len;
> >>>>>
> >>>>>     	sink_len = intel_read_sink_rates(intel_dp, sink_rates);
> >>>>>
> >>>>> -	source_len = intel_read_source_rates(intel_dp, source_rates);
> >>>>> +	source_len = intel_dp_source_rates(intel_dp, &source_rates);
> >>>>>
> >>>>>     	supported_len = intel_supported_rates(source_rates, source_len,
> >>>>>     				sink_rates, sink_len, supported_rates);
> >>>>>

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 14/13] drm/i915: Unconfuse DP link rate array names

[sonika]

On Friday 13 March 2015 11:10 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> To keep things clear rename the intel_dp->supported_rates[] to
> intel_dp->sink_rates[], and rename the supported_rates[] name we used
> elsewhere for the intersection of source and sink rates to
> common_rates[].
>
> Cc: Sonika Jindal <sonika.jindal@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c     | 70 ++++++++++++++++++-------------------
>   drivers/gpu/drm/i915/intel_dp_mst.c |  2 +-
>   drivers/gpu/drm/i915/intel_drv.h    |  5 +--
>   3 files changed, 39 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 715694a..393feed 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1135,9 +1135,9 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
>   static int
>   intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>   {
> -	if (intel_dp->num_supported_rates) {
> -		*sink_rates = intel_dp->supported_rates;
> -		return intel_dp->num_supported_rates;
> +	if (intel_dp->num_sink_rates) {
> +		*sink_rates = intel_dp->sink_rates;
> +		return intel_dp->num_sink_rates;
>   	}
>   
>   	*sink_rates = default_rates;
> @@ -1200,7 +1200,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>   
>   static int intersect_rates(const int *source_rates, int source_len,
>   			   const int *sink_rates, int sink_len,
> -			   int *supported_rates)
> +			   int *common_rates)
>   {
>   	int i = 0, j = 0, k = 0;
>   
> @@ -1208,7 +1208,7 @@ static int intersect_rates(const int *source_rates, int source_len,
>   		if (source_rates[i] == sink_rates[j]) {
>   			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
>   				return k;
> -			supported_rates[k] = source_rates[i];
> +			common_rates[k] = source_rates[i];
>   			++k;
>   			++i;
>   			++j;
> @@ -1221,8 +1221,8 @@ static int intersect_rates(const int *source_rates, int source_len,
>   	return k;
>   }
>   
> -static int intel_supported_rates(struct intel_dp *intel_dp,
> -				 int *supported_rates)
> +static int intel_dp_common_rates(struct intel_dp *intel_dp,
> +				 int *common_rates)
>   {
>   	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>   	const int *source_rates, *sink_rates;
> @@ -1233,7 +1233,7 @@ static int intel_supported_rates(struct intel_dp *intel_dp,
>   
>   	return intersect_rates(source_rates, source_len,
>   			       sink_rates, sink_len,
> -			       supported_rates);
> +			       common_rates);
>   }
>   
>   static void snprintf_int_array(char *str, size_t len,
> @@ -1256,8 +1256,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
>   {
>   	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>   	const int *source_rates, *sink_rates;
> -	int source_len, sink_len, supported_len;
> -	int supported_rates[DP_MAX_SUPPORTED_RATES];
> +	int source_len, sink_len, common_len;
> +	int common_rates[DP_MAX_SUPPORTED_RATES];
>   	char str[128]; /* FIXME: too big for stack? */
>   
>   	if ((drm_debug & DRM_UT_KMS) == 0)
> @@ -1271,9 +1271,9 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
>   	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
>   	DRM_DEBUG_KMS("sink rates: %s\n", str);
>   
> -	supported_len = intel_supported_rates(intel_dp, supported_rates);
> -	snprintf_int_array(str, sizeof(str), supported_rates, supported_len);
> -	DRM_DEBUG_KMS("supported rates: %s\n", str);
> +	common_len = intel_dp_common_rates(intel_dp, common_rates);
> +	snprintf_int_array(str, sizeof(str), common_rates, common_len);
> +	DRM_DEBUG_KMS("common rates: %s\n", str);
>   }
>   
>   static int rate_to_index(int find, const int *rates)
> @@ -1293,7 +1293,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
>   	int rates[DP_MAX_SUPPORTED_RATES] = {};
>   	int len;
>   
> -	len = intel_supported_rates(intel_dp, rates);
> +	len = intel_dp_common_rates(intel_dp, rates);
>   	if (WARN_ON(len <= 0))
>   		return 162000;
>   
> @@ -1302,7 +1302,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
>   
>   int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
>   {
> -	return rate_to_index(rate, intel_dp->supported_rates);
> +	return rate_to_index(rate, intel_dp->sink_rates);
>   }
>   
>   bool
> @@ -1324,15 +1324,15 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   	int max_clock;
>   	int bpp, mode_rate;
>   	int link_avail, link_clock;
> -	int supported_rates[DP_MAX_SUPPORTED_RATES] = {};
> -	int supported_len;
> +	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
> +	int common_len;
>   
> -	supported_len = intel_supported_rates(intel_dp, supported_rates);
> +	common_len = intel_dp_common_rates(intel_dp, common_rates);
>   
>   	/* No common link rates between source and sink */
> -	WARN_ON(supported_len <= 0);
> +	WARN_ON(common_len <= 0);
>   
> -	max_clock = supported_len - 1;
> +	max_clock = common_len - 1;
>   
>   	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
>   		pipe_config->has_pch_encoder = true;
> @@ -1357,7 +1357,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   
>   	DRM_DEBUG_KMS("DP link computation with max lane count %i "
>   		      "max bw %d pixel clock %iKHz\n",
> -		      max_lane_count, supported_rates[max_clock],
> +		      max_lane_count, common_rates[max_clock],
>   		      adjusted_mode->crtc_clock);
>   
>   	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
> @@ -1390,7 +1390,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   				lane_count <= max_lane_count;
>   				lane_count <<= 1) {
>   
> -				link_clock = supported_rates[clock];
> +				link_clock = common_rates[clock];
>   				link_avail = intel_dp_max_data_rate(link_clock,
>   								    lane_count);
>   
> @@ -1421,18 +1421,18 @@ found:
>   
>   	intel_dp->lane_count = lane_count;
>   
> -	if (intel_dp->num_supported_rates) {
> +	if (intel_dp->num_sink_rates) {
>   		intel_dp->link_bw = 0;
>   		intel_dp->rate_select =
> -			intel_dp_rate_select(intel_dp, supported_rates[clock]);
> +			intel_dp_rate_select(intel_dp, common_rates[clock]);
>   	} else {
>   		intel_dp->link_bw =
> -			drm_dp_link_rate_to_bw_code(supported_rates[clock]);
> +			drm_dp_link_rate_to_bw_code(common_rates[clock]);
>   		intel_dp->rate_select = 0;
>   	}
>   
>   	pipe_config->pipe_bpp = bpp;
> -	pipe_config->port_clock = supported_rates[clock];
> +	pipe_config->port_clock = common_rates[clock];
>   
>   	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
>   		      intel_dp->link_bw, intel_dp->lane_count,
> @@ -1455,7 +1455,7 @@ found:
>   	}
>   
>   	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
> -		skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
> +		skl_edp_set_pll_config(pipe_config, common_rates[clock]);
>   	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>   		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
>   	else
> @@ -3542,7 +3542,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>   	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>   		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>   	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> -	if (intel_dp->num_supported_rates)
> +	if (intel_dp->num_sink_rates)
>   		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
>   				&intel_dp->rate_select, 1);
>   
> @@ -3794,23 +3794,23 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>   	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
>   	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
>   	    (rev >= 0x03)) { /* eDp v1.4 or higher */
> -		__le16 supported_rates[DP_MAX_SUPPORTED_RATES];
> +		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
>   		int i;
>   
>   		intel_dp_dpcd_read_wake(&intel_dp->aux,
>   				DP_SUPPORTED_LINK_RATES,
> -				supported_rates,
> -				sizeof(supported_rates));
> +				sink_rates,
> +				sizeof(sink_rates));
>   
> -		for (i = 0; i < ARRAY_SIZE(supported_rates); i++) {
> -			int val = le16_to_cpu(supported_rates[i]);
> +		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
> +			int val = le16_to_cpu(sink_rates[i]);
>   
>   			if (val == 0)
>   				break;
>   
> -			intel_dp->supported_rates[i] = val * 200;
> +			intel_dp->sink_rates[i] = val * 200;
>   		}
> -		intel_dp->num_supported_rates = i;
> +		intel_dp->num_sink_rates = i;
>   	}
>   
>   	intel_dp_print_rates(intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 7e6f1259..971163e 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -55,7 +55,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>   
>   	rate = intel_dp_max_link_rate(intel_dp);
>   
> -	if (intel_dp->num_supported_rates) {
> +	if (intel_dp->num_sink_rates) {
>   		intel_dp->link_bw = 0;
>   		intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
>   	} else {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 4174198..a1baaa1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -627,8 +627,9 @@ struct intel_dp {
>   	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
>   	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>   	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> -	uint8_t num_supported_rates;
> -	int supported_rates[DP_MAX_SUPPORTED_RATES];
> +	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
> +	uint8_t num_sink_rates;
> +	int sink_rates[DP_MAX_SUPPORTED_RATES];
>   	struct drm_dp_aux aux;
>   	uint8_t train_set[4];
>   	int panel_power_up_delay;
This series looks good to me. So for all the patches 1 - 14,

Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>

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Re: [PATCH 06/13] drm/i915: Fully separate source vs. sink rates

[Daniel Vetter]

On Thu, Mar 12, 2015 at 05:10:32PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Remove the sink vs. source limit mess from intel_dp_max_link_bw() and
> just move the source restriction checks to intel_dp_source_rates().
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 22 ++++++++--------------
>  1 file changed, 8 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index aa373a2..61538f4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -126,19 +126,11 @@ int
>  intel_dp_max_link_bw(struct intel_dp *intel_dp)
>  {
>  	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
> -	struct drm_device *dev = intel_dp->attached_connector->base.dev;
>  
>  	switch (max_link_bw) {
>  	case DP_LINK_BW_1_62:
>  	case DP_LINK_BW_2_7:
> -		break;
> -	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
> -		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> -		     INTEL_INFO(dev)->gen >= 8) &&
> -		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
> -			max_link_bw = DP_LINK_BW_5_4;
> -		else
> -			max_link_bw = DP_LINK_BW_2_7;
> +	case DP_LINK_BW_5_4:

This hunk conflicts with the WaDisableHBR2 patch. Resolved it while
applying.
-Daniel

>  		break;
>  	default:
>  		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
> @@ -1151,10 +1143,8 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>  }
>  
>  static int
> -intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
> +intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>  {
> -	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> -
>  	if (INTEL_INFO(dev)->gen >= 9) {
>  		*source_rates = gen9_rates;
>  		return ARRAY_SIZE(gen9_rates);
> @@ -1162,7 +1152,11 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
>  
>  	*source_rates = default_rates;
>  
> -	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> +	if (INTEL_INFO(dev)->gen >= 8 ||
> +	    (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
> +		return (DP_LINK_BW_5_4 >> 3) + 1;
> +	else
> +		return (DP_LINK_BW_2_7 >> 3) + 1;
>  }
>  
>  static void
> @@ -1256,7 +1250,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
>  
> -	source_len = intel_dp_source_rates(intel_dp, &source_rates);
> +	source_len = intel_dp_source_rates(dev, &source_rates);
>  
>  	supported_len = intel_supported_rates(source_rates, source_len,
>  				sink_rates, sink_len, supported_rates);
> -- 
> 2.0.5
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 14/13] drm/i915: Unconfuse DP link rate array names

[Daniel Vetter]

On Tue, Mar 17, 2015 at 03:15:33PM +0530, sonika wrote:
> This series looks good to me. So for all the patches 1 - 14,
> 
> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>

All merged to dinq, thanks for patches&review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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